Ring amplifier

Abstract

This ring amplifier lowers output impedance, increases bandwidth, and improves slew rate. [Solution] A ring amplifier 10A in which multiple inverters are connected in series includes a first MOS transistor MP1 that constitutes the output stage inverter INV3d, a second MOS transistor MP2 connected in parallel to the first MOS transistor MP1, a capacitor C3 that feeds back the output signal OUT of the output stage inverter INV3d to the input side of the ring amplifier, and a differential amplifier B1p that attenuates the signal input to the first MOS transistor MP1 and inputs it to the gate of the second MOS transistor MP2.

Description

【Technical Field】 【0001】 This invention relates to a ring amplifier suitable for high-speed operation. 【Background Art】 【0002】 In recent years, by changing the residue amplifier used in a pipeline ADC (Analog to Digital Converter) or a pipeline SAR (Successive Approximation Register) from a conventional cascade amplifier to a ring amplifier, the performance of the ADC has been improved to achieve high-speed operation with low power consumption. 【0003】 FIG. 5 is a circuit diagram showing the configuration of a ring amplifier 10 which is an example of a conventional ring amplifier. This ring amplifier 10 is formed by connecting a plurality of inverters INV1, INV2p and INV2n, INV3 in series. An input signal IN is input to the inverter INV1 via a capacitor C1. The output node of the inverter INV1 is connected to the input nodes of the inverters INV2p and INV2n via capacitors C2p and C2n, respectively. The output node of the inverter INV2p is connected to the gate of the P-channel first MOS transistor MP1 of the output-stage inverter INV3. The output terminal of the inverter INV2n is connected to the gate of the N-channel first MOS transistor MN1 of the output-stage inverter INV3. The source of the first MOS transistor MP1 is connected to the power supply VDD, and the source of the first MOS transistor MN1 is grounded. Then, the drains of the first MOS transistor MP1 and the first MOS transistor MN1 are commonly connected and serve as the output node of the output-stage inverter INV3. The output node of this inverter INV3 is grounded via a capacitor C4 which is a load capacitor. Also, the output signal OUT of the inverter INV3 is fed back to the input node of the inverter INV1 via a capacitor C3. 【0004】 Figure 6 is a waveform diagram showing an example of the operation of the ring amplifier 10. Figure 6 shows the waveforms of the input signal IN, the signal at the input node Nd1 of the first MOS transistor MP1, the current IDP1 flowing through the first MOS transistor MP1, and the output signal OUT. 【0005】 When the input signal IN falls, the signal at the input node Nd1 of the first MOS transistor MP1 falls, the current IDP1 flowing through the first MOS transistor MP1 increases, and the output signal OUT rises. As the output signal OUT approaches the power supply voltage VDD, the signal at node Nd1 rises due to feedback via capacitor C3, and the first MOS transistor MP1 turns OFF. The above is an example of the operation of the ring amplifier 10. 【0006】 To ensure the stability of the ring amplifier 10, it is common practice to increase the output impedance of the output stage inverter INV3 and design it so that the first pole is determined at the output stage. However, it is known that increasing the impedance of the output stage reduces the current capability of the output stage and lowers the amplifier's slew rate. Therefore, in order to operate the ADC at high speed, it is necessary to improve the amplifier's slew rate while maintaining the amplifier's stability without increasing the current consumption. 【0007】 The ring amplifier disclosed in Patent Document 1, as shown in the ring amplifier 10 in Figure 5, consists of multiple inverters connected in series. The output stage inverter includes a first MOS transistor and a second MOS transistor connected in parallel to the first MOS transistor, and the connection / disconnection of the second MOS transistor is switched by a switch. In this ring amplifier, by turning the switch ON and connecting the second MOS transistor in parallel to the first MOS transistor, the impedance of the output stage is lowered and the slew rate is increased. [Prior art documents] [Patent Documents] 【0008】 [Patent Document 1] Japanese Patent Publication No. 2014-204226 [Overview of the Initiative] [Problems that the invention aims to solve] 【0009】 In the technology disclosed in Patent Document 1, while the slew rate of the amplifier improves during the ON period, stability is lost, resulting in the problem that the amplifier does not stabilize during the ON period. Furthermore, if the amplifier oscillates, and the value of the oscillation waveform is taken at the moment the switch is turned OFF, the high-impedance output stage drives the amplifier's output capacitance up to the final stabilization voltage, which may prevent the final stabilization voltage from being reached. 【0010】 This invention was made in view of the circumstances described above, and aims to provide a technical means to increase bandwidth and improve slew rate by lowering the output impedance only when the output of the ring amplifier is being passed through, rather than performing bandwidth control by digital control. [Means for solving the problem] 【0011】 This invention provides a ring amplifier in which a plurality of inverters are connected in series, comprising: a first MOS transistor constituting an output stage inverter; a second MOS transistor connected in parallel to the first MOS transistor; a feedback circuit that feeds back the output signal of the output stage inverter to the input side of the ring amplifier; and a transmission circuit that attenuates the signal input to the first MOS transistor and inputs it to the second MOS transistor. 【0012】 According to this invention, by turning on both the first MOS transistor and the second MOS transistor only when the output of the ring amplifier is being passed through, the output impedance can be lowered, the bandwidth increased, and the slew rate improved. [Brief explanation of the drawing] 【0013】 [Figure 1]This is a circuit diagram showing the configuration of a ring amplifier, which is the first embodiment of this invention. [Figure 2] This is a waveform diagram showing the operation of the ring amplifier. [Figure 3] This is a circuit diagram showing the configuration of a ring amplifier, which is a second embodiment of this invention. [Figure 4] This is a circuit diagram showing the configuration of a ring amplifier, which is a third embodiment of this invention. [Figure 5] This is a circuit diagram showing the configuration of a conventional ring amplifier. [Figure 6] This is a waveform diagram showing the operation of the ring amplifier. [Modes for carrying out the invention] 【0014】 The embodiments of this invention will be described below with reference to the drawings. 【0015】 <First Embodiment> Figure 1 is a circuit diagram showing the configuration of a ring amplifier 10A, which is a first embodiment of this invention. In Figure 1, parts corresponding to the components of the ring amplifier 10 in Figure 5 described above are denoted by the same reference numerals, and their descriptions are omitted. 【0016】 In the ring amplifier 10A, the output stage inverter INV3d is composed of a P-channel first MOS transistor MP1 and an N-channel first MOS transistor MN1, and a P-channel second MOS transistor MP2 and an N-channel second MOS transistor MN2 connected in parallel to them, respectively. The ring amplifier 10A is also provided with differential amplifiers B1p and B1n, each with a gain A less than 1. The differential amplifier B1p has its non-inverting input terminal connected to the power supply VDD, its inverting input terminal connected to the input node (i.e., gate) Nd1 of the first MOS transistor MP1, and its output terminal connected to the input node (i.e., gate) Nd2 of the second MOS transistor MP2. The differential amplifier B1n has its inverting input terminal grounded, its non-inverting input terminal connected to the input node (i.e., gate) of the first MOS transistor MN1, and its output terminal connected to the input node (i.e., gate) of the second MOS transistor MN2. The differential amplifiers B1p and B1n are transfer circuits that attenuate the signals input to the input nodes of the first MOS transistors MP1 and MN1 and input them to the input nodes of the second MOS transistors MP2 and MN2. 【0017】 Figure 2 is a waveform diagram showing an example of the operation of the ring amplifier 10A. Figure 2 shows the waveforms of the input signal IN, the signal at input node Nd1 of the first MOS transistor MP1, the signal at input node Nd2 of the second MOS transistor MP2, the current IDP1 flowing through the first MOS transistor MP1, the current IDP2 flowing through the second MOS transistor MP2, and the output signal OUT. 【0018】 When the input signal IN falls, the signal at the input node Nd1 of the first MOS transistor MP1 falls, and the current IDP1 flowing through the first MOS transistor MP1 increases. Thereafter, a signal that is A times (A < 1) the signal at node Nd1 is output from the differential amplifier B1p to the input node Nd2 of the MOS transistor MP2. Then, with a delay after the increase in the current IDP1, the second MOS transistor MP2 turns on, and the current IDP2 flows through the second MOS transistor MP2. When the output signal OUT rises and approaches the expected voltage value, the signal at node Nd1 rises toward the power supply VDD due to feedback through the capacitor C3, and the first MOS transistor MP1 and the second MOS transistor MP2 tend to turn off. At that time, since node Nd2 rises to the power supply voltage VDD earlier than node Nd1, the second MOS transistor MP2 turns off before the output signal OUT settles, and the operation of the final settlement is limited to the bandwidth determined by the output impedance of the MOS transistor MP1 and the load capacitor C4 and heads toward the final settlement. 【0019】 As described above, in this embodiment, when the input signal IN falls, only the first MOS transistor MP1 is in the ON state → the first MOS transistor MP1 and the second MOS transistor MP2 are ON and quickly charge the capacitor C4 (output stage through) → the first MOS transistor MP1 tends to turn off, and the second MOS transistor MP2 tends to turn off earlier than that. That is, in this embodiment, the output impedance decreases only during the period when the output stage is in the through state, and thereafter, the final settlement is performed only by the first MOS transistor MP1. 【0020】 The operation when the input signal IN falls has been described above. The operation when the input signal IN rises is basically the same. When the input signal IN rises, only the first MOS transistor MN1 is in the ON state → both the first MOS transistor MN1 and the second MOS transistor MN2 are in the ON state and quickly discharge the capacitor C4 (output stage through) → the first MOS transistor MN1 starts to turn OFF, and before that, the second MOS transistor MN2 starts to turn OFF. That is, the output impedance decreases only during the period when the output stage is in the through state, and then the final static state is achieved only by the first MOS transistor MN1. 【0021】 As described above, according to this embodiment, the output signal can be statically determined at high speed while ensuring stability. 【0022】 <Second Embodiment> FIG. 3 is a circuit diagram showing the configuration of the ring amplifier 10B according to the second embodiment of the present invention. In FIG. 3, parts corresponding to the components of the first embodiment are denoted by the same reference numerals, and their descriptions are omitted. 【0023】 In the ring amplifier 10B, the source followers B2p and B2n in FIG. 3 function as a transmission circuit that attenuates the signal input to the first MOS transistor and inputs it to the second MOS transistor. [[ID=^{16}]] 【0024】 The source follower B2p consists of a P-channel MOS transistor B2pa and a resistor B2pb. Here, the gate of the MOS transistor B2pa is connected to the input node of the first MOS transistor MP1, the drain is grounded, and the source is connected to the input node of the second MOS transistor MP2 and also connected to the power supply VDD through the resistor B2pb. In this embodiment, the voltage obtained by subtracting the threshold voltage Vth of the MOS transistor B2pa from the signal input to the first MOS transistor MP1 is input to the second MOS transistor MP2. 【0025】 The source follower B2n consists of an N-channel MOS transistor B2na and a resistor B2nb. Here, the gate of MOS transistor B2na is connected to the input node of the first MOS transistor MN1, the drain is connected to the power supply VDD, and the source is connected to the input node of the second MOS transistor MN2 and is also grounded via resistor B2nb. In this embodiment, the signal obtained by subtracting the threshold voltage Vth of MOS transistor B2na from the signal input to the first MOS transistor MN1 is input to the second MOS transistor MN2. 【0026】 In this embodiment as well, the same effects as in the first embodiment can be obtained. 【0027】 <Third Embodiment> Figure 4 is a circuit diagram showing the configuration of a ring amplifier 10C, which is a third embodiment of this invention. In Figure 4, parts corresponding to the components of the first embodiment are denoted by the same reference numerals, and their descriptions are omitted. 【0028】 In the ring amplifier 10C, the voltage divider circuits B3p and B3n in Figure 4 function as transfer circuits that attenuate the signal input to the first MOS transistor before inputting it to the second MOS transistor. 【0029】 In the voltage divider circuit B3p, resistors B3pa and B3pb are connected in series between the input node of the first MOS transistor MP1 and the power supply VDD, and the intermediate nodes of resistors B3pa and B3pb are connected to the input node of the second MOS transistor MP2. 【0030】 In the voltage divider circuit B3n, resistors B3na and B3nb are connected in series between the input node of the first MOS transistor MN1 and ground, and the intermediate nodes of resistors B3na and B3nb are connected to the input node of the second MOS transistor MN2. 【0031】 In this embodiment as well, the same effects as in the first embodiment can be obtained. [Explanation of symbols] 【0032】 10A, 10B, 10C... Ring amplifier; INV1, INV2p, INV2n, INV3d... Inverter; MP1, MN1... First MOS transistor; MP2, MN2... Second MOS transistor; B1p, B1n... Differential amplifier; B2p, B2n... Source follower; B3p, B3n... Voltage divider circuit; C1, C2p, C2n, C3, C4... Capacitors; B3pa, B3na... MOS transistor; B2pb, B2nb, B3pa, B3pb, B3na, B3nb... Resistors.

Claims

[Claim 1] In a ring amplifier with multiple inverters connected in series, The first MOS transistor that constitutes the inverter of the output stage, A second MOS transistor connected in parallel to the first MOS transistor, A feedback circuit that feeds back the output signal of the inverter in the output stage to the input side of the ring amplifier, A transmission circuit that attenuates the signal input to the first MOS transistor and inputs it to the second MOS transistor, A ring amplifier that includes a ring amplifier. [Claim 2] The ring amplifier according to claim 1, wherein the transmission circuit is an amplifier with a gain less than 1. [Claim 3] The ring amplifier according to claim 1, wherein the transmission circuit is a source follower circuit consisting of a MOS transistor and a resistor. [Claim 4] The ring amplifier according to claim 1, wherein the transmission circuit is a voltage divider circuit consisting of a plurality of resistors.

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