Smart time control for switching between different phases of a device via a single capacitor.

Abstract

The present invention provides an apparatus and method for generating different time / delay types using only a single capacitor. [Solution] The system 100 includes a first current source 102 that provides a first bias current and a second current source 104 that provides a second bias current, wherein the first bias current is greater than the second bias current. The system also includes a current switch, which receives the first and second bias currents at its two input terminals 103 and 105 and provides an output current at its output terminal 107. The output current is one of the first and second bias currents selected by the current switch control signal. The system further includes a capacitor 108 coupled between the output terminal and the ground terminal, which is charged by the output current and provides an output voltage at the output terminal.

Description

[Technical Field]

[0001] Time control is crucial for various phases of a device (e.g., a switching regulator). Specifically, after power is supplied to the regulator (power-up phase), the regulator enters the system enable (SYS_EN) phase, where the device waits for its internal power supply to stabilize, resulting in a time delay of approximately 100 microseconds. The SYS_EN phase is followed by the soft start (SS) phase, which typically lasts several milliseconds to provide a smooth output voltage (Vout). Due to these timing differences, the time control of the SYS_EN and SS phases has traditionally been handled by separate timing generation circuits. For example, the delay in the SYS_EN phase can be generated by a digital counter consisting of multiple D-flips, while the time in the SS phase can be generated by charging a capacitor. Furthermore, extra analog control circuit elements are often required to isolate the SYS_EN and SS phases. Such redundant circuit elements often result in significant chip size overhead and waste for the device. [Overview of the project]

[0002] In one example, the device includes a first current source configured to provide a first bias current and a second current source configured to provide a second bias current, wherein the first bias current is greater than the second bias current. The device further includes a current switch configured to receive a first bias current and a second bias current at its two input terminals and to provide an output current at its output terminal, wherein the output current is one of the first bias current and the second bias current, selected by a current switch control signal to the current switch. The device further includes a capacitor coupled between the output terminal and a ground terminal, which is charged by the output current and provides an output voltage at the output terminal.

[0003] In another example, a method includes providing a first bias current via a first current source and providing a second bias current via a second current source, wherein the first bias current is greater than the second bias current. This method further includes receiving the first and second bias currents at two input terminals of a current switch and providing an output current at the output terminal of the current switch, wherein the output current is one of the first and second bias currents, selected by a current switch control signal to the current switch. This method further includes charging a capacitor coupled between the output terminal and the ground terminal with the output current and providing an output voltage at the output terminal. [Brief explanation of the drawing]

[0004] [Figure 1] As an example, this is a schematic diagram of a time-controlled system for switching between different phases of a device.

[0005] [Figure 2] In one example, this is a graph illustrating the waveforms of multiple signals in Figure 1 that switch between various phases.

[0006] [Figure 3A] This graph illustrates the waveforms of the output voltage SS_INT and the comparison output signal DONE during the hiccup protection phase. [Figure 3B] In one example, this is a schematic diagram of a time control circuit element used during a hiccup current protection mode.

[0007] [Figure 4A] This graph illustrates the waveforms related to clock dithering in one example. [Figure 4B] This is a schematic diagram of the clock dithering circuit elements in one example. [Modes for carrying out the invention]

[0008] In drawings, the same reference number or other reference numerals are used to indicate identical or similar features (of function and / or structure).

[0009] Figure 1 is a schematic diagram of an example of a time-controlled system 100 for switching between different phases of a device. As shown in the example in Figure 1, the system 100 includes a first current source 102 configured to provide a first bias current I1 and a second current source 104 configured to provide a second bias current I2. In one example, the first bias current I1 is greater than the second bias current I2. The system 100 further includes a current switch 106, which is configured to receive the first bias current I1 from the first current source 102 and the second bias current I2 from the second current source 104 at its two input terminals 103 and 105, respectively. The current switch 106 is configured to provide an output current at its output terminal 107, which is one of the first bias current and the second bias current, selected by a current switch control signal SYS_EN to the current switch 106. A current switch control signal SYS_EN to the current switch 106 toggles between a first bias current I1 and a second bias current I2, where the first bias current I1 is greater than the second bias current I2 and charges faster. The system 100 further includes a single capacitor 108 coupled between the output terminal 107 and the ground terminal. During operation, the capacitor 108 is charged by the output current from the current switch 106, i.e., one of the first bias current I1 and the second bias current I2, and the capacitor 108 provides an output voltage SS_INT at the output terminal 107.

[0010] System 100, as shown in Figure 1, generates different time / delay types using only a single capacitor 108, thus eliminating redundant time control logic (e.g., digital counters and other digital and / or analog circuit elements) and extra capacitors required by the clock. As a result, system 100 reduces chip area and cost. By toggling between different bias currents I1 and I2 via a single current switch 106, system 100 controls the charging time of the single capacitor 108 so that it is either longer (e.g., ms) with a smaller bias current I2 or shorter (e.g., μs) with a larger bias current I1 for different switching phases of the device. In this way, the time control circuit elements that were conventionally separated for the SYS_EN and SS phases of the device can be integrated into a single circuit element, as will be described in detail below.

[0011] In one example, system 100 further includes a discharge switch 112 coupled between an output terminal 107 and a ground terminal, the discharge switch 112 being controlled by a discharge / reset signal. When the discharge signal turns off the discharge switch 112, the output voltage SS_INT maintains its current level. When the discharge signal turns on the discharge switch 112, the output terminal 107 is connected to the ground terminal, discharging capacitor 108 and resetting the output voltage SS_INT to low or zero.

[0012] In one example, system 100 further includes a voltage comparator 108, which takes an output voltage SS_INT and a reference voltage Vref as its two inputs and is configured to provide a comparison output voltage / signal DONE at its comparison output terminal 115 based on a comparison between the output voltage SS_INT and the reference voltage Vref. In one example, the comparison output signal DONE remains low when the output voltage SS_INT is less than the reference voltage Vref. The comparison output signal DONE becomes high when the output voltage SS_INT is equal to the reference voltage Vref.

[0013] In one example, the system 100 further includes a reset (RS) latch 116, which is configured to receive a comparison output signal DONE and a current switch control signal SYS_EN as its two inputs S and R, respectively, and to generate a latch output signal SS_DONE over a period of time. In one example, the reset (RS) latch 116 sets the latch output signal SS_DONE high based on the comparison output signal DONE and resets the latch output signal SS_DONE low based on the current switch control signal SYS_EN.

[0014] In one example, system 100 further includes a control logic unit 110, which receives a comparison output signal DONE and a latch output signal SS_DONE as its inputs and generates a current switch control signal SYS_EN to a current switch 106, which is configured to toggle between a first bias current I1 and a second bias current I2 as the output current from the current switch 106. In one example, the current switch control signal SYS_EN generated by the control logic unit 110 is an analog time control signal that separates various different phases of the device, such as a power-up phase and a system enable phase. In one example, the control logic unit 110 is configured to use a finite state machine to control transitions between various phases represented by the states of the finite state machine and to avoid various types of fault reset conditions via the current switch control signal SYS_EN.

[0015] In one example, the control logic unit 110 is configured to generate a discharge signal to turn the discharge switch 112 on or off to reset or maintain the output voltage SS_INT at the output voltage terminal 107, respectively. In one example, a set of periodic pulses of the comparison output signal DONE acts as a reset signal for discharging the capacitor 108. The control logic unit 110 is configured to count the number of periodic pulses of the comparison output signal DONE in the set in order to determine when the capacitor 108 should be discharged.

[0016] Figure 2 is a graph illustrating examples of the waveforms of the multiple signals in Figure 1 as they switch between various phases. As shown in Figure 2, the current switch control signal SYS_EN is initially low, which selects a large bias current I1 as the output current during the PRE_SS (or SYS_EN) phase. The output voltage SS_INT rises rapidly and linearly during the PRE_SS phase as the capacitor 108 is rapidly charged by the large bias current I1 until the output voltage SS_INT reaches the reference voltage Vref. At that point, the voltage comparator 108 sets the comparison output signal DONE to high, causing the control logic unit 110 to send a discharge signal, which turns on the discharge switch 112 to discharge the capacitor 108. Once the capacitor 108 is discharged, the output voltage SS_INT drops to low, which in turn causes the comparison output signal DONE to drop to low, generating a pulse in the comparison output signal DONE. After detecting and counting one or more such pulses in the comparison output signal DONE, for example, two pulses as shown in Figure 2, the control logic unit 110 raises the current switch control signal SYS_EN. As shown in the example in Figure 2, each fast charge cycle of the capacitor 108 takes approximately 40 μs. Thus, the current switch control signal SYS_EN provides a delay of approximately 80 μs over the system enable phase across two fast charge cycles.

[0017] When the current switch control signal SYS_EN goes high, the output current from the current switch 106 toggles from the large bias current I1 to the small bias current I2, and the capacitor 108 enters a slow charging phase such as the SS phase, during which the output voltage SS_INT rises slowly and linearly. As shown by the example in Figure 2, the slow charging SS phase can last about 4 ms until the output voltage SS_INT reaches the reference voltage Vref. At this time, instead of resetting the output voltage SS_INT, the control logic unit 110 can hold the output voltage SS_INT at a high level for a certain time period during the SS_DONE phase as shown in Figure 2 based on the latch output signal SS_DONE. Here, the latch output signal SS_DONE is generated by the reset latch 116 based on the comparison output signal DONE and the current switch control signal SYS_EN.

[0018] In one example, the output voltage SS_INT generated by the system 100 can be used (e.g., multiplexed) to meet the time requirements of additional phases and / or application examples other than the above-mentioned SYS_EN and SS phases. As a non-limiting example, the output voltage SS_INT can also be used for the time control of the hiccup protection and dithering phase / mode / feature following the SS_DONE phase. When the hiccup mode causes a continuous short circuit or fault state, for example, for a period of hiccup time (T_hiccup) such as 88 ms, the hiccup protection phase is activated to shut down the device.

[0019] Figure 3A is a graph illustrating an example of the waveforms of the output voltage SS_INT and the comparison output signal DONE during the hiccup protection phase, and Figure 3B is a schematic diagram of an example of the time control circuit element 300 used during the hiccup current protection mode.

[0020] As illustrated in the example in Figure 3A, the hiccup protection phase may include multiple slow charging cycles, each including a slow ramp-up and subsequent reset of the output voltage SS_INT, resulting in a set of periodic pulses in the comparison output signal DONE as the slow charging SS cycle described above. This set of periodic pulses in the comparison output signal DONE is then used as a clock input to a time control circuit element 300, which may be a digital counter including multiple D-flips 302 connected in series, as shown in Figure 3B. In one example, the set of periodic pulses in the comparison output signal DONE is selected / multiplexed from multiple clock sources. In one example, the number of D-flips 302 in the time control circuit element 300 is flexibly determined by the required hiccup time. As a non-limiting example, if each slow charging cycle is 4 ms, then 22 slow charging cycles and a corresponding number of D-flips 302 are required to obtain a hiccup time of 88 ms.

[0021] In the case of clock dithering, the triangular current source I1 is used to generate the oscillation current I osc Insert into or oscillate triangular current source I1 with current I osc By extracting from, the dithering current I dither A dithering current I is created. dither Using this, a clock with frequency f triangular dithering within a certain frequency range (fmin, fmax) is generated according to the following formula. TIFF2026097751000002.tif925

[0022] Figure 4A is a graph illustrating an example of waveforms related to clock dithering, and Figure 4B is a schematic diagram of an example of a clock dithering circuit element 400. The output voltage SS_INT generated by system 100 is a ramp signal, but as shown in Figure 4A, by controlling the discharge current and charge current each cycle, system 100 controls two threshold levels V thh and V thlIt can be further shaped into a triangular wave signal linearly modulated between. The voltage-current (V2I) conversion circuit 402 shown in FIG. 4B is used to convert the triangular wave of SS_INT into a triangular current source I1, and the value of I1 is limited within a certain range, where Imin (e.g., 0 A) < I1 < Imax (e.g., 37 nA). Then, the triangular current source I1 is supplied to a current comparator 404 that compares I1 with a reference current Iref and generates a first clock switching signal vgate1. In one example, vgate1 is also used as an input to a D flip 406 to generate a second clock switching signal vgate2 at approximately half the frequency of vgate1, as shown in FIG. 4A. Then, the clock switching signals vgate1 and vgate2 are used to control a set of FETs, such as 408, 410, and 412, to insert I1 into the oscillation current I osc or extract I1 from the oscillation current I osc to generate a dithering current I dither . For example, the dithering current I dither is used to generate a dithering clock within the following frequency range (fmin, fmax). · vgate1 = 1 and vgate2 = 0: I dither = I osc + I1, and the clock frequency f increases to fmax. · vgate1 = 0 and vgate2 = 0, I dither = I osc + I1, and the clock frequency f decreases to fref. · vgate1 = 1, vgate2 = 1, I dither = I osc - I1, and the clock frequency f decreases to fmin. · vgate1 = 0, vgate2 = 1, I dither = I osc - I1, and the clock frequency f increases to fref. Where fref is the reference frequency between fmin and fmax as shown in FIG. 4A.

[0023] In this description, the term “to connect” may include connections, communications, or signaling paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B in order to perform a certain action, then (a) in the first example, device A is connected to device B by a direct connection, or (b) in the second example, device A is connected to device B via an intermediary component C, such that device B is controlled by device A via a control signal generated by device A, provided that the intermediary component C does not alter the functional relationship between device A and device B.

[0024] Furthermore, in this document, the phrase "based on ~" means "based at least partially on ~". Therefore, if X is based on Y, X can be a function of Y and any number of other factors.

[0025] A device "configured" to perform a certain task or function may be configured (e.g., programmed and / or wired) at the time of manufacture by the manufacturer to perform that function, and / or may be configurable (or reconfigurable) after manufacture by the user to perform that function and / or other additional or alternative functions. Such configuration may be via firmware and / or software programming of the device, via the construction and / or layout of hardware components, via the interconnection of the devices, or a combination thereof.

[0026] In this document, unless otherwise stated, “approximately,” “about,” or “substantially” preceding a parameter means that it is within + / - 10% of that parameter, or, if the parameter is zero, a reasonable value near zero.

[0027] The embodiments described may be modified within the scope of the claims of the present invention, and other embodiments are possible.

Claims

1. It is a device, A first current source configured to provide a first bias current, A second current source configured to provide a second bias current, wherein the first bias current is greater than the second bias current, It is a current switch, The first bias current and the second bias current are received at these two input terminals. The output terminal provides output current. The current switch is configured such that the output current is selected by a current switch control signal to the current switch, and provides one of the first bias current and the second bias current, A capacitor coupled between the output terminal and the ground terminal, which is charged by the output current and provides an output voltage at the output terminal, A device including a device.

2. The apparatus according to claim 1, further comprising a discharge switch coupled between the output terminal and the ground terminal, wherein the discharge switch is controlled by a discharge signal.

3. The apparatus according to claim 2, further comprising a voltage comparator, The aforementioned voltage comparator, The output voltage and the reference voltage are received as the two inputs. A comparison output signal is provided based on a comparison between the output voltage and the reference voltage. A device configured in such a way.

4. The apparatus according to claim 3, further comprising a reset latch, The reset latch, The comparison output signal and the current switch control signal are received as inputs. Based on the comparison output signal and the current switch control signal, a latch output signal is generated for a certain period of time. A device configured in such a way.

5. The apparatus according to claim 4, further comprising a control logic unit, The control logic unit, The comparison output signal and the latch output signal are received as inputs. In order to select one of the first bias current and the second bias current as the output current from the current switch, a current switch control signal is generated for the current switch. A device configured in such a way.

6. The apparatus according to claim 5, A device wherein the control logic unit is configured to generate the discharge signal to the discharge switch in order to reset or maintain the output voltage at the output terminal.

7. The apparatus according to claim 5, A device in which the control logic unit is configured to control the output voltage for the system enable phase of the device by selecting the first bias current to charge the capacitor via the current switch control signal.

8. The apparatus according to claim 5, A device in which the control logic unit is configured to control the output voltage for the soft-start phase of a device by selecting the second bias current to charge the capacitor via the current switch control signal.

9. The apparatus according to claim 5, A device in which the control logic unit is configured to control the output voltage for the hiccup protection phase of the device, and the output voltage is used to generate a clock signal over a plurality of slow charging cycles.

10. The apparatus according to claim 5, A device in which the control logic unit is configured to control the output voltage with respect to clock dithering, and the output voltage is used to generate a clock having frequency triangular dithering within a certain frequency range.

11. It is a method, To provide a first bias current via a first current source, Providing a second bias current via a second current source, wherein the first bias current is greater than the second bias current. The current switch receives the first bias current and the second bias current at its two input terminals, The present invention provides an output current at the output terminal of the current switch, wherein the output current is one of the first bias current and the second bias current, which are selected by a current switch control signal to the current switch. The capacitor coupled between the output terminal and the ground terminal is charged by the output current, The output terminal provides an output voltage, Methods that include...

12. A method according to claim 11, further comprising discharging the capacitor via a discharge switch coupled between the output terminal and the ground terminal, wherein the discharge switch is controlled by a discharge signal.

13. A method according to claim 12, The voltage comparator receives the output voltage and the reference voltage as two inputs, A comparison output signal is provided based on a comparison between the output voltage and the reference voltage. Methods that further include the above.

14. The method according to claim 13, The comparison output signal and the current switch control signal are received as inputs to the reset latch, Based on the comparison output signal and the current switch control signal, a latch output signal is generated for a certain period of time. Methods that further include the above.

15. The method according to claim 14, The comparison output signal and the latch output signal are received as inputs to the control logic, In order to select one of the first bias current and the second bias current as the output current from the current switch, a current switch control signal is generated for the current switch, Methods that further include the above.

16. A method according to claim 15, further comprising generating the discharge signal to the discharge switch in order to reset or maintain the output voltage at the output terminal.

17. A method according to claim 15, further comprising controlling the output voltage for the system enable phase of the device by selecting the first bias current to charge the capacitor via the current switch control signal.

18. A method according to claim 15, further comprising controlling the output voltage for the soft-start phase of the device by selecting the second bias current to charge the capacitor via the current switch control signal.

19. A method according to claim 15, further comprising controlling the output voltage with respect to the hiccup phase of the device, wherein the output voltage is used to generate a clock signal over a plurality of slow charging cycles.

20. A method according to claim 15, further comprising controlling the output voltage for clock dithering, wherein the output voltage is used to generate triangular clock dithering having a frequency within a certain frequency range.

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