Imaging device

Abstract

It provides technology suitable for reducing noise. [Solution] The pixel substrate Q1, the specific peripheral substrate, and the photoelectric conversion unit 10 are stacked in the stacking direction Ds. The specific peripheral transistor includes a specific peripheral gate electrode. The specific peripheral gate electrode is a metal gate electrode. The specific peripheral gate electrode is located between the photoelectric conversion unit and the charge storage unit with respect to the stacking direction, and overlaps with the charge storage unit Z when viewed from the stacking direction Ds. The specific peripheral substrate is, for example, the first peripheral substrate Q2 or the second peripheral substrate Q3. The specific peripheral transistor is, for example, the first peripheral transistor Tr2 or the second peripheral transistor Tr3.

Claims

1. A photoelectric conversion unit comprising at least one lower electrode, an upper electrode, and a photoelectric conversion layer located between the at least one lower electrode and the upper electrode, which generates an electric charge by photoelectric conversion, The charge storage unit that stores the aforementioned charge, A pixel region including a pixel substrate and at least one pixel transistor provided on the pixel substrate, A specific peripheral substrate portion and a specific peripheral region including at least one specific peripheral transistor provided on the specific peripheral substrate portion, A laminated structure is formed in which the pixel substrate, the specific peripheral substrate, and the photoelectric conversion unit are stacked in the stacking direction. The at least one specified peripheral transistor includes a specified peripheral gate electrode, The aforementioned specific peripheral gate electrode is a metal gate electrode, The specified peripheral gate electrode is located between the photoelectric conversion unit and the charge storage unit with respect to the stacking direction, and overlaps with the charge storage unit when viewed from the stacking direction. Imaging device.

2. A substrate including the aforementioned pixel substrate portion, A substrate including the aforementioned specific peripheral substrate portion, A specific insulating film is provided, In the aforementioned stacked structure, the substrate including the pixel substrate portion, the specific insulating film, and the substrate including the specific peripheral substrate portion are stacked in this order in the stacking direction. Viewed from the stacking direction, the specific insulating film is located in an area of ​​50% or more of the substrate, including the pixel substrate portion. The imaging apparatus according to claim 1.

3. The specified peripheral gate electrode is located between the specified peripheral substrate portion and the photoelectric conversion portion with respect to the stacking direction. The imaging apparatus according to claim 1.

4. The charge storage unit is provided on the pixel substrate, In the aforementioned stacked structure, the pixel substrate portion, the specific peripheral substrate portion, and the photoelectric conversion portion are stacked in this order in the stacking direction. The imaging apparatus according to claim 1.

5. The at least one lower electrode includes two electrodes adjacent to each other, The aforementioned at least one specific peripheral transistor includes at least one predetermined transistor, Viewed from the stacking direction, the specific peripheral gate electrode of the at least one predetermined transistor overlaps with the position between the two electrodes. The imaging apparatus according to claim 1.

6. The aforementioned specific peripheral gate electrode includes at least one selected from the group consisting of titanium nitride, tantalum nitride, and tungsten. The imaging apparatus according to claim 1.

7. It includes a specific electrical path that passes through the specific peripheral substrate portion and electrically connects the photoelectric conversion portion and the charge storage portion, The imaging apparatus according to claim 1.

8. The thickness of the photoelectric conversion layer is less than or equal to the thickness of the pixel substrate. The imaging apparatus according to claim 1.

9. The aforementioned laminated structure includes an electrical path that electrically connects two substrates stacked on top of each other. The imaging apparatus according to claim 1.

10. The aforementioned specific peripheral substrate portion includes a support substrate, The aforementioned at least one specific peripheral transistor includes a source, a drain, and an oxide film. With respect to the aforementioned stacking direction, the oxide film is located between the combination of the source and the drain and the support substrate. The imaging apparatus according to claim 1.

11. The at least one specific peripheral transistor includes a source of a risen structure and a drain of a risen structure, The imaging apparatus according to claim 1.

12. The aforementioned at least one specific peripheral transistor includes a back gate electrode, Viewed from the aforementioned stacking direction, the back gate electrode overlaps with the charge storage portion. The imaging apparatus according to claim 1.

13. The aforementioned at least one specific peripheral transistor is a plurality of specific peripheral transistors. The imaging apparatus according to claim 1.

14. The aforementioned specific peripheral region comprises j × k unit structures that constitute a j x k array within a single pixel when viewed from the stacking direction, j is a natural number greater than or equal to 2, k is a natural number greater than or equal to 2, Each of the j × k unit structures comprises one or more transistors including a metal gate electrode. The one or more transistors in at least one of the j × k unit structures include the at least one specific peripheral transistor. The imaging apparatus according to claim 1.

15. A first peripheral region including a first peripheral substrate portion and at least one first peripheral transistor provided on the first peripheral substrate portion, The device comprises a second peripheral substrate portion and a second peripheral region including at least one second peripheral transistor provided on the second peripheral substrate portion, (A) The first peripheral substrate portion, the at least one first peripheral transistor, and the first peripheral region are, respectively, the specific peripheral substrate portion, the at least one specific peripheral transistor, and the specific peripheral region, or (B) The second peripheral substrate portion, the at least one second peripheral transistor, and the second peripheral region are, respectively, the specific peripheral substrate portion, the at least one specific peripheral transistor, and the specific peripheral region. The gate length of the at least one second peripheral transistor is smaller than the gate length of the at least one pixel transistor. The gate length of the at least one first peripheral transistor is smaller than the gate length of the at least one second peripheral transistor. The imaging apparatus according to claim 1.

16. In the aforementioned stacked structure, the pixel substrate, the second peripheral substrate, the first peripheral substrate, and the photoelectric conversion section are stacked in this order in the stacking direction. The imaging apparatus according to claim 15.

17. The first peripheral substrate portion and the second peripheral substrate portion are included in a single peripheral substrate. The imaging apparatus according to claim 15.

18. (B) The second peripheral substrate portion, the at least one second peripheral transistor, and the second peripheral region are, respectively, the specific peripheral substrate portion, the at least one specific peripheral transistor, and the specific peripheral region. The at least one first peripheral transistor is a plurality of first peripheral transistors, The at least one second peripheral transistor is a plurality of second peripheral transistors, Viewed from the stacking direction, one of the first peripheral region and the second peripheral region is located outside the other of the first peripheral region and the second peripheral region. Viewed from the stacking direction, the charge storage portion overlaps with the second peripheral region. The imaging apparatus according to claim 17.

19. The at least one first peripheral transistor includes a first peripheral terminal, The at least one second peripheral transistor includes a second peripheral gate electrode, (a) The first peripheral substrate portion, the at least one first peripheral transistor, the first peripheral region, and the first peripheral gate electrode are, respectively, the specific peripheral substrate portion, the at least one specific peripheral transistor, the specific peripheral region, and the specific peripheral gate electrode. The second peripheral gate electrode is a metal gate electrode. The second peripheral gate electrode is located between the photoelectric conversion unit and the charge storage unit with respect to the stacking direction, and overlaps with the charge storage unit when viewed from the stacking direction. The imaging apparatus according to claim 15.

20. Viewed from the stacking direction, at least a portion of the first peripheral gate electrode and at least a portion of the second peripheral gate electrode are in different positions from each other. The imaging device according to claim 19.

Images