Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device capable of reducing resistance between a semiconductor layer and wiring, and a method for manufacturing the same. [Solution] According to one embodiment, the semiconductor device comprises a substrate and a laminated film provided on the substrate and spaced apart from each other in a first direction perpendicular to the surface of the substrate. The device further comprises a first semiconductor layer provided between first and second insulating films included in the plurality of insulating films and extending in a second direction perpendicular to the first direction, and a second semiconductor layer provided on the side surface of the first semiconductor layer between the first and second insulating films. The device further comprises a first metal layer provided on the side surface of the second semiconductor layer between the first and second insulating films. The device further comprises a first wiring provided on the side surface of the first metal layer between the first and second insulating films and in contact with the upper surface of the first insulating film and the lower surface of the second insulating film, and a second wiring extending in the second direction, electrically connected to the first wiring, and corresponding to a bit line.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A three-dimensional semiconductor memory including an LBI (local block wiring) between a channel semiconductor layer and a bit line is known. In this case, an impurity semiconductor layer is provided between the channel semiconductor layer and the LBI. However, when a natural oxide film is formed on the surface of the impurity semiconductor layer, there is a problem that the contact resistance between the impurity semiconductor layer and the LBI increases.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provide a semiconductor device and a method for manufacturing the same capable of reducing the resistance between a semiconductor layer and a wiring.

Means for Solving the Problems

[0005] According to one embodiment, the semiconductor device comprises a substrate and a laminated film provided on the substrate and comprising a plurality of insulating films spaced apart from each other in a first direction perpendicular to the surface of the substrate. The device further comprises a first semiconductor layer provided between first and second insulating films included in the plurality of insulating films, extending in a second direction perpendicular to the first direction, and corresponding to a channel semiconductor layer, and a second semiconductor layer provided on the side surface of the first semiconductor layer between the first and second insulating films, and having a different composition from the first semiconductor layer. The device further comprises a first metal layer provided on the side surface of the second semiconductor layer between the first and second insulating films. The device further comprises a first wiring provided on the side surface of the first metal layer between the first and second insulating films, in contact with the upper surface of the first insulating film and the lower surface of the second insulating film, and a second wiring extending in the second direction, electrically connected to the first wiring, and corresponding to a bit line. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic plan view showing the structure of the semiconductor device of the first embodiment. [Figure 2] This is a plan view showing the structure of the first embodiment of the semiconductor device. [Figure 3] This is another plan view showing the structure of the semiconductor device of the first embodiment. [Figure 4] This is a perspective view showing the structure of the semiconductor device of the first embodiment. [Figure 5] This is another plan view showing the structure of the semiconductor device of the first embodiment. [Figure 6] This is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 7] This is another cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 8] This is a cross-sectional view (1 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] This is a plan view (2 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] This is a cross-sectional view (3 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] This is a cross-sectional view (4 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] This is a plan view (5 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] This is a cross-sectional view (6 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] This is a cross-sectional view (7 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] This is a plan view (8 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] This is a cross-sectional view (9 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 17] This is a cross-sectional view (10 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 18] This is a plan view (11 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 19] This is a cross-sectional view (12 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 20] This is a cross-sectional view (13 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 21] This is a cross-sectional view (14 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 22] This is a cross-sectional view (15 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 23] This is a plan view (16 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 24] This is a plan view (17 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 25] This is a plan view (18 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 26] This is a plan view (19 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 27] This is a plan view (20 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 28] This is a cross-sectional view (21 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 29] This is a cross-sectional view (22 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 30] This is a cross-sectional view (23 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 31] This is a cross-sectional view (24 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 32] This is a cross-sectional view (25 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 33] This is a cross-sectional view (26 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 34] This is a cross-sectional view (27 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 35] This is a cross-sectional view (28 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 36] This is a cross-sectional view (29 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 37] This is a cross-sectional view (30 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 38] This is a cross-sectional view (31 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 39] This is a cross-sectional view (32 / 32) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 40] This is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 41] This is a cross-sectional view showing the structure of a semiconductor device of a comparative example of the first embodiment. [Figure 42] This is a cross-sectional view (1 / 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 43] This is a cross-sectional view (2 / 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 44] This is a cross-sectional view (3 / 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 45] This is a cross-sectional view (4 / 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 46] This is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment. [Figure 47] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 48] This is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment. [Figure 49] This is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to the third embodiment. [Figure 50] This is a cross-sectional view (2 / 2) showing a method for manufacturing a semiconductor device according to the third embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will now be described with reference to the drawings. In Figures 1 to 50, identical components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0008] (First Embodiment) 1) Structure of the semiconductor device of the first embodiment Figure 1 is a schematic plan view showing the structure of a semiconductor device according to the first embodiment. The semiconductor device of this embodiment is, for example, a three-dimensional semiconductor memory.

[0009] Figure 1 shows the X, Y, and Z directions intersecting each other. The X and Y directions are parallel to the substrate surface (described later) and perpendicular to each other. The Z direction is perpendicular to the substrate surface (described later). The Z, Y, and X directions are examples of the first, second, and third directions, respectively.

[0010] The semiconductor device of this embodiment has multiple memory block regions R BLK And multiple hookup regions R HU and multiple bit line regions R BLIt includes a plurality of bit lines BL and a plurality of local block wirings LBI. Each local block wiring LBI is an example of a first wiring. Each bit line BL is an example of a second wiring.

[0011] Memory block region R BLK is arranged in a matrix along the X direction and the Y direction. The hook-up region R HU is arranged linearly along the X direction and is sandwiched between the memory block regions R BLK . Each hook-up region R HU corresponds to a plurality of memory block regions R HU arranged linearly in the ±Y direction of each hook-up region R. The bit line region R BLK extends in the Y direction and is sandwiched between the memory block regions R BL or between the hook-up regions R BLK . Each bit line region R HU corresponds to a plurality of memory block regions R BL arranged linearly in the Y direction adjacent to the +X direction of each bit line region R BL and a plurality of memory block regions R BLK arranged linearly in the Y direction adjacent to the -X direction of each bit line region R BL . BLK Each bit line BL extends in the Y direction and is arranged within the corresponding bit line region R

[0012] BL . Each local block wiring LBI extends in the X direction and is arranged between two memory block regions R BLK . Each local block wiring LBI is electrically connected to the two memory block regions R BLK and is also electrically connected to the corresponding bit line BL.Furthermore, each bit line BL is electrically connected to a peripheral circuit (not shown) via the corresponding hook-up region R HU . HU

[0013] Figure 2 is a plan view showing the structure of the semiconductor device of the first embodiment. Figure 3 is another plan view showing the structure of the semiconductor device of the first embodiment. Figure 4 is a perspective view showing the structure of the semiconductor device of the first embodiment.

[0014] Figure 2 shows an enlarged view of region A in Figure 1. Figure 3 shows an enlarged view of region B in Figure 2. Figure 4 is a perspective view corresponding to the plan view in Figure 3. Figure 2 shows two memory block regions R. BLK and one bit line region R BL Figures 3 and 4 show a single memory block region R BLK and one bit line region R BL This indicates that.

[0015] In Figure 2, each memory block region R BLK This refers to two adjacent memory cell regions R in the Y direction. MC And the two memory cell regions R MC A single ladder region R is provided between them. LD This includes the following. Figure 2 further shows each memory block region R BLK Select transistor region R provided in the +Y direction SGD And the selected transistor region R SGD Local block wiring area R provided in the +Y direction LBI This indicates that each local block wiring area R LBI It extends in the X direction and includes the local block wiring LBI described above. Each local block wiring region R in this embodiment LBI This refers to two adjacent memory block regions R in the Y direction. BLK It is located between them.

[0016] As shown in Figure 4, the semiconductor device of this embodiment comprises a substrate Sub and a laminated film 100 formed on top of the substrate Sub.

[0017] The substrate Sub is a semiconductor substrate, such as a silicon (Si) substrate. The substrate Sub may also be a Si substrate containing P-type impurities such as boron (B). In Figure 4, the X and Y directions are parallel to the surface of the substrate Sub, and the Z direction is perpendicular to the surface of the substrate Sub.

[0018] The laminated film 100 includes a plurality of insulating films 101 and a plurality of memory layers ML that are alternately stacked in the Z direction. The plurality of insulating films 101 are spaced apart from each other in the Z direction. Each insulating film 101 is, for example, an SiO2 film (silicon oxide film). Two insulating films 101 adjacent to each other within the plurality of insulating films 101 are examples of first and second insulating films.

[0019] Each memory layer ML includes multiple semiconductor layers 110. These multiple semiconductor layers 110 are adjacent to each other in the X direction and extend in the Y direction. In Figure 2, each semiconductor layer 110 comprises multiple memory cell regions R MC , ladder region R LD , and the selected transistor region R SGD It extends through the interior. Each semiconductor layer 110 functions as a channel region for multiple memory transistors (memory cells) and multiple selection transistors (selection gates). These multiple memory transistors and selection transistors are electrically connected in series and are called a memory string. Each semiconductor layer 110 is, for example, a polysilicon layer. This polysilicon layer is, for example, an undoped polysilicon layer. Each semiconductor layer 110 is an example of a first semiconductor layer.

[0020] Each memory cell region R MCThe laminate 100 includes a plurality of electrode layers 120 that extend in the Z direction so as to penetrate the laminate 100. In Figure 3, the plurality of electrode layers 120 are aligned in the Y direction between two semiconductor layers 110 that are adjacent to each other in the X direction. In Figure 3, an insulating film 123 is further formed between two electrode layers 120 that are adjacent to each other in the Y direction. The insulating film 123 extends in the Z direction within the laminate 100, similar to the electrode layers 120. Each electrode layer 120 includes an electrode material layer 122 having a columnar shape that extends in the Z direction and a barrier metal layer 121 having a tubular shape that extends in the Z direction around the electrode material layer 122. The barrier metal layer 121 is, for example, a TiN film (titanium nitride film). The electrode material layer 122 is, for example, a W (tungsten) layer. The insulating film 123 is, for example, an SiO2 film. Each electrode layer 120 functions as a gate electrode or word line of a plurality of memory transistors.

[0021] Each memory cell region R MC The memory insulating film further includes a plurality of memory insulating films 130 extending in the Z direction so as to penetrate the laminated film 100. Each memory insulating film 130 includes a block insulating film 133, a plurality of charge storage layers 132, and a plurality of tunnel insulating films 131. The block insulating film 133 has a tubular shape extending in the Z direction around the corresponding electrode layer 120. Each charge storage layer 132 is formed within one memory layer ML on the +X or -X side of the block insulating film 133. Each tunnel insulating film 131 is formed within one memory layer ML on the +X or -X side of the block insulating film 133 via the charge storage layer 132. Each tunnel insulating film 131 is further in contact with the side of the corresponding semiconductor layer 110. Each tunnel insulating film 131 is, for example, an SiO2 film. Each charge storage layer 132 is, for example, a polysilicon layer or a SiN film (silicon nitride film). The polysilicon layer is, for example, an undoped, P-type, or N-type polysilicon layer. The block insulating film 133 is, for example, an SiO2 film and / or a metal oxide film. The metal oxide film is, for example, an aluminum oxide film or a hafnium oxide film. Each charge storage layer 132 is capable of storing charge in a three-dimensional semiconductor memory.

[0022] Each ladder region R LDor each selected transistor region R SGD The laminated film 100 includes a plurality of contact plugs 140 extending in the Z direction. In Figure 3, each contact plug 140 is positioned between two semiconductor layers 110 adjacent to each other in the X direction. Each contact plug 140 is used to form a hole channel within the semiconductor layer 110 or to supply voltage to the hole channel formed within the semiconductor layer 110. Each contact plug 140 includes a metal layer 142 having a columnar shape extending in the Z direction, a semiconductor layer 141 having a tubular shape extending in the Z direction around the metal layer 142, and a semiconductor layer 143 having a tubular shape extending in the Z direction around the semiconductor layer 141. The metal layer 142 is, for example, a TiN film. The semiconductor layer 141 is, for example, a P-type polysilicon layer. The semiconductor layer 143 is, for example, an undoped polysilicon layer. Each contact plug 140 may not include a semiconductor layer 143. Each contact plug 140 is positioned between two insulating films 123 that are adjacent to each other in the Y direction.

[0023] Each ladder region R LD or each selected transistor region R SGD The laminated film 100 further includes a plurality of electrode layers 150 extending in the Z direction. In Figure 3, each electrode layer 150 is provided between two semiconductor layers 110 adjacent to each other in the X direction. Each electrode layer 150 functions as a gate electrode or gate wiring of a transistor. Each electrode layer 150 includes a metal layer 152 having a tubular shape extending in the Z direction around an insulating film 154, and a semiconductor layer 151 having a tubular shape extending in the Z direction around the metal layer 152. The insulating film 154 has a columnar shape extending in the Z direction. The sides of the semiconductor layer 151 are covered with an insulating film 153. The insulating film 153 has a tubular shape extending in the Z direction around the semiconductor layer 151. The insulating film 154 is, for example, an SiO2 film. The metal layer 152 is, for example, a TiN film. The semiconductor layer 151 is, for example, an N-type polysilicon layer. The insulating film 153 is, for example, an SiO2 film. Each electrode layer 150 is provided between two insulating films 123 that are adjacent to each other in the Y direction.

[0024] Each selected transistor region RSGD Within this, each memory layer ML includes a plurality of semiconductor layers 160 and a plurality of metal layers 162. Each semiconductor layer 160 is formed on the side surface of the corresponding semiconductor layer 110. Each semiconductor layer 160 is, for example, an impurity semiconductor layer, and more specifically, a polysilicon layer containing N-type impurities such as P (phosphorus). Each metal layer 162 is formed on the side surface of the corresponding semiconductor layer 160. Each metal layer 162 is, for example, a W (tungsten) layer, a Mo (molybdenum) layer, a Tc (technetium) layer, a Ru (ruthenium) layer, a Rh (rhodium) layer, a Re (rhenium) layer, an Os (osmium) layer, an Ir (iridium) layer, or a Pt (platinum) layer. Each semiconductor layer 160 is an example of a second semiconductor layer, and each metal layer 162 is an example of a first metal layer. Each selected transistor region R SGD The film further includes a plurality of insulating films 161. Each insulating film 161 extends in the Z direction within the laminated film 100 and is formed between two semiconductor layers 160 adjacent to each other in the X direction. Each insulating film 161 is, for example, an SiO2 film.

[0025] Each local block wiring area R LBI Within this, each memory layer ML includes a wiring layer 170. The wiring layer 170 is formed on the sides of a plurality of metal layers 162 and is electrically connected to a plurality of semiconductor layers 160 and a plurality of semiconductor layers 110 via the plurality of metal layers 162. The wiring layer 170 extends in the X direction and functions as a local block wiring LBI. The wiring layer 170 is, for example, a conductive metal layer. The wiring layer 170 (local block wiring LBI) is an example of the first wiring as described above. Each local block wiring region R LBI It further includes a plurality of insulating films 171 aligned in the X direction. Each insulating film 171 extends in the Z direction within the laminated film 100 and penetrates a plurality of wiring layers 170. Each insulating film 171 is, for example, an SiO2 film.

[0026] Each bit line region R BLWithin this, each memory layer ML includes a wiring layer 180. The wiring layer 180 is electrically connected to the wiring layer 170. The wiring layer 180 extends in the Y direction and functions as a bit line BL. The wiring layer 180 is, for example, a conductive metal layer. The wiring layers 170 and 180 may be formed by processing the same wiring material or by processing different wiring materials. That is, the wiring layers 170 and 180 may be different parts of the same layer or different layers. The wiring layer 180 (bit line BL) is an example of a second wiring, as described above. Each bit line region R BL It further includes a plurality of insulating films 181 and a plurality of insulating films 182 arranged alternately in the Y direction. The insulating films 181, 182 extend in the Z direction within the laminated film 100. Each insulating film 181 is, for example, an SiO2 film. Each insulating film 182 is, for example, an SiO2 film. Bit line region R in Figure 2 BL Inside, insulating films 181 and 182 are placed between two adjacent wiring layers 180 (bit lines BL) in the X direction.

[0027] Figure 5 is another plan view showing the structure of the semiconductor device of the first embodiment. Figure 6 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. Figure 7 is another cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0028] Figure 5 shows an enlarged view of region C in Figure 1. Figure 6 is a cross-sectional view of the XZ section along the line D-D' shown in Figure 5, viewed in the direction of the arrow. Figure 7 is a cross-sectional view of the YZ section along the line E-E' shown in Figure 5, viewed in the direction of the arrow.

[0029] Each hookup region R of this embodiment HU This consists of multiple leader line regions R arranged alternately in the X direction. LL and multiple contact electrode regions R CC This includes. Figure 5 shows two leader line regions R adjacent to each other in the X direction. LL And the two leader line regions R LL Contact electrode region R provided between CC This indicates that.

[0030] The laminated film 100 includes a plurality of insulating films 101 and a plurality of insulating films 102 that are alternately stacked in the Z direction, as shown in Figures 6 and 7. Each insulating film 102 is part of any one of the memory layers ML within the laminated film 100. Each insulating film 102 is, for example, a SiN film.

[0031] Each leader area R LL Within the memory, each memory layer ML includes a plurality of wiring layers 190 extending in the Y direction. Each wiring layer 190 is, for example, a conductive metal layer. Each wiring layer 190 is electrically connected to a corresponding wiring layer 180, which in turn is electrically connected to a corresponding wiring layer 170.

[0032] Each leader area R LL It further includes a plurality of insulating films 191 extending in the Z direction within the laminated film 100. Each leader line region R LL Within the structure, the multiple insulating films 191 are adjacent to each other in the Y direction and penetrate the multiple wiring layers 190. Each insulating film 191 is, for example, an SiO2 film.

[0033] Each contact electrode area R CC The laminated film 100 includes a plurality of contact electrodes CC provided within it. Each contact electrode CC includes a cylindrical portion 192 and a disc-shaped portion 193 provided below portion 192. Portion 192 penetrates one or more insulating films 101, and the sides of portion 192 are covered with insulating film 196. Portion 193 is provided within any one memory layer ML in the laminated film 100 and is electrically connected to one wiring layer 190 in the memory layer ML. Portion 192 includes an electrode material layer 195 extending in the Z direction and a barrier metal layer 194 extending in the Z direction around the electrode material layer 195. Portion 193 is, for example, a TiN film. The barrier metal layer 194 is, for example, a TiN film. The electrode material layer 195 is, for example, a W (tungsten) layer. The insulating film 196 is, for example, an SiO2 film.

[0034] 2) Method for manufacturing a semiconductor device according to the first embodiment Figures 8 to 39 are cross-sectional and plan views showing the manufacturing method of the semiconductor device according to the first embodiment. The cross-sectional views in Figure 8, etc., correspond to the cross-sectional view at the position of one XZ cross-section that cuts the laminated film 100 shown in Figure 4. The plan views in Figure 9, etc., correspond to the plan view in Figure 3. The cross-sectional views in Figures 30 to 39 correspond to the cross-sectional views in Figures 6 and 7.

[0035] First, a laminated film 100 is formed on top of the aforementioned substrate Sub (not shown) (Figure 8). The laminated film 100 is formed by alternately stacking multiple insulating films 101 and multiple insulating films 102 on top of the substrate Sub. The laminated film 100 shown in Figure 8 contains multiple insulating films 101 and multiple insulating films 102 alternately in the Z direction. These multiple insulating films 101 and multiple insulating films 102 are formed, for example, by CVD (Chemical Vapor Deposition).

[0036] Next, multiple recesses 123A are formed within the laminated film 100 by lithography and RIE (Reactive Ion Etching) (Figures 9 and 10). These multiple recesses 123A extend in the Y and Z directions and are adjacent to each other in the X or Y direction.

[0037] Next, multiple insulating films 123 and multiple insulating films 182 are formed within the multiple recesses 123A by CVD (Figure 11). The insulating film 123 is formed in each memory block region R BLK The insulating film 182 is formed within the recess 123A, and each bit line region R BL It is formed within the recess 123A.

[0038] Next, multiple recesses 120A, multiple contact holes 140A, and multiple recesses 161A are formed within the laminated film 100 and the multiple insulating films 123 by lithography and RIE (Figures 12 and 13). The recesses 120A, contact holes 140A, and recesses 161A penetrate the laminated film 100 in the Z direction. In the process shown in Figures 12 and 13, multiple recesses (not shown) are also formed in the regions corresponding to the multiple insulating films 191 mentioned above.

[0039] Next, multiple sacrificial layers 120B are formed in multiple recesses 120A by CVD (Figure 14). Next, multiple sacrificial layers 140B are formed in multiple contact holes 140A by CVD (Figures 15 and 16). Next, multiple sacrificial layers 161B are formed in multiple recesses 161A by CVD (Figures 15 and 16). In the process shown in Figures 15 and 16, multiple sacrificial layers (not shown) are also formed in the regions corresponding to the multiple insulating films 191 described above. The sacrificial layers 120B, 140B, and 161B may be formed simultaneously. This is also true for the sacrificial layers corresponding to the insulating films 191.

[0040] Next, multiple recesses 150A, 171A, and 181A are formed within the laminated film 100 by lithography and RIE (Figures 15 and 16). The recesses 150A, 171A, and 181A penetrate the laminated film 100 in the Z direction. Each recess 150A is formed between two adjacent insulating films 123 in the Y direction. Each recess 181A is formed within one insulating film 182 or between two adjacent insulating films 182 in the Y direction. Each local block wiring region R LBI Inside, multiple recesses 171A are formed so as to be aligned in the X direction.

[0041] Next, multiple sacrificial layers 181B are formed within multiple recesses 181A by CVD (Figure 17). Next, multiple sacrificial layers 150B are formed within multiple recesses 150A by CVD (Figures 18 and 19). Next, multiple sacrificial layers 171B are formed within multiple recesses 171A by CVD (Figures 18 and 19). Sacrificial layers 181B, 150B, and 171B may be formed simultaneously.

[0042] Next, multiple sacrificial layers 120B are removed from multiple recesses 120A by wet etching (Figures 18 and 19).

[0043] Next, multiple semiconductor layers 110 are formed within the laminated film 100 (Figure 20). Each semiconductor layer 110 is formed, for example, by replacing a portion of one insulating film 102 with a semiconductor layer 110. Specifically, portions of multiple insulating films 102 are removed by wet etching from multiple recesses 120A, thereby creating multiple cavities within the laminated film 100, and multiple semiconductor layers 110 are formed within these cavities by CVD. As a result, each semiconductor layer 110 is formed between two insulating films 101 adjacent to each other in the Z direction. Note that in the process shown in Figure 20, only a portion of each semiconductor layer 110 is formed, not the entirety of each semiconductor layer 110 as shown in Figure 3, etc.

[0044] Next, multiple tunnel insulating films 131 and multiple charge storage layers 132 are formed within the laminated film 100 (Figure 21). Between two insulating films 101 adjacent to each other in the Z direction, one tunnel insulating film 131 and one charge storage layer 132 are formed sequentially on one side surface of one semiconductor layer 110, from the semiconductor layer 110 toward the corresponding recess 120A. For example, a portion of the multiple semiconductor layers 110 is removed by wet etching from the multiple recesses 120A, thereby forming multiple cavities within the laminated film 100, and multiple tunnel insulating films 131 and multiple charge storage layers 132 are formed within these cavities by CVD. The tunnel insulating film 131 may be formed by oxidation of the semiconductor layer 110 instead of CVD.

[0045] Next, a block insulating film 133, a barrier metal layer 121, and an electrode material layer 122 are sequentially formed in each recess 120A by CVD (Figure 22).

[0046] Next, multiple sacrificial layers 140B are removed from multiple recesses 140A by wet etching (Figure 23).

[0047] Next, the remaining portions of each semiconductor layer 110 are formed within the laminated film 100 (Figure 24). The remaining portions of each semiconductor layer 110 are formed, for example, by replacing a portion of one insulating film 102 with a semiconductor layer 110, similar to the process in Figure 20. Specifically, portions of multiple insulating films 102 are removed by wet etching from multiple recesses 140A, thereby forming multiple cavities within the laminated film 100, and multiple semiconductor layers 110 are formed within these cavities by CVD. Each semiconductor layer 110 is formed between two insulating films 101 that are adjacent to each other in the Z direction.

[0048] Next, a semiconductor layer 143, a semiconductor layer 141, and a metal layer 142 are sequentially formed within each contact hole 140A by CVD (Figure 24). As a result, one contact plug 140 is formed within each contact hole 140A.

[0049] Next, multiple sacrificial layers 150B are removed from multiple recesses 150A by wet etching (Figure 24).

[0050] Next, by CVD, an insulating film 153, a semiconductor layer 151, a metal layer 152, and an insulating film 154 are sequentially formed within each recess 150A (Figure 25). As a result, an electrode layer 150 is formed within each recess 150A.

[0051] Next, multiple sacrificial layers 161B are removed from multiple recesses 161A by wet etching (Figure 25).

[0052] Next, multiple semiconductor layers 160 are formed within the laminated film 100 (Figure 26). Each semiconductor layer 160 is formed, for example, by replacing a portion of one insulating film 102 with a semiconductor layer 160. Specifically, portions of multiple insulating films 102 are removed by wet etching from multiple recesses 161A, thereby forming multiple cavities within the laminated film 100, and multiple semiconductor layers 160 are formed within these cavities by CVD. Between two insulating films 101 adjacent to each other in the Z direction, one semiconductor layer 160 is formed on the side surface of one semiconductor layer 110. Further details of the semiconductor layers 160 will be described later.

[0053] Next, insulating film 161 is formed in each recess 161A by CVD (Figure 26).

[0054] Next, multiple sacrificial layers 171B and multiple sacrificial layers 181B are removed from multiple recesses 171A and multiple recesses 181A, respectively, by wet etching (Figures 27 and 28). In the process shown in Figures 27 and 28, multiple sacrificial layers are also removed from the regions corresponding to the multiple insulating films 191 mentioned above.

[0055] Next, multiple metal layers 162 (not shown), multiple wiring layers 170 (not shown), multiple wiring layers 180, and multiple wiring layers 190 (not shown) are formed within the laminated film 100 (Figure 29). Each of the metal layers 162 and wiring layers 170, 180, and 190 is formed, for example, by replacing a portion of one insulating film 102 with the metal layer 162 and wiring layers 170, 180, and 190. Specifically, a portion of the multiple insulating films 102 is removed by wet etching from multiple recesses 171A and multiple recesses 181A, thereby forming multiple cavities within the laminated film 100, and the multiple metal layers 162, multiple wiring layers 170, multiple wiring layers 180, and multiple wiring layers 190 are formed within these cavities. Between two insulating films 101 adjacent to each other in the Z direction, one metal layer 162 is formed on the side surface of one semiconductor layer 160, one wiring layer 170 is formed on the sides of multiple metal layers 162, and one wiring layer 180 is formed so as to be electrically connected to the corresponding wiring layer 170. Further details of the metal layers 162, etc., will be described later. Subsequently, insulating films 171, 181, and 191 are formed in the recesses 171A, 181A, etc., by CVD. The wiring layer 190 and insulating film 191 are shown in Figure 30, which will be described later.

[0056] Next, multiple recessed CCAs are formed within the multilayer film 100 by lithography and RIE (Figures 30 and 31). As a result, the upper surface of one of the insulating films 101 within the multilayer film 100 is exposed within each recessed CCA.

[0057] Next, wet etching is used to remove portions of the multiple insulating films 102 exposed on the sides of each recessed CCA (Figures 32 and 33).

[0058] Next, insulating film 196 is formed on the bottom and side surfaces of each recessed CCA by CVD (Figures 34 and 35).

[0059] Next, the insulating film 196 and insulating film 101 are removed from the bottom surface of each recessed CCA by RIE (Figures 36 and 37). As a result, the upper surface of one of the insulating films 102 within the laminated film 100 is exposed within each recessed CCA.

[0060] Next, a portion of the insulating film 102 exposed on the bottom surface of each recessed CCA is removed by wet etching (Figures 38 and 39). As a result, the side surface of the corresponding wiring layer 190 is exposed within each recessed CCA. Subsequently, a contact electrode CC is formed within each recessed CCA.

[0061] In this way, the semiconductor device of this embodiment is manufactured.

[0062] 3) Details of the semiconductor device of the first embodiment Figure 40 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. Figure 40 shows a YZ cross-section along the straight line L shown in Figures 3 and 4.

[0063] Figure 40 shows a laminated film 100 containing multiple insulating films 101 spaced apart from each other in the Z direction. Figure 40 illustrates two insulating films 101 within the laminated film 100. Hereinafter, the upper insulating film 101 of the two insulating films 101 will be referred to as the "upper insulating film 101," the lower insulating film 101 of the two insulating films 101 will be referred to as the "lower insulating film 101," and the two insulating films 101 together will be referred to as the "upper and lower insulating films 101." The lower insulating film 101 is an example of the first insulating film, and the upper insulating film 101 is an example of the second insulating film.

[0064] Figure 40 further shows semiconductor layers 110, 160, 162, and 170, which are located between the upper and lower insulating films 101. The semiconductor layers 110, 160, 162, and 170 shown in Figure 40 are contained within one memory layer ML (Figure 4) in the multilayer film 100. Semiconductor layer 110 is an example of a first semiconductor layer. Semiconductor layer 160 is an example of a second semiconductor layer. 162 is an example of a first metal layer. 170 is an example of a first wiring.

[0065] The semiconductor layer 110 extends in the Y direction between the upper and lower insulating films 101. The semiconductor layer 110 is, for example, a polysilicon layer. In this embodiment, the semiconductor layer 110 is an undoped polysilicon layer. In this embodiment, the semiconductor layer 110 is a channel semiconductor layer and functions as a channel region of multiple memory cells.

[0066] The semiconductor layer 160 is formed on the side surface of the semiconductor layer 110. The semiconductor layer 110 is, for example, a polysilicon layer. In this embodiment, the semiconductor layer 160 is an impurity semiconductor layer, for example, an N-type polysilicon layer. The N-type impurity in the semiconductor layer 160 is, for example, P (phosphorus). The N-type impurity in the semiconductor layer 160 may also be As (arsenic). In this embodiment, since the semiconductor layer 110 is an undoped polysilicon layer and the semiconductor layer 160 is an impurity semiconductor layer, the semiconductor layer 160 has a different composition from the semiconductor layer 110.

[0067] The metal layer 162 is formed on the side surface of the semiconductor layer 160. The metal layer 162 in this embodiment has a plate-like shape that extends two-dimensionally in a planar or curved shape (see, for example, Figure 26). Specifically, the metal layer 162 in this embodiment extends in the Z direction and generally extends in the X direction (or in a direction inclined with respect to the X direction). The metal layer 162 is, for example, a W (tungsten) layer. The metal layer 162 may be formed of a metal element other than tungsten. In this case, the metal layer 162 may be, for example, a Mo (molybdenum) layer, a Tc (technetium) layer, a Ru (ruthenium) layer, a Rh (rhodium) layer, a Re (rhenium) layer, an Os (osmium) layer, an Ir (iridium) layer, or a Pt (platinum) layer. According to this embodiment, by forming the metal layer 162 on the side surface of the N-type semiconductor layer 160, it is possible to reduce the contact resistance between the semiconductor and the metal.

[0068] The wiring layer 170 is formed on the side surface of the semiconductor layer 160 and extends in the X direction between the upper and lower insulating films 101. The wiring layer 170, like the semiconductor layer 110, the semiconductor layer 160, and the metal layer 162, is in contact with the lower surface of the upper insulating film 101 and the upper surface of the lower insulating film 101. The wiring layer 170 functions as a local block wiring LBI that electrically connects the semiconductor layer 110 (channel region) and the aforementioned wiring layer 180 (bit line BL). The wiring layer 180 is provided between the upper and lower insulating films 101 and extends in the Y direction. The wiring layer 180 is an example of a second wiring. Note that the wiring layer 170 (local block wiring LBI) shown in Figure 40 is electrically connected to the wiring layer 180 (bit line) provided between the upper and lower insulating films 101, but it may also be electrically connected to the wiring layer 180 (bit line) provided between other insulating films 101.

[0069] The wiring layer 170 includes a barrier metal layer 172 and a wiring material layer 173. The barrier metal layer 172 is an example of a first layer. The wiring material layer 173 is an example of a second layer.

[0070] The barrier metal layer 172 is formed on the side surface of the metal layer 162, the lower surface of the upper insulating film 101, and the upper surface of the lower insulating film 101. The barrier metal layer 172 is, for example, a TiN film (titanium nitride film). The wiring material layer 173 is formed on the side surface, upper surface, and lower surface of the barrier metal layer 172. In this embodiment, the side surface of the metal layer 162, the lower surface of the upper insulating film 101, and the upper surface of the lower insulating film 101 are in contact with the barrier metal layer 172, but not with the wiring material layer 173.

[0071] Figure 40 further shows an insulating film 171 provided on the side surface of the laminated film 100. In Figure 40, a portion of the insulating film 171 is formed between the upper and lower insulating films 101. As a result, the insulating film 171 is formed on the side surface of the wiring layer 170, the side and bottom surface of the upper insulating film 101, and the side and top surface of the lower insulating film 101.

[0072] Figure 41 is a cross-sectional view showing the structure of a comparative example of the first embodiment.

[0073] The semiconductor device of this comparative example (Figure 41) has the same structure as the semiconductor device of the first embodiment (Figure 40). However, the semiconductor device of this comparative example includes a native oxide film 163 instead of a metal layer 162.

[0074] The native oxide film 163 is an oxide film formed when a portion of the semiconductor layer 160 is oxidized by natural oxidation from the side surface of the semiconductor layer 160. The native oxide film 163 is, for example, an SiO2 film. The native oxide film 163 in this comparative example has a plate-like shape that extends two-dimensionally in a planar or curved manner, similar to the metal layer 162 in the first embodiment.

[0075] The semiconductor layer 160 in this comparative example is formed as follows. First, the semiconductor layer 160 is formed on the side surface of the semiconductor layer 110 by CVD in the chamber of the CVD apparatus. At this time, the semiconductor layer 160 is formed not only between the upper and lower insulating films 101, but also on the side surface of the laminated film 100. Next, the semiconductor layer 160 is removed from the side surface of the laminated film 100 and other areas by wet etching outside the chamber. As a result, the semiconductor layer 160 is processed into the shape shown in Figure 41.

[0076] In this comparative example, the substrate Sub (Figure 4) is removed from the chamber during the process of forming the semiconductor layer 160. As a result, after wet etching outside the chamber, a native oxide film 163 is formed on the side surface of the semiconductor layer 160, as shown in Figure 41. Therefore, the resistance between the semiconductor layer 160 and the wiring layer 170 increases due to the native oxide film 163.

[0077] On the other hand, in this embodiment, a metal layer 162 is formed between the semiconductor layer 160 and the wiring layer 170 instead of the native oxide film 163. This makes it possible to lower the resistance between the semiconductor layer 160 and the wiring layer 170. A method for realizing such a structure will be described later.

[0078] Figures 42 to 45 are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment.

[0079] Figure 42(a) shows the semiconductor layer 110 formed between the upper and lower insulating films 101, the recess H2 provided between the upper and lower insulating films 101, and the recess H1 provided on the side surface of the laminated film 100. The state shown in Figure 42(a) corresponds to the state shown in Figure 25.

[0080] The recesses H1 and H2 are more specifically filled with insulating film 102, etc. However, for the sake of clarity, the illustration of insulating film 102, etc. is omitted in Figure 42(a), etc. As will be described later, before forming the semiconductor layer 160, metal layer 162, wiring layer 170, insulating film 171, etc. in the recesses H1 and H2, the insulating film 102, etc. is removed from the recesses H1 and H2 (see Figures 26 to 29).

[0081] Next, a semiconductor layer 160 is formed on the side surface of the semiconductor layer 110 (Figure 42(b)). As a result, the semiconductor layer 160 is formed not only between the upper and lower insulating films 101, but also on the side surface of the laminated film 100. That is, the semiconductor layer 160 is formed not only in the recess H2, but also in the recess H1. In this embodiment, the semiconductor layer 160 is formed by CVD in the chamber of the CVD apparatus.

[0082] Next, the semiconductor layer 160 is removed from the side surface of the laminated film 100 (Figure 43(a)). As a result, the semiconductor layer 160 in the recess H1 is removed, and furthermore, a portion of the semiconductor layer 160 in the recess H2 is removed. In this embodiment, the removal of the semiconductor layer 160 is performed by wet etching outside the chamber.

[0083] Therefore, after wet etching outside the chamber, a native oxide film 163 is formed on the side surface of the semiconductor layer 160 (Figure 43(a)). The native oxide film 163 in this embodiment is an oxide film formed when a part of the semiconductor layer 160 is oxidized by natural oxidation from the side surface of the semiconductor layer 160, similar to the comparative example above. The native oxide film 163 is, for example, an SiO2 film. The native oxide film 163 has a plate-like shape that extends two-dimensionally in a planar or curved shape.

[0084] Next, a conversion process is performed to convert a portion of the semiconductor layer 160 from its side surface to the metal layer 162 (Figure 43(b)). As a result, the metal layer 162 is formed on the side surface of the semiconductor layer 160 between the semiconductor layer 160 and the native oxide film 162 within the recess H2.

[0085] During the conversion process, the reaction shown in the following chemical formula (1) occurs.

[0086] 2WF6+3Si→2W+3SiF4···(1) However, W, F, and Si represent tungsten, fluorine, and silicon, respectively. The left side of chemical formula (1) shows that the conversion gas WF6 reacts with Si atoms in the semiconductor layer 160. The right side of chemical formula (1) shows that a portion of the semiconductor layer 160 (Si layer) is converted into the metal layer 162 (W layer), generating SiF4 gas.

[0087] Next, the native oxide film 163 is removed by wet etching (Figure 44(a)). As a result, the native oxide film 163 is removed from the side surface of the metal layer 162. The native oxidation of the semiconductor layer 160 after wet etching is suppressed because the side surface of the semiconductor layer 160 is covered by the metal layer 162. Alternatively, this wet etching can be omitted, leaving the native oxide film 163 on the side surface of the metal layer 162. This is because the native oxide film 163 will remain between the metal (metal layer 162) and the metal (wiring layer 170), rather than between the semiconductor and the metal.

[0088] Next, a barrier metal layer 172 and a wiring material layer 173 are formed sequentially within the recesses H1 and H2 (Figure 44(b)). As a result, the barrier metal layer 172 is formed on the side surface of the metal layer 162, the lower and side surfaces of the upper insulating film 101, and the upper and side surfaces of the lower insulating film 101, while the wiring material layer 173 is formed on the side surface, upper surface, and lower surface of the barrier metal layer 172.

[0089] Next, the barrier metal layer 172 and the wiring material layer 173 are removed from the sides of the laminated film 100 (Figure 45(a)). As a result, the barrier metal layer 172 and the wiring material layer 173 in the recess H1 are removed, and furthermore, some of the barrier metal layer 172 and the wiring material layer 173 in the recess H2 are removed. In this way, the wiring layer 170 shown in Figure 40 is formed. In Figure 40, the wiring layer 170 is in contact with the side of the metal layer 162, the lower surface of the upper insulating film 101, and the upper surface of the lower insulating film 101. The above-mentioned wiring layer 180 may be formed at the same time as the wiring layer 170, or it may be formed sequentially with the wiring layer 170.

[0090] Next, an insulating film 171 is formed in the recesses H1 and H2 (Figure 45(b)). In this way, the semiconductor device of this embodiment is manufactured.

[0091] In this embodiment, the metal layer 162 is formed by converting a portion of the semiconductor layer 160 into a metal layer 162 using WF6 gas, as shown in chemical formula (1). Therefore, the metal layer 162 may contain W atoms and F atoms. For example, the metal layer 162 may be a W layer containing F atoms as impurity atoms.

[0092] As described above, the semiconductor device of this embodiment includes a metal layer 162 between the semiconductor layer 160 and the wiring layer 170 (Figure 40). Therefore, according to this embodiment, it is possible to reduce the resistance between the semiconductor layer 160 and the wiring layer 170.

[0093] (Second Embodiment) Figure 46 is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment.

[0094] The semiconductor device of this embodiment (Figure 46) has a structure similar to that of the semiconductor device of the first embodiment (Figure 40). However, the metal layer 162 of this embodiment is formed in a different way than the metal layer 162 of the first embodiment. As a result, the thickness of the metal layer 162 of this embodiment is different from that of the metal layer 162 of the first embodiment. For example, the thickness of the metal layer 162 in the Y direction shown in Figure 46 is thicker than the thickness of the metal layer 162 in the Y direction shown in Figure 40. However, the thickness of the metal layer 162 of this embodiment may be the same as that of the metal layer 162 of the first embodiment, or it may be thinner than the metal layer 162 of the first embodiment.

[0095] Figure 47 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a second embodiment.

[0096] First, the steps shown in Figures 42(a) to 43(a) are performed. As a result, the structure shown in Figure 47(a) is formed. The state shown in Figure 47(a) corresponds to the state shown in Figure 43(a).

[0097] Next, a conversion process is performed to convert all of the native oxide film 163 and a portion of the semiconductor layer 160 from the side surface of the native oxide film 163 to the metal layer 162 (Figure 47(b)). As a result, the metal layer 162 is formed on the side surface of the semiconductor layer 160 within the recess H2.

[0098] In the conversion process of this embodiment, not only the reaction of chemical formula (1) described above occurs, but also the reactions of chemical formulas (2) and (3) below.

[0099] WF6+3H2→W+6HF ···(2) SiO2+4HF→SiF4+2H2O ···(3) However, W, F, H, and Si represent tungsten, fluorine, hydrogen, and silicon, respectively. Chemical formula (2) shows that the conversion gases WF6 and H2 react to produce W and HF. Chemical formula (3) shows that the above HF reacts with SiO2 in the native oxide film 163 to produce SiF4 and H2O. According to the reactions of chemical formulas (2) and (3), the native oxide film 163 (SiO2 film) is converted into the metal layer 162 (W layer). Furthermore, according to the reaction of chemical formula (1) above, the semiconductor layer 160 (Si layer) is converted into the metal layer 162 (W layer).

[0100] In this embodiment, the reactions of chemical formulas (2) and (3) proceed until the native oxide film 163 disappears, and the reaction of chemical formula (1) is completed before the semiconductor layer 160 disappears. As a result, all of the native oxide film 163 and part of the semiconductor layer 160 are converted into the metal layer 162. According to this embodiment, even if the thickness of the native oxide film 163 is thick, it is possible to form the metal layer 162 by the conversion process.

[0101] Next, the steps shown in Figures 44(b) to 45(b) are carried out. In this way, the semiconductor device of this embodiment is manufactured.

[0102] In this embodiment, the metal layer 162 is formed by converting all of the native oxide film 163 and part of the semiconductor layer 160 into a metal layer 162 using WF6 gas and H2, as shown in chemical formulas (1) to (3). Therefore, the metal layer 162 (or the interface between the metal layer 162 and the wiring layer 170) may contain not only W atoms, but also at least one of F atoms, H atoms, and O atoms. For example, the metal layer 162 may be a W layer containing F atoms as impurity atoms, and the interface between the metal layer 162 and the wiring layer 170 may contain O atoms as impurity atoms.

[0103] As described above, the semiconductor device of this embodiment includes a metal layer 162 between the semiconductor layer 160 and the wiring layer 170 (Figure 46). Therefore, according to this embodiment, similar to the first embodiment, it is possible to reduce the resistance between the semiconductor layer 160 and the wiring layer 170.

[0104] (Third embodiment) Figure 48 is a cross-sectional view showing the structure of a semiconductor device according to the third embodiment.

[0105] The semiconductor device of this embodiment (Figure 48) has a structure similar to that of the semiconductor device of the first embodiment (Figure 40). However, the semiconductor device of this embodiment includes a nitride film 165, a metallic silica nitride film 164, and a metal layer 162' instead of the metal layer 162. The nitride film 165, the metallic silica nitride film 164, and the metal layer 162' are included in the memory layer ML (Figure 4) provided between the upper and lower insulating films 101. The metal layer 162' is an example of a first metal layer, similar to the metal layer 162 of the first embodiment. The metallic silica nitride film 164 is an example of a second metal layer. The nitride film 165 is an example of a first film.

[0106] The nitride film 165 is formed on the side surface of the semiconductor layer 160 and is sandwiched between the semiconductor layer 160 and the metallic silica nitride film 164. The metallic silica nitride film 164 is formed on the side surface of the nitride film 165 and is sandwiched between the nitride film 165 and the metal layer 162'. The metal layer 162' is formed on the side surface of the metallic silica nitride film 164 and is sandwiched between the metallic silica nitride film 164 and the wiring layer 170. Each of the nitride film 165, the metallic silica nitride film 164, and the metal layer 162' in this embodiment has a plate-like shape that extends two-dimensionally in a planar or curved shape, similar to the metal layer 162 in the first embodiment.

[0107] The nitride film 165, the metallic silica nitride film 164, and the metal layer 162' are, for example, a SiN film, a WSiN film (tungsten silica nitride film), and a W (tungsten) layer, respectively. The metallic silica nitride film 164 and the metal layer 162' may be formed of a metallic element other than tungsten. In this case, the metallic silica nitride film 164 and the metal layer 162' may be, for example, a MoSiN film (molybdenum silica nitride film) and a Mo (molybdenum) layer, respectively. Examples of metallic elements other than tungsten and molybdenum include Tc (technetium), Ru (ruthenium), Rh (rhodium), Re (rhenium), Os (osmium), Ir (iridium), or Pt (platinum).

[0108] Figures 49 and 50 are cross-sectional views showing a method for manufacturing a semiconductor device according to a third embodiment.

[0109] First, the steps shown in Figures 42(a) to 44(a) are performed. As a result, the structure shown in Figure 49(a) is formed. The state shown in Figure 49(a) corresponds to the state shown in Figure 44(a). The metal layer 162 shown in Figure 49(a) is, as mentioned above, for example, a W (tungsten) layer. The metal layer 162 shown in Figure 49(a) is an example of a third metal layer.

[0110] Next, the metal layer 162 is nitrided (Figure 49(b)). As a result, the metal layer 162 is transformed into a metal nitride film 166. The metal nitride film 166 is, for example, a WN film (tungsten nitride film). The metal nitride film 166 is an example of a fourth metal layer.

[0111] Next, a barrier metal layer 172 is formed in the recesses H1 and H2 (Figure 50(a)). As a result, the barrier metal layer 172 is formed on the side surface of the metal layer 166, the lower surface and side surface of the upper insulating film 101, and the upper surface and side surface of the lower insulating film 101.

[0112] Next, the metal nitride film 166 is heated (Figure 50(b)). This causes the N atoms in the metal nitride film 166 to diffuse towards the semiconductor layer 160. As a result, the metal nitride film 166 is transformed into the metal layer 162'. Furthermore, a metal silica nitride film 164 is formed between the metal layer 162' and the semiconductor layer 160, on the side surface of the metal layer 162'. Furthermore, a nitride film 165 is formed between the metal layer 162' and the semiconductor layer 160, on the side surface of the metal silica nitride film 164. In Figure 50(b), the metal silica nitride film 164 is formed on the -Y direction side surface of the metal layer 162', and the nitride film 165 is formed on the -Y direction side surface of the metal silica nitride film 164. As described above, the metal layer 162', the metal silica nitride film 164, and the nitride film 165 are, for example, a W layer, a WSiN film, and a SiN film, respectively. In this embodiment, the W atoms in the metallic silicatride film 164 originate from the W atoms in the metallic nitride film 166, the N atoms in the metallic silicatride film 164 and nitride film 165 originate from the N atoms in the metallic nitride film 166, and the Si atoms in the metallic silicatride film 164 and nitride film 165 originate from the Si atoms in the semiconductor layer 160.

[0113] Next, the steps shown in Figures 44(b) to 45(b) are performed (excluding the step of forming the barrier metal layer 172). In this way, the semiconductor device of this embodiment is manufactured.

[0114] In this embodiment, a nitride film 165 is formed between the semiconductor layer 160 and the wiring layer 170 in the process shown in Figure 50(b). The nitride film 165 increases the resistance between the semiconductor layer 160 and the wiring layer 170. However, according to this embodiment, forming the nitride film 165 between the semiconductor layer 160 and the wiring layer 170 makes it possible to suppress the diffusion of a large amount of Si atoms from the semiconductor layer 160, thereby suppressing the generation of large or numerous voids within the semiconductor layer 160. The adverse effect on resistance due to voids is greater than the adverse effect on resistance due to the nitride film 165. According to this embodiment, by forming the nitride film 165 and suppressing the generation of voids, it is possible to reduce the resistance of the entire region including the semiconductor layer 160, the wiring layer 170, and the portions between them (165, 164, 162'). According to this embodiment, by forming a nitride film 165 between the semiconductor layer 160 and the wiring layer 170, it is possible to suppress the diffusion of a large amount of Si atoms from the semiconductor layer 160 even if heat is applied to the semiconductor layer 160 after the wiring layer 170 is formed.

[0115] In this embodiment, the metal layer 162' is formed via nitriding of the metal layer 162 and diffusion of N atoms from the metal nitride film 166. Therefore, the metal layer 162' (or the interface between the metal layer 162' and the wiring layer 170) may contain W atoms and N atoms. For example, the metal layer 162' may be a W layer containing N atoms as impurity atoms, and the interface between the metal layer 162' and the wiring layer 170 may contain N atoms as impurity atoms.

[0116] As described above, the semiconductor device of this embodiment includes a metal layer 162', etc., between the semiconductor layer 160 and the wiring layer 170 (Figure 48). Therefore, according to this embodiment, as with the first and second embodiments, it is possible to reduce the resistance between the semiconductor layer 160 and the wiring layer 170.

[0117] In the first to third embodiments, the fact that the semiconductor device of each embodiment has the structure shown in Figures 40, 46, 48, etc. can be investigated by analysis such as EDS (Energy Dispersive X-ray Spectroscopy). EDS is also called EDX. The boundaries between layers in each embodiment may be formed in a way that makes it difficult to distinguish the boundaries. For example, the boundaries between semiconductor layer 110, semiconductor layer 160, metal layer 162, barrier metal layer 172, and wiring material layer 173 in the first or second embodiment, and the boundaries between semiconductor layer 110, semiconductor layer 160, nitride film 165, metallic silica nitride film 164, metal layer 162', barrier metal layer 172, and wiring material layer 173 in the third embodiment may be formed in a way that makes it difficult to distinguish the boundaries. In this case, these layers may be referred to as "semiconductor region 110," "semiconductor region 160," "metal region 162," etc.

[0118] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and methods described herein can be implemented in a variety of other forms. Furthermore, various omissions, substitutions, and modifications can be made to the embodiments of the apparatus and methods described herein, without departing from the spirit of the invention. The appended claims and equivalents are intended to include such forms and modifications that are included in the scope and spirit of the invention. [Explanation of Symbols]

[0119] 100: Multilayer film, 101: Insulating film, 102: Insulating film 110: Semiconductor layer, 120: electrode layer, 120A: recess, 120B: sacrificial layer 121: Barrier metal layer, 122: Electrode material layer, 123: Insulating film, 123A: Recess 130: Memory insulating film, 131: Tunnel insulating film, 132: Charge storage layer, 133: Block insulating film, 140: Contact plug, 140A: Contact hole, 140B: Sacrificial layer 141: Semiconductor layer, 142: Metal layer, 143: Semiconductor layer, 150: Electrode layer, 150A: Recess, 150B: Sacrificial layer 151: Semiconductor layer, 152: Metal layer, 153: Insulating film, 154: Insulating film 160: Semiconductor layer, 161: Insulating film, 161A: Recess, 161B: Sacrificial layer 162: Metal layer, 162': Metal layer, 163: Natural oxide film, 164: Metallic silicate film, 165: Nitride film, 166: Metallic nitride film, 170: Wiring layer, 171: Insulating film, 171A: Recess, 171B: Sacrificial layer 172: Barrier metal layer, 173: Wiring material layer, 180: Wiring layer, 181: Insulating film, 181A: recess, 181B: sacrificial layer, 182: insulating film 190: wiring layer, 191: insulating film, 192: portion, 193: portion, 194: Barrier metal layer, 195: Electrode material layer, 196: Insulating film

Claims

1. circuit board and A laminated film comprising a plurality of insulating films provided on the substrate and spaced apart from each other in a first direction perpendicular to the surface of the substrate, A first semiconductor layer is provided between the first and second insulating films included in the plurality of insulating films, extending in a second direction perpendicular to the first direction, and corresponding to a channel semiconductor layer, A second semiconductor layer is provided between the first and second insulating films on the side surface of the first semiconductor layer and has a composition different from that of the first semiconductor layer, A first metal layer is provided on the side surface of the second semiconductor layer between the first and second insulating films, A first wiring is provided on the side surface of the first metal layer between the first and second insulating films, and is in contact with the upper surface of the first insulating film and the lower surface of the second insulating film. A second wiring extending in the second direction, electrically connected to the first wiring, and corresponding to a bit wire, A semiconductor device equipped with a semiconductor device.

2. The semiconductor device according to claim 1, wherein the first wiring extends in a third direction perpendicular to the first and second directions.

3. The semiconductor device according to claim 1, wherein the second semiconductor layer is an impurity semiconductor layer.

4. The semiconductor device according to claim 1, wherein the first metal layer comprises W (tungsten), Mo (molybdenum), Tc (technetium), Ru (ruthenium), Rh (rhodium), Re (rhenium), Os (osmium), Ir (iridium), or Pt (platinum).

5. The semiconductor device according to claim 1, wherein the first metal layer contains F (fluorine).

6. The semiconductor device according to claim 1, wherein the first metal layer contains N (nitrogen).

7. The semiconductor device according to claim 1, wherein the interface between the first metal layer and the first wiring contains O (oxygen).

8. The semiconductor device according to claim 1, wherein the interface between the first metal layer and the first wiring contains N (nitrogen).

9. The first wiring is, A first layer is provided on the side surface of the first metal layer between the first and second insulating films, and is in contact with the upper surface of the first insulating film and the lower surface of the second insulating film. The second layer is provided on the side, top, and bottom surfaces of the first layer, A semiconductor device according to claim 1, including the above.

10. The present invention further comprises a second metal layer provided between the second semiconductor layer and the first metal layer, The first metal layer contains a metal element, The second metal layer comprises the metal element, Si (silicon), and N (nitrogen). The semiconductor device according to claim 1.

11. The semiconductor device according to claim 10, wherein the metallic element is W (tungsten), Mo (molybdenum), Tc (technetium), Ru (ruthenium), Rh (rhodium), Re (rhenium), Os (osmium), Ir (iridium), or Pt (platinum).

12. The first film is further provided between the second semiconductor layer and the second metal layer, The first film comprises Si (silicon) and N (nitrogen), The semiconductor device according to claim 10.

13. A laminated film comprising a plurality of insulating films spaced apart from each other in a first direction, A first semiconductor layer is provided between the first and second insulating films included in the plurality of insulating films, A second semiconductor layer provided on the side surface of the first semiconductor layer between the first and second insulating films, A first metal layer is provided between the first and second insulating films on the side surface of the second semiconductor layer, and includes W (tungsten), Mo (molybdenum), Tc (technetium), Ru (ruthenium), Rh (rhodium), Re (rhenium), Os (osmium), Ir (iridium), or Pt (platinum), Between the first and second insulating films, a first wiring is provided on the side surface of the first metal layer, A semiconductor device equipped with a semiconductor device.

14. The semiconductor device according to claim 13, wherein the first wiring is in contact with the upper surfaces of the first and second insulating films and the lower surface of the second insulating film.

15. The semiconductor device according to claim 13, further comprising a second wiring electrically connected to the first wiring.

16. The semiconductor device according to claim 15, wherein the second wiring is a bit line.

17. A laminated film is formed which includes a plurality of insulating films spaced apart from each other in the first direction. A first semiconductor layer is formed between the first and second insulating films contained in the plurality of insulating films. A second semiconductor layer is formed on the side surface of the first semiconductor layer between the first and second insulating films. A first metal layer is formed on the side surface of the second semiconductor layer between the first and second insulating films. Between the first and second insulating films, a first wiring is formed on the side surface of the first metal layer, in contact with the upper surface of the first insulating film and the lower surface of the second insulating film. A second wiring is formed that is electrically connected to the first wiring. A method for manufacturing a semiconductor device, including the following.

18. The method for manufacturing a semiconductor device according to claim 17, wherein the first metal layer is formed by converting a portion of the second semiconductor layer into the first metal layer.

19. The method for manufacturing a semiconductor device according to claim 17, wherein the first metal layer is formed by converting a native oxide film formed on the side surface of the second semiconductor layer into a third metal layer, converting the third metal layer into a fourth metal layer by nitriding, and converting the fourth metal layer into a first metal layer.

20. The method for manufacturing a semiconductor device according to claim 19, wherein at least a portion of the first wiring is formed after the third metal layer is transformed into the fourth metal layer, but before the fourth metal layer is transformed into the first metal layer.

Images