memory devices

Abstract

To improve the integration density of memory devices. [Solution] A memory device according to one embodiment comprises: a first conductive pillar and a second conductive pillar, each extending in a first direction and aligned in a second direction intersecting the first direction; a first semiconductor layer and a second semiconductor layer, each extending in a second direction at a first position in the first direction and sandwiching the first conductive pillar and the second conductive pillar in a third direction intersecting the first and second directions; a first insulating film provided at a first position between the first semiconductor layer and the second semiconductor layer and between the first conductive pillar and the second conductive pillar, having a first portion along a circle centered on the first conductive pillar on the surface facing the first semiconductor layer and the second semiconductor layer; a first charge storage film provided at a first position between the first conductive pillar and the first semiconductor layer; and a second charge storage film provided at a first position between the first conductive pillar and the second semiconductor layer and separated from the first charge storage film.

Description

Technical Field

[0001] The embodiments relate to a memory device.

Background Art

[0002] As a memory device capable of storing data non-volatily, a NAND flash memory is known. In a memory device such as a NAND flash memory, a three-dimensional memory structure is adopted for high integration and large capacity.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the integration degree of the memory device.

Means for Solving the Problems

[0005] The memory device of the embodiment comprises: a first conductive pillar and a second conductive pillar, each extending in a first direction and aligned in a second direction intersecting the first direction; a first semiconductor layer and a second semiconductor layer, each extending in the second direction at a first position in the first direction and sandwiching the first conductive pillar and the second conductive pillar in a third direction intersecting the first and second directions; a first insulating film provided at the first position between the first semiconductor layer and the second semiconductor layer and between the first conductive pillar and the second conductive pillar, having a first portion along a circle centered on the first conductive pillar on the surface facing the first semiconductor layer and the second semiconductor layer; a first charge storage film provided at the first position between the first conductive pillar and the first semiconductor layer; and a second charge storage film provided at the first position between the first conductive pillar and the second semiconductor layer and separated from the first charge storage film. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of a memory system including a memory device according to the first embodiment. [Figure 2] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a memory device according to the first embodiment. [Figure 3] A plan view showing an example of a planar layout of a memory cell array according to the first embodiment. [Figure 4] A cross-sectional view along line IV-IV in Figure 3, showing an example of the cross-sectional structure of a memory cell array according to the first embodiment. [Figure 5] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the first embodiment. [Figure 6] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 7] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the first embodiment. [Figure 8] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 9]A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the first embodiment. [Figure 10] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 11] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the first embodiment. [Figure 12] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 13] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the first embodiment. [Figure 14] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 15] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the first embodiment. [Figure 16] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 17] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the first embodiment. [Figure 18] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 19] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the first embodiment. [Figure 20] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 21] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the first embodiment. [Figure 22] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 23] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the first embodiment. [Figure 24] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. [Figure 25] A plan view showing an example of the planar layout during the manufacturing process of the memory device according to the first embodiment. [Figure 26] A cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the first embodiment. [Figure 27] A circuit diagram showing an example of the circuit configuration of the memory cell array included in the memory device according to the modified example of the first embodiment. [Figure 28] A cross-sectional view showing an example of the cross-sectional structure of the memory cell array according to the modified example of the first embodiment. [Figure 29] A plan view showing an example of the planar layout of the memory cell array according to the second embodiment. [Figure 30] A cross-sectional view taken along the line XXX-XXX of FIG. 29, showing an example of the cross-sectional structure of the memory cell array according to the second embodiment. [Figure 31] A plan view showing an example of the planar layout during the manufacturing process of the memory device according to the second embodiment. [Figure 32] A cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the second embodiment. [Figure 33] A plan view showing an example of the planar layout during the manufacturing process of the memory device according to the second embodiment. [Figure 34] A cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the second embodiment. [Figure 35] A plan view showing an example of the planar layout during the manufacturing process of the memory device according to the second embodiment. [Figure 36] A cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the second embodiment. [Figure 37] A plan view showing an example of the planar layout during the manufacturing process of the memory device according to the second embodiment. [Figure 38] A cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the memory device according to the second embodiment. [Figure 39] A plan view showing an example of the planar layout during the manufacturing process of the memory device according to the second embodiment. [Figure 40]A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the second embodiment. [Figure 41] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the second embodiment. [Figure 42] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the second embodiment. [Figure 43] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the second embodiment. [Figure 44] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the second embodiment. [Figure 45] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the second embodiment. [Figure 46] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the second embodiment. [Figure 47] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the second embodiment. [Figure 48] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the second embodiment. [Figure 49] A plan view showing an example of a planar layout of a memory cell array according to the third embodiment. [Figure 50] A cross-sectional view along the LL line in Figure 49, showing an example of the cross-sectional structure of a memory cell array according to the third embodiment. [Figure 51] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the third embodiment. [Figure 52] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 53] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the third embodiment. [Figure 54] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 55] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the third embodiment. [Figure 56] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 57] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the third embodiment. [Figure 58] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 59] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the third embodiment. [Figure 60] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 61] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the third embodiment. [Figure 62] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 63] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the third embodiment. [Figure 64] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 65] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the third embodiment. [Figure 66] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 67] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the third embodiment. [Figure 68] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 69] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the third embodiment. [Figure 70] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 71]A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the third embodiment. [Figure 72] A cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. [Figure 73] A plan view showing an example of a planar layout of a memory cell array according to the fourth embodiment. [Figure 74] A cross-sectional view along the line LXXIV-LXXIV in Figure 73 shows an example of the cross-sectional structure of a memory cell array according to the fourth embodiment. [Figure 75] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the fourth embodiment. [Figure 76] A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Figure 77] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the fourth embodiment. [Figure 78] A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Figure 79] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the fourth embodiment. [Figure 80] A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Figure 81] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the fourth embodiment. [Figure 82] A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Figure 83] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the fourth embodiment. [Figure 84] A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Figure 85] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the fourth embodiment. [Figure 86]A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Figure 87] A plan view showing an example of a planar layout during the manufacturing process of a memory device according to the fourth embodiment. [Figure 88] A cross-sectional view showing an example of a cross-sectional structure of a memory device during the manufacturing process according to the fourth embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. The dimensions and proportions in the drawings are not necessarily the same as those in reality.

[0008] In the following explanation, components having substantially the same function and structure will be assigned the same reference numeral. When elements with similar structures need to be specifically distinguished, different letters or numbers may be added to the end of the same reference numeral.

[0009] 1. First Embodiment 1.1 Configuration 1.1.1 Memory System Figure 1 is a block diagram showing an example of the configuration of a memory system including a memory device according to the first embodiment. Memory system 1 is a storage device configured to be connected to an external host (not shown). Memory system 1 is, for example, an SD TM These include memory cards, UFS (universal flash storage), and SSDs (solid state drives). Memory system 1 includes a memory controller 2 and a memory device 3.

[0010] The memory controller 2 is composed of an integrated circuit, such as a system-on-a-chip (SoC). The memory controller 2 controls the memory device 3 based on requests from the host. Specifically, for example, the memory controller 2 writes data to the memory device 3 when requested to write by the host. The memory controller 2 also reads data from the memory device 3 when requested to read by the host and sends it to the host.

[0011] Memory device 3 is a non-volatile memory. Memory device 3 is, for example, a NAND flash memory. Memory device 3 stores data in a non-volatile manner.

[0012] Communication between the memory controller 2 and the memory device 3 conforms to, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0013] 1.1.2 Memory Devices Next, with reference to the block diagram shown in Figure 1, the internal configuration of the memory device according to the first embodiment will be described. The memory device 3 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0014] The memory cell array 10 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). The number of blocks BLK included in the memory cell array 10 may be one or less. A block BLK is a collection of multiple memory cells. A block BLK is used, for example, as a data erasure unit. The memory cell array 10 is also provided with multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0015] The command register 11 stores the command CMD received by the memory device 3 from the memory controller 2. The command CMD includes instructions that cause the sequencer 13 to perform read operations, write operations, erase operations, etc.

[0016] The address register 12 stores the address information ADD received by the memory device 3 from the memory controller 2. The address information ADD includes, for example, the block address BAd, the page address PAAd, and the column address CAD. For example, the block address BAd, the page address PAAd, and the column address CAD are used for selecting the block BLK, word line, and bit line, respectively.

[0017] The sequencer 13 controls the operation of the entire memory device 3. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16, etc., based on the command CMD stored in the command register 11, to perform read operations, write operations, erase operations, etc.

[0018] The driver module 14 generates voltages used in read, write, and erase operations. Then, based on the page address PAd stored in the address register 12, for example, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line.

[0019] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address Bad stored in the address register 12. Then, the row decoder module 15 transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0020] During a write operation, the sense amplifier module 16 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 2. During a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line and transfers the determination result to the memory controller 2 as read data DAT.

[0021] 1.1.3 Memory cell array <Circuit Configuration> Next, the circuit configuration of the memory cell array according to the first embodiment will be described.

[0022] Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array provided in the memory device according to the first embodiment. In Figure 2, one of the multiple block BLKs included in the memory cell array 10 is shown. As shown in Figure 2, the block BLK includes, for example, four string units SU0 to SU3.

[0023] Each string unit SU includes multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). The number of bit lines BL may be one or less. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, transfer transistors TT0 to TT7, and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film, and stores data nonvolatilically. Each transfer transistor TT includes a control gate and is used to form an auxiliary current path (channel) between adjacent memory cell transistors MT within the NAND string NS. Selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0024] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. The drain of selection transistor ST1 is connected to the associated bit line BL. The source of selection transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. The drain of selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of selection transistor ST2 is connected to the source line SL. Transfer transistors TT0 to TT7 are each connected in parallel with the memory cell transistors MT0 to MT7. Transfer transistors TT prevent unintended current flow or unintended current flow in the NAND string NS.

[0025] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The control gates of transfer transistors TT0 to TT7 are connected to word lines TWL0 to TWL7, respectively. The gates of selection transistors ST1 in string units SU0 to SU3 are connected to selection gate lines SGD0 to SGD3, respectively. The gates of multiple selection transistors ST2 are connected to selection gate line SGS.

[0026] Each bit line BL0 to BLm is assigned a different column address. Each bit line BL is shared among multiple block BLKs by a NAND string NS that is assigned the same column address. Word lines WL0 to WL7 and TWL0 to TWL7 are provided for each block BLK. Source lines SL are shared, for example, among multiple block BLKs.

[0027] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0028] A set of multiple memory cell transistors MT and transfer transistors TT connected to a common bit line BL within a single block BLK is called, for example, a layer unit LU. A single layer unit LU contains four NAND strings NS. Each of the four NAND strings NS contained in a single layer unit LU belongs to a string unit SU0 to SU3.

[0029] The circuit configuration of the memory cell array 10 provided by the memory device 3 is not limited to the configuration described above. For example, the number of string units SU included in each block BLK can be designed to any number. The number of memory cell transistors MT and transfer transistors TT, as well as selection transistors ST1 and ST2 included in each NAND string NS can each be designed to any number.

[0030] <Floor layout> Next, the planar layout of the memory cell array according to the first embodiment will be described.

[0031] The memory cell array 10 is located above the substrate. In the following, the plane parallel to the surface of the substrate will be referred to as the XY plane. The directions that intersect each other within the XY plane will be the X direction and the Y direction. The direction from the substrate toward the memory cell array will be referred to as the Z direction. The Z direction may also be interpreted as the upward direction.

[0032] Figure 3 is a plan view showing an example of a planar layout of a memory cell array according to the first embodiment. Figure 3 shows a plan view of a position in the memory cell array 10 that includes a structure that functions as a NAND string NS and whose position in the Z direction is approximately equal to that of the substrate. The portion shown in Figure 3 corresponds to one layer unit LU in the circuit diagram shown in Figure 2.

[0033] As shown in Figure 3, within the same layer, the memory cell array 10 includes multiple conductive pillars WP and TP, multiple memory structures MS, multiple insulators INS, channel structures CH, multiple word lines WL and TWL, and multiple contacts V1 and V2.

[0034] Each of the multiple conductive pillars WP and TP is a conductor having a columnar shape extending in the Z direction. The multiple conductive pillars WP and TP are arranged in a square in the XY plane. Specifically, conductive pillars WP and TP aligned in the X direction in the same row are arranged alternately. Conductive pillars WP and TP aligned in the Y direction in the same column are arranged one by one in sequence (alternatingly). That is, any conductive pillar WP is sandwiched between two adjacent conductive pillars TP in the X direction and between two adjacent conductive pillars TP in the Y direction. Similarly, any conductive pillar TP is sandwiched between two adjacent conductive pillars WP in the X direction and between two adjacent conductive pillars WP in the Y direction.

[0035] Each of the multiple insulators INS is an insulator that surrounds the outer circumference of the corresponding conductive pillar TP. In addition, the insulator INS surrounds a portion of the outer circumference of two conductive pillars WP adjacent to the corresponding conductive pillar TP in the Y direction. In other words, on the surface facing the channel structure CH, the insulator INS has a portion along a circle centered on the conductive pillar WP. That is, the insulator INS has a portion formed concentrically around the corresponding conductive pillar TP, and a portion formed concentrically around each of the two conductive pillars WP aligned with the conductive pillar TP in the Y direction. Through such insulators INS, conductive pillars WP and conductive pillars TP are arranged alternately in the Y direction in the same row. As a result, the insulator INS insulates between the conductive pillar TP and the two conductive pillars WP adjacent to the conductive pillar TP in the Y direction.

[0036] Each of the multiple memory structures MS is a multilayer film corresponding to the gate structure of a memory cell transistor MT. Two memory structures MS are arranged corresponding to one conductive pillar WP. Specifically, the two memory structures MS are provided on the outer periphery of the conductive pillar WP, separated from each other by an insulator INS. That is, the two memory structures MS corresponding to the conductive pillar WP are aligned in the X direction so as to sandwich the conductive pillar WP.

[0037] Then, a structure in which two such memory structures MS are partially arranged on the outer periphery of a conductive pillar WP, and an insulator INS surrounds the outer periphery of a conductive pillar TP, is repeated in this order in the Y direction (hereinafter also referred to as the "column structure"), and this structure is arranged in the X direction. In the example in Figure 3, an example is shown in which five column structures are arranged in the X direction.

[0038] Each of the multiple channel structures CH is a semiconductor extending in the Y direction. The channel structures CH are arranged between two adjacent column structures in the X direction. The multiple channel structures CH may be separated from each other at both ends in the Y direction, or they may be connected to each other via selection transistors ST1 and ST2 (not shown).

[0039] The memory structure MS, the conductive pillar WP flanking the memory structure MS, and the channel structure CH portion function as a single memory cell transistor MT. Each of the multiple conductive pillars TP, the insulator INS portion, and the conductive pillar TP flanking the insulator INS portion and the channel structure CH portion function as a transfer transistor TT. The channel structure CH and the portion of the two column structures flanking the channel structure CH that is in contact with the channel structure constitute a single NAND string NS. In Figure 3, the four NAND strings NS formed by the five column structures aligned in the X direction and the four channel structures CH positioned between each of the five column structures correspond to string units SU0 to SU3, respectively.

[0040] One end of the NAND string NS in the Y direction is connected to the bit line BL via a selection transistor ST1 (not shown). The other end of the NAND string NS in the Y direction is connected to the source line SL via a selection transistor ST2 (not shown).

[0041] Each of the multiple word lines WL and TWL extends in the X direction. The multiple word lines WL and TWL are aligned in the Y direction. When viewed in the Z direction, the word line WL is positioned to overlap with multiple conductive pillars WP aligned in the X direction. Conductive pillars WP are connected to the corresponding word line WL via contact V1. When viewed in the Z direction, the word line TWL is positioned to overlap with multiple conductive pillars TP aligned in the X direction. Conductive pillars TP are connected to the corresponding word line TWL via contact V2.

[0042] <Cross-sectional structure> Next, the cross-sectional structure of the memory cell array according to the first embodiment will be described.

[0043] Figure 4 is a cross-sectional view along line IV-IV in Figure 3, showing an example of the cross-sectional structure of a memory cell array according to the first embodiment. Figure 4 mainly shows the cross-sectional structure of the portion (A) where the channel structure CH and conductive pillar WP are adjacent in the X direction via the memory structure MS, the cross-sectional structure of the portion (B) where the conductive pillars WP and TP are adjacent in the Y direction, and the cross-sectional structure of the portion (C) where the channel structure CH and conductive pillar TP are adjacent in the X direction via the insulator INS.

[0044] As shown in Figure 4, the memory cell array 10 includes a substrate 20, insulating layers 21, 22, 23, 25, and 26, a semiconductor layer 24, conductive films 30 and 40, insulating films 31, 32, 33, 35, and 41, a charge storage film 34, and conductive layers 51a, 51b, 52a, and 52b.

[0045] The substrate 20 is, for example, a P-type semiconductor. An insulating layer 21 is provided on the upper surface of the substrate 20. The substrate 20 and the insulating layer 21 may include circuits not shown. The circuits included in the substrate 20 and the insulating layer 21 correspond to, for example, a low decoder module 15 and a sense amplifier module 16.

[0046] An insulating layer 22 is provided on the upper surface of the insulating layer 21. The insulating layer 22 functions as a stop film when processing the structure corresponding to the memory cell array 10 provided above it.

[0047] On the upper surface of the insulating layer 22, multiple insulating layers 23 and multiple semiconductor layers 24 are stacked alternately, one layer at a time. In the example shown in Figure 4, five insulating layers 23 and five semiconductor layers 24 are stacked alternately, one layer at a time. In other words, multiple semiconductor layers 24 are provided on the substrate 20, stacked at intervals in the Z direction. The number of stacked semiconductor layers 24 corresponds, for example, to the number of bit lines BL.

[0048] The insulating layer 23 includes, for example, silicon oxide. The semiconductor layer 24 includes, for example, polysilicon. The semiconductor layer 24 corresponds to the channel structure CH and functions as the current path for the NAND string NS.

[0049] An insulating layer 25 is provided on the upper surface of the top semiconductor layer 24. An insulating layer 26 is provided on the upper surface of the insulating layer 25. The insulating layers 25 and 26 contain, for example, silicon oxide.

[0050] The conductive film 30 is a conductor extending in the Z direction so as to intersect with the multiple semiconductor layers 24, and functions as a conductive pillar WP. The lower end of the conductive film 30 is located below the lowest semiconductor layer 24 and above the insulating layer 22. The upper end of the conductive film 30 is aligned with, for example, the upper end of the insulating layer 25. The conductive film 30 contains, for example, titanium nitride.

[0051] The insulating film 31 covers the lower and side surfaces of the conductive film 30. The insulating film 32 covers the lower and side surfaces of the insulating film 31. The lower end of the insulating film 32 is in contact with, for example, the insulating layer 22. The insulating film 33 is provided on the side surface of the insulating film 32, on the portion facing the semiconductor layer 24. The insulating film 33 is provided between two insulating layers 23 that sandwich the corresponding semiconductor layer 24 in the Z direction, or between insulating layers 23 and 25. The insulating film 31 contains, for example, aluminum oxide. The insulating film 32 contains, for example, silicon oxide. The insulating film 33 contains, for example, hafnium silicate. The insulating films 31, 32, and 33 function as block films of the memory cell transistor MT.

[0052] The charge storage film 34 is provided on the side surface of the insulating film 33 and is located between the insulating film 33 and the semiconductor layer 24. The charge storage film 34 is provided between two insulating layers 23 that sandwich the corresponding semiconductor layer 24 in the Z direction, or between insulating layers 23 and 25. The charge storage film 34 contains a material that has the function of storing charge. Specifically, the charge storage film 34 may contain a conductor such as silicon or a metal. Alternatively, the charge storage film 34 may contain an insulator such as silicon nitride. When it contains a conductor such as silicon or a metal, the charge storage film 34 functions as a floating gate of a floating gate type memory cell transistor MT. When it contains an insulator such as silicon nitride, the charge storage film 34 functions as a charge trap film of a MONOS (metal-oxide-nitride-oxide-silicon) type memory cell transistor MT.

[0053] The insulating film 35 is provided on the side surface of the charge storage film 34 and is located between the charge storage film 34 and the semiconductor layer 24. The insulating film 35 is provided between two insulating layers 23 that sandwich the corresponding semiconductor layer 24 in the Z direction, or between insulating layers 23 and 25. The insulating film 35 includes, for example, silicon oxide. The insulating film 35 functions as a tunnel film for the memory cell transistor MT.

[0054] The insulating films 31, 32, 33, and 35, as well as the charge storage film 34, function as the memory structure MS of the memory cell transistor MT.

[0055] The conductive film 40 is a conductor extending in the Z direction so as to intersect with the multiple semiconductor layers 24, and functions as a conductive pillar TP. The lower end of the conductive film 40 is located below the lowest semiconductor layer 24 and above the insulating layer 22. The upper end of the conductive film 40 is aligned with, for example, the upper end of the insulating layer 25. The conductive film 40 contains, for example, titanium nitride.

[0056] The insulating film 41 covers the lower and side surfaces of the conductive film 40. The portion of the insulating film 41 facing the semiconductor layer 24 functions as a gate insulating film of the transfer transistor TT. The insulating film 41 is continuous with the portion that contacts the insulating film 32 covering the conductive pillar WP at the same position as each of the multiple semiconductor layers 24 in the Z direction (i.e., the portion that functions as an insulator INS). The portion of the insulating film 41 that functions as an insulator INS at the same position as each of the multiple semiconductor layers 24 in the Z direction is a portion that extends radially in the Z direction relative to the portion of the insulating film 41 that extends in the Z direction, and is provided between the two insulating layers 23, or insulating layers 23 and 25. Therefore, the length (thickness) in the Z direction of the portion of the insulating film 41 that contacts the insulating film 32 covering the conductive pillar WP is approximately equal to the thickness of the semiconductor layer 24, and there is no portion that is longer than the thickness of the semiconductor layer 24. The insulating film 41 contains, for example, silicon oxide.

[0057] A conductive layer 51a, which functions as a contact V1, is provided on the upper surface of the conductive film 30. A conductive layer 52a, which functions as a word line WL, is provided on the upper surface of the conductive layer 51a. The conductive layer 52a contains, for example, copper.

[0058] A conductive layer 51b, which functions as a contact V2, is provided on the upper surface of the conductive film 40. A conductive layer 52b, which functions as a word line TWL, is provided on the upper surface of the conductive layer 51b. The conductive layer 52b contains, for example, copper.

[0059] 1.2 Manufacturing method Figures 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, and 25 are plan views showing an example of a planar layout during the manufacturing process of a memory device according to the first embodiment. Figures 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, and 26 are cross-sectional views showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the first embodiment. The cross-sectional views shown in Figures 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, and 26 correspond to cross-sections cut at the same position as the IV-IV line shown in Figure 3 in the planar layouts shown in Figures 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, and 25, respectively.

[0060] First, as shown in Figures 5 and 6, a laminated structure is formed on the upper surface of the substrate 20. Specifically, insulating layers 21 and 22 are laminated on the upper surface of the substrate 20 in that order. Subsequently, insulating layer 23 and sacrificial member 61 are repeatedly laminated on the upper surface of insulating layer 22 in that order. An insulating layer 25 is provided on the upper surface of the top layer sacrificial member 61. The sacrificial member 61 includes, for example, silicon nitride.

[0061] Next, as shown in Figures 7 and 8, an insulating film 62 and sacrificial members 63 are provided in the region of the laminated structure where multiple conductive pillars WP and TP are planned to be provided. Specifically, multiple holes are provided in the region where multiple conductive pillars WP and TP are planned to be provided. Specifically, the multiple holes are provided in a square arrangement when viewed in the Z direction. Each of the multiple holes penetrates the insulating layer 25, the multiple sacrificial members 61, and the multiple insulating layers 23. The bottom of each of the multiple holes reaches the insulating layer 22.

[0062] A thin insulating film 62 is formed inside each of the multiple holes. Subsequently, each of the multiple holes is filled with a sacrificial member 63. The insulating film 62 includes, for example, silicon oxide. The sacrificial member 63 includes, for example, polysilicon.

[0063] Here, the multiple holes are formed so as not to interfere with each other at any position in the Z direction. Therefore, at the positions in the Z direction where the insulating layer 23, sacrificial member 61, and insulating layer 25 are provided, the insulating layer 23, sacrificial member 61, and insulating layer 25 are located between the multiple holes aligned in the Y direction, respectively.

[0064] Next, as shown in Figures 9 and 10, the sacrificial members 63 and insulating films 62 provided in the region corresponding to the conductive pillar WP are removed, thereby forming multiple holes H1. As a result, multiple sacrificial members 61, which are stacked at a distance from each other, are exposed inside the multiple holes H1. Subsequently, the sacrificial members 61 are partially removed from the multiple holes H1. This forms grooves that spread concentrically from the center of the multiple holes H1, for each layer where the sacrificial members 61 are provided. Note that each of the multiple grooves formed inside the holes H1 is formed to a depth that does not reach the insulating film 62 adjacent to the hole H1 in the Y direction. In other words, the insulating film 62 is not exposed inside the grooves formed inside the holes H1.

[0065] Next, as shown in Figures 11 and 12, the multiple holes H1 are filled by the sacrificial member 64, the insulating film 65, and the sacrificial member 66. Specifically, the multiple grooves formed in each of the multiple holes H1 are filled by the sacrificial member 64. Then, a thin insulating film 65 is formed inside each of the multiple holes H1. After that, each of the multiple holes H1 is filled by the sacrificial member 66. The sacrificial member 64 includes, for example, amorphous silicon. The insulating film 65 includes, for example, silicon oxide. The sacrificial member 66 includes, for example, polysilicon.

[0066] Next, as shown in Figures 13 and 14, multiple holes H2 are formed by removing the sacrificial member 63 and insulating film 62 provided in the region corresponding to the conductive pillar TP. As a result, multiple sacrificial members 61, which are stacked spaced apart from each other, are exposed inside the multiple holes H2. Subsequently, the sacrificial members 61 are partially removed through the multiple holes H2. This forms grooves that spread concentrically from the center of the multiple holes H2, for each layer in which the sacrificial members 61 are provided. The grooves formed inside the holes H2 are formed to a depth similar to, for example, the grooves formed inside hole H1 (embedded by the sacrificial member 64). Inside the grooves formed inside the holes H2, adjacent sacrificial members 64 in the Y direction are exposed, but adjacent sacrificial members 64 in the X direction are not exposed.

[0067] Subsequently, the insulating layers 23 and 25 are partially removed through multiple holes H2. As a result, the insulating layers 23 and 25 are removed through grooves formed within the holes H2. Therefore, the grooves formed within the holes H2 become larger in the Z direction than the film thickness of the sacrificial member 61. In other words, multiple insulating layers 23 and 25 are thinned.

[0068] Next, as shown in Figures 15 and 16, the sacrificial member 64 is partially removed through multiple holes H2. This divides the sacrificial member 64 into two parts that sandwich the sacrificial member 66 in the X direction. That is, at the position where the sacrificial member 64 is formed in the Z direction, the portion of the insulating film 65 facing the holes H2 is exposed inside the holes H2. The region where the sacrificial member 64 remains after being divided into two parts corresponds to the region where the memory structure MS is planned to be provided.

[0069] Next, as shown in Figures 17 and 18, multiple holes H2 are filled by the insulating film 41 and the conductive film 40. Specifically, the groove formed by the removal of the sacrificial member 64 is filled by the insulating film 41. Subsequently, multiple holes H2 are filled by the conductive film 40. The insulating film 41 provided between the conductive film 40 and the sacrificial member 61 functions as a gate insulating film of the transfer transistor TT.

[0070] As mentioned above, the groove in hole H2 where the sacrificial member 61 is exposed is enlarged in the Z direction due to the removal of the insulating layers 23 and 25, and therefore is not blocked by the insulating film 41. In this way, the thickness of the gate insulating film of the transfer transistor TT is adjusted so that it does not become too thick.

[0071] Next, as shown in Figures 19 and 20, the sacrificial members 66 and insulating film 65 provided in the region corresponding to the conductive pillar WP are removed, thereby forming multiple holes H3. Multiple sacrificial members 64, which are stacked separately from each other, are exposed inside the multiple holes H3. Subsequently, the multiple sacrificial members 64 are removed through the multiple holes H3. This forms multiple grooves in each of the multiple holes H3. Sacrificial members 61 are exposed inside each of the multiple grooves. Subsequently, the multiple sacrificial members 61 are removed through the multiple grooves formed in each of the multiple holes H3. As a result, the multiple holes H3 are connected into one through the multiple grooves.

[0072] Next, as shown in Figures 21 and 22, a semiconductor layer 24 is formed through multiple holes H3 connected by multiple grooves. As a result, the region of each of the multiple holes H3 where the channel structure CH is to be formed is filled by the semiconductor layer 24. The multiple holes H3 are then separated again by the semiconductor layer 24.

[0073] Next, as shown in Figures 23 and 24, an insulating film 35, a charge storage film 34, and an insulating film 33 are formed through a plurality of holes H3. As a result, each of the plurality of grooves formed in each of the plurality of holes H3 is filled by the laminated film of the insulating film 35, the charge storage film 34, and the insulating film 33.

[0074] Next, as shown in Figures 25 and 26, the multiple holes H3 are filled by the formation of an insulating film 32, an insulating film 31, and a conductive film 30 through the multiple holes H3.

[0075] Subsequently, the upper structure of the stacked structure of the memory cell array 10 is formed. Thus, the memory device 3 is formed.

[0076] 1.3 Effects of the First Embodiment According to the first embodiment, the region where multiple holes corresponding to conductive pillars WP and TP are formed is a laminated structure of an insulating layer 23 and a sacrificial member 61. This makes processing easier than, for example, when the region where multiple holes corresponding to conductive pillars WP and TP are formed contains a mixture of regions where a laminated structure of silicon oxide layers and silicon nitride layers is processed and regions where a laminated structure consisting only of silicon oxide layers is processed. Therefore, the increase in manufacturing cost of the memory device 3 can be suppressed.

[0077] Furthermore, multiple holes corresponding to the conductive pillars WP and TP are formed simultaneously. This allows the process of machining the laminated structure of the insulating layer 23 and the sacrificial member 61 in the Z direction to be completed in a single step. As a result, the increase in manufacturing costs of the memory device 3 can be suppressed.

[0078] Furthermore, the NAND string NS is composed of memory cell transistors MT formed around conductive pillars WP and transfer transistors TT formed around conductive pillars TP. This facilitates current control in the NAND string NS and reduces interference between opposing memory cell transistors MT.

[0079] 1.4 Modifications of the First Embodiment The first embodiment described above can be modified in various ways.

[0080] For example, in the first embodiment described above, a case in which a memory cell transistor MT and a transfer transistor TT are provided in the NAND string NS was described, but the invention is not limited to this. For example, the transfer transistor TT may not be provided.

[0081] Figure 27 is a circuit diagram showing an example of the circuit configuration of a memory cell array in a memory device according to a modified example of the first embodiment. Figure 27 corresponds to Figure 2 in the first embodiment.

[0082] As shown in Figure 27, the NAND string NS may be configured without a transfer transistor TT. Specifically, the NAND string NS may consist of a plurality of memory cell transistors MT0 to MT7 connected in series, and selection transistors ST1 and ST2 provided at both ends of the plurality of memory cell transistors MT, respectively. In this case, the conductive pillar TP may be replaced with an insulating pillar RP made of an insulating material.

[0083] Figure 28 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array according to a modified example of the first embodiment. Figure 28 corresponds to Figure 4 in the first embodiment.

[0084] As shown in Figure 28, in the first embodiment, the conductive film 40 and the insulating film 41 may be replaced by an insulating film 41A. The insulating film 41A is formed by collectively filling a plurality of grooves formed in the hole H2 and the hole H2 itself. In this case, the insulating film 41A further has a portion along a circle centered on the insulating pillar RP on the surface facing the semiconductor layer 24.

[0085] With the above configuration, similar to the first embodiment, it is possible to form a structure in which NAND strings NS extending horizontally to the substrate 20 are stacked in the Z direction, while limiting the process of processing the stacked structure on the substrate 20 in the Z direction to just one step.

[0086] 2. Second Embodiment Next, a memory device according to the second embodiment will be described. The memory device according to the second embodiment differs from the first embodiment in that memory cells are formed in all of the holes obtained by processing the stacked structure on the substrate 20 in the Z direction. In the following, the configuration and manufacturing method that differ from the first embodiment will be mainly described. The configuration and manufacturing method that are the same as those of the first embodiment will be omitted as appropriate.

[0087] 2.1 Configuration <Circuit Configuration> First, the circuit configuration of the memory cell array according to the second embodiment will be described.

[0088] The circuit configuration of the memory cell array 10 in the second embodiment is equivalent to the circuit configuration of the memory cell array 10 in the modified example of the first embodiment. That is, the NAND string NS included in the memory cell array 10 is composed of a plurality of memory cell transistors MT0 to MT7 connected in series, and selection transistors ST1 and ST2 provided at both ends of the plurality of memory cell transistors MT, respectively.

[0089] <Floor layout> Next, the planar layout of the memory cell array according to the second embodiment will be described.

[0090] Figure 29 is a plan view showing an example of a planar layout of a memory cell array according to the second embodiment. Figure 29 corresponds to Figure 3 in the first embodiment.

[0091] As shown in Figure 29, in the same layer, the memory cell array 10 includes a plurality of conductive pillars WP1 and WP2, a plurality of memory structures MS, a plurality of insulators INS, a channel structure CH, a plurality of word lines WL, and a plurality of contacts V1 and V2.

[0092] Each of the multiple conductive pillars WP1 and WP2 is a conductor having a columnar shape extending in the Z direction. The multiple conductive pillars WP1 and WP2 are arranged in a staggered pattern in the XY plane. Specifically, conductive pillars WP1 and WP2 aligned in the Y direction in the same row are arranged one by one in sequence (alternating). Then, pairs of conductive pillars WP1 and WP2 aligned alternately in the Y direction are arranged with a half-pitch offset in the X direction. Here, half a pitch is, for example, half the distance between the centers of the conductive pillars WP1 and WP2 aligned in the Y direction.

[0093] Furthermore, the conductive pillars WP1 and WP2 may have different shapes when viewed in the Z direction. Specifically, conductive pillar WP1 can have a shape close to a perfect circle because the distance from the center does not change significantly between the portion along the memory structure MS and the portion along the insulator INS. In contrast, conductive pillar WP2 can have a shape that deviates from a perfect circle because the distance from the center changes significantly between the portion along the memory structure MS and the portion along the insulator INS.

[0094] Each of the multiple insulators INS is an insulator that surrounds the portion of the outer circumference of the corresponding conductive pillar WP1 that faces the adjacent conductive pillar WP2 in the Y direction. For each conductive pillar WP1, two insulators INS are provided spaced apart from each other, each facing the two conductive pillars WP2 adjacent to the conductive pillar WP1 in the Y direction. The portion of the insulator INS that is in contact with the channel structure CH is formed, for example, in a concentric circular shape centered on the conductive pillars WP1 and WP2 that sandwich the insulator INS in the Y direction. The portion of the insulator INS formed in a concentric circular shape centered on the conductive pillars WP1 and WP2 has a convex shape that protrudes in the X direction toward the channel structure CH. Through these two insulators INS, conductive pillars WP1 and WP2 are arranged alternately in the Y direction in the same row. In this way, the insulators INS insulate between conductive pillar WP1 and conductive pillar WP2 that is adjacent to it in the Y direction.

[0095] Each of the multiple memory structures MS is a multilayer film corresponding to the gate structure of a memory cell transistor MT. Two memory structures MS are arranged for each of the conductive pillars WP1 and WP2. Specifically, the two memory structures MS are provided on the outer periphery of each of the conductive pillars WP1 and WP2, separated from each other by an insulator INS. That is, the two memory structures MS corresponding to conductive pillar WP1 are aligned in the X direction so as to sandwich conductive pillar WP1. The two memory structures MS corresponding to conductive pillar WP2 are aligned in the X direction so as to sandwich conductive pillar WP1.

[0096] Then, a structure in which two such memory structures MS are arranged on the outer periphery of a conductive pillar WP1, an insulator INS, two memory structures MS are arranged on the outer periphery of a conductive pillar WP2, and an insulator INS is repeated in this order in the Y direction (hereinafter also referred to as the "column structure"), and these are arranged in the X direction with a half-pitch offset. In the example in Figure 29, an example is shown in which five column structures are arranged in the X direction.

[0097] Each of the multiple channel structures CH is a semiconductor extending in the Y direction. The channel structures CH are arranged between two adjacent column structures in the X direction. The multiple channel structures CH may be separated from each other at both ends in the Y direction, or they may be connected to each other via selection transistors ST1 and ST2 (not shown).

[0098] The memory structure MS, the conductive pillar WP1 flanking the memory structure MS, and the channel structure CH all function as one memory cell transistor MT. The memory structure MS, the conductive pillar WP2 flanking the memory structure MS, and the channel structure CH all function as one memory cell transistor MT. The channel structure CH and the portion of the two column structures flanking the channel structure CH that is in contact with the channel structure constitute one NAND string NS. In Figure 29, the four NAND strings NS formed by the five column structures aligned in the X direction and the four channel structures CH positioned between each of the five column structures correspond to string units SU0 to SU3, respectively.

[0099] One end of the NAND string NS in the Y direction is connected to the bit line BL via a selection transistor ST1 (not shown). The other end of the NAND string NS in the Y direction is connected to the source line SL via a selection transistor ST2 (not shown).

[0100] Each of the multiple word lines WL extends in the X direction. The multiple word lines WL are aligned in the Y direction. When viewed in the Z direction, the word lines WL are positioned to overlap with the multiple conductive pillars WP1 and WP2 aligned in the X direction. Conductive pillars WP1 and WP2 are connected to the corresponding word lines WL via contacts V1 and V2, respectively.

[0101] <Cross-sectional structure> Next, the cross-sectional structure of the memory cell array according to the second embodiment will be described.

[0102] Figure 30 is a cross-sectional view along the line XXX-XXX in Figure 29, showing an example of the cross-sectional structure of the memory cell array according to the second embodiment. Figure 30 corresponds to Figure 4 in the first embodiment.

[0103] As shown in Figure 30, the memory cell array 10 includes a substrate 20, insulating layers 21, 22, 23, 25, and 26, a semiconductor layer 24, a conductive film 30, insulating films 31, 32, 33, 35, and 71, a charge storage film 34, and conductive layers 51a, 51b, 52a, and 52b.

[0104] The laminated structure, including the substrate 20, insulating layers 21, 22, 23, 25, and 26, and the semiconductor layer 24, is the same as that of the first embodiment.

[0105] The conductive film 30 is a conductor extending in the Z direction so as to intersect with the multiple semiconductor layers 24, and functions as a conductive pillar WP1 or WP2. The lower end of the conductive film 30 is located below the lowest semiconductor layer 24 and above the insulating layer 22. The upper end of the conductive film 30 is aligned with, for example, the upper end of the insulating layer 25. The conductive film 30 contains, for example, titanium nitride.

[0106] The memory structure MS, including the insulating films 31, 32, 33, and 35, and the charge storage film 34, is equivalent to that of the first embodiment.

[0107] Each of the multiple insulating films 71 is provided at the same position as each of the multiple semiconductor layers 24 in the Z direction and functions as an insulator INS. The insulating films 71 extend in the XY plane and are provided between two insulating layers 23, or between insulating layers 23 and 25. Therefore, the length (film thickness) of the insulating film 71 in the Z direction is approximately equal to the film thickness of the semiconductor layer 24, and there are no portions that are longer than the film thickness of the semiconductor layer 24. The insulating film 71 includes, for example, silicon oxide.

[0108] A conductive layer 51a, which functions as a contact V1, is provided on the upper surface of the conductive film 30, which functions as a conductive pillar WP1. A conductive layer 52a, which functions as a word line WL, is provided on the upper surface of the conductive layer 51a. The conductive layer 52a contains, for example, copper.

[0109] A conductive layer 51a, which functions as a contact V2, is provided on the upper surface of the conductive film 30, which functions as a conductive pillar WP2. A conductive layer 52a, which functions as a word line WL, is provided on the upper surface of the conductive layer 51a. The conductive layer 52a contains, for example, copper.

[0110] 2.2 Manufacturing method Figures 31, 33, 35, 37, 39, 41, 43, 45, and 47 are plan views showing an example of a planar layout during the manufacturing process of a memory device according to the second embodiment. Figures 32, 34, 36, 38, 40, 42, 44, 46, and 47 are cross-sectional views showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the second embodiment. The cross-sectional views shown in Figures 32, 34, 36, 38, 40, 42, 44, 46, and 47 correspond to cross-sections cut at positions equivalent to the XXX-XXX line shown in Figure 29 in the planar layouts shown in Figures 31, 33, 35, 37, 39, 41, 43, 45, and 47, respectively.

[0111] First, a laminated structure is formed on the upper surface of the substrate 20. The process for forming the laminated structure is equivalent to that shown in Figures 3 and 4 of the first embodiment.

[0112] Next, as shown in Figures 31 and 32, multiple holes are provided in the region of the laminated structure where multiple conductive pillars WP1 and WP2 are to be installed. The multiple holes are arranged in a staggered pattern when viewed in the Z direction. Each of the multiple holes penetrates the insulating layer 25, the multiple sacrificial members 61, and the multiple insulating layers 23. The bottom of each of the multiple holes reaches the insulating layer 22. A thin insulating film 62 is formed inside each of the multiple holes. Subsequently, each of the multiple holes is filled by the sacrificial member 63.

[0113] Here, the multiple holes are formed so as not to interfere with each other at any position in the Z direction. Therefore, at the positions in the Z direction where the insulating layer 23, sacrificial member 61, and insulating layer 25 are provided, the insulating layer 23, sacrificial member 61, and insulating layer 25 are located between the multiple holes aligned in the Y direction, respectively.

[0114] Next, as shown in Figures 33 and 34, multiple holes H4 are formed by removing the sacrificial member 63 and insulating film 62 provided in the region corresponding to the conductive pillar WP1. As a result, multiple sacrificial members 61, which are stacked at a distance from each other, are exposed inside the multiple holes H4. Subsequently, the sacrificial members 61 are partially removed from the multiple holes H4. As a result, grooves radiating concentrically from the center of the multiple holes H4 are formed for each layer in which the sacrificial members 61 are provided. Each of the multiple grooves formed inside the hole H4 is formed to a depth that reaches the insulating film 62 adjacent to the hole H4 in the Y direction. Furthermore, each of the multiple grooves formed inside the hole H4 is formed to a depth that reaches another hole H4 adjacent to the hole H4 in the X direction. Therefore, an insulating film 62 adjacent to the hole H4 in the Y direction is exposed inside each of the multiple grooves formed inside the hole H4. In addition, the hole H4 is connected to another hole H4 adjacent to it in the X direction via the multiple grooves.

[0115] Next, as shown in Figures 35 and 36, the multiple holes H4 are filled by the sacrificial member 64, the insulating film 65, and the sacrificial member 66. Specifically, the multiple grooves formed in each of the multiple holes H4 are filled by the sacrificial member 64. Then, a thin insulating film 65 is formed inside each of the multiple holes H4. After that, each of the multiple holes H4 is filled by the sacrificial member 66.

[0116] Next, as shown in Figures 37 and 38, the sacrificial members 63 and insulating film 62 provided in the region corresponding to the conductive pillar WP2 are removed, thereby forming multiple holes H5. As a result, multiple sacrificial members 61 and multiple sacrificial members 64 provided on the same layer are exposed inside the multiple holes H5. Subsequently, the sacrificial members 64 are partially removed through the multiple holes H5. This forms grooves that spread concentrically from the center of the multiple holes H5, for each layer where the sacrificial members 64 are provided. Each of the multiple grooves formed inside the hole H5 is formed to a depth similar to, for example, the groove formed inside the hole H4 (embedded by the sacrificial member 64). Therefore, inside each of the multiple grooves formed inside the hole H5, the insulating film 65 adjacent to the hole H5 in the Y direction is exposed. Each of the multiple grooves formed inside the hole H5 has a contour that, when viewed in the Z direction, includes a portion along a concentric circle centered on the hole H5 and a portion along a concentric circle centered on the hole H4.

[0117] Next, as shown in Figures 39 and 40, the multiple holes H5 are filled with insulating film 71, insulating film 67, and sacrificial member 68. Specifically, the multiple grooves formed in each of the multiple holes H5 are filled with insulating film 71. As a result, the insulating film 71 has a shape that, when viewed in the Z direction, consists of a portion along concentric circles centered on the hole H5 and a portion along concentric circles centered on the hole H4. Then, a thin insulating film 67 is formed inside each of the multiple holes H5. After that, each of the multiple holes H5 is filled with sacrificial member 68. The insulating film 67 includes, for example, silicon oxide. The sacrificial member 68 includes, for example, polysilicon.

[0118] Next, as shown in Figures 41 and 42, the sacrificial member 66 and insulating film 65 provided in the region corresponding to conductive pillar WP1, and the sacrificial member 68 and insulating film 67 provided in the region corresponding to conductive pillar WP2 are removed, thereby forming multiple holes H6. Inside the hole H6 corresponding to conductive pillar WP1, multiple sacrificial members 64, stacked at a distance from each other, are exposed. Inside the hole H6 corresponding to conductive pillar WP2, multiple sacrificial members 61, stacked at a distance from each other, are exposed.

[0119] Next, multiple sacrificial members 64 are removed through the holes H6 corresponding to the conductive pillar WP1. This exposes multiple sacrificial members 61 that are stacked separately from each other inside the holes H6 corresponding to the conductive pillar WP1. Subsequently, multiple sacrificial members 61 are removed through the multiple holes H6. As a result, the multiple holes H6 are connected into one via multiple grooves.

[0120] Next, as shown in Figures 43 and 44, a semiconductor layer 24 is formed through multiple holes H6 connected by multiple grooves. As a result, the region of each of the multiple holes H6 where the channel structure CH is to be formed is filled by the semiconductor layer 24. The multiple holes H6 are then separated again by the semiconductor layer 24.

[0121] Next, as shown in Figures 44 and 45, an insulating film 35, a charge storage film 34, and an insulating film 33 are formed through a plurality of holes H6. As a result, each of the plurality of grooves formed in each of the plurality of holes H6 is filled by the laminated film of the insulating film 35, the charge storage film 34, and the insulating film 33.

[0122] Next, as shown in Figures 46 and 47, the multiple holes H6 are filled by forming the insulating film 32, the insulating film 31, and the conductive film 30 through the multiple holes H6.

[0123] Subsequently, the upper structure of the stacked structure of the memory cell array 10 is formed. Thus, the memory device 3 is formed.

[0124] 2.3 Effects according to the second embodiment According to the second embodiment, the region where multiple holes corresponding to the conductive pillars WP1 and WP2 are formed is a laminated structure of an insulating layer 23 and a sacrificial member 61. This makes processing easier than, for example, when the region where multiple holes corresponding to the conductive pillars WP1 and WP2 are formed contains a mixture of regions where a laminated structure of silicon oxide layers and silicon nitride layers is processed and regions where a laminated structure consisting only of silicon oxide layers is processed. Therefore, the increase in manufacturing costs of the memory device 3 can be suppressed.

[0125] Furthermore, multiple holes corresponding to the conductive pillars WP1 and WP2 are formed simultaneously. This allows the process of machining the laminated structure of the insulating layer 23 and the sacrificial member 61 in the Z direction to be completed in a single step. As a result, the increase in manufacturing costs of the memory device 3 can be suppressed.

[0126] Furthermore, when forming multiple holes corresponding to conductive pillars WP1 and WP2, all holes correspond to either conductive pillar WP1 or WP2. This allows for a higher integration density of memory cell transistors MT compared to when some of the collectively formed holes are used as conductive pillars WP1 and WP2.

[0127] 3. Third Embodiment Next, a memory device according to the third embodiment will be described. The memory device according to the third embodiment differs from the second embodiment in that the shape of the memory structure MS is significantly different in the conductive pillars WP1 and WP2. Below, the configuration and manufacturing method that differ from the second embodiment will be mainly described. The configuration and manufacturing method equivalent to that of the second embodiment will be omitted as appropriate.

[0128] 3.1 Configuration <Circuit Configuration> First, the circuit configuration of the memory cell array according to the third embodiment will be described.

[0129] The circuit configuration of the memory cell array 10 in the third embodiment is equivalent to the circuit configuration of the memory cell array 10 in the second embodiment. That is, the NAND string NS included in the memory cell array 10 is composed of a plurality of memory cell transistors MT0 to MT7 connected in series, and selection transistors ST1 and ST2 provided at both ends of the plurality of memory cell transistors MT, respectively.

[0130] <Floor layout> Next, the planar layout of the memory cell array according to the third embodiment will be described.

[0131] Figure 49 is a plan view showing an example of a planar layout of a memory cell array according to the third embodiment. Figure 49 corresponds to Figure 29 in the second embodiment.

[0132] As shown in Figure 49, in the same layer, the memory cell array 10 includes a plurality of conductive pillars WP1 and WP2, a plurality of memory structures MS, a plurality of insulators INS, a channel structure CH, a plurality of word lines WL, and a plurality of contacts V1 and V2.

[0133] Each of the multiple conductive pillars WP1 and WP2 is a conductor having a columnar shape extending in the Z direction. The multiple conductive pillars WP1 and WP2 are arranged in a staggered pattern in the XY plane. Specifically, conductive pillars WP1 and WP2 aligned in the Y direction in the same row are arranged one by one in sequence (alternating). Then, pairs of conductive pillars WP1 and WP2 aligned alternately in the Y direction are arranged with a half-pitch offset in the X direction. Here, half a pitch is, for example, half the distance between the centers of the conductive pillars WP1 and WP2 aligned in the Y direction.

[0134] Each of the multiple insulators INS is an insulator that surrounds the portion of the outer circumference of the corresponding conductive pillar WP1 that faces the adjacent conductive pillar WP2 in the Y direction. Two insulators INS are provided for each conductive pillar WP1, spaced apart from each other in the Y direction. The portion of the insulator INS that is in contact with the channel structure CH is formed, for example, in a concentric circle with conductive pillar WP1 at the center. Through these two insulators INS, conductive pillars WP1 and WP2 are arranged alternately in the Y direction in the same row. As a result, the insulators INS insulate conductive pillar WP1 from conductive pillar WP2 that is adjacent to it in the Y direction.

[0135] Each of the multiple memory structures MS is a multilayer film corresponding to the gate structure of a memory cell transistor MT. Two memory structures MS are arranged for each of the conductive pillars WP1 and WP2. Specifically, the two memory structures MS are provided on the outer periphery of each of the conductive pillars WP1 and WP2, separated from each other by an insulator INS. That is, the two memory structures MS corresponding to conductive pillar WP1 are aligned in the X direction, sandwiching conductive pillar WP1. The two memory structures MS corresponding to conductive pillar WP2 are also aligned in the X direction, sandwiching conductive pillar WP1. The shapes of the two memory structures MS corresponding to conductive pillar WP1 and the two memory structures MS corresponding to conductive pillar WP2 may differ when viewed in the Z direction. Specifically, the two memory structures MS corresponding to conductive pillar WP1 are shorter than the two memory structures MS corresponding to conductive pillar WP2.

[0136] Then, a structure in which two such memory structures MS are arranged on the outer periphery of a conductive pillar WP1, an insulator INS, two memory structures MS are arranged on the outer periphery of a conductive pillar WP2, and an insulator INS is repeated in this order in the Y direction (hereinafter also referred to as the "column structure"), and these are arranged in the X direction with a half-pitch offset. In the example in Figure 49, an example is shown in which five column structures are arranged in the X direction.

[0137] Each of the multiple channel structures CH is a semiconductor extending in the Y direction. The channel structures CH are arranged between two adjacent column structures in the X direction. The multiple channel structures CH may be separated from each other at both ends in the Y direction, or they may be connected to each other via selection transistors ST1 and ST2 (not shown).

[0138] The memory structure MS, the conductive pillar WP1 flanking the memory structure MS, and the channel structure CH all function as one memory cell transistor MT. The memory structure MS, the conductive pillar WP2 flanking the memory structure MS, and the channel structure CH all function as one memory cell transistor MT. The channel structure CH and the portion of the two column structures flanking the channel structure CH that is in contact with the channel structure constitute one NAND string NS. In Figure 49, the four NAND strings NS formed by the five column structures aligned in the X direction and the four channel structures CH positioned between each of the five column structures correspond to string units SU0 to SU3, respectively.

[0139] One end of the NAND string NS in the Y direction is connected to the bit line BL via a selection transistor ST1 (not shown). The other end of the NAND string NS in the Y direction is connected to the source line SL via a selection transistor ST2 (not shown).

[0140] Each of the multiple word lines WL extends in the X direction. The multiple word lines WL are aligned in the Y direction. When viewed in the Z direction, the word lines WL are positioned to overlap with the multiple conductive pillars WP1 and WP2 aligned in the X direction. Conductive pillars WP1 and WP2 are connected to the corresponding word lines WL via contacts V1 and V2, respectively.

[0141] <Cross-sectional structure> Next, the cross-sectional structure of the memory cell array according to the third embodiment will be described.

[0142] Figure 50 is a cross-sectional view along the LL line in Figure 49, showing an example of the cross-sectional structure of the memory cell array according to the third embodiment. Figure 50 corresponds to Figure 30 in the second embodiment.

[0143] As shown in Figure 50, the memory cell array 10 includes a substrate 20, insulating layers 21, 22, 23, 25, and 26, a semiconductor layer 24, a conductive film 30, insulating films 31, 32, 33, 35, and 72, a charge storage film 34, and conductive layers 51a, 51b, 52a, and 52b.

[0144] The laminated structure, including the substrate 20, insulating layers 21, 22, 23, 25, and 26, and the semiconductor layer 24, is equivalent to that of the second embodiment.

[0145] The conductive film 30 is a conductor extending in the Z direction so as to intersect with the multiple semiconductor layers 24, and functions as a conductive pillar WP1 or WP2. The lower end of the conductive film 30 is located below the lowest semiconductor layer 24 and above the insulating layer 22. The upper end of the conductive film 30 is aligned with, for example, the upper end of the insulating layer 25. The conductive film 30 contains, for example, titanium nitride.

[0146] The memory structure MS, including the insulating films 31, 32, 33, and 35, and the charge storage film 34, is equivalent to that of the second embodiment.

[0147] Each of the multiple insulating films 72 is provided at the same position as each of the multiple semiconductor layers 24 in the Z direction and functions as an insulator INS. The insulating film 72 extends in the XY plane and is provided between two insulating layers 23, or between insulating layers 23 and 25. Therefore, the length (film thickness) of the insulating film 72 in the Z direction is approximately equal to the film thickness of the semiconductor layer 24, and there are no portions that are longer than the film thickness of the semiconductor layer 24. The insulating film 72 includes, for example, silicon oxide.

[0148] The structures of the conductive layers 51a and 51b, and the conductive layers 52a and 52b are the same as those in the second embodiment.

[0149] 3.2 Manufacturing method Figures 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, and 71 are plan views showing an example of a planar layout during the manufacturing process of a memory device according to the third embodiment. Figures 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, and 72 are cross-sectional views showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the third embodiment. The cross-sectional views shown in Figures 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, and 72 correspond to cross-sections cut at the same position as the LL line shown in Figure 49 in the planar layouts shown in Figures 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, and 71, respectively.

[0150] First, a structure equivalent to that shown in Figures 31 and 32 of the second embodiment is formed by a process equivalent to that of the second embodiment.

[0151] Next, as shown in Figures 51 and 52, multiple holes H7 are formed by removing the sacrificial member 63 and insulating film 62 provided in the region corresponding to the conductive pillar WP1. As a result, multiple sacrificial members 61, which are stacked at a distance from each other, are exposed inside the multiple holes H7. Subsequently, the sacrificial members 61 are partially removed from the multiple holes H7. As a result, grooves radiating concentrically from the center of the multiple holes H7 are formed for each layer in which the sacrificial members 61 are provided. Note that each of the multiple grooves formed inside the holes H7 is formed to a depth that does not reach the insulating film 62 adjacent to the hole H7 in the Y direction. In other words, the insulating film 62 is not exposed inside the grooves formed inside the holes H7.

[0152] Next, as shown in Figures 53 and 54, the multiple holes H7 are filled by the sacrificial member 64, the insulating film 65, and the sacrificial member 66. Specifically, the multiple grooves formed in each of the multiple holes H7 are filled by the sacrificial member 64. Then, a thin insulating film 65 is formed inside each of the multiple holes H7. After that, each of the multiple holes H7 is filled by the sacrificial member 66.

[0153] Next, as shown in Figures 55 and 56, multiple holes H8 are formed by removing the sacrificial member 63 and insulating film 62 provided in the region corresponding to the conductive pillar WP2. As a result, multiple sacrificial members 61, which are stacked apart from each other, are exposed inside the multiple holes H8. Subsequently, the sacrificial members 61 are partially removed through the multiple holes H8. This creates grooves that spread concentrically from the center of the multiple holes H8, for each layer in which the sacrificial members 61 are provided. The grooves formed inside the holes H8 are formed to a depth similar to, for example, the grooves formed inside the hole H7 (embedded by the sacrificial member 64). Inside the grooves formed inside the holes H8, adjacent sacrificial members 64 in the Y direction are exposed, but adjacent sacrificial members 64 in the X direction are not exposed.

[0154] Subsequently, the insulating layers 23 and 25 are partially removed through multiple holes H8. As a result, the insulating layers 23 and 25 are removed through grooves formed within the holes H8. Therefore, the grooves formed within the holes H8 become larger in the Z direction than the film thickness of the sacrificial member 61. In other words, multiple insulating layers 23 and 25 are thinned.

[0155] Next, as shown in Figures 57 and 58, the sacrificial member 64 is partially removed through multiple holes H8. This divides the sacrificial member 64 into two parts that sandwich the sacrificial member 66 in the X direction. That is, at the position where the sacrificial member 64 is formed in the Z direction, the portion of the insulating film 65 facing the holes H8 is exposed inside the holes H8. The region where the sacrificial member 64, now divided into two parts, remains corresponds to the region where the memory structure MS is planned to be provided.

[0156] Next, as shown in Figures 59 and 60, the multiple holes H8 are filled by the insulating film 72 and the sacrificial member 69. Specifically, the groove formed by removing the sacrificial member 64 is filled by the insulating film 72. Subsequently, the multiple holes H8 are filled by the sacrificial member 69. The sacrificial member 69 includes, for example, polysilicon.

[0157] As described above, the groove in the hole H8 formed after the removal of the sacrificial member 61 is enlarged in the Z direction due to the removal of the insulating layers 23 and 25, and therefore is not blocked by the insulating film 72. For this reason, the sacrificial member 69 is also formed inside the groove that is not blocked after the insulating film 72 is formed.

[0158] Next, as shown in Figures 61 and 62, a portion of the sacrificial member 66 and insulating film 65 provided in the region corresponding to conductive pillar WP1, and a portion of the sacrificial member 69 and insulating film 72 provided in the region corresponding to conductive pillar WP2 are removed, thereby forming a plurality of holes H9. Inside the holes H9 corresponding to conductive pillar WP1, a plurality of sacrificial members 64, which are stacked at a distance from each other, are exposed. On the other hand, in the plurality of grooves formed in the holes H9 corresponding to conductive pillar WP2, the insulating film 72 formed on the sacrificial member 61 remains.

[0159] Next, multiple sacrificial members 64 are removed through the holes H9 corresponding to the conductive pillar WP1. As a result, multiple grooves are formed in each of the multiple holes H9 corresponding to the conductive pillar WP1.

[0160] Next, as shown in Figures 63 and 64, a portion of the insulating film 72 is removed through a plurality of holes H9. This exposes the sacrificial member 61 inside each of the plurality of grooves formed in each of the plurality of holes H9 corresponding to the conductive pillar WP2.

[0161] Next, as shown in Figures 65 and 66, multiple sacrificial members 61 are removed through multiple holes H9. This connects the multiple holes H9 into one through multiple grooves.

[0162] Next, as shown in Figures 67 and 68, a semiconductor layer 24 is formed through multiple holes H9 that are connected via multiple grooves. As a result, the region of each of the multiple holes H9 where the channel structure CH is to be formed is filled by the semiconductor layer 24. The multiple holes H9 are then separated again by the semiconductor layer 24.

[0163] Next, as shown in Figures 69 and 70, an insulating film 35, a charge storage film 34, and an insulating film 33 are formed through a plurality of holes H9. As a result, each of the plurality of grooves formed in each of the plurality of holes H9 is filled by the laminated film of the insulating film 35, the charge storage film 34, and the insulating film 33.

[0164] Next, as shown in Figures 71 and 72, the multiple holes H9 are filled by the formation of the insulating film 32, the insulating film 31, and the conductive film 30 through the multiple holes H9.

[0165] Subsequently, the upper structure of the stacked structure of the memory cell array 10 is formed. Thus, the memory device 3 is formed.

[0166] 3.3 Effects of the Third Embodiment According to the third embodiment, the region where multiple holes corresponding to the conductive pillars WP1 and WP2 are formed is a laminated structure of an insulating layer 23 and a sacrificial member 61. This makes processing easier than, for example, when the region where multiple holes corresponding to the conductive pillars WP1 and WP2 are formed contains a mixture of regions where a laminated structure of silicon oxide layers and silicon nitride layers is processed and regions where a laminated structure consisting only of silicon oxide layers is processed. Therefore, the increase in manufacturing costs of the memory device 3 can be suppressed.

[0167] Furthermore, multiple holes corresponding to the conductive pillars WP1 and WP2 are formed simultaneously. This allows the process of machining the laminated structure of the insulating layer 23 and the sacrificial member 61 in the Z direction to be completed in a single step. As a result, the increase in manufacturing costs of the memory device 3 can be suppressed.

[0168] Furthermore, when forming multiple holes corresponding to conductive pillars WP1 and WP2, all holes correspond to either conductive pillar WP1 or WP2. This allows for a higher integration density of memory cell transistors MT compared to when some of the collectively formed holes are used as conductive pillars WP1 and WP2.

[0169] 4. Fourth Embodiment Next, a memory device according to the fourth embodiment will be described. The memory device according to the fourth embodiment differs from the third embodiment in that the shape of the memory structure MS is the same for the conductive pillars WP1 and WP2, and the shape of the insulator INS is X-shaped. Below, the configuration and manufacturing method that differ from the third embodiment will be mainly described. The configuration and manufacturing method that are the same as those of the third embodiment will be omitted as appropriate.

[0170] 4.1 Configuration <Circuit Configuration> First, the circuit configuration of the memory cell array according to the fourth embodiment will be described.

[0171] The circuit configuration of the memory cell array 10 in the fourth embodiment is equivalent to the circuit configuration of the memory cell array 10 in the third embodiment. That is, the NAND string NS included in the memory cell array 10 is composed of a plurality of memory cell transistors MT0 to MT7 connected in series, and selection transistors ST1 and ST2 provided at both ends of the plurality of memory cell transistors MT, respectively.

[0172] <Floor layout> Next, the planar layout of the memory cell array according to the fourth embodiment will be described.

[0173] Figure 73 is a plan view showing an example of a planar layout of a memory cell array according to the fourth embodiment. Figure 73 corresponds to Figure 49 in the third embodiment.

[0174] As shown in Figure 73, in the same layer, the memory cell array 10 includes a plurality of conductive pillars WP1 and WP2, a plurality of memory structures MS, a plurality of insulators INS, a channel structure CH, a plurality of word lines WL, and a plurality of contacts V1 and V2.

[0175] Each of the multiple conductive pillars WP1 and WP2 is a conductor having a columnar shape extending in the Z direction. The multiple conductive pillars WP1 and WP2 are arranged in a staggered pattern in the XY plane. Specifically, conductive pillars WP1 and WP2 aligned in the Y direction in the same row are arranged one by one in sequence (alternating). Then, pairs of conductive pillars WP1 and WP2 aligned alternately in the Y direction are arranged with a half-pitch offset in the X direction. Here, half a pitch is, for example, half the distance between the centers of the conductive pillars WP1 and WP2 aligned in the Y direction.

[0176] Furthermore, conductive pillars WP1 and WP2 may have equivalent shapes when viewed in the Z direction. Specifically, since the distance from the center does not change significantly between the portion along the memory structure MS and the portion along the insulator INS, conductive pillars WP1 and WP2 can have a shape close to a perfect circle.

[0177] Each of the multiple insulators INS is an insulator that surrounds the opposing portions of the outer circumference of the corresponding conductive pillars WP1 and WP2. Two insulators INS are provided for each conductive pillar WP1, spaced apart from each other in the Y direction. The portion of the insulator INS that is in contact with the channel structure CH has, for example, a portion formed concentrically around each of the conductive pillars WP1 and WP2. The portion of the insulator INS formed concentrically around each of the conductive pillars WP1 and WP2 has a concave shape such that the channel structure CH penetrates in the X direction. Through these two insulators INS, conductive pillars WP1 and WP2 are arranged alternately in the Y direction in the same row. In this way, the insulators INS insulate conductive pillar WP1 from conductive pillar WP2 that is adjacent to conductive pillar WP1 in the Y direction.

[0178] Each of the multiple memory structures MS is a multilayer film corresponding to the gate structure of a memory cell transistor MT. Two memory structures MS are arranged for each of the conductive pillars WP1 and WP2. Specifically, the two memory structures MS are provided on the outer periphery of each of the conductive pillars WP1 and WP2, separated from each other by an insulator INS. That is, the two memory structures MS corresponding to conductive pillar WP1 are aligned in the X direction so as to sandwich conductive pillar WP1. The two memory structures MS corresponding to conductive pillar WP2 are aligned in the X direction so as to sandwich conductive pillar WP1.

[0179] Then, a structure in which two such memory structures MS are arranged on the outer periphery of a conductive pillar WP1, an insulator INS, two memory structures MS are arranged on the outer periphery of a conductive pillar WP2, and an insulator INS is repeated in this order in the Y direction (hereinafter also referred to as the "column structure"), and these are arranged in the X direction with a half-pitch offset. In the example in Figure 73, an example is shown in which five column structures are arranged in the X direction.

[0180] Each of the multiple channel structures CH is a semiconductor extending in the Y direction. The channel structures CH are arranged between two adjacent column structures in the X direction. The multiple channel structures CH may be separated from each other at both ends in the Y direction, or they may be connected to each other via selection transistors ST1 and ST2 (not shown).

[0181] The memory structure MS, the conductive pillar WP1 flanking the memory structure MS, and the channel structure CH portion function as one memory cell transistor MT. The memory structure MS, the conductive pillar WP2 flanking the memory structure MS, and the channel structure CH portion function as one memory cell transistor MT. The channel structure CH and the portion of the two column structures flanking the channel structure CH that is in contact with the channel structure constitute one NAND string NS. In Figure 73, the four NAND strings NS formed by the five column structures aligned in the X direction and the four channel structures CH positioned between each of the five column structures correspond to string units SU0 to SU3, respectively.

[0182] One end of the NAND string NS in the Y direction is connected to the bit line BL via a selection transistor ST1 (not shown). The other end of the NAND string NS in the Y direction is connected to the source line SL via a selection transistor ST2 (not shown).

[0183] Each of the multiple word lines WL extends in the X direction. The multiple word lines WL are aligned in the Y direction. When viewed in the Z direction, the word lines WL are positioned to overlap with the multiple conductive pillars WP1 and WP2 aligned in the X direction. Conductive pillars WP1 and WP2 are connected to the corresponding word lines WL via contacts V1 and V2, respectively.

[0184] <Cross-sectional structure> Next, the cross-sectional structure of the memory cell array according to the fourth embodiment will be described.

[0185] Figure 74 is a cross-sectional view along the line LXXIV-LXXIV in Figure 73, showing an example of the cross-sectional structure of the memory cell array according to the fourth embodiment. Figure 74 corresponds to Figure 50 in the third embodiment.

[0186] As shown in Figure 74, the memory cell array 10 includes a substrate 20, insulating layers 21, 22, 23, 25, and 26, a semiconductor layer 24, a conductive film 30, insulating films 31, 32, 33, 35, and 73, a charge storage film 34, and conductive layers 51a, 51b, 52a, and 52b.

[0187] The laminated structure, including the substrate 20, insulating layers 21, 22, 23, 25, and 26, and the semiconductor layer 24, is equivalent to that of the third embodiment.

[0188] The conductive film 30 is a conductor extending in the Z direction so as to intersect with the multiple semiconductor layers 24, and functions as a conductive pillar WP1 or WP2. The lower end of the conductive film 30 is located below the lowest semiconductor layer 24 and above the insulating layer 22. The upper end of the conductive film 30 is aligned with, for example, the upper end of the insulating layer 25. The conductive film 30 contains, for example, titanium nitride.

[0189] The memory structure MS, including the insulating films 31, 32, 33, and 35, and the charge storage film 34, is equivalent to that of the third embodiment.

[0190] Each of the multiple insulating films 73 is provided at the same position as each of the multiple semiconductor layers 24 in the Z direction and functions as an insulator INS. The insulating films 73 extend in the XY plane and are provided between two insulating layers 23, or between insulating layers 23 and 25. Therefore, the length (film thickness) of the insulating film 73 in the Z direction is approximately equal to the film thickness of the semiconductor layer 24, and there are no portions that are longer than the film thickness of the semiconductor layer 24. The insulating film 73 includes, for example, silicon oxide.

[0191] The structures of the conductive layers 51a and 51b, and the conductive layers 52a and 52b are the same as those in the second embodiment.

[0192] 4.2 Manufacturing method Figures 75, 77, 79, 81, 83, 85, and 87 are plan views showing an example of a planar layout during the manufacturing process of a memory device according to the fourth embodiment. Figures 76, 78, 80, 82, 84, 86, and 88 are cross-sectional views showing an example of a cross-sectional structure during the manufacturing process of a memory device according to the fourth embodiment. The cross-sectional views shown in Figures 76, 78, 80, 82, 84, 86, and 88 correspond to cross-sections cut at the same position as the LXXIV-LXXIV line shown in Figure 73 in the planar layouts shown in Figures 75, 77, 79, 81, 83, 85, and 87, respectively.

[0193] First, a structure equivalent to that shown in Figures 57 and 58 of the third embodiment is formed by a process equivalent to that of the third embodiment.

[0194] Next, as shown in Figures 75 and 76, the multiple holes H8 are filled by the insulating film 81, the sacrificial member 82, and the sacrificial member 83. Specifically, a thin insulating film 81 is formed within the multiple holes H8. Each of the multiple grooves formed in each of the multiple holes H8 is not blocked by the insulating film 81. Subsequently, each of the multiple grooves formed in each of the multiple holes H8 is filled by the sacrificial member 82. Then, the multiple holes H8 are filled by the sacrificial member 83. The insulating film 81 includes, for example, silicon oxide. The sacrificial member 82 includes, for example, silicon nitride. The sacrificial member 83 includes, for example, polysilicon.

[0195] Next, as shown in Figures 77 and 78, multiple holes H10 are formed by removing the sacrificial member 66 and insulating film 65 provided in the region corresponding to the conductive pillar WP1. When the insulating film 65 is removed, the insulating film 81 exposed inside the holes H10 is also removed. As a result, multiple sacrificial members 64 and 82, which are stacked separately from each other, are exposed inside the holes H10. Subsequently, multiple sacrificial members 82 are removed through the multiple holes H10. As a result, multiple grooves are formed inside the holes H10, and sacrificial members 83 are exposed within these grooves.

[0196] Next, as shown in Figures 79 and 80, the multiple holes H10 are filled by the insulating film 73 and the sacrificial member 84. Specifically, the groove formed by removing the sacrificial member 82 is filled by the insulating film 73. Subsequently, the multiple holes H10 are filled by the sacrificial member 84. The sacrificial member 84 includes, for example, polysilicon.

[0197] Next, as shown in Figures 81 and 82, a portion of the sacrificial member 84 and insulating film 73 provided in the region corresponding to conductive pillar WP1, and a portion of the sacrificial member 83 and insulating film 81 provided in the region corresponding to conductive pillar WP2 are removed, thereby forming a plurality of holes H11. Inside the holes H11 corresponding to conductive pillar WP1, a plurality of sacrificial members 64 and 82, which are stacked at a distance from each other, are exposed.

[0198] Next, multiple sacrificial members 82 are removed through the holes H11 corresponding to the conductive pillar WP2. As a result, multiple grooves are formed in each of the multiple holes H11 corresponding to the conductive pillar WP2. Note that, since an insulating film 81 is formed on the sacrificial members 61 inside the multiple grooves in each of the multiple holes H11 corresponding to the conductive pillar WP2, the sacrificial members 61 are not exposed.

[0199] Next, multiple sacrificial members 64 are removed through the holes H11 corresponding to conductive pillar WP1. As a result, multiple grooves are formed in each of the multiple holes H11 corresponding to conductive pillar WP1, and the sacrificial members 61 are exposed inside these grooves. Subsequently, multiple sacrificial members 61 are removed through the holes H11 corresponding to conductive pillar WP1. Furthermore, the insulating film 81 is removed through the hole H11 corresponding to conductive pillar WP2. As a result, the multiple holes H11 are connected into one via the multiple grooves.

[0200] Next, as shown in Figures 83 and 84, a semiconductor layer 24 is formed through multiple holes H11 that are connected via multiple grooves. As a result, the region of each of the multiple holes H11 where the channel structure CH is to be formed is filled by the semiconductor layer 24. The multiple holes H11 are then separated again by the semiconductor layer 24.

[0201] Next, as shown in Figures 85 and 86, an insulating film 35, a charge storage film 34, and an insulating film 33 are formed through a plurality of holes H11. As a result, each of the plurality of grooves formed in each of the plurality of holes H11 is filled by the laminated film of the insulating film 35, the charge storage film 34, and the insulating film 33.

[0202] Next, as shown in Figures 87 and 88, the multiple holes H11 are filled by the formation of an insulating film 32, an insulating film 31, and a conductive film 30 through the multiple holes H11.

[0203] Subsequently, the upper structure of the stacked structure of the memory cell array 10 is formed. Thus, the memory device 3 is formed.

[0204] 4.3 Effects of the Fourth Embodiment According to the fourth embodiment, the region where multiple holes corresponding to the conductive pillars WP1 and WP2 are formed is a laminated structure of an insulating layer 23 and a sacrificial member 61. This makes processing easier than, for example, when the region where multiple holes corresponding to the conductive pillars WP1 and WP2 are formed contains a mixture of regions where a laminated structure of silicon oxide layers and silicon nitride layers is processed and regions where a laminated structure consisting only of silicon oxide layers is processed. Therefore, the increase in manufacturing costs of the memory device 3 can be suppressed.

[0205] Furthermore, multiple holes corresponding to the conductive pillars WP1 and WP2 are formed simultaneously. This allows the process of machining the laminated structure of the insulating layer 23 and the sacrificial member 61 in the Z direction to be completed in a single step. As a result, the increase in manufacturing costs of the memory device 3 can be suppressed.

[0206] Furthermore, when forming multiple holes corresponding to conductive pillars WP1 and WP2, all holes correspond to either conductive pillar WP1 or WP2. This allows for a higher integration density of memory cell transistors MT compared to when some of the collectively formed holes are used as conductive pillars WP1 and WP2.

[0207] 5. Other variations Furthermore, various modifications can be applied to the first, second, third, and fourth embodiments described above.

[0208] In the first embodiment described above, the case in which the conductive pillars WP and TP are arranged in a square orientation when viewed in the Z direction was explained, but the invention is not limited to this. For example, the conductive pillars WP and TP may be arranged in a staggered arrangement when viewed in the Z direction.

[0209] In the modified example of the first embodiment described above, the case in which the conductive pillar WP and the insulating pillar RP are arranged in a square orientation when viewed in the Z direction was explained, but the invention is not limited to this. For example, the conductive pillars WP and TP may be arranged in a staggered arrangement when viewed in the Z direction.

[0210] In the second, third, and fourth embodiments described above, the case in which the conductive pillars WP1 and WP2 are arranged in a staggered pattern when viewed in the Z direction was explained, but the invention is not limited to this. For example, the conductive pillars WP1 and WP2 may be arranged in a square pattern when viewed in the Z direction.

[0211] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0212] 1…Memory system 2…Memory controller 3…Memory devices 10…Memory cell array 11... Command Register 12…Address Register 13… Sequencer 14…Driver module 15… Raw Decoder Module 16…Sense Amp Module 20... Circuit board 21, 22, 23, 25, 26… Insulating layer 24... Semiconductor layer 30, 40… Conductive film 31, 32, 33, 35, 41, 41A, 62, 65, 67, 71, 72, 73, 81… Insulating film 34...Charge storage film 51, 52… Conductive layer 61, 63, 64, 66, 68, 69, 82, 83, 84… Sacrificial members

Claims

1. A first conductive pillar and a second conductive pillar, each extending in a first direction and aligned in a second direction intersecting the first direction, Each of the first semiconductor layers extends in the second direction at a first position in the first direction, sandwiching the first conductive pillar and the second conductive pillar in a third direction intersecting the first and second directions, A first insulating film is provided at the first position between the first semiconductor layer and the second semiconductor layer and between the first conductive pillar and the second conductive pillar, and has a first portion along a circle centered on the first conductive pillar on the surfaces facing the first semiconductor layer and the second semiconductor layer, A first charge storage film is provided between the first conductive pillar and the first semiconductor layer at the first position, A second charge storage film is provided between the first conductive pillar and the second semiconductor layer at the first position and is separated from the first charge storage film, Equipped with, Memory device.

2. The first insulating film further has a second portion along a circle centered on the second conductive pillar on the surface facing the first semiconductor layer and the second semiconductor layer. The memory device according to claim 1.

3. The first portion and the second portion of the first insulating film form a convex shape. The memory device according to claim 2.

4. The first portion and the second portion of the first insulating film form a concave shape. The memory device according to claim 2.

5. A third charge storage film is provided between the second conductive pillar and the first semiconductor layer at the first position, A fourth charge storage film is provided between the second conductive pillar and the second semiconductor layer at the first position and is separated from the third charge storage film, Furthermore, The first charge storage film and the second charge storage film have different shapes from the third charge storage film and the fourth charge storage film. The memory device according to claim 1.

6. The first charge storage film and the second charge storage film are shorter than the third charge storage film and the fourth charge storage film. The memory device according to claim 5.

7. The first insulating film surrounds the first conductive pillar, The memory device according to claim 1.

8. The first insulating film further has a third portion along a circle centered at a position different from that of the first conductive pillar and the second conductive pillar on the surface facing the first semiconductor layer and the second semiconductor layer. The memory device according to claim 1.

9. Each extends in the second direction at a second position different from the first position in the first direction, and a third semiconductor layer and a fourth semiconductor layer sandwich the first conductive pillar and the second conductive pillar in the third direction, A second insulating film is provided at the second position between the third semiconductor layer and the fourth semiconductor layer and between the first conductive pillar and the second conductive pillar, and has a fourth portion along a circle centered on the first conductive pillar on the surface facing the third semiconductor layer and the fourth semiconductor layer, A fifth charge storage film is provided between the first conductive pillar and the third semiconductor layer at the second position, A sixth charge storage film is provided at the second position between the first conductive pillar and the fourth semiconductor layer, and is separated from the fifth charge storage film, It also has, The memory device according to claim 1.

10. The first insulating film and the second insulating film are separated from each other. The memory device according to claim 9.

11. The first insulating film and the second insulating film are formed as a continuous film. The memory device according to claim 9.

12. The invention further comprises an insulating layer provided between the first insulating film and the second insulating film. The memory device according to claim 9.

13. Each of the third and fourth conductive pillars extends in the first direction, is aligned in the second direction, and is provided on the opposite side of the first and second conductive pillars relative to the first semiconductor layer. The first conductive pillar, the second conductive pillar, the third conductive pillar, and the fourth conductive pillar are arranged in a square orientation when viewed in the first direction. The memory device according to claim 1.

14. Each of the third and fourth conductive pillars extends in the first direction, is aligned in the second direction, and is provided on the opposite side of the first and second conductive pillars relative to the first semiconductor layer. The first conductive pillar, the second conductive pillar, the third conductive pillar, and the fourth conductive pillar are arranged in a staggered pattern when viewed in the first direction. The memory device according to claim 1.

15. The circuit board is further equipped, The first direction is a direction substantially perpendicular to the substrate, The second and third directions are substantially horizontal with respect to the substrate. The memory device according to claim 1.

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