Printed circuit board

Abstract

This invention provides a printed circuit board that allows for electrical connection to the underside when embedding electronic components such as interconnect bridges, ensuring stability and reliability even when connections are made at a fine pitch, thereby improving the performance and efficiency of semiconductor packages while efficiently managing manufacturing costs. [Solution] The present invention relates to a printed circuit board comprising an insulator, a cavity penetrating a portion of the insulator and having a bottom surface, a plurality of wiring layers each disposed within the insulator, an electronic component at least partially disposed within the cavity, and a sealing material covering at least a portion of the insulator and the electronic component and filling at least a portion of the cavity, wherein one of the plurality of wiring layers includes a pad that is at least partially exposed from the insulator through the cavity, the electronic component is connected to the pad via a connecting member, and the pad contains a nanotwin metal.

Description

Technical Field

[0001] The present invention relates to a printed circuit board that can be used as a package substrate or the like.

Background Art

[0002] Currently, in the semiconductor package market, as the amount of data used in data centers, automotive electronics, AI solutions, etc. has exploded, the competition in packaging technologies related to high-performance computing for processing and storing this data has become increasingly fierce. However, with the higher performance of semiconductors, the transistor density and power density have increased, resulting in problems such as a large increase in costs, process complexity, and fab investment costs in the semiconductor design and manufacturing processes. To solve this, efforts have continued to overcome the limitations occurring in all processes of semiconductors through innovation in packaging technologies. For example, various packaging platforms such as 2.nD, 2.5D, and 3D have been introduced, and their own advanced packaging technologies have been developed. In particular, as the number of HBMs increases with the improvement of GPU and AI performance, as a solution for large substrates and die-to-die connections, technologies for embedding interconnect bridges in package substrates have been actively developed. On the other hand, currently disclosed interconnect bridge embedding technologies usually attach interconnect bridges inside the substrate using DAF or the like, and thus electrical connection is only possible on the upper side of the interconnect bridge. In this case, in addition to signal transmission loss, there may also be some disadvantages in terms of power characteristics.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the various objects of the present invention is to provide a printed circuit board that can ensure stability and reliability even when electrical connection is possible on the lower side and connection is possible at a fine pitch when embedding electronic components such as interconnect bridges.

[0004] Another of the various objectives of the present invention is to provide a printed circuit board that can efficiently manage manufacturing costs while improving the performance and efficiency of semiconductor packages. [Means for solving the problem]

[0005] One of the various solutions proposed in this invention is to form a blind cavity having a bottom surface in a multilayer substrate structure, place and embed electronic components such as interconnect bridges in the cavity, connect the electronic components to pads exposed on the bottom surface of the cavity using connecting members, and at this time, form the pads exposed on the bottom surface of the cavity with a metal layer containing nanotwin metal.

[0006] For example, a printed circuit board according to one example includes an insulator, a cavity penetrating a portion of the insulator and having a bottom surface, a plurality of wiring layers each disposed within the insulator, an electronic component at least partially disposed within the cavity, and a sealing material covering at least a portion of the insulator and the electronic component and filling at least a portion of the cavity, wherein one of the plurality of wiring layers includes a pad that is at least partially exposed from the insulator through the cavity, the electronic component is connected to the pad via a connecting member, and the pad may contain a nanotwin metal.

[0007] For example, a printed circuit board according to one example includes a plurality of insulating layers, a plurality of wiring layers each disposed within the plurality of insulating layers, a cavity that penetrates one or more of the plurality of insulating layers and exposes at least a portion of one of the wiring layers from the plurality of insulating layers, an interconnect bridge in which at least a portion is disposed within the cavity, and a sealing material disposed on the plurality of insulating layers, covering at least a portion of the interconnect bridge and filling at least a portion of the cavity, wherein one of the wiring layers contains nanotwinned copper, and at least a portion of the exposed part of one of the wiring layers is connected to the interconnect bridge via a connecting member. [Effects of the Invention]

[0008] One of the various effects of the present invention is to provide a printed circuit board that allows for electrical connection to the underside when embedding electronic components such as interconnect bridges, and that ensures stability and reliability even when connections are made at a fine pitch.

[0009] Another effect of the present invention is that it can provide a printed circuit board that can improve the performance and efficiency of semiconductor packages while also efficiently managing manufacturing costs. [Brief explanation of the drawing]

[0010] [Figure 1] This is a block diagram illustrating an example of an electronic equipment system. [Figure 2] This is a perspective view showing a schematic example of an electronic device. [Figure 3] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 4] Figure 3 is a schematic cross-sectional view showing an enlarged view of the R region of the printed circuit board. [Figure 5] Figure 3 is a schematic cross-sectional view showing an example of the manufacturing process of a printed circuit board. [Figure 6] Figure 3 is a schematic cross-sectional view showing an example of the manufacturing process of a printed circuit board. [Modes for carrying out the invention]

[0011] The present invention will be described below with reference to the attached drawings. In the drawings, the shape and size of elements may be enlarged or reduced (or highlighted or simplified) for clearer explanation.

[0012] Figure 1 is a block diagram illustrating an example of an electronic equipment system.

[0013] Referring to the drawing, the electronic device 1000 houses the main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, etc. These, in combination with other electronic components described later, form various signal lines 1090.

[0014] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). It goes without saying that other forms of chip-related electronic components may also be included. Furthermore, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may also be in the form of a package that includes the chips and electronic components mentioned above.

[0015] Network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth®, 3G, 4G, 5G, and later. It also goes without saying that network-related component 1030 may be combined with chip-related component 1020.

[0016] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, and MLCCs (multi-layer ceramic condensers). However, they are not limited to these, and may also include passive elements in the form of chip components used for various other applications. It goes without saying that other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0017] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that are or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. However, it is not limited to these, and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. Needless to say, other electronic components used for various purposes may also be included, depending on the type of electronic device 1000.

[0018] Electronic device 1000 can be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smartwatch, automobile, server, etc. However, it is not limited to these, and it goes without saying that it may be any other electronic device that processes data.

[0019] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0020] Referring to the drawings, the electronic device could be, for example, a smartphone 1100. Inside the smartphone 1100 is a motherboard 1110, to which various components 1120 are physically and / or electrically connected. In addition, other components, such as a camera module 1130 and / or a speaker 1140, may or may not be physically and / or electrically connected to the motherboard 1110. Some of the components 1120 may be the chip-related components described above, and may, for example, be a component package 1121, but are not limited to this. The component package 1121 may be in the form of a printed circuit board on which electronic components, including active and / or passive components, are mounted on the surface. Alternatively, the component package 1121 may be in the form of a printed circuit board with the active and / or passive components built-in. On the other hand, it goes without saying that the electronic device is not necessarily limited to a smartphone 1100, but may be other electronic devices as described above.

[0021] FIG. 3 is a cross-sectional view schematically showing an example of a printed circuit board.

[0022] FIG. 4 is a cross-sectional view schematically showing an enlarged view of the R region of the printed circuit board of FIG. 3.

[0023] Referring to the drawings, a printed circuit board 100 according to an example may include an insulator 115, a cavity C that penetrates a part of the insulator 115 and has a bottom surface, a plurality of wiring layers 121 respectively disposed in the insulator 115, a plurality of via layers 131 respectively disposed in the insulator 115 and connected to one or more of the plurality of wiring layers 121, an electronic component 150 at least partially disposed in the cavity C, and a sealing material 112 that covers at least a part of each of the insulator 115 and the electronic component 150 and fills at least a part of the cavity C. At least a part of any one of the plurality of wiring layers 121, i.e., wiring layer M, may be exposed from the insulator 115 through the cavity C. The exposed at least a part may include a pad P. The electronic component 150 may be connected to the pad P via a connection member 160. Any one of the plurality of wiring layers 121, i.e., wiring layer M, and any one of the plurality of via layers 131 connected thereto, i.e., via layer V, may each include a nanobainite metal, for example, nanobainite copper. The pad P included in any one of the wiring layers M may also include a nanobainite metal, for example, nanobainite copper. The connection member 160 may include solder. An intermediate layer 170 may be disposed between the pad P and the connection member 160.

[0024] Thus, in this example, the printed circuit board 100 allows the electronic components 150 placed and embedded in the cavity C to be electrically connected to any of the multiple wiring layers 121 M on the underside, thereby preventing signal transmission loss and providing a structure that is more advantageous in terms of power characteristics. In this case, the pads P of any of the wiring layers M connected to the connecting member 160 such as solder can contain nanotwin metal, for example nanotwin copper, which can suppress the generation and growth of Kirkendall voids and improve reliability. For example, such a nanotwin copper structure has many triple points where twin boundaries and grain boundaries intersect, which can hinder the movement of vacancies (v), thereby suppressing the generation and growth of Kirkendall voids and the like as described above. Therefore, when multiple first electrodes 151 having a fine pitch, positioned below the electronic component 150, are thermocompression-bonded to multiple pads P via multiple connecting members 160, superior stability and reliability can be ensured. For example, in the intermediate layer 170, or the intermetallic compound (IMC) layer contained therein, reliability can be ensured by preventing the occurrence of voids and cracks through the effects described above. On the other hand, an insulating material 180 can be further positioned below the cavity C, filling at least a portion of the area below the cavity C and covering at least a portion of each of the multiple first electrodes 151, the multiple pads P, and the multiple connecting members 160, thereby further improving the stability and reliability described above.

[0025] On the other hand, a printed circuit board 100 according to one example may further include a build-up wiring layer 122 disposed on a sealing material 112, a plurality of first build-up vias 132 that penetrate at least a portion of the sealing material 112 and connect at least a portion of the build-up wiring layer 122 to a plurality of second electrodes 152 disposed on the upper side of an electronic component 150, and one or more second build-up vias 133 that penetrate at least a portion of both the sealing material 112 and the insulator 115 together and connect at least another portion of the build-up wiring layer 122 to the uppermost wiring layer 121 among a plurality of wiring layers 121. The electronic component 150 may be an interconnect bridge with a plurality of first electrodes 151 disposed on the lower side and a plurality of second electrodes 152 disposed on the upper side. Various forms of circuits and vias can be arranged inside the electronic component 150, for example, inside an interconnect bridge, to provide electrical connection paths between a plurality of first electrodes 151, electrical connection paths between a plurality of second electrodes 152, and / or electrical connection paths between a plurality of first and second electrodes 151, 152. The interconnect bridge may be, but is not limited to, a silicon interconnect bridge, and may also be an organic substrate containing high-density wiring, i.e., an organic interconnect bridge.

[0026] Thus, in the example printed circuit board 100, the electronic component 150 can be electrically connected to multiple wiring layers 121 and / or build-up wiring layers 122 on both the lower and upper sides via multiple first and second electrodes 151 and 152. Therefore, when the electronic component 150 includes an interconnect bridge, as described above, the example printed circuit board 100 can prevent signal transmission loss, have a more advantageous structure in terms of power characteristics, and can be used as an interconnect bridge embedded package substrate that enables die-to-die interconnection in the 2.1D form. In this case, the performance and efficiency of the semiconductor package can be improved while manufacturing costs can be efficiently managed. In addition, as described above, it can have excellent stability and reliability.

[0027] On the other hand, if necessary, multiple insulating layers, multiple wiring layers, and multiple via layers can be further arranged below the insulator 115 of the printed circuit board 100 according to one example. For example, the structure of the printed circuit board 100 according to one example can be applied to the upper region of a multilayer core board including a core layer or a multilayer core board with a coreless structure. For example, the structure of the printed circuit board 100 according to one example can be applied and utilized as at least a part in a wider variety of multilayer board structures.

[0028] In the following section, the components of an example printed circuit board 100 will be described in more detail with reference to the drawings.

[0029] The insulator 115 may include a plurality of insulating layers 111. The plurality of wiring layers 121 and the plurality of via layers 131 may each be arranged within the plurality of insulating layers 111. The plurality of insulating layers 111 and the sealing material 112 may each include an organic insulating material. As the organic insulating material, thermosetting resins such as epoxy resin, thermoplastic resins such as polyimide, or materials in which these insulating resins are mixed with an inorganic filler such as silica, or resins impregnated with an inorganic filler into a core material such as glass fiber, for example, prepreg, ABF (Ajinomoto Build-up Film), PID (Photo Imageble Dielectric), RCC (Resin Coated Copper) insulating materials can be used, but are not limited to these. The number of layers of the plurality of insulating layers 111 is not particularly limited. The plurality of insulating layers 111 may be integrated with each other and their boundaries may not be separated, or they may have boundaries separated from each other.

[0030] The multiple wiring layers 121 and build-up wiring layers 122 can each contain a metal. Examples of metals include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Preferably, copper (Cu) can be included. Each of the multiple wiring layers 121 and build-up wiring layers 122 can each include a seed layer and a metal layer formed by plating on the seed layer. The seed layer can be rolled copper foil or electrolytic copper foil of RCC (Resin Clad Copper). Alternatively, the seed layer can be formed by electroless copper plating or electroless nickel plating, and may also be formed by electrolytic nickel plating. The metal layer can be formed by electrolytic plating, or by plating to form nanotwinned copper. Each of the multiple wiring layers 121 and build-up wiring layers 122 can perform various functions depending on the design of the layer. For example, they can include ground patterns, power patterns, signal patterns, etc. These patterns can each include line, trace, plane, pad, and so on.

[0031] Each of the multiple via layers 131 may include a connecting via. Each connecting via of the multiple via layers 131, as well as the first and second build-up vias 132 and 133, may each contain a metal, which may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Preferably, it may contain copper (Cu). Each of the multiple via layers 131, as well as the first and second build-up vias 132 and 133, may each include a seed layer formed on the wall surface of a through-hole formed on the wall surface of a via hole, and a metal layer formed by plating on the seed layer. The seed layer may be formed by electroless copper plating or electroless nickel plating, or it may be formed by electrolytic nickel plating. The metal layer may be formed by electrolytic plating, or it may be formed by plating to form nanotwinned copper. Each of the connecting vias in the multiple via layers 131, as well as the first and second build-up vias 132 and 133, can perform various functions depending on the design. For example, they can include ground vias, power vias, signal vias, etc. Each of the connecting vias in the multiple via layers 131, as well as the first and second build-up vias 132 and 133, can have a substantially tapered shape. Each of the connecting vias in the multiple via layers 131, as well as the first and second build-up vias 132 and 133, can be multiple in number.

[0032] Any of the wiring layers 121, specifically wiring layer M, and any of the via layers 131, specifically via layer V, can each contain a nanotwinned metal, more specifically nanotwinned copper, as described above. For example, a pad P contained in any of the wiring layers M can contain a nanotwinned metal, more specifically nanotwinned copper. The nanotwinned copper can contain a plurality of columnar grains, and at least a portion of the plurality of columnar grains can contain nanotwinings. A metal layer containing such nanotwinned copper can be formed on a seed layer. The seed layer can contain copper, nickel, etc., which can be used in printed circuit boards, such as package substrates, and can include, for example, electrolytic copper foil, rolled copper foil, electrolytic copper layer, electroless copper layer, electrolytic nickel layer, and / or electroless nickel layer. In this case, the seed layer can contain a crystal structure that is not preferentially oriented on the (111) plane, for example, random orientation, preferentially oriented on the (200) plane, and / or preferentially oriented on the (220) plane. For example, when measuring and analyzing the crystal orientation state of a seed layer using SAED (Selected Area Electron Diffraction), the (111) plane and other (hkl) planes may both exhibit ring patterns of similar intensity. In this case, it is difficult to consider that the (111) plane is predominantly oriented. On the other hand, if the (111) plane is strongly oriented, the (111) plane may exhibit a partial ring or point morphology, while other (hkl) planes may exhibit a relatively low-intensity partial ring morphology. Thus, when a seed layer contains a crystal structure that does not preferentially orient to the (111) plane, the

[0111] direction of at least one columnar crystal grain containing nanotwinned copper nanotwinned in the metal layer can be tilted at an angle (θ) greater than 0 degrees and less than or equal to 25 degrees with respect to the growth direction. In this case, stability and reliability can be more effectively improved. The metal layer can have (111) plane nanotwinned copper accounting for 80% to less than 100% in cross-section and 90% to less than 100% on the surface.Furthermore, the metal layer can have a thickness of approximately 1 μm to 10 μm, or approximately 1 μm to 5 μm, and the size of at least one columnar crystal grain containing nanotwinned copper can also be approximately 1 μm to 10 μm, or approximately 1 μm to 5 μm. A transition layer can be placed in the boundary region between the metal layer and the seed layer, and the transition layer can include a part of the seed layer and a part of the initial growth layer of the metal layer. The transition layer can be formed with a thickness of 20% or less of the thickness of the metal layer, but is not limited to this.

[0033] On the other hand, a randomly oriented crystal structure can mean that in a polycrystalline metal or thin film structure, the crystal grains are not aligned in a specific direction but are randomly distributed in all directions. This can occur when, in a metallic structure, each crystal grain is positioned independently of the others and no preferential orientation is observed. For example, no dominant orientation is shown for any particular plane, and the directions of all crystal grains are distributed independently. This can be measured using methods such as X-ray diffraction (XRD), pole figure, SAED (Selected Area Electron Diffraction), and EBSD (Electron Backscatter Diffraction). For example, in X-ray diffraction (XRD) data, the peak intensity of each diffracted plane can be approximately the same as or similar to the relative intensity ratio in an ideal polycrystalline sample. To quantitatively evaluate this, a texture coefficient can be calculated, and the texture coefficient of all planes can be close to 1. Alternatively, the intensity can be uniformly distributed in a pole figure. Or, in electron diffraction (SAED or EBSD), the orientation can be distributed in various directions, and no dominance of a particular direction can be shown.

[0034] Furthermore, a crystal structure with preferred orientation of the (200) plane can mean that in a polycrystalline metal or thin film structure, the (200) plane, a specific crystal plane, is preferred over other planes or is primarily aligned. This can occur in a metallic crystal structure when the lattice plane indicated by Miller index 200 preferentially grows or is oriented due to specific process conditions, energy states, or interactions with the substrate. This can be measured using methods such as X-ray diffraction (XRD), pole figures, SAED (Selected Area Electron Diffraction), and EBSD (Electron Backscatter Diffraction). For example, in X-ray diffraction (XRD) data, the preferred orientation of the (200) plane can be confirmed by the relative prominence of the (200) peak compared to other peaks. To quantitatively evaluate this, a texture coefficient can be calculated, and if the texture coefficient of the (200) plane is relatively large compared to other planes, for example, if it is 1.5 or greater, it can be determined that the (200) plane has preferred orientation. Alternatively, the orientation can be confirmed by analyzing the diffraction radius and intensity of the (200) plane in the pole figure. Or, the preferred orientation can be confirmed by analyzing the fraction and orientation distribution of crystal grains having the (200) plane direction in electron diffraction (SAED or EBSD).

[0035] Furthermore, a crystal structure with preferred orientation of the (220) plane can mean that in a polycrystalline metal or thin film structure, the (220) plane, a specific crystal plane, is preferred or primarily aligned to other planes. This can occur in a metallic crystal structure when the lattice plane indicated by Miller index 220 preferentially grows or is oriented due to specific process conditions, energy states, or interactions with the substrate. This can be measured using methods such as X-ray diffraction (XRD), pole figures, SAED (Selected Area Electron Diffraction), and EBSD (Electron Backscatter Diffraction). For example, in X-ray diffraction (XRD) data, the preferred orientation of the (220) plane can be confirmed by the relative prominence of the (220) peak compared to other peaks. To quantitatively evaluate this, a texture coefficient can be calculated, and if the texture coefficient of the (220) plane is relatively large compared to other planes, for example, if it is 1.5 or greater, it can be determined that the (220) plane has preferred orientation. Alternatively, the orientation can be confirmed by analyzing the diffraction radius and intensity of the (220) plane in the pole figure. Or, the preferred orientation can be confirmed by analyzing the fraction and orientation distribution of crystal grains having the (220) plane direction in electron diffraction (SAED or EBSD).

[0036] The electronic component 150 may include various types of active and / or passive elements. For example, the electronic component 150 may include various types of integrated circuit dies or semiconductor chips. The electronic component 150 may also be an interconnect bridge. The interconnect bridge may be, but is not limited to, a silicon interconnect bridge, and may also be an organic substrate including high-density wiring, i.e., an organic interconnect bridge. A plurality of first electrodes 151 may be arranged on the lower surface of the electronic component 150, and a plurality of second electrodes 152 may be arranged on the upper surface. Various forms of circuits and vias may be arranged inside the electronic component 150 to provide electrical connection paths between the plurality of first electrodes 151, electrical connection paths between the plurality of second electrodes 152, and / or electrical connection paths between the plurality of first and second electrodes 151, 152.

[0037] The first and second electrodes 151 and 152 may contain metal. The metal may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Preferably, it may contain copper (Cu), but is not limited thereto. The first and second electrodes 151 and 152 may each have a microbump structure. The first and second electrodes 151 and 152 may each have a structure combining pads and microbumps. There may be multiple first and second electrodes 151 and 152.

[0038] The connecting member 160 may include a conductive material, such as solder. The solder may include tin (Sn), which is a low-melting-point metal. For example, the solder may be, but is not limited to, a tin (Sn)-silver (Ag)-copper (Cu) alloy. The connecting member 160 may be in the form of a ball or a bump. There may be multiple connecting members 160.

[0039] The intermediate layer 170 can be an intermetallic compound (IMC) layer formed by reflow after solder bumps are formed on a surface treatment layer formed on the pad P. The intermediate layer 170 can consist of multiple layers, and may include, but is not limited to, one or more of, a Cu3Sn layer 171 and a Cu6Sn5 layer 172. On the other hand, the surface treatment layer can be formed by various methods and materials as described later.

[0040] The insulating material 180 can provide electrical insulation, thermal stability, and mechanical stability. The insulating material 180 may include, but is not limited to, a nonconductive film (NCF), and may also include nonconductive adhesives (NCA), polyimide films, silicone-based adhesives or films, UV-curable films or adhesives, heat-melt fused films, polyurethane adhesives, thermoplastic polymers, and the like.

[0041] Figures 5 and 6 are schematic cross-sectional views illustrating an example of the manufacturing process of the printed circuit board shown in Figure 3.

[0042] Referring to Figure 5, first, the first wiring layer 121 can be formed in a circuit formation process, the first insulating layer 111 covering it can be formed in an insulating material lamination process, via holes penetrating the first insulating layer 111 can be formed by laser processing, and the first via layer 131 and the second wiring layer 121 can be formed in a circuit formation process. On the other hand, the first via layer 131 and the second wiring layer 121 can be via layers V and wiring layers M containing a nanotwin metal, such as nanotwin copper. Such via layers V and wiring layers M can be formed in a seed layer formation process, such as electroless copper plating or electroless nickel plating, and a plating process for forming a nanotwin metal layer applied on the seed layer, such as a plating process for forming nanotwin copper. The wiring layer M can be formed to include a plurality of pads P having a fine pitch for component mounting. Next, a plurality of insulating layers 111, a plurality of wiring layers 121, and a plurality of via layers 131 can be formed in a build-up process. The plurality of insulating layers 111 can constitute an insulator 115. Next, a blind cavity C can be formed by blasting or other processes. Multiple pads P can be exposed through the cavity C. Multiple pads P can be used as a stopper layer for blasting.

[0043] Referring to Figure 6, a surface treatment layer 175 can then be formed on the surface of the pad P. The surface treatment layer 175 can be formed by electrolytic gold plating, electroless gold plating, electroless tin plating, electroless silver plating, electroless nickel plating / substitution gold plating, OSP (Organic Solderability Preservative), ENIG (Electroless Nickel Immersion Gold), ImSn (Immersion Tin), ImAg (Immersion Silver), DIG (Direct Immersion Gold), and / or HASL (Hot Air Solder Leveling), etc. Next, electronic components 150 can be placed in the cavity C and mounted using connecting members 160. For example, multiple first electrodes 151 and multiple pads P can be connected using multiple connecting members 160, and then a reflow process can be performed. At this time, an intermediate layer 170 can be formed. On the other hand, if necessary, an insulating material 180 such as a non-conductive film (NCF) can be formed on the underside of the cavity C in an insulating material lamination process or a coating process. For example, after aligning the electronic components 150 using a non-conductive film (NCF), multiple first electrodes 151 and multiple pads P can be joined by a thermal compression method using solder. Next, sealing material 112 can be formed on multiple insulating layers 111, covering at least a portion of the electronic components 150 and filling at least a portion of the cavity C, through insulating material coating or insulating material lamination processes. Furthermore, via hole formation processes such as laser processing and circuit formation processes can be performed on the sealing material 112 to form a build-up wiring layer 122 and multiple first and second build-up vias 132 and 133. On the other hand, multiple first build-up vias 132 can be connected to multiple second electrodes 152, respectively. Therefore, they can be formed with a fine pitch.

[0044] Through a series of processes, the printed circuit board 100 according to the example described above can be manufactured. The rest of the explanation may be substantially the same as that described for the printed circuit board 100 according to the example. It goes without saying that the contents described in the example of manufacturing can be applied substantially the same way to the printed circuit board 100 according to the example described above.

[0045] In this invention, the expression "cover" can include not only covering the entire surface but also covering at least a portion of it, and can include not only direct covering but also indirect covering. Similarly, the expression "fill" can include not only completely filling the surface but also filling at least a portion of it, and can also include roughly filling the surface. For example, it can include cases where there are some gaps or voids. Furthermore, the expression "enclose" can include not only completely enclosing the surface but also partially enclosing and roughly enclosing it. Moreover, "expose" can include not only completely exposing the surface but also partially exposing it, and exposure can mean exposing the structure from being embedded. For example, a cavity exposing a pad may mean exposing the pad from an insulator, and a surface treatment layer or the like may be further placed on the exposed pad.

[0046] In this invention, the determination can be made by including process errors, positional deviations, and measurement errors that occur during the manufacturing process. For example, having a substantially certain shape can include not only cases where the shape is exactly that, but also cases where it is roughly that shape. Similarly, being substantially tapered can include not only a completely tapered form, but also a roughly tapered form. This can be determined, for example, from the overall shape.

[0047] In this invention, "cross-sectional" can mean the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when an object is viewed from the side. Furthermore, "planar" can mean the planar shape when an object is cut horizontally, or the planar shape when an object is viewed from above or below.

[0048] In this invention, terms such as "lower side," "lower part," and "lower surface" are used for convenience to mean the downward direction relative to the cross-section of the drawing, while terms such as "upper side," "upper part," and "upper surface" are used to mean the opposite direction. However, this is merely a definition of direction for explanatory purposes, and it goes without saying that the scope of rights in the patent claims is not particularly limited by such descriptions of direction, and the concepts of "up" and "down" can change at any time.

[0049] In this invention, the term "connected" includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" includes both physical connection and non-connection. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0050] In this invention, the crystal structure, thickness, and other properties can be measured based on the cross-section obtained by polishing or cutting the printed circuit board. For example, after obtaining a sample including the cut cross-section, necessary experiments can be performed based on it. The cut cross-section can be a vertical or horizontal cross-section, and the respective values ​​can be measured based on the required cut cross-section. On the other hand, when measuring values, if the values ​​are not constant, the values ​​can be determined by the average value of the values ​​measured at any five locations.

[0051] The expression "example" as used in this invention does not mean that each embodiment is identical to the others, but is provided to highlight and explain the unique and distinct features of each. However, the examples presented above do not preclude their implementation in combination with features of other examples. For example, even if a matter described in one example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that contradicts or is contrary to that description.

[0052] The terms used in this invention are for illustrative purposes only and are not intended to limit the invention. In this context, singular expressions include plural expressions unless they clearly mean something different in context. [Explanation of Symbols]

[0053] 1000 electronic equipment 1010 Mainboard 1020 Chip-related components 1030 Network-related components 1040 Other parts 1050 Camera 1060 Antenna 1070 Display 1080 Battery 1090 signal line 1100 Smartphone 1110 Motherboard 1120 parts 1121 Component Package 1130 Camera Module 1140 speaker 100 Printed Circuit Boards 111 Insulating layer 112 Sealing material 115 Insulator 121 Wiring layer 122 Build-up wiring layer 131 Beer Layer 132, 133 Build-up beer 150 Electronic Components 151, 152 electrode 160 Connecting Member 170, 171, 172 Middle layer 175 Surface treatment layer 180 Insulating material C Cavity M wiring layer V via layer P Pad v Vacancy

Claims

1. Insulator and, A cavity having a bottom surface that penetrates a portion of the aforementioned insulator, Multiple wiring layers are arranged within the aforementioned insulator, An electronic component, at least a portion of which is located within the cavity, The set includes a sealing material that covers at least a portion of the insulator and the electronic component and fills at least a portion of the cavity, Any of the plurality of wiring layers includes a pad that is at least partially exposed from the insulator through the cavity. The aforementioned electronic component is connected to the pad via a connecting member. The aforementioned pad contains a nanotwin metal. Printed circuit board.

2. The aforementioned nanotwinned metal includes nanotwinned copper. A printed circuit board according to claim 1.

3. The aforementioned nanotwinned copper contains a plurality of columnar crystal grains, At least a portion of the plurality of columnar crystal grains contains nanotwin crystals. A printed circuit board according to claim 2.

4. The pad protrudes from the bottom surface of the cavity. A printed circuit board according to claim 1.

5. A first electrode is positioned below the aforementioned electronic component. The connecting member connects the first electrode and the pad to each other. A printed circuit board according to claim 1.

6. The connecting member includes solder, An intermediate layer is placed between the pad and the connecting member. The aforementioned intermediate layer is Cu ３ Sn layer and Cu ６ Sn ５ Including one or more layers, The printed circuit board according to claim 5.

7. The insulating material further includes filling at least a portion of the lower side of the cavity and covering at least a portion of the first electrode, the pad, and the connecting member, The printed circuit board according to claim 5.

8. The insulator further includes a plurality of via layers, each of which is disposed within the insulator and connected to one or more of the plurality of wiring layers, Any of the via layers mentioned above is connected to any of the wiring layers that include the pad that is at least partially exposed. A printed circuit board according to claim 1.

9. Each of the interconnected wiring layers and via layers includes a seed layer and a metal layer placed on the seed layer, The seed layer includes one or more of the following: electrolytic copper foil, rolled copper foil, electrolytic copper layer, electroless copper layer, electrolytic nickel layer, and electroless nickel layer. The aforementioned metal layer contains nanotwinned copper. A printed circuit board according to claim 8.

10. Each of the interconnected wiring layers and via layers further includes a transition layer located in the boundary region between the seed layer and the metal layer. A printed circuit board according to claim 9.

11. A build-up wiring layer placed on the sealing material, A first build-up via penetrates at least a portion of the sealing material and connects at least a portion of the build-up wiring layer to a second electrode located above the electronic component, The system further includes a second build-up via that penetrates at least a portion of the sealing material and the insulator together, and connects at least another portion of the build-up wiring layer to the uppermost wiring layer among the plurality of wiring layers. A printed circuit board according to claim 8.

12. Multiple insulating layers, A plurality of wiring layers are arranged within each of the plurality of insulating layers, A cavity that penetrates one or more of the plurality of insulating layers and exposes at least a portion of any of the plurality of wiring layers from the plurality of insulating layers, An interconnect bridge, at least a portion of which is located within the cavity, The set includes a sealing material disposed on the plurality of insulating layers, covering at least a portion of the interconnect bridge and filling at least a portion of the cavity, Either of the aforementioned wiring layers contains nanotwinned copper, At least a portion of any of the aforementioned wiring layers is connected to the interconnect bridge via a connecting member. Printed circuit board.

13. The aforementioned nanotwinned copper contains a plurality of columnar crystal grains, At least a portion of the plurality of columnar crystal grains contains nanotwin crystals. The printed circuit board according to claim 12.

14. The cavity has a bottom surface, At least a portion of any of the aforementioned wiring layers that is exposed protrudes above the bottom surface of the cavity. The printed circuit board according to claim 12.

15. The connecting member connects at least a portion of the exposed wiring layer of any of the aforementioned wiring layers to the first electrode located below the interconnect bridge. The printed circuit board according to claim 12.

16. The connecting member includes solder, An intermediate layer is placed between at least a portion of the exposed wiring layer and the connecting member. The aforementioned intermediate layer is Cu ３ Sn layer and Cu ６ Sn ５ Including one or more layers, A printed circuit board according to claim 15.

17. The insulating material further includes filling at least a portion of the lower side of the cavity and covering at least a portion of the first electrode, at least a portion of either of the wiring layers, and at least a portion of the connecting member, A printed circuit board according to claim 15.

18. A plurality of via layers, each disposed within the plurality of insulating layers and connected to one or more of the plurality of wiring layers, A build-up wiring layer placed on the sealing material, A first build-up via penetrates at least a portion of the sealing material and connects at least a portion of the build-up wiring layer to a second electrode located above the interconnect bridge, The system further includes a second build-up via that penetrates at least a portion of the sealing material and the uppermost insulating layer among the plurality of insulating layers, and connects at least another portion of the build-up wiring layer to the uppermost wiring layer among the plurality of wiring layers. The printed circuit board according to claim 12.

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