Peripheral circuit systems for memory devices and memory devices

Abstract

We provide peripheral circuit systems for memory devices and memory devices themselves. [Solution] In a memory device 10 including a memory and peripheral circuit system, the peripheral circuit system includes a first peripheral circuit 103 electrically connected to the memory array of the memory device and a second peripheral circuit 105 electrically connected to the memory array. The first peripheral circuit and the second peripheral circuit are arranged along the longitudinal direction Z.

Description

Technical Field

[0001] The present disclosure relates to a peripheral circuit system of a memory device and a memory device.

Background Art

[0002] A memory device includes a memory array for data storage and a peripheral circuit system for controlling the memory array. As the footprint of the peripheral circuit system increases, the performance, durability, power consumption, and reliability of the memory device usually improve. However, increasing the footprint of the peripheral circuit system has an adverse effect on the area reduction of the memory device.

Summary of the Invention

[0003] The present disclosure relates to a peripheral circuit system of a memory device and a memory device, whereby the footprint of the peripheral circuit system can be increased without increasing the area of the memory device. The performance, durability, power consumption, and reliability of the memory device can be improved.

[0004] According to an embodiment of the present disclosure, a peripheral circuit system of a memory device is provided. The peripheral circuit system includes a first peripheral circuit electrically connected to a memory array of the memory device and a second peripheral circuit electrically connected to the memory array. The first peripheral circuit and the second peripheral circuit are arranged along the vertical direction.

[0005] According to an embodiment of the present disclosure, a memory device is provided. The memory device includes a first semiconductor structure including a first peripheral circuit and a second semiconductor structure including a second peripheral circuit and a memory array. The first semiconductor structure is joined to the second semiconductor structure. The first peripheral circuit is electrically connected to the memory array. The second peripheral circuit is electrically connected to the memory array.

[0006] Embodiments of the present disclosure provide a memory device. The memory device includes a first semiconductor structure including a first peripheral circuit, a second semiconductor structure including a second peripheral circuit, and a third semiconductor structure including a memory array. The first, second, and third semiconductor structures are arranged longitudinally. The first peripheral circuit is electrically connected to the memory array. The second peripheral circuit is electrically connected to the memory array.

[0007] The above and other embodiments of this disclosure should be better understood in relation to the following detailed description of non-limiting embodiments. The following description is made with reference to the accompanying drawings. [Brief explanation of the drawing]

[0008] [Figure 1] Schematic diagrams of memory devices according to several embodiments of this disclosure are illustrated.

[0009] [Figure 2] Schematic diagrams of memory devices according to several embodiments of this disclosure are illustrated.

[0010] [Figure 3] Schematic diagrams of memory devices according to several embodiments of this disclosure are illustrated.

[0011] [Figure 4] Schematic diagrams of memory devices according to several embodiments of this disclosure are illustrated.

[0012] [Figure 5] Schematic cross-sectional views of memory devices according to several embodiments of this disclosure are illustrated.

[0013] [Figure 6] Schematic cross-sectional views of memory devices according to several embodiments of this disclosure are illustrated.

[0014] [Figure 7] Schematic cross-sectional views of memory devices according to several embodiments of this disclosure are illustrated.

[0015] [Figure 8] Schematic cross-sectional views of memory devices according to several embodiments of this disclosure are illustrated. [Modes for carrying out the invention]

[0016] Various embodiments are described more fully below with reference to the accompanying drawings, which are provided for illustrative and explanatory purposes only, not for limiting purposes. For clarity, components may not be drawn to scale. Furthermore, some components and / or reference numbers may be omitted from some drawings. It is considered that elements and features of one embodiment can be usefully incorporated into another embodiment without further description. In examples, the same / similar elements are shown using the same / similar reference numbers.

[0017] In this specification and the accompanying claims, ordinal numbers such as “first” and “second” used to describe elements do not suggest or represent a particular location in the structure, or an order of construction, or an order of manufacture. These ordinal numbers are used solely to clearly distinguish multiple elements by the same name. In this specification and the accompanying claims, spatial relation terms such as “on,” “above,” “over,” “upper,” “top,” “below,” “beneath,” “under,” “lower,” and “bottom” may be used to describe the relative spatial or positional relationship between one element and another, as illustrated in the drawings. These spatial or positional relationships may be direct or indirect unless otherwise specified. These spatial relation terms are intended to encompass various orientations of the structure, in addition to the orientation depicted in the drawings. The structure may be inverted or rotated at various angles, and the spatial relation descriptions used herein may be interpreted accordingly. In this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. In this specification and the appended claims, the term “and / or” includes any combination of one or more of the related items listed.

[0018] Furthermore, as used herein and in the claims, the term "electrically connected" can refer to an ohmic contact between elements, or a current flowing through each element, or an operative relationship between elements. The operative relationship may mean, for example, that one element is used to move another element, but there may not be a direct current flowing between these two elements. As used herein and in the claims, the term "functional surface" can refer to a surface on which electronic components such as transistors, diodes, resistors, or capacitors are formed.

[0019] As used herein and in the claims, the term "interconnection structure" can broadly include any suitable type of interconnection structure, for example, an interconnection structure formed in an intermediate process (MEOL) or an interconnection structure formed in a wiring process (BEOL). The interconnection structure can include one or more lateral interconnect lines and / or one or more vertical interconnect vias. The interconnect lines and interconnect vias may include, but are not limited to, conductive materials such as tungsten, cobalt, copper, aluminum, silicide, or any combination thereof. Further, the interconnection structure may include one or more interlayer dielectric layers. The interconnect lines and interconnect vias may be formed in the interlayer dielectric layers. The interlayer dielectric layers may include, but are not limited to, dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant dielectric materials, or any combination thereof.

[0020] Embodiments in accordance with the present disclosure can be applied to many different types of memory devices. The memory device may include a volatile memory array or a non-volatile memory array. In some embodiments, the present disclosure can be applied to a NAND-type flash memory device with vertical channels.

[0021] A memory device includes a memory array and a peripheral circuit system. The peripheral circuit system includes a first peripheral circuit electrically connected to the memory array and a second peripheral circuit electrically connected to the memory array. The memory array may include a plurality of memory strings. Each of the plurality of memory strings may include a memory cell. The memory array may be used for storing data. The first and second peripheral circuits may be used to control the memory cells of the memory array. For example, the first and second peripheral circuits may be used to read, write, or erase the memory cells. The first and second peripheral circuits may include different components, but this disclosure is not limited thereto. In this disclosure, the memory array, the first peripheral circuit, and the second peripheral circuit are arranged along the longitudinal direction. The memory array, the first peripheral circuit, and the second peripheral circuit may be stacked vertically. The first peripheral circuit may be located above or below the second peripheral circuit in the longitudinal direction.

[0022] Referring to FIG. 1, FIG. 1 illustrates a schematic diagram of a memory device 10 according to some embodiments of the present disclosure. The memory device 10 includes a memory 101 and a peripheral circuit system. The peripheral circuit system includes a first peripheral circuit 103 and a second peripheral circuit 105. The first peripheral circuit 103 is electrically connected to the memory array 101. The second peripheral circuit 105 is electrically connected to the memory array 101. The first peripheral circuit 103 may be electrically connected to the second peripheral circuit 105. The first peripheral circuit 103 is disposed above the memory array 101 in the Z direction (e.g., the vertical direction). The second peripheral circuit 105 is disposed below the first peripheral circuit 103 in the Z direction. The second peripheral circuit 105 is disposed below the memory array 101 in the Z direction. The first peripheral circuit 103 and the second peripheral circuit 105 are disposed on opposite sides sandwiching the memory array 101. The first peripheral circuit 103 includes a high-speed drive circuit. The high-speed drive circuit includes at least one page buffer and at least one input / output circuit. The second peripheral circuit 105 includes a high-voltage drive circuit. The high-voltage drive circuit includes at least one charge pump circuit and at least one load decoder.

[0023] The first peripheral circuit 103 is located within the first semiconductor structure 110W. The memory array 101 and the second peripheral circuit 105 are located within the second semiconductor structure 120W. In one embodiment, the second semiconductor structure 120W includes a substrate, the second peripheral circuit 105 may be formed on a first side of the substrate, and then the memory array 101 may be formed on a second side of the substrate, opposite to the first side. The first semiconductor structure 110W and the second semiconductor structure 120W are arranged along the Z direction. The first semiconductor structure 110W and the second semiconductor structure 120W may be stacked on top of each other in the Z direction. The first semiconductor structure 110W is stacked on top of the second semiconductor structure 120W in the Z direction. The first semiconductor structure 110W is hybrid-junctioned to the second semiconductor structure 120W. The first semiconductor structure 110W has a functional side and a back side opposite the functional side. The second semiconductor structure 120W has a functional surface and a back surface opposite the functional surface. The first semiconductor structure 110W is bonded to the second semiconductor structure 120W in a face-to-face orientation. The functional surface of the first semiconductor structure 110W is bonded to the functional surface of the second semiconductor structure 120W. The first semiconductor structure 110W and the second semiconductor structure 120W can be different semiconductor wafers or chips.

[0024] Referring to Figure 2, Figure 2 illustrates schematic diagrams of memory devices 20 according to several embodiments of the present disclosure. The difference between memory device 20 and memory device 10 shown in Figure 1 is that the memory array and peripheral circuit system of memory device 20 are arranged within three semiconductor structures (a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure). Memory device 20 includes a memory 101 and a peripheral circuit system. The peripheral circuit system includes a first peripheral circuit 103 and a second peripheral circuit 105. The first peripheral circuit 103 is electrically connected to the memory array 101. The second peripheral circuit 105 is electrically connected to the memory array 101. The first peripheral circuit 103 may be electrically connected to the second peripheral circuit 105. The first peripheral circuit 103 and the second peripheral circuit 105 are located on opposite sides of the memory array 101. The first peripheral circuit 103 is positioned on the memory array 101 and the second peripheral circuit 105 in the Z direction. The memory array 101 is positioned on the second peripheral circuit 105 in the Z direction.

[0025] The first peripheral circuit 103 is located within the first semiconductor structure 210W. The second peripheral circuit 105 is located within the second semiconductor structure 220W. The memory array 101 is located within the third semiconductor structure 230W. The first semiconductor structure 210W, the second semiconductor structure 220W, and the third semiconductor structure 230W are arranged along the Z direction. The first semiconductor structure 210W, the second semiconductor structure 220W, and the third semiconductor structure 230W may be stacked on top of each other in the Z direction. The third semiconductor structure 230W is located between the first semiconductor structure 210W and the second semiconductor structure 220W in the Z direction. The third semiconductor structure 230W is stacked on top of the second semiconductor structure 220W in the Z direction. The first semiconductor structure 210W is stacked on top of the third semiconductor structure 230W in the Z direction. The first semiconductor structure 210W is hybrid-bonded to the third semiconductor structure 230W. The second semiconductor structure 220W is hybrid-bonded to the third semiconductor structure 230W. The first semiconductor structure 210W has a functional surface and a back surface opposite to the functional surface. The second semiconductor structure 220W has a functional surface and a back surface opposite to the functional surface. The third semiconductor structure 230W has a functional surface and a back surface opposite to the functional surface. The first semiconductor structure 210W is bonded to the third semiconductor structure 230W in a face-to-face orientation. The second semiconductor structure 220W is bonded to the third semiconductor structure 230W in a face-to-back orientation. The functional surface of the first semiconductor structure 210W is bonded to the functional surface of the third semiconductor structure 230W. The back surface of the third semiconductor structure 230W is bonded to the functional surface of the second semiconductor structure 220W. The first semiconductor structure 210W, the second semiconductor structure 220W, and the third semiconductor structure 230W can be different semiconductor wafers or chips.

[0026] Referring to Figure 3, Figure 3 illustrates schematic diagrams of memory devices 30 according to several embodiments of the present disclosure. The difference between memory device 30 and memory device 20 shown in Figure 2 is that the arrangement order of the first, second, and third semiconductor structures in memory device 30 differs from that of memory device 20, and the configuration of the memory array, first peripheral circuit, and second peripheral circuit in memory device 30 differs from that of memory device 20. Memory device 30 includes a memory 101 and a peripheral circuit system. The peripheral circuit system includes a first peripheral circuit 103 and a second peripheral circuit 105. The first peripheral circuit 103 is electrically connected to the memory array 101. The second peripheral circuit 105 is electrically connected to the memory array 101. The first peripheral circuit 103 may be electrically connected to the second peripheral circuit 105. The first peripheral circuit 103 and the second peripheral circuit 105 are located on opposite sides of the memory array 101. The second peripheral circuit 105 is located on the memory array 101 and the first peripheral circuit 103 in the Z direction. The memory array 101 is located on the first peripheral circuit 103 in the Z direction.

[0027] The first peripheral circuit 103 is located within the first semiconductor structure 310W. The second peripheral circuit 105 is located within the second semiconductor structure 320W. The memory array 101 is located within the third semiconductor structure 330W. The first semiconductor structure 310W, the second semiconductor structure 320W, and the third semiconductor structure 330W are arranged along the Z direction. The first semiconductor structure 310W, the second semiconductor structure 320W, and the third semiconductor structure 330W may be stacked on top of each other in the Z direction. The third semiconductor structure 330W is located between the first semiconductor structure 310W and the second semiconductor structure 320W in the Z direction. The third semiconductor structure 330W is stacked on top of the first semiconductor structure 310W in the Z direction. The second semiconductor structure 320W is stacked on top of the third semiconductor structure 330W in the Z direction. The first semiconductor structure 310W is hybrid-bonded to the third semiconductor structure 330W. The second semiconductor structure 320W is hybrid-bonded to the third semiconductor structure 330W. The first semiconductor structure 310W has a functional surface and a back surface opposite to the functional surface. The second semiconductor structure 320W has a functional surface and a back surface opposite to the functional surface. The third semiconductor structure 330W has a functional surface and a back surface opposite to the functional surface. The second semiconductor structure 320W is bonded to the third semiconductor structure 330W in a face-to-face orientation. The first semiconductor structure 310W is bonded to the third semiconductor structure 330W in a face-to-back orientation. The functional surface of the third semiconductor structure 330W is bonded to the functional surface of the second semiconductor structure 320W. The functional surface of the first semiconductor structure 310W is bonded to the back surface of the third semiconductor structure 330W. The first semiconductor structure 310W, the second semiconductor structure 320W, and the third semiconductor structure 330W can be different semiconductor wafers or chips.

[0028] Referring to Figure 4, which illustrates schematic diagrams of memory devices 40 according to several embodiments of the present disclosure. The difference between memory device 40 and memory device 20 shown in Figure 2 is that the arrangement order of the first semiconductor structure, second semiconductor structure, and third semiconductor structure in memory device 40 differs from the arrangement order of the first semiconductor structure, second semiconductor structure, and third semiconductor structure in memory device 20, and the configuration of the memory array, first peripheral circuit, and second peripheral circuit in memory device 40 differs from the configuration of the memory array, first peripheral circuit, and second peripheral circuit in memory device 20.

[0029] The memory device 40 includes a memory 101 and a peripheral circuit system. The peripheral circuit system includes a first peripheral circuit 103 and a second peripheral circuit 105. The first peripheral circuit 103 is electrically connected to the memory array 101. The second peripheral circuit 105 is electrically connected to the memory array 101. The first peripheral circuit 103 may be electrically connected to the second peripheral circuit 105. The second peripheral circuit 105 and the memory array 101 are located on opposite sides of the first peripheral circuit 103. The first peripheral circuit 103 and the second peripheral circuit 105 are located on the same side of the memory array 101. In the Z direction, the second peripheral circuit 105 is located on the memory array 101 and the first peripheral circuit 103. In the Z direction, the first peripheral circuit 103 is located on the memory array 101.

[0030] The first peripheral circuit 103 is located within the first semiconductor structure 410W. The second peripheral circuit 105 is located within the second semiconductor structure 420W. The memory array 101 is located within the third semiconductor structure 430W. The first semiconductor structure 410W, the second semiconductor structure 420W, and the third semiconductor structure 430W are arranged along the Z direction. The first semiconductor structure 410W, the second semiconductor structure 420W, and the third semiconductor structure 430W may be stacked on top of each other in the Z direction. In the Z direction, the first semiconductor structure 410W is located between the third semiconductor structure 430W and the second semiconductor structure 420W. In the Z direction, the second semiconductor structure 420W is stacked on top of the first semiconductor structure 410W. In the Z direction, the first semiconductor structure 410W is stacked on top of the third semiconductor structure 430W. The first semiconductor structure 410W is hybrid-bonded to the second semiconductor structure 420W. The first semiconductor structure 410W is hybrid-bonded to the third semiconductor structure 430W. The first semiconductor structure 410W has a functional surface and a back surface opposite to the functional surface. The second semiconductor structure 420W has a functional surface and a back surface opposite to the functional surface. The third semiconductor structure 430W has a functional surface and a back surface opposite to the functional surface. The first semiconductor structure 410W is bonded to the second semiconductor structure 420W in a face-to-face orientation. The third semiconductor structure 430W is bonded to the first semiconductor structure 410W in a face-to-back orientation. The functional surface of the first semiconductor structure 410W is bonded to the functional surface of the second semiconductor structure 420W. The functional surface of the third semiconductor structure 430W is bonded to the back surface of the first semiconductor structure 410W. The first semiconductor structure 410W, the second semiconductor structure 420W, and the third semiconductor structure 430W can be different semiconductor wafers or chips.

[0031] Referring to Figure 5, which illustrates a schematic cross-sectional view showing one of the component configurations of a memory device 10 according to several embodiments of the present disclosure. The memory device 10 includes a first semiconductor structure 110W and a second semiconductor structure 120W. The first semiconductor structure 110W includes a first peripheral circuit 103. The first semiconductor structure 110W includes a device layer 112, an interconnect structure 113, via elements 114, pads 115, and input / output pads 116. The device layer 112 includes a semiconductor layer 1120 and a transistor T1. The semiconductor layer 1120 may include semiconductor materials such as doped or undoped single-crystal silicon, doped or undoped polycrystalline silicon, and germanium. Figure 5 shows that the transistor T1 is located on the surface of the semiconductor layer 1120, but the present disclosure is not limited thereto. The transistor T1 may be located near the surface of the semiconductor layer 1120. In other words, the transistor T1 may be entirely located on the surface of the semiconductor layer 1120; or alternatively, a portion of the transistor T1 (e.g., the gate structure) may be located on the surface of the semiconductor layer 1120, and another portion of the transistor T1 (e.g., the drain structure and / or source structure) may be located below the surface of the semiconductor layer 1120 and within the semiconductor layer 1120; or alternatively, the transistor T1 may be entirely located within the semiconductor layer 1120. The interconnection structure 113 is located on the first side of the semiconductor layer 1120. The transistor T1 may be electrically connected to the interconnection structure 113. The interconnection structure 113 may contain conductive material. Via elements 114 may penetrate the semiconductor layer 1120. Via elements 114 may be located between the pad 115 and the input / output pad 116. Via elements 114, pad 115, and input / output pad 116 may be electrically connected to each other. Via elements 114 may contain conductive material. For example, via elements are through-silicon (TSV) elements. Pad 115 is located on the first side of semiconductor layer 1120. Input / output pads 116 are located on the second side of semiconductor layer 1120. The second side of semiconductor layer 1120 is opposite to the first side of semiconductor layer 1120. Pad 115 may contain a conductive material.The input / output pad 116 may contain conductive material.

[0032] In the embodiment shown in Figure 5, the surface including the pad 115 and the interconnect structure 113 may be defined as the functional surface of the first semiconductor structure 110W, and the surface including the input / output pad 116 may be defined as the back surface of the first semiconductor structure 110W. The device layer 112, interconnect structure 113, via element 114, pad 115, and input / output pad 116 may form part of the first peripheral circuit 103; or alternatively, the first peripheral circuit 103 may include the device layer 112, interconnect structure 113, via element 114, pad 115, and input / output pad 116. The input / output pad 116 may be part of the input / output circuit of the first peripheral circuit 103. Transistor T1 may be electrically connected to the page buffer of the first peripheral circuit 103, or may be part of the page buffer of the first peripheral circuit 103. The input / output pad 116 is connected to a voltage V DD or voltage V SS It can be used to receive voltages such as those mentioned above.

[0033] In one embodiment, the transistor T1 can be a complementary metal-oxide-semiconductor (CMOS) field-effect transistor.

[0034] The semiconductor structure 120W includes a memory array 101 and a second peripheral circuit 105. The semiconductor structure 120W includes a device layer 122, an interconnect structure 123, a substrate 130, a stacked structure 131, a conductive element 132, a memory string 133, a stepped structure 141, a plug element 142, a conductive structure 143, and a contact element 144. The substrate 130 may include a dielectric material. The device layer 122 includes a semiconductor layer 1220 and a transistor T2. The semiconductor layer 1220, the transistor T2, and the interconnect structure 123 may be located on the first side of the substrate 130. The stacked structure 131, the conductive element 132, the memory string 133, the stepped structure 141, the plug element 142, the conductive structure 143, and the contact element 144 may be located on the second side of the substrate 130. The second side of the substrate 130 is opposite to the first side of the substrate 130.

[0035] The semiconductor layer 1220 may include semiconductor materials such as doped or undoped single-crystal silicon, doped or undoped polycrystalline silicon, and germanium. Figure 5 shows that the transistor T2 is located on the surface of the semiconductor layer 1220, but the disclosure is not limited thereto. The transistor T2 may be located near the surface of the semiconductor layer 1220. That is, the transistor T2 may be located entirely on the surface of the semiconductor layer 1120; or alternatively, a portion of the transistor T2 (e.g., the gate structure) may be located on the surface of the semiconductor layer 1220, and another portion of the transistor T2 (e.g., the drain structure and / or source structure) may be located below the surface of the semiconductor layer 1220 and within the semiconductor layer 1220; or alternatively, the transistor T2 may be located entirely within the semiconductor layer 1220. The interconnect structure 123 is located on top of the semiconductor layer 1220. The transistor T2 may be electrically connected to the interconnect structure 123. The interconnect structure 123 may include a conductive material. The device layer 122 and interconnect structure 123 can form part of the second peripheral circuit 105; or alternatively, the second peripheral circuit 105 may include the device layer 122 and interconnect structure 123. Transistor T2 may be electrically connected to the charge pump circuit and low decoder of the second peripheral circuit 105. In one embodiment, transistor T2 may be a complementary metal oxide semiconductor field-effect transistor.

[0036] The stacked structure 131 and the memory string 133 may be arranged within the array region MR of the second semiconductor structure 120W. The stacked structure 131 is placed on a substrate 130. The stacked structure 131 may include conductive layers 1311 and insulating layers 1312 that are alternately stacked along the Z direction. These conductive layers 1311 are separated from each other by the insulating layers 1312. The conductive layers 1311 and insulating layers 1312 may be extended along the X direction (e.g., transverse direction) and / or the Y direction (e.g., transverse direction). The X, Y, and Z directions are orthogonal to each other. The conductive layers 1311 may contain a conductive material, which may include, but is not limited to, doped or undoped polycrystalline silicon, metal, or a combination thereof. The insulating layers 1312 may contain an insulating material, which may include, but is not limited to, silicon oxide. The memory string 133 is placed on a substrate 130. These memory strings 133 are arranged on the substrate 130, spaced apart from each other. The memory strings 133 extend along the Z direction and penetrate the stacked structure 131. The stacked structure 131 may surround the memory strings 133. Each memory string 133 contains memory cells. In one embodiment, each memory string 133 may include memory cells arranged spaced apart along the Z direction. The memory strings 133 can form a memory array 101. The memory array 101 is located between the substrate 130 and the first semiconductor structure 110W. The memory strings 133 can be AND, NOR, or NAND type memory strings. The conductive layer 1311 of the stacked structure 131 is electrically connected to the memory cells of the memory strings 133. Conductive elements 132 are located on top of the memory strings 133. Conductive elements 132 are electrically connected to the memory strings 133. The memory string 133 may be electrically connected to the interconnection structure 113 of the first semiconductor structure 110W via conductive elements 132. In one embodiment, each conductive layer 1311 can function as a word line. In one embodiment, the conductive elements 132 may include at least one bit line.In one embodiment, the conductive element 132 may include at least one conductive stripe and at least one interlayer connector, the conductive stripe and the interlayer connector comprising a conductive material, and the conductive stripe may function as a bit wire.

[0037] In one embodiment, each memory string 133 may include an insulating pillar, a channel layer surrounding the insulating pillar, and a memory layer surrounding the channel layer and the insulating pillar. The memory layer may include a multilayer structure. For example, the memory layer may include a tunnel layer on the outer sidewall of the channel layer, a storage layer on the outer sidewall of the tunnel layer, and a blocking layer on the outer sidewall of the storage layer. The memory layer may include multilayer structures known from memory technology, such as ONO (oxide-nitride-oxide), ONONO (oxide-nitride-oxide-nitride-oxide), ONONONO (oxide-nitride-oxide-oxide-nitride-oxide-oxide), SONOS (silicon-oxide-nitride-oxide-silicon), BE-SONOS (bandgap-adjustable silicon-oxide-nitride-oxide-silicon), TANOS (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon), MA BE-SONOS (bandgap-adjustable silicon-oxide-nitride-oxide-silicon combining metal and high dielectric constant material), and combinations of such layers. The channel layer may contain semiconductor materials such as doped or undoped polycrystalline silicon. The insulating pillars may contain insulating materials such as silicon oxide. Memory cells can be defined in the memory layer at the intersection of the conductive layer 1311 and the memory string 133.

[0038] The stepped structure 141 and the plug element 142 may be located within the peripheral region of the second semiconductor structure 120W. The peripheral region may be adjacent to the array region MR. The peripheral region may surround the array region MR. The stepped structure 141 is located on the substrate 130. The stepped structure 141 may be located on one side of the laminated structure 131. The stepped structure 141 includes stepped conductive layers 1411 and stepped insulating layers 1412 that are alternately stacked along the Z direction. These stepped conductive layers 1411 are separated from each other by the stepped insulating layers 1412. The stepped conductive layers 1411 and stepped insulating layers 1412 may extend along the X direction and / or the Y direction. Each of these stepped conductive layers 1411 has a different lateral area in the XY plane (the plane formed by the X and Y directions). For example, the lateral area of ​​the stepped conductive layer 1411 gradually decreases along the direction away from the substrate 130. For example, the lateral surface area of ​​a stepped conductive layer 1411 located in a lower layer (closer to the substrate 130) is greater than the lateral surface area of ​​a stepped conductive layer 1411 located in a higher layer (further from the substrate 130). The stepped conductive layer 1411 may include, but is not limited to, a conductive material such as doped or undoped polycrystalline silicon, a metal, or a combination thereof. The stepped insulating layer 1412 may include, but is not limited to, an insulating material such as silicon oxide.

[0039] The stepped conductive layer 1411 of the stepped structure 141 may be electrically connected to the conductive layer 1311 of the laminated structure 131. In one embodiment, the conductive layer 1311 of the laminated structure 131 and the stepped conductive layer 1411 of the stepped structure 141 may have a one-to-one correspondence. That is, a certain conductive layer 1311 and a stepped conductive layer 1411 corresponding to this conductive layer 1311 may have the same height (or layer) in the Z direction.

[0040] The plug element 142 is positioned on the stepped conductive layer 1411 of the stepped structure 141. Any plug element 142 may be positioned on the stepped conductive layer 1411 at a different level. The plug element 142 is electrically connected to the stepped conductive layer 1411 on which it is positioned, and is electrically connected to the conductive layer 1311 located at the same level as the stepped conductive layer 1411. The conductive structure 143 is positioned on top of the plug element 142. The conductive structure 143 may be electrically connected between the plug element 142 and the interconnecting structure 123. The plug element 142 and the conductive structure 143 may contain conductive material.

[0041] The contact element 144 may extend along the Z direction and penetrate the substrate 130. The contact element 144 may be electrically connected to the via element 114, pad 115, and input / output pad 116 of the first semiconductor structure 110W. The contact element 144 may be electrically connected to the interconnect structure 123. The first peripheral circuit 103 may be electrically connected to the second peripheral circuit 105 via the contact element 144. The contact element 144 may contain a conductive material.

[0042] In the embodiment shown in Figure 5, the surface including the conductive element 132 and the contact element 144 can be defined as the functional surface of the second semiconductor structure 120W. Thus, the first semiconductor structure 110W is bonded to the second semiconductor structure 120W in a face-to-face orientation. In one embodiment, a signal can be propagated between the memory cells of the memory string 133 of the second semiconductor structure 120W, the conductive element 132 of the second semiconductor structure 120W, and the page buffer in the first peripheral circuit 103 of the first semiconductor structure 110W. In one embodiment, a signal can be propagated between the conductive layer 1311 of the second semiconductor structure 120W, the stepped conductive layer 1411 of the second semiconductor structure 120W, the plug element 142 of the second semiconductor structure 120W, the conductive structure 143 of the second semiconductor structure 120W, and the raw decoder in the second peripheral circuit 105 of the second semiconductor structure 120W. In the first semiconductor structure 110W, the power supply network and signal network are provided on the functional surface of the first semiconductor structure 110W. The second semiconductor structure 120W may include a CMOS under-array design.

[0043] Referring to Figure 6, which illustrates a schematic cross-sectional view showing one of the component configurations of a memory device 10 according to several embodiments of the present disclosure. The difference between the structure shown in Figure 6 and the structure shown in Figure 5 is that the structure of the first semiconductor structure 110W' shown in Figure 6 is different from the structure of the first semiconductor structure 110W shown in Figure 5. The memory device 10 includes a first semiconductor structure 110W' and a second semiconductor structure 120W. The first semiconductor structure 110W' includes a first peripheral circuit 103. The first semiconductor structure 110W' includes a device layer 612, a first interconnect structure 613, a second interconnect structure 614, via elements 617, a third interconnect structure 618, and input / output pads 116. The device layer 612 includes semiconductor materials such as doped or undoped single-crystal silicon, doped or undoped polycrystalline silicon, and germanium. The device layer 612 may include transistors such as fin-type field-effect transistors (FinFETs) or complementary metal-oxide-semiconductor (CMOS) field-effect transistors. The first interconnection structure 613 and the second interconnection structure 614 are located on opposite sides of the device layer 612. The third interconnection structure 618 and the second interconnection structure 614 are located on opposite sides of the device layer 612. The first interconnection structure 613 and the third interconnection structure 618 are located on the same side of the device layer 612. The first interconnection structure 613 and the third interconnection structure 618 are located between the device layer 612 and the second semiconductor structure 120W. The second interconnection structure 614 is located between the device layer 612 and the input / output pads 116. The first interconnection structure 613 may be electrically connected to the transistors of the device layer 612. The first interconnection structure 613 may be electrically connected to the conductive element 132 and memory string 133 of the second semiconductor structure 120W. Via element 617 penetrates the device layer 612. Via element 617 may be electrically connected between the third interconnection structure 618 and the second interconnection structure 614. Input / output pad 116 may be electrically connected to the second interconnection structure 614.The input / output pad 116 may be electrically connected to the contact element 144 of the second semiconductor structure 120W via the second interconnection structure 614, via element 617, and third interconnection structure 618. The first interconnection structure 613, the second interconnection structure 614, via element 617, and third interconnection structure 618 may contain conductive material. For example, via element 617 may be a micro-through-silicon (μTSV) element.

[0044] In the embodiment shown in Figure 6, the surface including the first interconnection structure 613 and the third interconnection structure 618 may be defined as the functional surface of the first semiconductor structure 100W', and the surface including the input / output pads 116 may be defined as the back surface of the first semiconductor structure 100W'. In the first semiconductor structure 110W', the power supply network is provided on the back surface, which may improve power consumption and performance. The first semiconductor structure 110W' includes a back surface power supply network (BSPDN). In the first semiconductor structure 110W', the signal network is provided on the functional surface of the first semiconductor structure 110W'.

[0045] The device layer 612, the first interconnection structure 613, the second interconnection structure 614, the via element 617, the third interconnection structure 618, and the input / output pad 116 may form part of the first peripheral circuit 103; or alternatively, the first peripheral circuit 103 may include the device layer 612, the first interconnection structure 613, the second interconnection structure 614, the via element 617, the third interconnection structure 618, and the input / output pad 116. The input / output pad 116 may be part of the input / output circuit of the first peripheral circuit 103. The transistors of the device layer 612 may be electrically connected to the page buffer of the first peripheral circuit 103, or may be part of the page buffer of the first peripheral circuit 103. The input / output pad 116 is connected to a voltage V DD or voltage V SS It can be used to receive voltages such as those mentioned above.

[0046] In the embodiment shown in Figure 6, the first semiconductor structure 110W' is bonded to the second semiconductor structure 120W in a face-to-face orientation. In one embodiment, a signal can be propagated between the memory cells of the memory string 133 of the second semiconductor structure 120W, the conductive element 132 of the second semiconductor structure 120W, and the page buffer in the first peripheral circuit 103 of the first semiconductor structure 110W'. In one embodiment, a signal can be propagated between the conductive layer 1311 of the second semiconductor structure 120W, the stepped conductive layer 1411 of the second semiconductor structure 120W, the plug element 142 of the second semiconductor structure 120W, the conductive structure 143 of the second semiconductor structure 120W, and the raw decoder in the second peripheral circuit 105 of the second semiconductor structure 120W.

[0047] In the embodiments shown in Figures 5 and 6, the second peripheral circuit 105 and the memory array 101 are located within the same semiconductor structure (wafer or chip), while the first peripheral circuit 103 is located within a separate semiconductor structure (wafer or chip); such a configuration avoids damage to the first peripheral circuit caused by the high-temperature process used to form the memory array. Because the high-voltage drive circuit of the second peripheral circuit has a higher temperature tolerance, the high-temperature process used to form the memory array does not damage the second peripheral circuit. Therefore, by providing the second peripheral circuit and memory array within the same semiconductor structure, the overall performance of the memory device can be improved.

[0048] Referring to Figure 7, Figure 7 illustrates a schematic cross-sectional view showing one of the component configurations of a memory device 20 according to several embodiments of the present disclosure.

[0049] The memory device 20 includes a first semiconductor structure 210W, a second semiconductor structure 220W, and a third semiconductor structure 230W. The first semiconductor structure 210W includes a first peripheral circuit 103. The first semiconductor structure 210W includes a device layer 612, a first interconnect structure 613, a second interconnect structure 614, a via element 617, a third interconnect structure 618, and an input / output pad 116. In this embodiment, the first semiconductor structure 210W is similar to the first semiconductor structure 110W', and the configuration and description of the components within the first semiconductor structure 210W may refer to the description related to the first semiconductor structure 110W'. The first interconnect structure 613 and the third interconnect structure 618 are located between the device layer 612 and the third semiconductor structure 230W. The second interconnect structure 614 is located between the device layer 612 and the input / output pad 116. The first interconnection structure 613 may be electrically connected to the conductive element 732 and memory string 733 of the third semiconductor structure 230W. The input / output pad 116 may be electrically connected to the contact element 744 of the third semiconductor structure 230W via the second interconnection structure 614, via element 617, and the third interconnection structure 618.

[0050] The third semiconductor structure 230W includes a memory array 101. The third semiconductor structure 230W includes a substrate 730, a laminated structure 731, a conductive element 732, a memory string 733, a stepped structure 741, a plug element 742, a conductive structure 743, and a contact element 744. The substrate 730 may include a dielectric material. The laminated structure 731 and the memory string 733 may be arranged within the array region MR of the third semiconductor structure 230W. The laminated structure 731 is placed on the substrate 730. The laminated structure 731 may include conductive layers 7311 and insulating layers 7312 that are alternately stacked along the Z direction. These conductive layers 7311 are separated from each other by the insulating layers 7312. The conductive layers 7311 and insulating layers 7312 may be extended along the X and / or Y directions. The conductive layer 7311 may contain a conductive material, which may include, but is not limited to, doped or undoped polycrystalline silicon, a metal, or a combination thereof. The insulating layer 7312 may contain an insulating material, which may include, but is not limited to, silicon oxide. The memory strings 733 are arranged on the substrate 730. These memory strings 733 are arranged apart from each other on the substrate 730. The memory strings 733 may extend along the Z direction and penetrate the stacked structure 731. The stacked structure 731 may surround the memory strings 733. Each memory string 733 contains memory cells. In one embodiment, each memory string 733 may include memory cells arranged apart along the Z direction. In one embodiment, the structure of the memory string 733 may be similar to the structure of the memory string 133. The memory strings 733 can form a memory array 101. The memory array 101 is arranged on the substrate 730. The memory array 101 is located between the substrate 730 and the first semiconductor structure 210W. The memory string 733 can be an AND, NOR, or NAND type memory string. The conductive layer 7311 of the stacked structure 731 is electrically connected to the memory cells of the memory string 733. The conductive element 732 is located on top of the memory string 733.The conductive element 732 is electrically connected to the memory string 733. The memory string 733 may be electrically connected to the interconnection structure 613 of the first semiconductor structure 210W via the conductive element 732. In one embodiment, each conductive layer 1311 can function as a word line. In one embodiment, the conductive element 732 may include at least one bit line. In one embodiment, the conductive element 732 may include at least one conductive stripe and at least one interlayer connector, the conductive stripe and interlayer connector containing a conductive material, and the conductive stripe can function as a bit line.

[0051] The stepped structure 741 and the plug element 742 may be located within the peripheral region of the third semiconductor structure 230W. The peripheral region may be adjacent to the array region MR. The peripheral region may surround the array region MR. The stepped structure 741 is located on the substrate 730. The stepped structure 741 may be located on one side of the laminated structure 731. The stepped structure 741 includes stepped conductive layers 7411 and stepped insulating layers 7412 that are alternately stacked along the Z direction. These stepped conductive layers 7411 are separated from each other by the stepped insulating layers 7412. The stepped conductive layers 7411 and stepped insulating layers 7412 may extend along the X and / or Y directions. Each of these stepped conductive layers 7411 has a different lateral area in the XY plane. For example, the lateral area of ​​the stepped conductive layer 7411 gradually decreases along the direction away from the substrate 730. For example, the lateral surface area of ​​a stepped conductive layer 7411 located in a lower layer (closer to the substrate 730) is greater than the lateral surface area of ​​a stepped conductive layer 7411 located in a higher layer (further from the substrate 730). The stepped conductive layer 7411 may include, but is not limited to, a conductive material such as doped or undoped polycrystalline silicon, a metal, or a combination thereof. The stepped insulating layer 7412 may include, but is not limited to, an insulating material such as silicon oxide.

[0052] The stepped conductive layer 7411 of the stepped structure 741 may be electrically connected to the conductive layer 7311 of the laminated structure 731. In one embodiment, the conductive layer 7311 of the laminated structure 731 and the stepped conductive layer 7411 of the stepped structure 741 may have a one-to-one correspondence. That is, a certain conductive layer 7311 and a stepped conductive layer 7411 corresponding to this conductive layer 7311 may have the same height (or layer) in the Z direction.

[0053] The plug element 742 is located on the substrate 730. The plug element 742 is located on the stepped conductive layer 7411 of the stepped structure 741. Any plug element 742 may be located on the stepped conductive layer 7411 at different levels. The plug element 742 is electrically connected to the stepped conductive layer 7411 on which it is located, and is electrically connected to the conductive layer 7311 located at the same level as this stepped conductive layer 7411. The conductive structure 743 is located on top of the plug element 742. The conductive structure 743 penetrates the substrate 730. The conductive structure 743 may be electrically connected between the plug element 742 and the interconnection structure 723 of the semiconductor structure 220W. The word lines of the memory device 20 may be electrically connected to the second semiconductor structure 220W via the plug element 742 and the conductive structure 743. The plug element 742 and the conductive structure 743 may contain conductive material. The contact element 744 may extend along the Z direction and penetrate the substrate 730. The contact element 744 may be electrically connected to the interconnection structure 723 of the second semiconductor structure 220W. The contact element 744 may contain a conductive material.

[0054] The semiconductor structure 220W includes a second peripheral circuit 105. The semiconductor structure 220W includes a device layer 722 and an interconnect structure 723. The device layer 722 includes a semiconductor layer 7220 and a transistor T3. The semiconductor layer 7220 may include semiconductor materials such as doped or undoped single-crystal silicon, doped or undoped polycrystalline silicon, and germanium. Figure 7 shows that the transistor T3 is located on the surface of the semiconductor layer 7220, but the disclosure is not limited thereto. The transistor T3 may be located near the surface of the semiconductor layer 7220. In other words, the transistor T3 may be entirely located on the surface of the semiconductor layer 7220; or alternatively, a portion of the transistor T3 (e.g., the gate structure) may be located on the surface of the semiconductor layer 7220, and another portion of the transistor T3 (e.g., the drain structure and / or source structure) may be located below the surface of the semiconductor layer 7220 and within the semiconductor layer 7220; or alternatively, the transistor T3 may be entirely located within the semiconductor layer 7220. The interconnection structure 723 is located on the semiconductor layer 7220. The transistor T3 may be electrically connected to the interconnection structure 723. The interconnection structure 723 may contain conductive material. The device layer 722 and the interconnection structure 723 can form part of the second peripheral circuit 105; or alternatively, the second peripheral circuit 105 may include the device layer 722 and the interconnection structure 723. The transistor T3 may be electrically connected to the charge pump circuit and the low decoder of the second peripheral circuit 105. In one embodiment, transistor T3 can be a complementary metal oxide semiconductor field-effect transistor.

[0055] In the embodiment shown in Figure 7, the surface including the first interconnection structure 613 and the third interconnection structure 618 may be defined as the functional surface of the first semiconductor structure 210W, and the surface including the input / output pads 116 may be defined as the back surface of the first semiconductor structure 210W. In the first semiconductor structure 210W, the power supply network is provided on the back surface, which may improve power consumption and performance. The first semiconductor structure 210W includes a back-side power supply network (BSPDN). In the first semiconductor structure 210W, the signal network is provided on the functional surface of the first semiconductor structure 210W. In the embodiment shown in Figure 7, the surface including the conductive element 732 and the contact element 744 may be defined as the functional surface of the third semiconductor structure 230W, and the surface of the substrate 730 not used for arranging the memory string 733 may be defined as the back surface of the third semiconductor structure 230W. The surface including the interconnection structure 723 may be defined as the functional surface of the second semiconductor structure 220W. Therefore, the first semiconductor structure 210W is bonded to the third semiconductor structure 230W in a face-to-face orientation, and the second semiconductor structure 220W is bonded to the third semiconductor structure 230W in a face-to-back orientation. In one embodiment, a signal can be propagated between the memory cells of the memory string 733 of the third semiconductor structure 230W, the conductive element 732 of the third semiconductor structure 230W, and the page buffer in the first peripheral circuit 103 of the first semiconductor structure 210W. In one embodiment, a signal can be propagated between the conductive layer 7311 of the third semiconductor structure 230W, the stepped conductive layer 7411 of the third semiconductor structure 230W, the plug element 742 of the third semiconductor structure 230W, the conductive structure 743 of the third semiconductor structure 230W, and the raw decoder in the second peripheral circuit 105 of the second semiconductor structure 220W.

[0056] Referring to Figure 8, Figure 8 illustrates a schematic cross-sectional view showing one of the component configurations of a memory device 30 according to several embodiments of the present disclosure.

[0057] The memory device 30 includes a first semiconductor structure 310W, a second semiconductor structure 320W, and a third semiconductor structure 330W. The first semiconductor structure 310W includes a first peripheral circuit 103. The first semiconductor structure 310W includes a device layer 612, a first interconnect structure 613, a second interconnect structure 614, a via element 617, a third interconnect structure 618, and an input / output pad 116. In this embodiment, the first semiconductor structure 310W is similar to the first semiconductor structure 110W' and the first semiconductor structure 210W, and the configuration and description of the components within the first semiconductor structure 310W may refer to the descriptions related to the first semiconductor structure 110W' and the first semiconductor structure 210W. The first interconnect structure 613 and the third interconnect structure 618 are located between the device layer 612 and the third semiconductor structure 330W. The second interconnection structure 614 is located between the device layer 612 and the input / output pads 116. The first interconnection structure 613 may be electrically connected to the conductive elements 832 and memory strings 733 of the third semiconductor structure 330W. The input / output pads 116 may be electrically connected to the contact elements 744 of the third semiconductor structure 330W via the second interconnection structure 614, via elements 617, and the third interconnection structure 618.

[0058] The third semiconductor structure 330W includes a memory array 101. The third semiconductor structure 330W includes a substrate 730, a stacked structure 731, a conductive element 832, a memory string 733, a stepped structure 741, a plug element 742, a conductive structure 843, and a contact element 744. The stacked structure 731 and the memory string 733 may be arranged within the array region MR of the third semiconductor structure 330W. The memory array 101 is located between the substrate 730 and the second semiconductor structure 320. The conductive element 832 is located on top of the memory string 733. The conductive element 832 may penetrate the substrate 730. The conductive element 832 is electrically connected to the memory string 733. The memory array 101 (or memory string 733) may be electrically connected to the interconnect structure 613 of the first semiconductor structure 310W via the conductive element 832. In one embodiment, the conductive element 832 may include at least one bit line. In one embodiment, the conductive element 832 may include at least one conductive stripe and at least one interlayer connector, the conductive stripe and interlayer connector comprising a conductive material, and the conductive stripe may function as a bit line. The conductive element 832 shown in Figure 8 may extend beyond the underside of the laminated structure 731 and the underside of the memory string 733, penetrate the substrate 730, and be electrically connected to the interconnection structure 613 of the first semiconductor structure 310W located beneath the third semiconductor structure 330W.

[0059] The stepped structure 741 and the plug element 742 may be located within the peripheral region of the third semiconductor structure 330W. The peripheral region may be adjacent to the array region MR. The peripheral region may surround the array region MR. The stepped structure 741 is located on the substrate 730. The stepped structure 741 may be located on one side of the laminated structure 731. The stepped conductive layer 7411 of the stepped structure 741 may be electrically connected to the conductive layer 7311 of the laminated structure 731. The plug element 742 is electrically connected to the stepped conductive layer 7411 on which the plug element 742 is located, and is electrically connected to the conductive layer 7311 located at the same hierarchical level as this stepped conductive layer 7411. The conductive structure 843 is located on top of the plug element 742. The conductive structure 843 may be electrically connected between the plug element 742 and the interconnection structure 723 of the second semiconductor structure 320W. The contact element 744 may extend along the Z direction and penetrate the substrate 730. The contact element 744 may be electrically connected to the interconnection structure 723 of the second semiconductor structure 320W. The contact element 744 may be electrically connected to the third interconnection structure 618 of the first semiconductor structure 310W.

[0060] The semiconductor structure 320W includes a second peripheral circuit 105. The semiconductor structure 320W includes a device layer 722 and an interconnect structure 723. The device layer 722 includes a semiconductor layer 7220 and a transistor T3. Figure 8 shows that the transistor T3 is located on the surface of the semiconductor layer 7220, but the disclosure is not limited thereto. The transistor T3 may be located near the surface of the semiconductor layer 7220. That is, the transistor T3 may be located entirely on the surface of the semiconductor layer 7220; or alternatively, a portion of the transistor T3 (e.g., the gate structure) may be located on the surface of the semiconductor layer 7220, and another portion of the transistor T3 (e.g., the drain structure and / or source structure) may be located below the surface of the semiconductor layer 7220 and inside the semiconductor layer 7220; or alternatively, the transistor T3 may be located entirely inside the semiconductor layer 7220. The interconnect structure 723 is located on top of the semiconductor layer 7220. The interconnection structure 723 may be located between the semiconductor layer 7220 and the third semiconductor structure 330W. Transistor T3 may be electrically connected to the interconnection structure 723. The device layer 722 and the interconnection structure 723 may form part of the second peripheral circuit 105; or alternatively, the second peripheral circuit 105 may include the device layer 722 and the interconnection structure 723. Transistor T3 may be electrically connected to the charge pump circuit and the low decoder of the second peripheral circuit 105.

[0061] In the embodiment shown in Figure 8, the surface including the first interconnection structure 613 and the third interconnection structure 618 may be defined as the functional surface of the first semiconductor structure 310W, and the surface including the input / output pads 116 may be defined as the back surface of the first semiconductor structure 310W. In the first semiconductor structure 310W, the power supply network is provided on the back surface, which may improve power consumption and performance. The first semiconductor structure 310W includes a back-side power supply network (BSPDN). In the first semiconductor structure 310W, the signal network is provided on the functional surface of the first semiconductor structure 310W. In the embodiment shown in Figure 8, the surface including the conductive structure 843 and the contact elements 744 may be defined as the functional surface of the third semiconductor structure 330W, and the surface of the substrate 730 not used for arranging the memory string 733 may be defined as the back surface of the third semiconductor structure 330W. In the embodiment shown in Figure 8, the surface including the interconnection structure 723 may be defined as the functional surface of the second semiconductor structure 320W. Therefore, the third semiconductor structure 330W is bonded to the second semiconductor structure 320W in a face-to-face orientation, and the first semiconductor structure 310W is bonded to the third semiconductor structure 330W in a face-to-back orientation. In one embodiment, a signal can be propagated between the memory cells of the memory string 733 of the third semiconductor structure 330W, the conductive element 832 of the third semiconductor structure 330W, and the page buffer in the first peripheral circuit 103 of the first semiconductor structure 310W. In one embodiment, a signal can be propagated between the conductive layer 7311 of the third semiconductor structure 330W, the stepped conductive layer 7411 of the third semiconductor structure 330W, the plug element 742 of the third semiconductor structure 330W, the conductive structure 843 of the third semiconductor structure 330W, and the raw decoder in the second peripheral circuit 105 of the second semiconductor structure 320W.

[0062] In one embodiment, the memory device according to the Disclosure may include 32 or more faces, each face may include a plurality of blocks, each block may include a plurality of pages, and each page may include memory cells. In one embodiment, the memory device according to the Disclosure may include 32 or more I / Os (i.e., 32 or more data paths); for example, the memory device according to the Disclosure may include 1024 I / Os.

[0063] This disclosure provides a peripheral circuit system for a memory device, and a memory device including the peripheral circuit system and a memory array. In this disclosure, a portion of the peripheral circuit system (a first peripheral circuit) and another portion of the peripheral circuit system (a second peripheral circuit) are arranged along the longitudinal direction, thereby increasing the footprint of the peripheral circuit system without increasing the area (lateral area) of the memory device, and improving the performance, durability, power consumption, and reliability of the memory device while taking into account the need to reduce the area of ​​the memory device.

[0064] It should be noted that the structures described above are provided for illustrative purposes only. This disclosure is not limited to the configurations disclosed above. Other embodiments having different configurations of known elements may also be applicable. Furthermore, the illustrated structures may be adjusted and modified based on the actual needs of practical application. It should be noted that the configurations in the figures are, of course, drawn for illustrative purposes only and not for limitation. Accordingly, it is known to those skilled in the art that the relevant elements and layers within the memory device, and the shapes or positional relationships of those elements, may be adjusted or modified according to the actual requirements of practical application and / or manufacturing processes.

[0065] While this disclosure has been described using examples and in terms of exemplary embodiments, it should be understood that this disclosure is not limited thereto. Rather, it is intended to cover a variety of variations and similar configurations and procedures, and therefore the appended claims should be interpreted in the broadest way to encompass all such variations and similar configurations and procedures.

Claims

1. A peripheral circuit system for a memory device, A first peripheral circuit electrically connected to the memory array of the memory device; and A second peripheral circuit electrically connected to the memory array. Equipped with, A peripheral circuit system in which the first peripheral circuit and the second peripheral circuit are arranged along the longitudinal direction.

2. The peripheral circuit system according to claim 1, wherein the second peripheral circuit has at least one charge pump circuit and at least one low decoder.

3. The peripheral circuit system according to claim 1, wherein the first peripheral circuit has at least one page buffer and at least one input / output circuit.

4. The peripheral circuit system according to any one of claims 1 to 3, wherein the first peripheral circuit and the second peripheral circuit are arranged on opposite sides of the memory array.

5. The peripheral circuit system according to any one of claims 1 to 3, wherein the first peripheral circuit and the second peripheral circuit are located on the same side of the memory array.

6. A peripheral circuit system according to any one of claims 1 to 3, wherein the first peripheral circuit is arranged in a first semiconductor structure, the second peripheral circuit is arranged in a second semiconductor structure, the first semiconductor structure and the second semiconductor structure are stacked along the longitudinal direction, and the first semiconductor structure is hybrid-bonded to the second semiconductor structure.

7. A first semiconductor structure having a first peripheral circuit; and Second semiconductor structure having a second peripheral circuit and a memory array Equipped with, A memory device in which the first semiconductor structure is bonded to the second semiconductor structure, the first peripheral circuit is electrically connected to the memory array, and the second peripheral circuit is electrically connected to the memory array.

8. The memory device according to claim 7, wherein the first peripheral circuit and the second peripheral circuit are arranged on opposite sides of the memory array.

9. The memory device according to claim 7, wherein the first peripheral circuit includes at least one page buffer and at least one input / output circuit, and the second peripheral circuit includes at least one charge pump circuit and at least one raw decoder.

10. The memory device according to any one of claims 7 to 9, wherein the second semiconductor structure has a substrate and contact elements, the second peripheral circuit is disposed on the first side of the substrate, the memory array is disposed on the second side of the substrate and between the substrate and the first semiconductor structure, the first side is opposite to the second side, and the first peripheral circuit is electrically connected to the second peripheral circuit via the contact elements.

11. The memory device according to claim 10, wherein the first semiconductor structure comprises a device layer, a first interconnection structure, a second interconnection structure, via elements, a third interconnection structure, and input / output pads, the first interconnection structure and the second interconnection structure are arranged on opposite sides of the device layer, the second interconnection structure is located between the input / output pads and the device layer, the first interconnection structure and the third interconnection structure are located between the device layer and the second semiconductor structure, and the via elements penetrate the device layer.

12. The memory device according to claim 11, wherein the input / output pads are electrically connected to the second semiconductor structure via the second interconnection structure, the via elements, and the third interconnection structure.

13. A first semiconductor structure having a first peripheral circuit; A second semiconductor structure having a second peripheral circuit; and Third semiconductor structure having a memory array Equipped with, A memory device in which the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are arranged along the longitudinal direction, the first peripheral circuit is electrically connected to the memory array, and the second peripheral circuit is electrically connected to the memory array.

14. The memory device according to claim 13, wherein the third semiconductor structure is arranged in the longitudinal direction between the first semiconductor structure and the second semiconductor structure.

15. The memory device according to claim 13, wherein the first peripheral circuit includes at least one page buffer and at least one input / output circuit, and the second peripheral circuit includes at least one charge pump circuit and at least one low decoder.

16. The memory device according to claim 15, wherein the first semiconductor structure is bonded to the third semiconductor structure in a face-to-face manner, and the second semiconductor structure is bonded to the third semiconductor structure in a face-to-back manner.

17. The memory device according to claim 15, wherein the second semiconductor structure is bonded to the third semiconductor structure in a face-to-face manner, and the first semiconductor structure is bonded to the third semiconductor structure in a face-to-back manner.

18. The memory device according to claim 13, wherein the third semiconductor structure comprises a substrate, a word line, a plug element, and a conductive structure, the word line, the plug element, and the memory array are located on the substrate, the conductive structure penetrates the substrate, and the word line is electrically connected to the second semiconductor structure via the plug element and the conductive structure.

19. The memory device according to claim 13, wherein the third semiconductor structure has a substrate and conductive elements, the memory array is on the substrate, the conductive elements penetrate the substrate, and the memory array is electrically connected to the first semiconductor structure via the conductive elements.

20. The memory device according to any one of claims 13 to 19, wherein the first semiconductor structure is arranged longitudinally between the third semiconductor structure and the second semiconductor structure.

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