A method for simultaneously transmitting data and measuring distance.

Abstract

For example, this provides a simultaneous data transfer and distance measurement method that enables highly accurate distance measurement even at high data transfer speeds of at least 1 gigabit per second (1 Gbit / s). [Solution] The present invention relates to a method for simultaneously transmitting data and measuring distance between a first device and a second device, wherein the first device and the second device each have a transmitting device configured for optical data transmission, a receiving device configured for optical data reception, and a control unit coupled to and / or at least partially integrated with the transmitting device and the receiving device, and a data signal is transmitted from the first device to the second device. The method is characterized in that a received clock signal is generated from the data signal to indicate the clock information of the data signal, the phase position of the received clock signal is identified, and the distance between the first device and the second device is identified from the phase position.

Description

[Technical Field]

[0001] The present invention relates to a method for simultaneously transmitting data and measuring distance between a first device and a second device, wherein the first device and the second device each comprise a transmitting device configured for optical data transmission, a receiving device configured for optical data reception, and a control unit coupled to and / or at least partially integrated with the transmitting device and the receiving device. In this regard, a data signal is transmitted from the first device to the second device. [Background technology]

[0002] A method for simultaneously transmitting data and measuring distance is used, for example, in high-bay warehouses, where the autonomous vehicle (e.g., storage and retrieval unit: SRU) establishes a continuous data connection with the base station in order to transmit control data and / or sensor data between the base station and the autonomous vehicle, and to determine the vehicle's position (i.e., distance from the base station) as accurately as possible.

[0003] Such a method for simultaneously transmitting data and measuring distance is known, for example, from Patent Document 1. In the method described in that document, a considerable amount of oversampling and an intentional shift of the system clock are performed in order to achieve accurate distance measurement. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] DE 10 2014 111 589 A1 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, since clear oversampling is usually impossible when the data transfer rate in the data signal is too high, the above method is only possible at low data transfer rates.

[0006] Therefore, the fundamental objective of the present invention is to specify a simultaneous data transfer and distance measurement method that enables highly accurate distance measurement even at high data transfer speeds of, for example, at least 1 gigabit per second (1 Gbit / s). [Means for solving the problem]

[0007] This objective is satisfied by the method described in claim 1.

[0008] The method according to the present invention is characterized in that a received clock signal is generated from a data signal by a second device in particular, indicating the clock information of the data signal, the phase position of the received clock signal is identified, and in particular, the distance between the first device and the second device is identified from at least the phase position.

[0009] This invention is based on the understanding that highly accurate distance measurement is possible even at high data transfer speeds by using only the clock signal of the data signal, rather than the data signal itself. Furthermore, an advantage of this invention is that the hardware conventionally required to receive such data signals can be used in the same way for distance measurement, and especially for generating the received clock signal.

[0010] Further details of the present invention are described below.

[0011] The method according to the present invention is used for simultaneous data transfer and distance measurement between a first device and a second device. The first device can be, for example, the base station mentioned earlier, and the second device can be a device attached to an unmanned vehicle. However, in principle, the first device and the second device can be of the same design.

[0012] The first and second devices may have a maximum distance of, for example, 100m, 300m, or 500m between them. Each of the devices comprises a transmitter configured for optical data transmission and a receiver configured for optical data reception. The transmitter and receiver can also be configured as a single unit to form a transceiver. The transmitter and receiver (or transceiver) are coupled to a control unit via a data connection and / or at least partially integrated into the control unit. For example, the light emitter (e.g., a laser diode or LED) of the transmitter and the light receiver (e.g., a photodiode) of the receiver can be coupled to the control unit and connected, for example, to the output or input of the control unit. The generation of signals for the light emitter and / or the processing of signals for the light receiver can be performed in the control unit, i.e., integrated.

[0013] During operation of the apparatus, a data signal is optically transmitted from the first apparatus to the second apparatus. Furthermore, the second apparatus can also optically transmit a data signal to the first apparatus. The data signal is optically transmitted by each transmitting device and optically received by the receiving device of the other apparatus.

[0014] The aforementioned data signals (and other data signals described later) particularly include payloads, such as control data or sensor data for (autonomous) vehicles. Preferably, the data signals transmitted from the first device to the second device are different from the data signals transmitted from the second device to the first device. Therefore, the data signals are not simply reflected in the first or second device. The information transmitted between devices along with the data signals can be binary encoded by on-off keying (OOK). That is, when transmitting a binary 1, the light emitter of the transmitting device is switched on, for example, and when transmitting a binary 0, it is switched off. The light emitter can be configured as a laser, particularly as a laser diode.

[0015] The data signal preferably includes a serial data signal, and more particularly has the aforementioned payload.

[0016] Preferably, both data transmission and distance measurement are achieved using only a single communication channel, i.e., a communication channel for optical data transmission between two devices. There is a point-to-point connection between the two devices. In particular, there is a straight line-of-sight between the two devices.

[0017] For distance measurement, the time required for the data bits of the data signal to reach from the first device to the second device or vice versa can be determined. Then, based on the constant propagation speed of the data signal transmitted by light (i.e., the speed of light), the distance between the first device and the second device can be determined. This can be done, for example, by one of such designed units among a plurality of control units.

[0018] In the present invention, a received clock signal is generated or restored from the data signal. The received clock signal preferably includes the clock information of the data signal, i.e., timing information. For example, in the case of a serial signal, the serial signal can be restored in the receiving device and / or the control unit of the receiving device using the clock information or timing information. The received clock signal can be, for example, a square wave signal in which each edge indicates the time position of an individual data bit in the data signal. In the present invention, the phase position of the received clock signal is ordinarily determined or evaluated, and the phase position can be obtained, for example, by evaluating the position of each edge of the received clock signal.

[0019] By determining or evaluating the phase position according to the present invention, the distance between the first device and the second device can be determined much more accurately than by evaluating only the transmitted symbols, bytes, words, or timestamps, for example. And the determined distance can be output as a distance signal by at least one of the devices, and in particular, can be used during the operation of the device or the vehicle equipped with the device.

[0020] The generation of the received clock signal and / or evaluation of its phase position required according to the present invention can be performed in part or in whole in the control unit. The data signal underlying the received clock signal preferably has a data transfer rate of at least 1 gigabit per second or at least 1.3 Gbit / s.

[0021] Advantageous embodiments of the present invention can be understood from the specification, the drawings and the dependent claims.

[0022] In the first embodiment, the received clock signal includes a clock data recovery signal (CDR signal). The CDR signal can be generated, for example, by a PLL circuit (phase-locked loop circuit).

[0023] The unit that generates the CDR signal may be located in the receiving unit and / or control unit, and may enable the receiving side to reconstruct the serial signal within the data signal.

[0024] The received clock signal can be the CDR signal itself, a signal containing the CDR signal, or a signal that can be derived from the CDR signal. Preferably, the received clock signal does not contain any payload from the data signal. For example, the received clock signal can be a square wave signal that does not contain any data information. The square wave signal can have, for example, only the same square wave pulses that repeat at the same intervals.

[0025] In contrast to the received clock signal, the data signal therefore contains a payload that can be modulated and superimposed on the data signal.

[0026] In another embodiment, the received clock signal is preferably divided into predetermined multiples (frequency) by a serial-parallel converter. A frequency divider can also be used as an alternative to or in addition to the serial-parallel converter. For example, the serial-parallel converter may be a 20-bit converter. The frequency of the received clock signal or the frequency of edge occurrences in the received clock signal can be divided into predetermined multiples (e.g., 20 in this case) by the 20-bit converter.

[0027] Instead of 20 as the predetermined multiple, other numbers such as 5, 10, 15, 25, 36, 50, 64, 100, or 132 are also possible. In particular, the predetermined multiple is the value of the number of bits used to encode a data word or byte in the (optical) data signal. The predetermined multiple can also be within the range of half and twice the value mentioned earlier. When using the 8B10B scheme, which will be discussed later, as the encoding method, one data word is represented by two bytes, so each data word is encoded with 20 bits, and therefore in this case, the predetermined multiple is 20.

[0028] Dividing the received clock signal into predetermined multiples is particularly useful in facilitating subsequent sampling of the received clock signal, as will be discussed later.

[0029] In another embodiment, the received clock signal is output to the output of a control unit and, preferably, input again to the input of the same control unit. The control unit can be an FPGA (Field Programmable Gate Array), particularly a single FPGA, an ASIC (Application Specific Integrated Circuit), particularly a single ASIC, or an integrated circuit in general, particularly a single integrated circuit. The output and input of the control unit can be, for example, output pins or input pins. Alternatively, the output of the control unit (e.g., an output pin) can be sampled or directly input, thereby eliminating the need to physically send the received clock signal outside the control unit.

[0030] Outputting the received clock signal later and re-inputting it has the advantage of allowing the control unit to use hardware suitable for detecting the phase position, enabling detection with very high resolution, although this is usually only available at a dedicated input of the control unit. Therefore, the output and input of the control unit can belong to the same integrated circuit.

[0031] Alternatively, the input can be placed in another integrated circuit, such as an external evaluation unit, and the received clock signal can be transmitted to that external evaluation unit.

[0032] In another embodiment, the received clock signal includes multiple edges, of which at least two, preferably three, and particularly preferably four edges are sampled and / or evaluated to determine the phase position.

[0033] In particular, the multiple edges are sampled as a set (i.e., for example, simultaneously and / or as a common signal) in a single sampling process.

[0034] The number of edges mentioned above can be the minimum value, but it is also possible to sample and / or evaluate exactly that specified number of edges. Similarly, a larger number of edges can be handled in the same way, for example, 6, 8, 10, 15, 20, 32, or even 64 edges.

[0035] In another embodiment, the edge gradient of each edge of the received clock signal, particularly all edges, is reduced, preferably by a delay element, before the phase position is determined. Thus, the gradient of each edge in the received clock signal is artificially or intentionally reduced. This helps to map more sampling points onto the edges.

[0036] In particular, the control unit can be configured to sample each edge of the received clock signal at multiple sampling points, for example, at least four, eight, or twelve sampling points on that edge.

[0037] In addition to or as a substitute for the aforementioned delay elements (e.g., I / O delay blocks), operational amplifiers, logic gates, etc., can also be used to reduce the edge slope.

[0038] Delay elements and / or additional jitter units can be used to add composite jitter to the received clock signal, either alternatively or additionally, to reduce the edge slope of each edge in the received clock signal. The composite jitter can be set to, for example, 4 ps to 60 ps or 2 ps to 100 ps. The composite jitter can be changed between different sampling processes to determine the phase position. Since the magnitude of the composite jitter is known, it can be taken into account (and, for example, calculated) when determining the phase position. By changing the composite jitter, edges can be shifted slightly between different sampling processes, thereby allowing sampling points to exist not only before and after the edge, but also directly on the edge.

[0039] Specifically, this makes it possible to generate sampling points on the edge that can not only correspond to the value of the received clock signal before or after the edge (i.e., 0 or 1), but can also take an intermediate value, i.e., represent an "analog" value. For example, if an intermediate value is available, the location of the edge can be determined more precisely by using that intermediate value to pinpoint the zero crossing point (e.g., corresponding to the N / 2 threshold in Figure 4).

[0040] In another embodiment, at least one sampling process, particularly binary sampling, is performed to determine the phase position, in which preferably multiple edges of the received clock signal are sampled simultaneously or together each time, preferably by a double data rate circuit (DDR circuit).

[0041] The phase position is determined by the sampling process, in particular by identifying the precise time position of one or more edges of the received clock signal.

[0042] The DDR circuit allows for the evaluation of both falling and rising edges. For example, four clocks can be sampled or evaluated together. This effectively allows sampling of four clocks, each with two edges, at an 8x sampling rate. This 8x sampling rate should be understood in comparison to the computing unit's sampling clock or system clock. For example, if the computing unit's system clock is 390MHz, an 8x sampling rate results in an effective sampling rate of 3.12 gigasamples per second. This makes it possible to sample and identify phase positions with great precision.

[0043] The sampling rate eight times higher than in the above example can be achieved, in particular, preferably by performing sampling at each time point shifted in addition to each time point predetermined by the system clock or sampling clock. Typically, the device can be configured to generate multiple (e.g., four) additional signals that are phase-shifted relative to the sampling clock or system clock, for example using another PLL circuit, from the sampling clock or system clock, and to similarly use these additional signals for sampling the edges of the received clock signal. The phase shift of the additional signals can be 45°, 90°, 135°, 225°, 270° and / or 315°. The phase shift of the additional signals can be generated, in particular, by a SERDES unit (serializer-deserializer unit) available in many FPGAs. The additional signals can be used to sample the received clock signal, in particular by sampling multiple edges in combination.

[0044] Roughly speaking, the sampling rate, especially the effective sampling rate, can be 1 gigasample per second or more, 2 gigasamples per second or more, or 3 gigasamples per second or more.

[0045] In another embodiment, the final phase position is obtained by creating a histogram from multiple phase positions identified in multiple sampling processes.

[0046] In particular, a system clock or sampling clock is formed by preferably coherently accumulating sampling points. A predetermined time sequence, for example, a predetermined number of clock cycles (i.e., combinations of edges) of a received clock signal, is sampled. That is, sampling is repeated, for example, N times. In this regard, in each sampling process, at a certain time t (0 to n), the binary state at that time t is accumulated. Thus, a histogram of depth N is created. Preferably, the distance between the first device and the second device is determined (at least) from the final phase position. Therefore, the final phase position should be understood as the result of determining the phase position, and that final phase position is included in determining or calculating the distance between the first device and the second device.

[0047] In particular, the histogram is created by preferably coherently accumulating multiple sampling processes over a measurement time of, for example, 10 μs. During the accumulation, edge positions obtained from multiple sampling processes are recorded in the histogram. Specifically, the histogram may include, for example, 10, 100, or 1000 sampling processes.

[0048] For example, in a single sampling process, four edges are sampled and recorded in a histogram. Then, the phase position can be determined, for example, based on the third rising edge in the histogram. Accordingly, the final phase position is determined by, for example, the third rising edge.

[0049] In principle, the distance can be determined from the current phase position after each processing step, but it is preferable to determine it from the final phase position.

[0050] The sampling of multiple edges described so far may be advantageous because the sequence (falling / rising edges) is repeated after one clock cycle of the received clock signal. If the coarse measurement (described later) changes, for example, in the least significant bit (LSB) based on the transmission and reception times, it is preferable to account for the change in the phase measurement by switching to another rising edge to determine the final phase position. Since this switching can occur in both positive and negative directions, it is advantageous if the combination includes at least three (rising) edges.

[0051] Preferably, the distance between the first and second devices is repeatedly determined, for example, at least every 1 μs, 10 μs, or 100 μs. Since each of these times is sufficiently short, even if phase drift occurs in the system clock, it does not lead to significant distortion of the measured distance. In particular, since the first and second devices remain within each other's field of view in all cases, continuous distance measurement is possible. If the position of the edge used to determine the distance moves within the histogram, a new distance value is also generated. If the position of the edge used to determine the distance moves further within the histogram, to the edge of the histogram, or even disappears from the histogram, the adjacent (rising) edge is used to determine the distance.

[0052] In another embodiment, the distance between the first device and the second device is additionally determined based on characters encoded in the data signal.

[0053] While distance determination based on the phase position of the received clock signal allows for very accurate distance measurements, it can be ambiguous over long distances. Therefore, to generate unambiguous distances, an additional (coarser) distance measurement based on characters encoded in the data signal can be used. This can be done, for example, through timestamp exchange, which will be explained in more detail later. If the time resolution of timestamp exchange is one-third of the system clock (390MHz / 3=130MHz), the time resolution is 7.7ns. This corresponds to a distance resolution of 2.3m.

[0054] In data signals, transmitted characters can exist as encoded data words, for example, encoded using the 8B10B scheme. Such encoding has the advantage of eliminating the DC component of the optical signal. Alternatively, for example, 16B18B or 64B66B encoding can be used for optical data transmission between a first and second device. In general, other encodings without a DC component can also be chosen.

[0055] In another embodiment, determining the distance based on characters encoded in the data signal includes the following steps: The first device transmits a first data signal to the second device. The first data signal is transmitted at time t SycA It contains and / or defines (as an encoded character). • The second device receives the first data signal at time t RecB Save it. The second device transmits a second data signal to the first device. The second data signal is transmitted at time t SycB It contains and / or defines (as an encoded character). • The first device receives the second data signal at time t RecA Save it.

[0056] Reception time t RecA and t RecBcan preferably be sent to the other device through a data signal respectively. In particular, the transmission time can be determined, that is, specified, by the transmission of the data signal. However, at that time, the transmission time can only be sent to the other device later.

[0057] Generally speaking, the two devices can exchange the reception time and / or the transmission time with each other through a data signal. For example, the reception time and / or the transmission time can also be exchanged within the same time grid, that is, at the same time interval, used when specifying the distance between the two devices from the phase position of the reception clock signal (for example, 10 μs). The reception time and / or the transmission time are, for example, counter indication values generated by a system clock. By synchronizing the exchange of the reception time and / or the transmission time and the specification of the phase position, the distance between the two devices can be specified particularly accurately.

[0058] The flight time can be calculated particularly using the following formula. [Formula 1] TOF_A = 1 / 2[(t RecA -t SycB ) + (t RecB -t SycA )]

[0059] And the distance between the devices can be specified by multiplying the flight time by the speed of light.

[0060] In the above-described manner, it is understood that in any case, the first device and the second device can be interchanged.

[0061] Due to the tolerance of components and other influences, the time bases of the first device and the second device may be different. The offset between the time base of the first device and the time base of the second device can be calculated using the following formula. [Formula 2] Offset = 1 / 2[(t RecA -t SycB ) - (t RecB -t SycA )]

[0062] Distance measurements based on transmission and reception times can be considered coarse, while distance measurements based on the received clock signal can be considered precise.

[0063] Coarse measurements can limit the approximate distance range between the first and second devices. Within this defined distance "window," the correct distance can be determined based on distance measurements on the received clock signal. Thus, ambiguous distance measurements based on the received clock signal can become unambiguous through coarse measurements.

[0064] To initialize distance measurement, i.e., to establish a connection between the first and second devices, a special comma word can be transmitted. Since the two transmitting and receiving devices are preferably always facing each other in normal or linear travel mode, thereby ensuring continuous exchange of data signals, it is sufficient to identify the rising edge to be evaluated in the histogram only once when establishing the connection. Furthermore, in order to evaluate the correct edge during resynchronization, it is necessary to first generate a clock twice as fast for timestamp exchange, or to establish this uniqueness with a double measurement and a phase-shifted cycle. A clock twice as fast can be obtained, for example, by temporarily using twice the count rate for the counter indicator values ​​indicating the transmission and / or reception times.

[0065] Phase drift between the system clocks of the two devices can cause blurring of the histogram. Since this is undesirable, the first and second devices can be configured such that the phase drift between the system clocks of the first and second devices within a 10 μs measurement time is less than 200 ps, ​​preferably less than 100 ps, ​​and more preferably less than 50 ps.

[0066] To compensate for errors in the specified distance caused by phase drift between system clocks, the two devices can each independently determine the distance between the first and second devices, then exchange the determined distances through data signals, and take the average of the two distance values.

[0067] In another embodiment, the reception of data signals, the generation of received clock signals, and the determination of the phase position of said received clock signals are performed by the same control unit, in particular by the same FPGA. As previously described, an ASIC or other integrated circuit can be used instead of an FPGA.

[0068] Using the same control unit allows both distance determination and phase position detection based on encoded character data signals to be performed using the same system clock of the control unit. This reduces inaccuracies caused by different clocks, which in turn improves the accuracy of distance measurement and lowers hardware requirements.

[0069] The present invention further relates to an apparatus for simultaneously transmitting data and measuring distance. The apparatus comprises a transmitting device configured for optical data transmission, a receiving device configured for optical data reception, and a control unit coupled to and / or at least partially integrated with the transmitting and receiving devices, wherein the apparatus is configured to receive a data signal from a second device, particularly using the receiving device. In the present invention, the apparatus is configured to generate a received clock signal from the data signal, indicating clock information of the data signal, and the apparatus is further configured to determine the phase position of the received clock signal, and in particular to determine the distance between the apparatus and the second device from the phase position.

[0070] Another subject of the present invention is a system comprising two such devices, one of which functions as the first device and the other as the second device. The first and second devices can be arranged in a straight line of sight to each other. At least one of the devices can be installed in a vehicle, particularly an autonomous vehicle.

[0071] In the system described above, an additional communication channel may be provided between the first and second devices, which is used for temperature compensation, particularly for temperature drift of the system clocks between them. This additional channel may be configured, for example, for optical data transmission or for wireless data transmission. Temperature drift compensation can further compensate for differences in the system clocks of the devices, thereby enabling more accurate distance measurement. For example, the temperature of each device and / or correction values ​​for the device temperatures can be transmitted through the additional channel, and temperature drift can be compensated based on these values.

[0072] The statements relating to the methods according to the present invention also apply to the apparatus and systems according to the present invention. This applies particularly to embodiments and advantages. Furthermore, unless otherwise explicitly stated, all features described herein are understood to be combinable.

[0073] The present invention will be described below with reference to the drawings, merely as an example. The drawings are as follows. [Brief explanation of the drawing]

[0074] [Figure 1] A schematic diagram illustrating an unmanned transport system. [Figure 2] A schematic diagram showing the internal design of a device for distance measurement. [Figure 3] A diagram illustrating the transmission of data signals for distance measurement. [Figure 4] A diagram showing a histogram for recording the positions of edges. [Modes for carrying out the invention]

[0075] Figure 1 schematically shows an unmanned transport system 10 equipped with a storage and retrieval unit (SRU) 12 as an unmanned transport vehicle. A first device 14 is attached to the SRU 12 and has a first transmitter 16 and a first receiver 18. The first transmitter 16 has a light source 17 in the form of a laser diode or LED, as shown in Figure 2. The first receiver 18 also has a light receiver 19 in the form of a photodiode, as also shown in Figure 2. The first transmitter 16 and the first receiver 18 together constitute a transceiver 20.

[0076] The first device further includes a control unit 22 (shown in Figure 2) which is at least partially equipped with a transceiver 20.

[0077] The second device 26 is fixedly mounted, for example, to a wall 24. The second device 26 is designed in the same way as the first device 14 and therefore includes a second transmitter 28, a second receiver 30, and a control unit (not shown).

[0078] The orientation of the first device 14 and the second device 26 is such that the first transmitting device 16 transmits a data signal 32a (which is transmitted using an optical beam) to the second receiving device 30. Accordingly, the second transmitting device 28 transmits a second data signal 32b to the first receiving device 18. The optical data signal 32 can have a data transfer rate of 1.3 gigabits per second in particular.

[0079] The first data signal 32a and the second data signal 32b together form a transmission channel 34, through which a binary encoded payload is transmitted, for example, using a square wave pulse.

[0080] Figure 2 shows the first device 14 and the second device 26 in more detail. In particular, the internal design of the second device 26 is shown in more detail. The second device 26 is equipped with the light source 17 for transmitting data signals 32, and the light source 17 is coupled to an 8B10B encoder 38 via an amplifier 36 that converts the data signals generated by the control unit 22 into 8B10B format.

[0081] To receive the optical data signal from the first device 14, the second device 26 is equipped with a photodetector 19, which is then coupled to a CDR block 40 (clock data recovery block) via an amplifier 36. The CDR block 40 extracts the received clock signal 42 from the data signal 32. This signal initially has a frequency of 1.3 GHz, which corresponds to the data transfer rate of the data signal 32.

[0082] Furthermore, the CDR block 40 generates a serial data stream, which is decoded by the 8B10B decoder 44 and returned to the format originally used by the first device. Then, from the decoded signal, the reception time or transmission time, for example t RecA It is possible to identify this.

[0083] The received clock signal 42 is transmitted to a 20-bit serial-parallel converter 46. The serial-parallel converter 46 divides the frequency of the received clock signal by 20, resulting in the received clock signal 42 having a frequency of 65 MHz. The received clock signal 42 is then output from the control unit 22 through output pin 48 and input back into the control unit 22 through input pin 50. For this purpose, output pin 48 and input pin 50 can be directly electrically connected to each other.

[0084] The received clock signal 42 is then supplied from the input pin 50 to the delay element 52, and subsequently amplified again by the amplifier 36. The delay element 52 intentionally or artificially reduces the edge slope of each edge included in the received clock signal 42.

[0085] Finally, the received clock signal 42 is supplied to the DDR circuit 54. This samples the clock with two edges of the received clock signal four times, resulting in a sampling rate of 3.12 gigasamples per second (eight times the 390MHz clock).

[0086] For sampling the received clock signal 42, the DDR circuit 54 receives the clock signal generated by the clock generator 60 of the control unit 22. The clock signal is also supplied to the counter 62 which functions as the internal clock of each device 14, 26. The transmission time of the transmitted or received data (t in Figure 2) is further transmitted via the counter 62. SycA ) or at the time of receipt (t RecA ) can be identified.

[0087] Then, each sampled edge is plotted in histogram 56 over a sampling period of, for example, 10 μs. Figure 4 shows such a histogram 56 in more detail. Four rising edges are recorded in the histogram 56. The N / 2 threshold 58 is plotted in the histogram 56. The position of each edge is determined by interpolating the intersection with the N / 2 threshold 58, thereby obtaining picosecond-precision resolution. In particular, as shown in Figure 4, a third rising edge can be recorded, and the position of this edge can be used to indicate the final phase position.

[0088] By identifying the edge positions of the received clock signal 42, the phase position of the received clock signal 42 can be determined, and through that phase position, precise measurement of the distance between the first device 14 and the second device 26 is possible. Since the phase measurement (or histogram) includes four edges, the total measurement range in the phase measurement can be, for example, 4 × 15.4 ns, or 4 × 4.6 m. This is wider than the range of ambiguity in the coarse measurement described later.

[0089] The rough measurement will now be explained with reference to Figure 3. In the example shown in Figure 3, the rough measurement is initiated by the second device 26. For simplicity, and to use the same formula as previously stated, the second device 26 will also be referred to as device A, and the first device 14 will also be referred to as device B.

[0090] In Figure 3, it can be seen that the first device 14 and the second device 26 have different time bases. At time 0ns in the second device 26, the internal clock of the first device 14 is already at 68ns.

[0091] For rough measurement, a second device 26, i.e., device A, is used at time t SycA At (0ns), the first data signal 32a is sent to the first device. This first data signal is received by the first device 14 30ns later, at which point the internal clock of this device is at 98ns. This point in time is t RecB It is stored in the first device 14. Then, 10ns later, the first device sends the second data signal 32b to the second device 26. At that time, the transmission time is t SycB It is stored as (108ns), and the reception time of the second data signal 32b (70ns) is t RecA It will be saved as such.

[0092] Using the transmission and reception times thus identified, the flight time of the data signal 32 can be determined by the following formula. TOF_A=1 / 2[(t RecA -t SycB )+(t RecB -t SycA )]

[0093] In this example, the optical propagation time is 30 ns. In this regard, if, for example, the time resolution of timestamp exchange is 7.7 ns, the inaccuracy of coarse measurements or the distance resolution can be within the range of 2.3 m.

[0094] Furthermore, precise measurements using histograms can achieve an even higher accuracy, for example, 10 ps, ​​thereby increasing the distance resolution to 3 mm. Therefore, this significant improvement in distance resolution is achieved simultaneously with a very high data transfer rate. [Explanation of Symbols]

[0095] 10…Transportation systems 12…SRU 14…First device 16…First Transmitter 17...Light source 18…First receiving device 19…Receiver 20... Transmitter / Receiver 22…Control Unit 24... Wall 26...Second device 28... Second Transmitter 30...Second receiving device 32...Data signal 34…Transmission Channel 36… Amplifier 38…8B10B encoder 40…DDR Block 42... Received clock signal 44...8B10B Decoder 46…Serial-to-Parallel Converter 48…Output pins 50…Input pins 52... Delay element 54...DDR circuit 56... Histogram 58…N / 2 threshold 60... Clock generator 62... Counter

Claims

1. A method for simultaneously transmitting data and measuring distance between a first device (14) and a second device (16), wherein the first device (14) and the second device (16) each have transmitting devices (16, 28) configured for optical data transmission, receiving devices (18, 30) configured for optical data reception, and a control unit (22) coupled to and / or at least partially integrated with the transmitting devices (16, 28) and the receiving devices (18, 30), and a data signal (32) is transmitted from the first device (14) to the second device (26), A received clock signal (42) is generated from the data signal (32) to indicate the clock information of the data signal (32), the phase position of the received clock signal (42) is determined, and the distance between the first device (14) and the second device (26) is determined from the phase position. A method characterized by the following.

2. The method according to claim 1, wherein the received clock signal (42) includes or is based on a clock data recovery signal, i.e., a CDR signal.

3. The method according to claim 1 or 2, wherein the received clock signal (42) is preferably divided into predetermined multiples by a serial-to-parallel converter (46).

4. The method according to any one of claims 1 to 3, wherein the received clock signal (42) is output to the output (48) of the control unit (22), and preferably input again to the input (50) of the control unit (22).

5. The method according to any one of claims 1 to 4, wherein the received clock signal (42) includes a plurality of edges, of which at least two, preferably three, and particularly preferably four edges are sampled and / or evaluated to identify the phase position.

6. The method according to claim 5, wherein the edge slope of each edge of the received clock signal (42) is reduced, preferably by a delay element (52), before the phase position is determined.

7. The method according to any one of claims 1 to 6, wherein at least one sampling process, particularly a binary sampling process, is performed to determine the phase position, and in the process, a plurality of clocks and / or edges of the received clock signal (42) are preferably sampled simultaneously or together each time, preferably by a double data rate circuit, i.e., a DDR circuit (54).

8. The method according to any one of claims 1 to 7, wherein a final phase position is obtained by creating a histogram from a plurality of phase positions identified in a plurality of sampling processes, and the distance between the first device (14) and the second device (26) is determined from the final phase position.

9. The method according to any one of claims 1 to 8, wherein the distance between the first device (14) and the second device (26) is additionally determined based on characters encoded in the data signal (32).

10. The method according to claim 9, comprising the following steps for determining the distance based on characters encoded in the data signal (32). - The first device (14) transmits a first data signal (32) to the second device (26). The first data signal (32) is transmitted at time t ＳｙｃＡ It includes and / or specifies. - The second device (26) receives the first data signal (32) at time t ＲｅｃＢ Save it. The second device (26) transmits a second data signal (32) to the first device (14). The second data signal (32) is transmitted at time t ＳｙｃＢ It includes and / or specifies. - The first device (14) receives the second data signal (32) at time t ＲｅｃＡ Save it.

11. The method according to any one of claims 1 to 10, wherein the reception of the data signal (32), the generation of the received clock signal (42), and the determination of the phase position of the received clock signal (42) are performed by the same control unit (22), particularly by the same FPGA.

12. A device (14) that simultaneously transmits data and measures distance, comprising a transmitting device (16, 28) configured for optical data transmission, a receiving device (18, 30) configured for optical data reception, and a control unit (22) coupled to the transmitting device (16, 28) and the receiving device (18, 30), and configured to receive a data signal (32) from a second device (26), The device (14) is configured to generate a received clock signal (42) indicating the clock information of the data signal (32) from the data signal (32), and is further configured to identify the phase position of the received clock signal (42) and to identify the distance between the first device (14) and the second device (26) from the phase position. A device characterized by the following.

13. A system comprising two devices (14, 26) as described in claim 12, wherein one of them functions as a second device (26).

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