Power converter

Abstract

To stabilize the operation of a circuit composed of multiple power semiconductor elements. [Solution] The power conversion device 1 comprises a signal generation unit 2 that generates an on / off command signal, a gate drive circuit 3 that receives the on / off command signal and generates a delayed on / off command signal by delaying the on / off command signal by a predetermined time, and a switching unit 4 that generates an output current using a power semiconductor element 41 that operates based on the delayed on / off command signal. The gate drive circuit 3 includes a first variable resistance element 31 disposed between the signal generation unit 2 and the switching unit 4, a capacitor 34 disposed between the wiring connecting the first variable resistance element 31 to the switching unit 4 and a first reference potential 35, a second variable resistance element 32 connected in parallel with the first variable resistance element 31, and a diode 33 provided on the path connecting the first variable resistance element 31 and the second variable resistance element 32 in parallel.

Description

Technical Field

[0001] The present invention relates to a power conversion device.

Background Art

[0002] The magnitude of the current required by a load device is gradually increasing. An example of a load device is a motor. In this case, the device that supplies current to the load device that is a motor is an inverter. The inverter is composed of components that can handle a relatively large current called so-called power semiconductor elements. Patent Documents 1 to 4 disclose technologies related to circuits composed of power semiconductor elements.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] A device that supplies current to a load device comprises multiple power semiconductor elements. The characteristics of these power semiconductor elements vary within a predetermined range. This variation in the characteristics of the power semiconductor elements can have various effects on the operation and components of the device that supplies current to the load device, and can even cause the device to become unstable. Therefore, so-called screening is sometimes performed, in which the individual characteristics of the power semiconductor elements are inspected in advance, and elements with similar characteristics are combined. When screening is performed, the range of variation in the characteristics of the power semiconductor elements can be reduced compared to when screening is not performed. However, some variation in the characteristics of the power semiconductor elements still remains.

[0005] The present invention provides a power conversion device that achieves stable operation of a circuit composed of multiple power semiconductor elements through a simple circuit configuration. [Means for solving the problem]

[0006] A power conversion device according to one embodiment of the present invention comprises: a signal generation unit that generates an on / off command signal to turn a power semiconductor element on or off; a gate drive circuit that receives the on / off command signal and generates a delayed on / off command signal by delaying the on / off command signal by a predetermined time; and a switching unit that generates an output current using a power semiconductor element that operates based on the delayed on / off command signal. The gate drive circuit includes: a first resistive element disposed between the signal generation unit and the switching unit; a capacitor disposed between the wiring connecting the first resistive element to the switching unit and a reference potential; a second resistive element connected in parallel with the first resistive element; and a diode provided on a path connecting the first resistive element and the second resistive element in parallel.

[0007] In this power conversion device, the gate drive circuit generates a delayed on / off command signal, which is delayed by a predetermined time in response to the on / off command signal output by the signal generation unit. By adjusting this delay time, it becomes possible to suppress unintended operation caused by variations in the characteristics of power semiconductor elements. As a result, the operation of a circuit composed of multiple power semiconductor elements can be stabilized.

[0008] In the power conversion device described above, the gate drive circuit may switch between a first state, which generates a first delayed on / off command signal that delays the on / off command signal by a first delay time determined by the electrical resistance value of either the first or second electrical resistance element and the capacitance value of the capacitor, and a second state, which generates a second delayed on / off command signal that delays the on / off command signal by a second delay time determined by the combined electrical resistance value of the first and second electrical resistance elements connected in parallel and the capacitance value of the capacitor. This operation makes it possible to individually adjust the first delay time when in the first state and the second delay time when in the second state. As a result, the delay time when the on / off command signal switches from low to high and the delay time when the on / off command signal switches from high to low can be set individually.

[0009] In the power conversion device described above, only one diode may be placed on the path connecting the first resistive element and the second resistive element in parallel, such that the diode switches between a first state and a second state in response to a delayed on / off command signal. With this configuration, the operation of a circuit composed of multiple power semiconductor elements can be stabilized with a simple circuit configuration.

[0010] In the power conversion device described above, the input of the diode may be connected to a second resistive element, and the output of the diode may be connected to a first resistive element and a signal generator. Alternatively, the input of the diode may be connected to a signal generator, and the output of the diode may be connected to a first resistive element. Furthermore, the input of the diode may be connected to a second resistive element and a capacitor, and the output of the diode may be connected to a first resistive element. In addition, the input of the diode may be connected to a first resistive element and a capacitor, and the output of the diode may be connected to a second resistive element. With these configurations, a circuit capable of switching between a first state and a second state can be constructed using a single diode.

[0011] In the power conversion device described above, the gate drive circuit further includes a gate driver located in the wiring connecting the signal generation unit to the switching unit, and the gate driver may accept a first input voltage and a second input voltage and generate an amplitude-adjusted delayed on / off command signal having a frequency based on the on / off command signal and an amplitude defined by the first input voltage and the second input voltage. This configuration makes it possible to stabilize the signal supplied to the power semiconductor element.

[0012] In the power conversion device described above, the first resistive element, the second resistive element, the diode, and the capacitor constitute a delay time adjustment circuit, and the gate driver may be placed between the signal generation unit and the delay time adjustment circuit. Alternatively, the gate driver may be placed between the delay time adjustment circuit and the power semiconductor element. These configurations also allow for the stabilization of the signal supplied to the power semiconductor element.

[0013] In the power conversion device described above, a voltage adjustment circuit may be further provided that supplies a first input voltage to the gate driver. The voltage adjustment circuit may include a variable resistance element, and the variable resistance element may be used to adjust the first input voltage supplied to the gate driver. With this configuration, the first input voltage supplied to the gate driver can be adjusted.

[0014] In the above power conversion device, at least one of the first electrical resistance element and the second electrical resistance element may be a variable electrical resistance element whose electrical resistance value can be changed. According to this configuration, at least one of the first delay time and the second delay time can be adjusted to a desired value.

Advantages of the Invention

[0015] According to the power conversion device of the present invention, stabilizing the operation of a circuit constituted by a plurality of power semiconductor elements can be achieved with a simple circuit configuration.

Brief Description of the Drawings

[0016] [Figure 1] FIG. 1 is a schematic circuit diagram of an inverter including a power conversion device according to the first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing the power conversion device according to the first embodiment. [Figure 3] FIG. 3(a) is a circuit diagram showing a power conversion device according to the first modification of the first embodiment. FIG. 3(b) is a circuit diagram showing a power conversion device according to the second modification of the first embodiment. FIG. 3(c) is a circuit diagram showing a power conversion device according to the third modification of the first embodiment. [Figure 4] FIG. 4 is a circuit diagram showing the power conversion device according to the second embodiment. [Figure 5] FIG. 5 is a circuit diagram showing the power conversion device according to the third embodiment. [Figure 6] FIG. 6 is a circuit diagram showing a power conversion device according to a modification of the third embodiment. [Figure 7] FIG. 7 is a circuit diagram showing the power conversion device according to the fourth embodiment. [Figure 8] FIG. 8 is a circuit diagram showing a power conversion device according to a modification of the fourth embodiment.

Modes for Carrying Out the Invention

[0017] Hereinafter, embodiments for implementing the present invention will be described in detail while referring to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant descriptions are omitted.

[0018] <First Embodiment> The power conversion device 1 according to the first embodiment shown in FIG. 1 is used in an inverter. The inverter converts the DC current received from a DC power source into an AC current. For this conversion, the power semiconductor element 41 is used. Each power semiconductor element 41 has a limit on the allowable current value. Therefore, in order to further increase the current that can be output from the inverter, a circuit configuration for obtaining a large current is adopted by connecting the power semiconductor elements 41 in parallel.

[0019] Specifically, the power conversion device 1 includes a signal generation unit 2, a plurality of gate drive circuits 3, and a plurality of switching units 4. One signal generation unit 2, one gate drive circuit 3, and one switching unit 4 constitute one module. A pair of modules constitutes one arm.

[0020] The signal generation unit 2 supplies an on / off command signal to each of the plurality of gate drive circuits 3. The on / off command signal has a pulse waveform in which a high voltage and a low voltage are switched according to a predetermined frequency.

[0021] The gate drive circuit 3 generates a gate drive signal (delayed on / off command signal) to be provided to the switching unit 4 based on the on / off command signal received from the signal generation unit 2. That is, the gate drive circuit 3 receives the on / off command signal from the signal generation unit 2, generates a gate drive signal based on the on / off command signal, and supplies the generated gate drive signal to the switching unit 4. The gate drive circuit 3 includes a delay time adjustment circuit 30 as a basic component.

[0022] The gate drive circuit 3 will now be described in more detail. As shown in Figure 2, the gate drive circuit 3 includes a first variable electrical resistance element 31 (first electrical resistance element), a second variable electrical resistance element 32 (second electrical resistance element), a diode 33, and a capacitor 34. These electrical elements constitute the delay time adjustment circuit 30, which is the filter circuit described above.

[0023] The first variable resistance element 31 is positioned in the path connecting the signal generation unit 2 and the power semiconductor element 41. In this path, the first end of a capacitor 34 is connected between the first variable resistance element 31 and the power semiconductor element 41. The second end of the capacitor 34 is connected to the first reference potential 35. The second variable resistance element 32 is connected in parallel with the first variable resistance element 31. The diode 33 is connected between the signal generation unit 2 and the second variable resistance element 32. More specifically, the input of the diode 33 is connected to the second variable resistance element 32, and the output of the diode 33 is connected to the first variable resistance element 31 and the signal generation unit 2. With this connection configuration, the current supplied from the signal generation unit 2 cannot flow directly into the second variable resistance element 32.

[0024] The gate drive circuit 3 outputs a gate drive signal (delayed on / off command signal) according to the characteristics of the power semiconductor element 41. According to the characteristics of the power semiconductor element 41, the delay time applied to the on / off command signal generated by the signal generation unit 2 is set for each power semiconductor element 41. The delay time is determined by the resistance value of the first variable electrical resistance element 31 and the resistance value of the second variable electrical resistance element 32. Assuming that the characteristics of the power semiconductor elements 41 are different, the resistance value of the first variable electrical resistance element 31 constituting the first gate drive circuit 3 may be different from the resistance value of the first variable electrical resistance element 31 constituting the first gate drive circuit 3 shown in the lower part of Figure 2. Also, the resistance value of the second variable electrical resistance element 32 constituting the first gate drive circuit 3 may be different from the resistance value of the second variable electrical resistance element 32 constituting the first gate drive circuit 3 shown in the lower part of Figure 2.

[0025] The orientation of diode 33 can also be defined by the direction of the current. For example, the direction of the current flowing from the signal generation unit 2 to charge capacitor 34 is called the ON direction. The direction of the current flowing to discharge capacitor 34 is called the OFF direction. In this case, diode 33 shown in Figure 2 can be said to be positioned in the OFF direction before the second variable electrical resistance element 32.

[0026] The switching unit 4 is positioned between the drive voltage source and the inverter output, and is responsible for connecting the current path from the drive voltage source to the inverter and interrupting that path. Through the operation of multiple switching units 4, for example, the DC current received from the drive voltage source can be converted into a three-phase AC current and supplied to the load device (motor).

[0027] The switching unit 4 includes a power semiconductor element 41 and a diode 42. An example of the power semiconductor element 41 is an IGBT. The output of the diode 42 is connected to the collector of the power semiconductor element 41. The input of the diode 42 is connected to the emitter of the power semiconductor element 41. This connection of the diode 42 prevents unintended current flow from the collector side to the emitter side of the power semiconductor element 41.

[0028] The gate of the power semiconductor element 41 is connected to the gate drive circuit 3. When the gate receives a high voltage in the gate drive signal, current flows from the collector to the emitter. When the gate receives a low voltage in the gate drive signal, no current flows from the collector to the emitter.

[0029] Furthermore, the gate drive circuit 3 may include a second reference potential 36 as an additional element. The collector of the power semiconductor element 41 is connected to the second reference potential 36.

[0030] <Operation of the gate drive circuit> Next, the operation of the gate drive circuit 3 will be described. The gate drive circuit 3 switches between a first state in which it generates a first gate drive signal that is delayed by a first delay time determined by the electrical resistance value of either the first variable electrical resistance element 31 or the second variable electrical resistance element 32 and the capacitance value of the capacitor 34, and a second state in which it generates a second gate drive signal that is delayed by a second delay time determined by the combined electrical resistance value of the first variable electrical resistance element 31 and the second variable electrical resistance element 32 connected in parallel and the capacitance value of the capacitor 34. This operation makes it possible to individually adjust the first delay time when in the first state and the second delay time when in the second state. As a result, the delay time when the on / off command signal switches from Low to High and the delay time when the on / off command signal switches from High to Low can be set individually. For example, it is possible to make the delay time when switching from High to Low (off) greater than the delay time when switching from Low to High (on).

[0031] <Effects and Effects> Screening is sometimes performed to reduce variations in multiple parallel power semiconductor elements. This screening is time-consuming and costly. Even after screening, the possibility of drain current imbalance remains. Therefore, it is necessary to ensure a current margin to tolerate the occurrence of drain current imbalance.

[0032] In view of these problems, the power converter 1 includes a signal generation unit 2 that generates an on / off command signal, a gate drive circuit 3 that receives the on / off command signal and generates a delayed on / off command signal by delaying the on / off command signal by a predetermined time, and a switching unit 4 that generates an output current using a power semiconductor element 41 that operates based on the delayed on / off command signal. The gate drive circuit 3 includes a first variable resistance element 31 disposed between the signal generation unit 2 and the switching unit 4, a capacitor 34 disposed between the wiring connecting the first variable resistance element 31 to the switching unit 4 and a first reference potential 35, a second variable resistance element 32 connected in parallel with the first variable resistance element 31, and a diode 33 provided on the path connecting the first variable resistance element 31 and the second variable resistance element 32 in parallel.

[0033] According to this power conversion device 1, the gate drive circuit 3 generates a delayed on / off command signal, which is delayed by a predetermined time in response to the on / off command signal output by the signal generation unit 2. By adjusting this delay time, it becomes possible to suppress unintended operation caused by variations in the characteristics of the power semiconductor element 41. For example, even if the characteristics of the first power semiconductor element 41 and the second power semiconductor element 41 do not match, since a gate drive circuit 3 that generates a delayed on / off command signal corresponding to the switching section 4 including the power semiconductor element 41 is connected to each switching section 4, the operation of the switching section 4 based on the delayed on / off command signal can be synchronized. As a result, the operation of the circuit composed of multiple power semiconductor elements 41 can be stabilized.

[0034] The power converter 1 employs a variable resistance element as the electrical resistance element constituting the delay time adjustment circuit 30. The variable resistance element allows for independent adjustment of the signal delay time relative to the ON time and the signal delay time relative to the OFF time. As a result, the time it takes for the gate signal to reach the gate of the power semiconductor element 41 can be adjusted. This adjustment of the arrival time eliminates current imbalance.

[0035] Only one diode 33 is placed on the path connecting the first variable electrical resistance element 31 and the second variable electrical resistance element 32 in parallel, so that it switches between a first state and a second state in response to an on / off command signal. This configuration reduces the number of components required for the circuit that generates the delay.

[0036] The input of diode 33 is connected to the second variable resistor element 32, and the output of diode 33 is connected to the first variable resistor element 31 and the signal generation unit 2. With this configuration, a circuit capable of switching between a first state and a second state can be constructed using a single diode 33.

[0037] Below, three modifications of the power converter 1 of the first embodiment are presented. In each modification, the position of the diode 33 is different. The power converters 1A, 1B, and 1C of the first to third modifications can also obtain the same effect as the power converter 1 of the first embodiment.

[0038] <First modified example of the first embodiment> In the first modified power converter 1A shown in Figure 3(a), the diode 33A is positioned between the signal generation unit 2 and the first variable electrical resistance element 31 that constitutes the delay time adjustment circuit 30A. In other words, the diode 33A can be said to be positioned in the ON direction before the first variable electrical resistance element 31.

[0039] <Second variation of the first embodiment> In the second modified power converter 1B shown in Figure 3(b), the diode 33B is positioned between the first variable resistance element 31, which constitutes the delay time adjustment circuit 30B, and the power semiconductor element 41. More specifically, the diode 33B is positioned between the first variable resistance element 31 and the first end of the capacitor 34. In other words, the diode 33B can be said to be positioned in the ON direction after the first variable resistance element 31.

[0040] <Third Modification of the First Embodiment> In the third modified power converter 1C shown in Figure 3(c), the diode 33C is positioned between the second variable resistance element 32, which constitutes the delay time adjustment circuit 30C, and the power semiconductor element 41. More specifically, the diode 33C is positioned between the second variable resistance element 32 and the first end of the capacitor 34. In other words, the diode 33C can be said to be positioned in the off direction after the second variable resistance element 32.

[0041] <Second Embodiment> In the first embodiment, the power converter 1 supplied on / off command signals to multiple gate drive circuits 3 from a single signal generation unit 2. As shown in Figure 1, two gate drive circuits 3 were connected to the signal generation unit 2. In other words, the multiple gate drive circuits 3 in the power converter 1 of the first embodiment received a common on / off command signal output from a single signal generation unit 2.

[0042] In contrast, as shown in Figure 4, in the power converter 1D of the second embodiment, one gate drive circuit 3 is connected to one signal generation unit 2. Another gate drive circuit 3D is connected to another signal generation unit 2D.

[0043] With this configuration, the on / off command signal received by one gate drive circuit 3 can be the same as, or different from, the on / off command signal received by another gate drive circuit 3D. Specifically, the frequency of the on / off command signal received by one gate drive circuit 3 can be the same as, or different from, the frequency of the on / off command signal received by the other gate drive circuit 3D. Similarly, the amplitude of the on / off command signal received by a first gate drive circuit 3 can be the same as, or different from, the amplitude of the on / off command signal received by the other gate drive circuit 3D. The amplitude of the on / off command signal is a value that can be defined by the High voltage and Low voltage mentioned above.

[0044] Thus, even with a configuration in which signal generation units 2 and 2D are provided for each gate drive circuit 3 and 3D, it is possible to perform the function of adjusting the delay time of the gate signal supplied to the power semiconductor element 41. Therefore, the power converter 1D of the second embodiment can obtain the same effects as the power converter 1 of the first embodiment.

[0045] <Third Embodiment> The power converter 1E of the first embodiment was composed of a minimum number of circuit elements for delaying the on / off command signal. In addition to the circuit elements for delaying the on / off command signal, the power converter has additional circuit elements for auxiliary functions. The power converter 1E of the third embodiment shown in Figure 5 can perform a current buffer function in addition to the function of delaying the on / off command signal. Therefore, the power converter 1E of the third embodiment has a gate driver 37E as a circuit element for the current buffer function.

[0046] The power converter 1E of the third embodiment is the power converter 1 of the first embodiment with the addition of a gate driver 37E. Therefore, in the following description, the power converter 1E of the third embodiment will be described with a focus on the gate driver 37E, and the circuit configuration common to the power converter 1 of the first embodiment, such as the delay time adjustment circuit 30E, will be omitted from the description.

[0047] The gate driver 37E is positioned between the signal generation unit 2 and the delay time adjustment circuit 30E. More specifically, a connection point P50E is provided on the line connecting the signal generation unit 2 and the first delay time adjustment circuit 30E1, and a line connecting to the second delay time adjustment circuit 30E2 branches off from this connection point P50E. In one gate drive circuit 3, the first gate driver 37E1 is positioned between this connection point P50E and the first delay time adjustment circuit 30E1. In another gate drive circuit 3, the second gate driver 37E2 is positioned on the line extending from connection point P50E to the second delay time adjustment circuit 30E2. In other words, one gate driver 37E is connected to one delay time adjustment circuit 30E.

[0048] The input of the gate driver 37E is connected to the signal generation unit 2. Therefore, the input of the gate driver 37E receives an on / off command signal. A positive voltage source 38 and a negative voltage source 39 are connected to the gate driver 37E. The positive voltage source 38 supplies a gate positive voltage to the gate driver 37E. The gate positive voltage is the gate voltage that turns the power semiconductor element 41 ON. An example of a gate positive voltage is 0V or a positive voltage. The negative voltage source 39 supplies a gate negative voltage to the gate driver 37E. The gate negative voltage is the gate voltage that turns the power semiconductor element 41 OFF. An example of a gate positive voltage is 0V or a negative voltage. The gate driver 37E can supply an on / off command signal defined by the gate positive voltage and the gate negative voltage to the delay time adjustment circuit 30E. Furthermore, with this configuration, first, the gate driver 37E, which receives the on / off command signal output by the signal generation unit 2, generates an on / off command signal defined by the gate positive voltage and the gate negative voltage. The on / off command signals, defined by the gate positive voltage and gate negative voltage, are then supplied to the delay time adjustment circuit 30E, delayed for a predetermined time, and then supplied to the power semiconductor element 41.

[0049] The gate drive circuit 3E further includes a gate driver 37E positioned in the wiring connecting the signal generation unit 2 to the switching unit 4. The gate driver 37E may accept a first input voltage and a second input voltage and generate an amplitude-adjusted delayed on / off command signal having a frequency based on the on / off command signal and an amplitude defined by the first input voltage and the second input voltage. This configuration allows for stabilization of the signal supplied to the power semiconductor element 41.

[0050] The first variable resistor 31, the second variable resistor 32, the diode 33, and the capacitor 34 constitute the delay time adjustment circuit 30E. The gate driver 37 is placed between the signal generation unit 2 and the delay time adjustment circuit 30E. This configuration also allows for the stabilization of the signal supplied to the power semiconductor element 41.

[0051] Since the power converter 1E of the third embodiment also has a delay time adjustment circuit 30E, similar to the power converter 1 of the first embodiment, it can achieve the same effects and advantages as the power converter 1 of the first embodiment.

[0052] <Modified form of the third embodiment> The location where the gate driver 37E is placed is not limited to between the signal generation unit 2 and the delay time adjustment circuit 30E. Figure 6 is a circuit diagram showing a modified power converter 1F of the third embodiment. As shown in Figure 6, in the power converter 1F, which is a modified example of the third embodiment, the gate driver 37F is placed between the delay time adjustment circuit 30F and the power semiconductor element 41. That is, the input of the gate driver 37F is connected to the delay time adjustment circuit 30F. The output of the gate driver 37F is connected to the gate of the power semiconductor element 41. With this configuration, the on / off command signal generated by the signal generation unit 2 is first supplied to the delay time adjustment circuit 30F and delayed for a predetermined time. Then, the delayed on / off command signal, which has been delayed for a predetermined time, is supplied to the gate driver 37F, and the gate driver 37F supplies an amplitude-adjusted delayed on / off command signal, defined by the gate positive voltage and the gate negative voltage, to the gate of the power semiconductor element 41. In other words, in the power converter 1F, which is a modified version of the third embodiment, the order of the delay processing of the on / off command signal and the generation processing of the on / off command signal defined by the gate positive voltage and the gate negative voltage is reversed compared to the power converter 1E, which is the third embodiment.

[0053] <Fourth Embodiment> In addition to the power converter 1E of the third embodiment, a function to further improve the current imbalance of the power semiconductor element 41 may be added as a further additional function. As shown in Figure 7, the power converter 1G of the fourth embodiment further has a voltage adjustment circuit 5G for improving the current imbalance of the power semiconductor element 41.

[0054] The power converter 1G of the fourth embodiment shown in Figure 7 is a modified version of the power converter 1F of the third embodiment with the addition of a voltage adjustment circuit 5G. Therefore, in the following description, the power converter 1G of the fourth embodiment will be described focusing on the voltage adjustment circuit 5G, and the circuit configuration common to the power converter 1F, which is a modified version of the third embodiment, such as the delay time adjustment circuit 30G and the gate driver 37G, will be omitted from the description.

[0055] The gate drive circuit 3G includes a voltage adjustment circuit 5G. In other words, in the power converter 1G of the fourth embodiment, the voltage adjustment circuit 5G is considered a component of the gate drive circuit 3. The voltage adjustment circuit 5G outputs a positive gate voltage that the gate driver 37G accepts. In other words, the voltage adjustment circuit 5G corresponds to the positive voltage source 38 described in the third embodiment.

[0056] The voltage regulation circuit 5G includes a regulator 51, a first fixed electrical resistance element 53, a variable electrical resistance element 54, and a second fixed electrical resistance element 55. The input of the regulator 51 is connected to a positive voltage source 57 and receives the voltage output by the positive voltage source 57. Another input of the regulator 51 is connected to a reference potential 52. A gate positive voltage is output from the output of the regulator 51. In other words, the output of the regulator 51 is connected to the gate driver 37G and supplies the gate positive voltage to the gate driver 37G.

[0057] From the line connecting the output of the regulator 51 and the gate driver 37G, a circuit element extends that connects to the reference potential 52 via a first fixed resistance element 53, a variable resistance element 54, and a second fixed resistance element 55. By adjusting the variable resistance element 54, the gate positive voltage can be adjusted. Furthermore, a line extends from the line connecting the variable resistance element 54 and the second fixed resistance element 55 that connects to the regulator.

[0058] The power converter 1G of the fourth embodiment, having such a configuration, can achieve the same effects as the power converter 1G of the first embodiment through the function of the delay time adjustment circuit 30G. Furthermore, the power converter 1G of the fourth embodiment can generate a gate positive voltage in the voltage adjustment circuit 5G and supply this gate positive voltage to the gate driver 37G. As a result, the imbalance in the current of the power semiconductor element 41 can be improved.

[0059] <Modified form of the fourth embodiment> In the power converter 1H of the fourth embodiment, the voltage adjustment circuit 5H was treated as a component of the gate drive circuit 3. The voltage adjustment circuit 5H may be provided outside the gate drive circuit 3 and not treated as a component of the gate drive circuit 3. For example, as shown in Figure 8, the power converter 1H, which is a modified example of the fourth embodiment, has a configuration in which the voltage adjustment circuit 5H and the signal generation unit 2 are provided on the first substrate 61, and the gate drive circuit 3 is provided on a second substrate 62 separate from the first substrate 61. With such a configuration, the variable electrical resistance element 54 for adjusting the gate positive voltage can be placed in a position that is easy to adjust.

[0060] <Note> This disclosure includes the following components:

[0061] This disclosure includes [1] a signal generating unit that generates an on / off command signal to turn a power semiconductor element on or off, A gate drive circuit that receives the aforementioned on / off command signal and generates a delayed on / off command signal by delaying the aforementioned on / off command signal by a predetermined time, The system includes a switching unit that generates an output current using the power semiconductor element that operates based on the delayed on / off command signal, The gate drive circuit is, A first electrical resistance element is disposed between the signal generation unit and the switching unit, A capacitor is placed between the wiring connecting the first electrical resistance element to the switching section and the reference potential, A second resistive element connected in parallel with the first resistive element, A power conversion device comprising a diode provided on a path connecting the first electrical resistance element and the second electrical resistance element in parallel.

[0062] This disclosure includes [2] "The gate drive circuit is, A first state in which a first delayed on / off command signal is generated, which is the on / off command signal delayed by a first delay time determined by the electrical resistance value of either the first electrical resistance element or the second electrical resistance element and the capacitance value of the capacitor, The power conversion device described in [1] above, wherein the device switches between a second state in which it generates a second delayed on / off command signal, which is the on / off command signal delayed by a second delay time determined by the combined electrical resistance value of the first electrical resistance element and the second electrical resistance element connected in parallel and the capacitance value of the capacitor, and a second state in which it generates a second delayed on / off command signal.

[0063] This disclosure relates to [3] "the power conversion device according to [2] above, wherein the diode is arranged in a path connecting the first resistive element and the second resistive element in parallel, such that the diode switches between the first state and the second state in response to the delayed on / off command signal."

[0064] This disclosure includes [4] "the input of the diode is connected to the second electrical resistance element, The output of the diode is connected to the first electrical resistance element and the signal generating unit, and is a power conversion device as described in any one of the above [1] to [3].

[0065] This disclosure includes [5] "the input of the diode is connected to the signal generating unit, The output of the diode is connected to the first electrical resistance element, and is a power conversion device as described in any one of the above items [1] to [3].

[0066] This disclosure includes [6] "the input of the diode is connected to the second resistive element and the capacitor, The output of the diode is connected to the first electrical resistance element, and is a power conversion device as described in any one of the above items [1] to [3].

[0067] This disclosure includes [7] "the input of the diode is connected to the first electrical resistance element and the capacitor, The output of the diode is connected to the second electrical resistance element, and is a power conversion device as described in any one of the above items [1] to [3].

[0068] This disclosure further includes [8] "the gate drive circuit further comprises a gate driver arranged in the wiring connecting the signal generation unit to the switching unit, The power converter according to any one of the above [1] to [7], wherein the gate driver accepts a first input voltage and a second input voltage and generates an amplitude-adjusted delayed on / off command signal having a frequency based on the on / off command signal and an amplitude defined by the first input voltage and the second input voltage.

[0069] This disclosure includes [9] "The first resistive element, the second resistive element, the diode and the capacitor constitute a delay time adjustment circuit, The gate driver is the power conversion device described in [8] above, which is arranged between the signal generation unit and the delay time adjustment circuit.

[0070] This disclosure includes

[10] "The first resistive element, the second resistive element, the diode and the capacitor constitute a delay time adjustment circuit, The gate driver is the power conversion device described in [8] above, which is positioned between the delay time adjustment circuit and the power semiconductor element.

[0071]

[11] The disclosure further comprises a voltage adjustment circuit that provides the first input voltage to the gate driver, The voltage adjustment circuit includes a variable electrical resistance element, and the variable electrical resistance element adjusts the first input voltage supplied to the gate driver, as described in any one of the above [8] to

[10] .

[0072] This disclosure relates to

[12] "the power conversion device according to any one of [1] to

[11] above, wherein at least one of the first electrical resistance element and the second electrical resistance element is a variable electrical resistance element whose electrical resistance value can be changed." [Explanation of symbols]

[0073] 1,1A,1B,1C,1D,1E,1F,1G,1H Power converter 2.2D Signal Generation Unit 3, 3D, 3G gate drive circuit 4. Switching section 5G, 5H Voltage Regulating Circuit 30E, 30F Delay Time Adjustment Circuit 30E1 First Delay Time Adjustment Circuit 30E2 First Delay Time Adjustment Circuit 31. First variable electrical resistance element (first electrical resistance element) 32. Second variable electrical resistance element (second electrical resistance element) 33,42 diodes 34 Capacitors 37, 37E, 37F, 37G gate drivers 37E1 First Gate Driver 37E2 Second Gate Driver 41 Power semiconductor devices 52 Reference Potential 54 Variable Resistance Element

Claims

1. A signal generation unit that generates on / off command signals to turn power semiconductor elements on or off, A gate drive circuit that receives the aforementioned on / off command signal and generates a delayed on / off command signal by delaying the aforementioned on / off command signal by a predetermined time, The system includes a switching unit that generates an output current using the power semiconductor element that operates based on the delayed on / off command signal, The gate drive circuit is, A first electrical resistance element is disposed between the signal generation unit and the switching unit, A capacitor is placed between the wiring connecting the first electrical resistance element to the switching section and the reference potential, A second resistive element connected in parallel with the first resistive element, A power conversion device comprising: a diode provided on a path connecting the first electrical resistance element and the second electrical resistance element in parallel;

2. The gate drive circuit is, A first state in which a first delayed on / off command signal is generated, which is the on / off command signal delayed by a first delay time determined by the electrical resistance value of either the first electrical resistance element or the second electrical resistance element and the capacitance value of the capacitor, The power conversion device according to claim 1, wherein the device switches between a second state in which it generates a second delayed on / off command signal, which is the on / off command signal delayed by a second delay time determined by the combined electrical resistance value of the first electrical resistance element and the second electrical resistance element connected in parallel and the capacitance value of the capacitor, and a second state in which it generates a second delayed on / off command signal.

3. The power conversion device according to claim 2, wherein the diode is arranged in a single location on a path connecting the first resistive element and the second resistive element in parallel, such that it switches between the first state and the second state in response to the delayed on / off command signal.

4. The input of the diode is connected to the second electrical resistance element. The power conversion device according to any one of claims 1 to 3, wherein the output of the diode is connected to the first electrical resistance element and the signal generating unit.

5. The input of the diode is connected to the signal generating unit. The power conversion device according to any one of claims 1 to 3, wherein the output of the diode is connected to the first electrical resistance element.

6. The input of the diode is connected to the second resistive element and the capacitor. The power conversion device according to any one of claims 1 to 3, wherein the output of the diode is connected to the first electrical resistance element.

7. The input of the diode is connected to the first electrical resistance element and the capacitor, The power conversion device according to any one of claims 1 to 3, wherein the output of the diode is connected to the second electrical resistance element.

8. The gate drive circuit further includes a gate driver arranged in the wiring connecting the signal generation unit to the switching unit, The power converter according to claim 1, wherein the gate driver accepts a first input voltage and a second input voltage and generates an amplitude-adjusted delayed on / off command signal having a frequency based on the on / off command signal and an amplitude defined by the first input voltage and the second input voltage.

9. The first resistive element, the second resistive element, the diode, and the capacitor constitute a delay time adjustment circuit. The power conversion device according to claim 8, wherein the gate driver is disposed between the signal generation unit and the delay time adjustment circuit.

10. The first resistive element, the second resistive element, the diode, and the capacitor constitute a delay time adjustment circuit. The power conversion device according to claim 8, wherein the gate driver is disposed between the delay time adjustment circuit and the power semiconductor element.

11. The gate driver is further provided with a voltage adjustment circuit that supplies the first input voltage, The power conversion device according to claim 8, wherein the voltage adjustment circuit includes a variable electrical resistance element, and the variable electrical resistance element adjusts the first input voltage supplied to the gate driver.

12. The power conversion device according to claim 1, wherein at least one of the first electrical resistance element and the second electrical resistance element is a variable electrical resistance element capable of changing its electrical resistance value.

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