Indication device

Abstract

To provide a display device that can improve yield. [Solution] According to the embodiment, the display device has a display area including a plurality of pixels for displaying an image, a plurality of dummy pixels including a first dummy sub-pixel that does not display an image, a dummy pixel area surrounding the display area, an outer peripheral area surrounding the dummy pixel area, a partition wall disposed in the display area, the dummy pixel area, and the outer peripheral area, and including a conductive lower part and an upper part having an end protruding from the side surface of the lower part, a first laminated film disposed on the first dummy sub-pixel and including a first organic layer, a first sealing layer made of an inorganic insulating material and disposed above the first laminated film, a second laminated film disposed in the outer peripheral area and including a second organic layer, and a second sealing layer made of an inorganic insulating material and disposed above the second laminated film. The partition wall is formed continuously from the dummy pixel area to the outer peripheral area.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for improving the yield are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a display device capable of improving the yield.

Means for Solving the Problems

[0005] Generally, according to the embodiment, the display device has a display area including a plurality of pixels for displaying an image, a plurality of dummy pixels including a first dummy sub-pixel that does not display an image, a dummy pixel area surrounding the display area, an outer peripheral area surrounding the dummy pixel area, a partition wall disposed in the display area, the dummy pixel area, and the outer peripheral area, and including a conductive lower part and an upper part having an end protruding from the side surface of the lower part, a first laminated film disposed on the first dummy sub-pixel and including a first organic layer, a first sealing layer made of an inorganic insulating material and disposed above the first laminated film, a second laminated film disposed in the outer peripheral area and including a second organic layer, and a second sealing layer made of an inorganic insulating material and disposed above the second laminated film. The partition wall is formed continuously from the dummy pixel area to the outer peripheral area.

[0006] In another embodiment, the display device includes a display area having a plurality of pixels for displaying an image, a plurality of dummy pixels having a first dummy sub-pixel and a second dummy sub-pixel that do not display an image, a dummy pixel area surrounding the display area, an outer peripheral area surrounding the dummy pixel area, a partition wall disposed in the display area, the dummy pixel area, and the outer peripheral area, and having a conductive lower part and an upper part having an end protruding from the side surface of the lower part, a first laminated film disposed on the first dummy sub-pixel and including a first organic layer, a first sealing layer formed of an inorganic insulating material and disposed above the first laminated film, a second laminated film disposed on the second dummy sub-pixel and including a second organic layer that includes a light-emitting layer different from the first organic layer, and a second sealing layer formed of an inorganic insulating material and disposed above the second laminated film.

[0007] The partition wall is formed continuously from the dummy pixel region to the outer peripheral region. The outer peripheral region includes a first region surrounding the dummy pixel region and a second region positioned between the first region and the dummy pixel region. The second sealing layer is further positioned in the first region. The first sealing layer positioned in the second region is in contact with the second sealing layer positioned in the first region above the partition wall located between the first and second regions. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example of the configuration of a display device according to the first embodiment. [Figure 2] Figure 2 is a schematic plan view showing an example of the layout of subpixels that make up a single pixel. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view of another example of a display device along line III-III in Figure 2. [Figure 5] Figure 5 is a schematic plan view of the display device according to the first embodiment. [Figure 6] Figure 6 is a schematic plan view, enlarged, of the area enclosed by frame VI in Figure 5. [Figure 7] Figure 7 is a schematic plan view showing the configuration of the sealing layer arranged in the display area, dummy pixel area, and outer perimeter area. [Figure 8] Figure 8 is a schematic plan view, enlarged, of the area enclosed by frame VIII in Figure 7. [Figure 9] Figure 9 is a schematic cross-sectional view of the dummy pixel region and the outer region along the IX-IX line in Figure 7. [Figure 10] Figure 10 is a schematic cross-sectional view of the dummy pixel region and the outer region along line XX in Figure 7. [Figure 11] Figure 11 is a flowchart showing an example of a method for manufacturing a display device. [Figure 12A] Figure 12A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 12B] Figure 12B is a schematic cross-sectional view showing the process following Figure 12A. [Figure 12C] Figure 12C is a schematic cross-sectional view showing the process following Figure 12B. [Figure 12D] Figure 12D is a schematic cross-sectional view showing the process following Figure 12C. [Figure 12E] Figure 12E is a schematic cross-sectional view showing the process following Figure 12D. [Figure 12F] Figure 12F is a schematic cross-sectional view showing the process following Figure 12E. [Figure 12G] Figure 12G is a schematic cross-sectional view showing the process following Figure 12F. [Figure 12H] Figure 12H is a schematic cross-sectional view showing the process following Figure 12G. [Figure 12I] Figure 12I is a schematic cross-sectional view showing the process following Figure 12H. [Figure 12J] Figure 12J is a schematic cross-sectional view showing the process following Figure 12I. [Figure 13] Figure 13 is a schematic plan view showing the display device according to the comparative example. [Figure 14] Figure 14 is a schematic cross-sectional view of the display device taken along line XIV-XIV in Figure 13. [Figure 15] Figure 15 is a schematic plan view of the display device according to the second embodiment. [Figure 16] Figure 16 is a schematic enlarged view of part XVI in Figure 15. [Figure 17] Figure 17 is a schematic cross-sectional view of the dummy pixel region and the outer peripheral region taken along line XVII-XVII in Figure 15. [Figure 18] Figure 18 is a schematic plan view of the display device according to the third embodiment. [Figure 19] Figure 19 is a schematic plan view of the region surrounded by frame XIX in Figure 5, enlarged. [Figure 20]Figure 20 is a schematic plan view, enlarged, of the area enclosed by the frame XX in Figure 5. [Figure 21] Figure 21 is a schematic plan view of the display device according to the fourth embodiment. [Figure 22] Figure 22 is a schematic cross-sectional view of the dummy pixel region and the outer region along the line XXII-XXII in Figure 21. [Figure 23] Figure 23 is a schematic plan view of another example of the display device according to the fourth embodiment. [Figure 24] Figure 24 is a schematic cross-sectional view of the dummy pixel region and the outer region along the line XXIV-XXIV in Figure 23. [Figure 25] Figure 25 is a schematic plan view, enlarged, of the area enclosed by frame XXV in Figure 5. [Figure 26] Figure 26 is a schematic plan view of another example of a display device. [Figure 27] Figure 27 is a schematic plan view, enlarged, of the area enclosed by frame XXVII in Figure 5. [Figure 28] Figure 28 is a schematic plan view of another example of a display device. [Figure 29] Figure 29 is a schematic plan view, enlarged, of the area enclosed by frame XXIX in Figure 5. [Figure 30] Figure 30 is a schematic plan view of another example of a display device. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the drawings. It should be noted that the disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation; however, these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and in each drawing, components that perform the same or similar functions as those described above in previously shown drawings are denoted by the same reference numerals, and redundant detailed explanations may be omitted as appropriate.

[0010] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis will be referred to as the first direction X, the direction along the Y axis as the second direction Y, and the direction along the Z axis as the third direction Z. Viewing the various elements parallel to the third direction Z is called a plan view.

[0011] Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0012] [First Embodiment] Figure 1 shows an example configuration of a display device DSP according to this embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0013] In this embodiment, the shapes of the substrate 10 and the display area DA in plan view are circular. However, the shapes of the substrate 10 and the display area DA in plan view are not limited to circular, and may be other shapes such as rectangles, squares, or ellipses.

[0014] The display area DA comprises a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. Each pixel PX includes a plurality of sub-pixels SP that display different colors. In this embodiment, it is assumed that each pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. Each pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0015] The display device DSP further includes a terminal section T located in the peripheral region SA. A flexible circuit board, for example, that supplies voltage and signals for driving the display device DSP, is connected to the terminal section T.

[0016] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0017] The display area DA is arranged with multiple scan lines G that supply scan signals to the pixel circuit 1 of each sub-pixel SP, multiple signal lines S that supply video signals to the pixel circuit 1 of each sub-pixel SP, and multiple power lines PL. In the example in Figure 1, the scan lines G and power lines PL extend in the first direction X, and the signal lines S extend in the second direction Y.

[0018] The gate electrode of pixel switch 2 is connected to scan line G. One of the source and drain electrodes of pixel switch 2 is connected to signal line S, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to power line PL and capacitor 4, and the other is connected to display element DE.

[0019] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0020] Figure 2 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3 that constitute a single pixel PX. In the example in Figure 2, sub-pixels SP1 and SP3 are aligned in the second direction Y. Also, sub-pixels SP1 and SP3 are aligned with sub-pixel SP2 in the first direction X.

[0021] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP1 and SP3 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP2 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0022] A rib layer 5 (inorganic insulating layer) is arranged in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively.

[0023] In the example in Figure 2, pixel apertures AP1, AP2, and AP3 are all rectangular. The area of ​​pixel aperture AP1 is larger than the area of ​​pixel aperture AP3. Also, the area of ​​pixel aperture AP2 is larger than the area of ​​pixel aperture AP1. Pixel aperture AP2 is a rectangle that is longer in the second direction Y than pixel apertures AP1 and AP3. However, the shapes of pixel apertures AP1, AP2, and AP3 are not limited to this example.

[0024] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3.

[0025] The portion of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlaps with the pixel aperture AP1 constitutes the display element DE1 of the sub-pixel SP1. The portion of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlaps with the pixel aperture AP2 constitutes the display element DE2 of the sub-pixel SP2. The portion of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlaps with the pixel aperture AP3 constitutes the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0026] A conductive partition wall 6 is positioned above the rib layer 5. The partition wall 6 serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition wall 6 overlaps the rib layer 5 overall and has a similar planar shape to the rib layer 5. The partition wall 6 is formed to surround the lower electrodes LE1, LE2, and LE3.

[0027] The partition wall 6 has multiple slits SL. In the example in Figure 2, each slit SL extends in the second direction Y. For example, sub-pixels SP1, SP2, and SP3 that constitute a single pixel PX are located between two adjacent slits SL in the first direction X.

[0028] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, scan line G, signal line S, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.

[0029] The lower electrodes LE1, LE2, and LE3 are positioned on top of the organic insulating layer 12. The rib layer 5 is positioned on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross-section of Figure 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12.

[0030] The partition wall 6 includes a conductive lower section 61 positioned on the rib layer 5 and an upper section 62 positioned on top of the lower section 61. The upper section 62 has a greater width than the lower section 61. As a result, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of partition wall 6 is called an overhang.

[0031] In the example shown in Figure 3, the lower section 61 has a bottom layer 63 positioned on top of the rib layer 5 and an axial layer 64 positioned on top of the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the axial layer 64. In the example shown in Figure 3, both ends of the bottom layer 63 protrude from the sides of the axial layer 64.

[0032] Furthermore, in the example shown in Figure 3, the upper section 62 includes a first top layer 65 and a second top layer 66 positioned on top of the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, it is not limited to this, and the first top layer 65 and the second top layer 66 may have equivalent widths.

[0033] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0034] Display element DE1 includes a cap layer CP1 covering the upper electrode UE1. Display element DE2 includes a cap layer CP2 covering the upper electrode UE2. Display element DE3 includes a cap layer CP3 covering the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.

[0035] In the following explanation, a multilayer containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as multilayer film FL1, a multilayer containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as multilayer film FL2, and a multilayer containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as multilayer film FL3.

[0036] The multilayer films FL1, FL2, and FL3 are positioned above the lower electrodes LE1, LE2, and LE3. The rib layer 5 is positioned below the partition wall 6 and the multilayer films FL1, FL2, and FL3. The sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE11, SE12, and SE13, respectively.

[0037] The sealing layer SE11 continuously covers the display element DE1, which includes the multilayer film FL1, and the surrounding partition wall 6. The sealing layer SE12 continuously covers the display element DE2, which includes the multilayer film FL2, and the surrounding partition wall 6. The sealing layer SE13 continuously covers the display element DE3, which includes the multilayer film FL3, and the surrounding partition wall 6.

[0038] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0039] A cover member, such as a polarizing plate, touch panel, protective film, or cover glass, may be further placed on top of the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer, such as OCA (Optical Clear Adhesive). The electrodes constituting the touch panel may be placed on top of the sealing layer SE2.

[0040] In the example shown in Figure 3, the ends of the sealing layers SE11 and SE12 are in contact (tightly attached) above the partition 6 between sub-pixels SP1 and SP2. Also, the ends of the sealing layers SE11 and SE13 are in contact (tightly attached) on the partition 6 between sub-pixels SP1 and SP3. Furthermore, although not shown, the ends of the sealing layers SE12 and SE13 are in contact (tightly attached) on the partition 6 between sub-pixels SP2 and SP3.

[0041] Focusing on the sealing layer SE12, the sealing layer SE12 has an overlapping portion SE121 located above the partition wall 6. The overlapping portion SE121 is in contact with the end of the sealing layer SE11. The overlapping portion SE121 may include a projection 121a that protrudes upward. Above the partition wall 6 between the sub-pixels SP1 and SP2, the projection 121a is located above the sealing layer SE11.

[0042] Furthermore, the superimposed portion SE121 may further include an extension portion 121b that extends toward the gap G1 formed between the sealing layer SE11 and the upper part 62 of the partition wall 6. This gap is created when the laminated film FL1 disappears during the manufacturing process.

[0043] A laminated film FL2 may be placed between the partition wall 6 and the overlapping portion SE121. However, this laminated film FL2 may disappear during the manufacturing process. In this case, a gap will be created between the sealing layer SE12 and the partition wall 6.

[0044] Similarly, focusing on the sealing layer SE13, the sealing layer SE13 has an overlapping portion SE131 located above the partition wall 6. The overlapping portion SE131 is in contact with the end of the sealing layer SE11. The overlapping portion SE131 may include a projection 131a that protrudes upward. Above the partition wall 6 between the sub-pixels SP1 and SP3, the projection 131a is located above the sealing layer SE11.

[0045] Furthermore, the superimposed portion SE131 may further include an extension portion 131b that extends toward the gap G1 formed between the sealing layer SE11 and the upper part 62 of the partition wall 6. This gap is created when the laminated film FL1 disappears during the manufacturing process.

[0046] A laminated film FL3 is placed between the partition wall 6 and the overlapping portion SE131. If this laminated film FL3 disappears during the manufacturing process, a gap will be created between the sealing layer SE13 and the partition wall 6.

[0047] Figure 4 is a schematic cross-sectional view of another example of a display device DSP along the line III-III in Figure 2. In Figure 4, the shape of the overlapping portions SE121 and SE131 of the sealing layers SE12 and SE13 differs from the example in Figure 3.

[0048] Focusing on the sealing layer SE12, the protrusion 121a of the sealing layer SE12 may overlap with the sealing layer SE11. In the example in Figure 4, the protrusion 121a includes a portion 121c that overlaps with the sealing layer SE11. In the third direction Z, the partition wall 6, the sealing layer SE11, and the protrusion 121a of the sealing layer SE12 are arranged in this order. The portion 121c may or may not be in contact with the sealing layer SE11.

[0049] Similarly, focusing on the sealing layer SE13, the protrusion 131a of the sealing layer SE13 may overlap with the sealing layer SE11. In the example in Figure 4, the protrusion 131a includes a portion 131c that overlaps with the sealing layer SE11. In the third direction Z, the partition wall 6, the sealing layer SE11, and the protrusion 131a of the sealing layer SE13 are arranged in this order. The portion 131c may or may not be in contact with the sealing layer SE11.

[0050] Although not shown in Figures 3 and 4, focusing on the area above the partition wall 6 between sub-pixels SP2 and SP3, the superimposed portion SE131 may include a projection 131a that protrudes upward. The projection 131a is located above the sealing layer SE12. In the example in Figure 4, above the partition wall 6 between sub-pixels SP2 and SP3, the partition wall 6, the sealing layer SE12, and the projection 131a of the sealing layer SE13 are aligned in this order in the third direction Z.

[0051] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0052] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of this reflective layer, respectively. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0053] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0054] The organic layers OR1, OR2, and OR3 are composed of multiple thin films, each containing an emissive layer. The emissive layers contained in the organic layers OR1, OR2, and OR3 are all different from each other. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in the third direction Z in sequence. However, the organic layers OR1, OR2, and OR3 may also have other structures, such as a so-called tandem structure containing multiple emissive layers.

[0055] The cap layers CP1, CP2, and CP3 have a laminated structure in which multiple transparent layers are stacked, for example. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0056] The bottom layer 63 and axial layer 64 of the partition wall 6 are formed of a metallic material. For example, the metallic material for the bottom layer 63 can be molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb). For example, the metallic material for the axial layer 64 can be aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). The axial layer 64 may also be formed of an insulating material.

[0057] The first top layer 65 of the partition wall 6 is formed of, for example, a metallic material. The second top layer 66 of the partition wall 6 is formed of, for example, a conductive oxide. As the metallic material forming the first top layer 65, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide forming the second top layer 66, for example, ITO or IZO can be used. The upper part 62 may consist of three or more layers, or it may be formed of a single layer. Furthermore, the upper part 62 may include a layer formed of an insulating material.

[0058] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the video signal on the signal line S through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0059] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the red wavelength range.

[0060] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0061] Figure 5 is a schematic plan view of a display device (DSP). In this example, the peripheral region SA contains a dummy pixel region DMY surrounding the display region DA, and an outer peripheral region OP. No image is displayed in the dummy pixel region DMY.

[0062] The outer region OP surrounds the dummy pixel region DMY. The partition wall 6 is also located in both the dummy pixel region DMY and the outer region OP. In the outer region OP, the partition wall 6 is covered by a sealing layer, which will be described later.

[0063] A dam structure DS1 is positioned outside the sealing layer located in the outer peripheral region OP. The terminal section T is located outside the dam structure DS1. For example, the dummy pixel region DMY, the outer peripheral region OP, and the dam structure DS1 are all circular and concentric with the display region DA.

[0064] In the outer peripheral region OP, the partition wall 6 is connected to the lower power supply lines via multiple contact parts CN1. These power supply lines are connected to terminal T, from which a common voltage is supplied. The common voltage of the partition wall 6 is supplied to the upper electrodes UE1, UE2, and UE3 that are in contact with the partition wall 6. In the example in Figure 5, the multiple contact parts CN1 are arranged in an arc shape on the terminal T side.

[0065] Figure 6 is a schematic plan view showing an enlarged view of the area enclosed by frame VI in Figure 5. In Figure 6, some parts, such as the sealing layer located in the display area DA, dummy pixel area DMY, and outer peripheral area OP, are omitted. The area enclosed by frame VI corresponds to, for example, a part of the left side of a circular display device DSP.

[0066] In Figure 6, the boundaries between the display area DA and the dummy pixel area DMY, and the boundaries between the dummy pixel area DMY and the outer area OP are defined as boundaries B1 and B2, respectively, and are shown by dashed lines. Figure 6 shows a magnified view of the pixels PX of the display area DA.

[0067] As shown in Figure 6, the dummy pixel region DMY contains multiple dummy pixels DPX. For example, as shown in the enlarged view in Figure 6, dummy pixel DPX includes dummy sub-pixels DP1, DP2, and DP3. Dummy sub-pixels DP1, DP2, and DP3 have a structure similar to the sub-pixels SP1, SP2, and SP3 shown in Figure 2.

[0068] Dummy sub-pixel DP1 comprises a lower electrode LE1, an organic layer OR1, an upper electrode UE1, and a sealing layer SE11. Dummy sub-pixel DP2 comprises a lower electrode LE2, an organic layer OR2, an upper electrode UE2, and a sealing layer SE12. Dummy sub-pixel DP3 comprises a lower electrode LE3, an organic layer OR3, an upper electrode UE3, and a sealing layer SE13.

[0069] However, the dummy sub-pixels DP1, DP2, and DP3 are configured not to emit light. This configuration can be achieved, for example, by cutting a part of the pixel circuit 1 (shown in Figure 1) in each of the dummy sub-pixels DP1, DP2, and DP3.

[0070] Furthermore, the pixel apertures AP1, AP2, and AP3 may be omitted in each of the dummy sub-pixels DP1, DP2, and DP3. As a result, the rib layer 5 is interposed between the organic layers OR1, OR2, OR3 and the lower electrodes LE1, LE2, LE3, and the voltage required to cause them to emit light is no longer applied to the organic layers OR1, OR2, OR3.

[0071] Part of the partition wall 6 is located in the dummy pixel region DMY and surrounds each of the multiple dummy pixels DPX. More specifically, the partition wall 6 surrounds the lower electrodes LE1, LE2, and LE3 of the dummy sub-pixels DP1, DP2, and DP3, respectively.

[0072] For example, the aperture pattern of the partition wall 6 is the same in the display area DA and the dummy pixel area DMY. That is, the partition wall 6 has apertures 71, 72, and 73 in the sub-pixels SP1, SP2, and SP3, respectively, and apertures 81, 82, and 83 in the dummy sub-pixels DP1, DP2, and DP3, respectively. The dummy sub-pixels DP1, DP2, and DP3 are provided in the areas that include apertures 81, 82, and 83, respectively.

[0073] Openings 81, 82, and 83 have the same shape as openings 71, 72, and 73, respectively. Furthermore, the arrangement of openings 81, 82, and 83 is the same as the arrangement of openings 71, 72, and 73.

[0074] The display area DA is provided with the aforementioned slit SL. The dummy pixel area DMY is also provided with slit SL. In contrast, the outer peripheral area OP is not provided with slit SL.

[0075] As described above, partition walls 6 are also located in the outer peripheral region OP. The partition walls 6 located in the outer peripheral region OP are formed in continuity with the partition walls 6 located in the dummy pixel region DMY. The partition walls 6 have a plurality of openings 91 provided in the outer peripheral region OP.

[0076] The aperture pattern of partition wall 6 in the outer peripheral region OP is different from, for example, the aperture pattern of partition wall 6 in the display region DA and the dummy pixel region DMY. Also, the shape of aperture 91 is different from apertures 71, 72, 73 and apertures 81, 82, 83.

[0077] Multiple openings 91 are arranged in a first direction X and a second direction Y. For example, multiple openings 91 arranged in the first direction X may be connected via a slit 92 extending in the first direction X. The shapes of the openings 91 (width in the first direction X, width in the second direction Y) may be different. Note that the shape of the openings 91 is not limited to the illustrated example and may be other shapes.

[0078] In this embodiment, the outlines of the display area DA, the dummy pixel area DMY, and the outer perimeter area OP are all circular. Such outlines can be achieved by making the boundary B1 between the display area DA and the dummy pixel area DMY, and the boundary B2 between the dummy pixel area DMY and the outer perimeter area OP, stepwise, as shown in Figure 6. When boundary B2 is stepwise, as enclosed by frame A, there are locations where the openings 81, 82, and 83 of the dummy pixel area DMY and the opening 91 of the outer perimeter area OP are aligned in the first direction X.

[0079] In this embodiment, slits SL are not provided in the locations where openings 81, 82, 83 and opening 91 are aligned in the first direction X. In other words, the partition wall 6 located in the outer peripheral region OP is connected to and not separated from the partition wall 6 located in the dummy pixel region DMY. Figure 6 shows a part of the left side of the display device DSP, but the right side of the display device DSP is configured similarly.

[0080] Note that the display area DA and the dummy pixel area DMY have lower electrodes LE1, LE2, and LE3, as well as pixel circuits, but these are not located in the outer peripheral area OP.

[0081] Figure 7 is a schematic plan view showing the configuration of sealing layers SE11, SE12, and SE13 arranged in the display area DA, dummy pixel area DMY, and outer peripheral area OP. Figure 8 is a schematic plan view showing an enlarged view of the area enclosed by frame VIII in Figure 7.

[0082] Figure 7 shows the region shown in Figure 6. Figure 8 shows only the sealing layers SE11, SE12, and SE13. In Figures 7 and later, sealing layer SE11 may have a downward-sloping diagonal line pattern, sealing layer SE12 may have a dotted diagonal line pattern, and sealing layer SE13 may have an upward-sloping diagonal line pattern.

[0083] Focusing on the dummy pixel region DMY, the sealing layer SE11 is located on dummy sub-pixel DP1, the sealing layer SE12 is located on dummy sub-pixel DP2, and the sealing layer SE13 is located on dummy sub-pixel DP3. The sealing layer SE12 is located, for example, across multiple dummy sub-pixels DP2 aligned in the second direction Y.

[0084] Here, among the dummy pixels DPX, the dummy pixel DPX located closest to the outer region OP is shown as dummy pixel DPA. Dummy pixel DPA is located on the outermost side of the dummy pixel region DMY.

[0085] As shown in Figure 8, focusing on a single dummy pixel DPA, the sealing layers SE11, SE12, and SE13 are in contact with each other (closely attached) at their edges, just like the sealing layers SE11, SE12, and SE13 arranged in the display area DA.

[0086] Furthermore, focusing on the dummy pixels DPA aligned in the second direction Y, the sealing layers SE11 and SE13 are arranged alternately in the second direction Y, and their ends are in contact with each other. From the perspective of the slit SL, at least one of the sealing layers SE11, SE12, and SE13 may overlap the slit SL.

[0087] Focusing on the outer peripheral region OP, in the example shown in Figure 7, the sealing layer SE13 is positioned above the partition wall 6. In other words, each of the openings 91 in the outer peripheral region OP overlaps with the sealing layer SE13.

[0088] The sealing layer SE13 located in the outer peripheral region OP is connected to the sealing layer SE13 located in the dummy sub-pixel DP3 of the dummy pixel DPA. Here, the sealing layer SE13 located in the dummy sub-pixel DP3 of the dummy pixel DPA is referred to as sealing layer 13A, and the sealing layer SE13 located in the outer peripheral region OP is referred to as sealing layer 13B.

[0089] The sealing layer 13B is formed continuously with the sealing layer 13A above the partition wall 6 (partition wall 6C in Figure 10) located between the dummy pixel region DMY and the outer peripheral region OP. In other words, the sealing layer 13B is connected to the sealing layer 13A. It can also be said that the sealing layer 13B is formed integrally with the sealing layer 13A. Focusing on the boundary B2, the sealing layer SE13 is formed so as to overlap (straddle) the boundary B2.

[0090] Here, the boundary between the sealing layer located in the outer region OP and the sealing layer located in the dummy pixel region DMY is defined as boundary B3 (shown in Figure 8). In Figure 8, boundary B3 is shown as a dashed line.

[0091] Focusing on the left side of the display device DSP, boundary B3 is formed between the sealing layers 13A and 13B and the sealing layers SE11 and SE12 placed on the dummy pixel DPA. In this case, boundary B3 is formed in a zigzag pattern. Even focusing on a single dummy pixel DPA, boundary B3 is formed in a zigzag pattern.

[0092] The sealing layer 13B is in contact with (in close contact with) the sealing layer SE11 located on the dummy sub-pixel DP1 of the dummy pixel DPA. Similarly, the sealing layer 13A is in contact with (in close contact with) the sealing layers SE11 and SE12 located on the dummy sub-pixels DP1 and DP2 of the dummy pixel DPA, respectively. In other words, the sealing layers located on the dummy pixel DPA and the outer peripheral region OP are in close contact with each other, and no gaps are formed between these sealing layers.

[0093] Figure 9 is a schematic cross-sectional view of the dummy pixel region DMY and the outer peripheral region OP along the IX-IX line in Figure 7. In this figure, the substrate 10, circuit layer 11, organic insulating layer 12, sealing layer SE2, and resin layers RS1 and RS2 are omitted.

[0094] In the following description, the partition wall 6 located in the dummy pixel region DMY will be referred to as partition wall 6A, the partition wall 6 located in the outer peripheral region OP will be referred to as partition wall 6B, and the partition wall 6 located at the boundary B2 between the dummy pixel region DMY and the outer peripheral region OP will be referred to as partition wall 6C. Although not shown in the figures, the lower part 61 has a bottom layer 63 and an axial layer 64 (shown in Figure 3), and the upper part 62 has a first top layer 65 and a second top layer 66 (shown in Figure 3).

[0095] The dummy sub-pixel DP1 has a lower electrode LE1 (not shown), a multilayer film FL1, and a sealing layer SE11. The sealing layer SE11 is positioned above the multilayer film FL1. The dummy sub-pixel DP2 has a lower electrode LE2 (not shown), a multilayer film FL2, and a sealing layer SE12. The sealing layer SE12 is positioned above the multilayer film FL2.

[0096] In the example in Figure 9, no pixel apertures are provided in the rib layer 5 for the dummy sub-pixels DP1 and DP2. The sealing layer SE12 continuously covers the laminated film FL2 and a portion of the partition wall 6A. The sealing layer SE11 continuously covers the laminated film FL1 and a portion of the partition walls 6A and 6C. The sealing layer SE13 continuously covers the laminated film FL3, partition wall 6B, and a portion of partition wall 6C.

[0097] Focusing on the sealing layer SE12, the sealing layer SE12 has an overlapping portion SE121 located above the partition wall 6A between the dummy sub-pixels DP1 and DP2. The overlapping portion SE121 is in contact with the edge of the sealing layer SE11. In other words, the overlapping portion SE121 is not separated from the edge of the sealing layer SE11. The overlapping portion SE121 may include a projection 121a that protrudes upward. Above the partition wall 6A, the projection 121a is located above the sealing layer SE11.

[0098] Furthermore, the superimposed portion SE121 may further include an extension portion 121b that extends toward the gap formed between the sealing layer SE11 and the upper part 62 of the partition wall 6A. This gap is created when the laminated film FL1 disappears during the manufacturing process.

[0099] The protruding portion 121a of the sealing layer SE12 may overlap with the sealing layer SE11. Specifically, the protruding portion 121a may include a portion 121c (shown by a dashed line in Figure 9) that overlaps with the sealing layer SE11. In this case, in the third direction Z, the partition wall 6A, the sealing layer SE11, and the protruding portion 121a of the sealing layer SE12 are arranged in this order. The portion 121c may or may not be in contact with the sealing layer SE11.

[0100] Focusing on the sealing layer SE13, the sealing layer SE13 has an overlapping portion SE131 located above the partition wall 6C between the dummy sub-pixel DP1 and the outer peripheral region OP. The overlapping portion SE131 is in contact with the end of the sealing layer SE11. The overlapping portion SE131 may include a projection 131a that protrudes upward. Above the partition wall 6C, the projection 131a is located above the sealing layer SE11.

[0101] Furthermore, the superimposed portion SE131 may further include an extension portion 131b that extends toward the gap formed between the sealing layer SE11 and the upper part 62 of the partition wall 6C. This gap is created when the laminated film FL1 disappears during the manufacturing process. The laminated film FL3 is positioned between the partition wall 6C and the superimposed portion SE131. The laminated film FL3 is surrounded by the partition wall 6C, the superimposed portion SE131, and the extension portion 131b.

[0102] The protruding portion 131a of the sealing layer SE13 may overlap with the sealing layer SE11. Specifically, the protruding portion 131a may include a portion 131c (shown by a dashed line in Figure 9) that overlaps with the sealing layer SE11. In this case, in the third direction Z, the partition wall 6C, the sealing layer SE11, and the protruding portion 131a of the sealing layer SE13 are arranged in this order. The portion 131c may or may not be in contact with the sealing layer SE11.

[0103] Figure 10 is a schematic cross-sectional view of the dummy pixel region DMY and the outer peripheral region OP along the XX line in Figure 7. In this figure, the substrate 10, circuit layer 11, organic insulating layer 12, sealing layer SE2, and resin layers RS1 and RS2 are omitted.

[0104] Although not shown, the lower part 61 has a bottom layer 63 and an axial layer 64 (shown in Figure 3), and the upper part 62 has a first top layer 65 and a second top layer 66 (shown in Figure 3). The dummy sub-pixel DP3 has a lower electrode LE3 (not shown), a multilayer film FL3, and a sealing layer 13A. The sealing layer 13A is located above the multilayer film FL3.

[0105] In the example shown in Figure 10, no pixel aperture is provided in the rib layer 5 of the dummy subpixel DP3. The laminated film FL3 is positioned on the upper part 62 of the partition wall 6B and the partition wall 6C between the dummy subpixel DP3 and the outer peripheral region OP, as well as on the apertures 83 and 91. In the outer peripheral region OP, the sealing layer 13B is positioned above the laminated film FL3.

[0106] In other words, the sealing layer SE13 (sealing layer 13A and sealing layer 13B) continuously covers the laminated film FL3, partition wall 6B, and partition wall 6C. Sealing layer 13A is connected to sealing layer 13B above partition wall 6C.

[0107] Focusing on the sealing layer SE13, the superimposed portion SE131 is located above the partition wall 6A between the dummy sub-pixels DP2 and DP3. The superimposed portion SE131 is in contact with the end of the sealing layer SE12. The superimposed portion SE131 may include a projection 131a that protrudes upward. Above the partition wall 6A, the projection 131a is located above the sealing layer SE12.

[0108] Furthermore, in the example shown in Figure 10, the superimposed portion SE131 may further include an extension portion 131b that extends toward the gap formed between the sealing layer SE12 and the upper part 62 of the partition wall 6A. A laminated film FL3 is positioned between the partition wall 6A and the superimposed portion SE131.

[0109] Furthermore, the protruding portion 131a of the sealing layer SE13 may overlap with the sealing layer SE11. Specifically, the protruding portion 131a may include a portion 131c (shown by a dashed line in Figure 10) that overlaps with the sealing layer SE11. In this case, in the third direction Z, the partition wall 6A, the sealing layer SE12, and the protruding portion 131a of the sealing layer SE13 are arranged in this order. The portion 131c may or may not be in contact with the sealing layer SE12.

[0110] Next, an example of a method for manufacturing a display device DSP will be described. Figure 11 is a flowchart of an example of a method for manufacturing a display device DSP. Figures 12A to 12J are schematic cross-sectional views showing the manufacturing process of a display device DSP. In Figures 12A to 12J, the focus is mainly on the display area DA, and elements below the organic insulating layer 12 are omitted.

[0111] In forming the DSP display device, first a circuit layer 11 and an organic insulating layer 12 are formed on the substrate 10 (step PR1 in Figure 11). Next, as shown in Figure 12A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR2 in Figure 11).

[0112] Next, as shown in Figure 12B, a rib layer 5 is formed covering the lower electrodes LE1, LE2, and LE3 (step PR3 in Figure 11). At this point, the pixel apertures AP1, AP2, and AP3 are not yet provided on the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0113] After the formation of the rib layer 5, a process for forming the partition wall 6 is carried out (process PR4 in Figure 11). In process PR4, as shown in Figure 12C, a first layer L1 for processing into the bottom layer 63, a second layer L2 for processing into the axial layer 64, a third layer L3 for processing into the first top layer 65, and a fourth layer L4 for processing into the second top layer 66 are formed in order. Furthermore, a resist R1 is placed on top of the fourth layer L4. The resist R1 is patterned to the shape of the partition wall 6. The first layer L1, second layer L2, third layer L3, and fourth layer L4 can be formed, for example, by sputtering.

[0114] Subsequently, the first layer L1, second layer L2, third layer L3, and fourth layer L4 are patterned using the resist R1 as a mask. In one example, the first layer L1 is formed of titanium nitride, the second layer L2 is formed of aluminum, the third layer L3 is formed of titanium, and the fourth layer L4 is formed of ITO. In this case, the patterning may include wet etching to remove the portion of the fourth layer L4 exposed from the resist R1, dry etching to remove the portions of the first layer L1, second layer L2, and third layer L3 exposed from the resist R1, and wet etching to reduce the width of the second layer L2.

[0115] After step PR4, a partition wall 6 is formed in the display area DA, as shown in Figure 12D. After the formation of the partition wall 6, the resist R1 is removed (peeled off). In the wet etching process described above, which reduces the width of the second layer L2, the second top layer 66 (fourth layer L4) may also be slightly eroded. If this erosion occurs, the width of the second top layer 66 becomes smaller than the width of the first top layer 65.

[0116] Next, a process is carried out to create pixel apertures AP1, AP2, and AP3 (process PR5 in Figure 11). In this process PR5, a resist R2 is formed to cover the partition wall 6, as shown in Figure 12E. Furthermore, dry etching is performed on the rib layer 5 using the resist R2 as a mask. As a result, pixel apertures AP1, AP2, and AP3 that expose the lower electrodes LE1, LE2, and LE3 are formed on the rib layer 5, as shown in Figure 12F. After the dry etching, the resist R2 is removed (peeled off).

[0117] After step PR5, a process for forming the display element DE1 is carried out (step PR6 in Figure 11). In forming the display element DE1, first, as shown in Figure 12G, a multilayer film FL1 and a sealing layer SE11 are formed. As shown in Figure 3, the multilayer film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel aperture AP1, an upper electrode UE1 that covers the organic layer OR1, and a cap layer CP1 that covers the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed, for example, by vapor deposition. The sealing layer SE11 can be formed, for example, by CVD.

[0118] The laminated film FL1 and the sealing layer SE11 are formed not only in the display area DA but also in the peripheral area SA (dummy pixel area DMY and outer peripheral area OP). The laminated film FL1 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6.

[0119] Next, the multilayer film FL1 and the sealing layer SE11 are patterned. In this patterning process, as shown in Figure 12G, a resist R3 is placed on top of the sealing layer SE11. The resist R3 covers the subpixel SP1 and a portion of the surrounding partition wall 6.

[0120] Subsequently, an etching process is performed using resist R3 as a mask. As a result, as shown in Figure 12H, the portions of the multilayer film FL1 and the encapsulation layer SE11 that are exposed from resist R3 are removed.

[0121] In other words, of the multilayer film FL1 and the sealing layer SE11, the portion that overlaps with the lower electrode LE1 is retained, and the other portions are removed. As a result, the display element DE1 is formed on the sub-pixel SP1.

[0122] Furthermore, focusing on the dummy pixel region DMY, the multilayer film FL1 and sealing layer SE11 located on the dummy sub-pixel DP1 remain. In the outer peripheral region OP, the multilayer film FL1 and sealing layer SE11 are removed by this etching process.

[0123] The etching process includes wet etching and dry etching performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching steps, the resist R3 is removed (exfoliated).

[0124] Furthermore, during wet etching of the multilayer film FL1, the portion of the multilayer film FL1 located above the partition wall 6 and below the sealing layer SE11 is also removed. This creates a gap between the sealing layer SE11 above the partition wall 6 and the partition wall 6. Since the multilayer film FL1 constituting the display element DE1 is completely surrounded by the sealing layer SE11 and the partition wall 6, it is not eroded by the wet etching described above.

[0125] Prior to the wet etching described above, a laminated film FL1 is also formed in the gap between the partition wall 6 and the sealing layer SE11. This laminated film FL1 in the gap is removed during the wet etching process by the etching solution penetrating from near the edge of the sealing layer SE11 downwards.

[0126] After step PR6, a process for forming the display element DE2 is carried out (step PR7 in Figure 11). The display element DE2 can be formed using the same procedure as the display element DE1. That is, in forming the display element DE2, the multilayer film FL2 and the sealing layer SE12 are formed over the entire display area DA and peripheral area SA (dummy pixel area DMY and outer peripheral area OP). As shown in Figure 3, the multilayer film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel aperture AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.

[0127] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed, for example, by vapor deposition. The sealing layer SE12 can be formed, for example, by CVD. The multilayer film FL2 is divided into multiple parts by overhanging partitions 6. The sealing layer SE12 continuously covers each divided part of the multilayer film FL2 and the partitions 6. By patterning the multilayer film FL2 and the sealing layer SE12, a display element DE2 is formed on the sub-pixel SP2, as shown in Figure 12I.

[0128] Above the partition wall 6 between sub-pixels SP1 and SP2, the ends of the sealing layers SE11 and SE12 are in contact. If the sealing layer SE12 is formed to be in contact with the sealing layer SE11, a protrusion 121a may be formed on the superimposed portion SE121 of the sealing layer SE12, which is formed in a later step than the sealing layer SE11. Furthermore, an extension 121b may be formed on the sealing layer SE12, extending toward the gap G1 formed between the sealing layer SE11 and the upper part 62 of the partition wall 6.

[0129] Furthermore, a laminated film FL2 is also formed in the gap between the partition wall 6 and the sealing layer SE12. This laminated film FL2 in the gap is removed during wet etching by the etching solution penetrating from near the edge of the sealing layer SE12 downwards.

[0130] Furthermore, focusing on the dummy pixel region DMY, the stacked film FL2 and sealing layer SE12 located in the dummy sub-pixel DP2 remain. If the sealing layer SE12 is formed in contact with the sealing layer SE11, a protrusion 121a may be formed on the superimposed portion SE121 of the sealing layer SE12, which is formed in a later process than the sealing layer SE11.

[0131] Furthermore, the sealing layer SE12 may have an extension portion 121b that extends toward the gap formed between the sealing layer SE11 and the upper part 62 of the partition wall 6. In the outer peripheral region OP, the laminated film FL2 and the sealing layer SE12 are removed by the etching process.

[0132] After step PR7, a process for forming the display element DE3 is carried out (step PR8 in Figure 11). The display element DE3 can be formed using the same procedure as the display elements DE1 and DE2.

[0133] In other words, in the formation of the display element DE3, the multilayer film FL3 and the sealing layer SE13 are formed over the entire display area DA and peripheral area SA (dummy pixel area DMY and outer peripheral area OP). As shown in Figure 3, the multilayer film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel aperture AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3.

[0134] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed, for example, by vapor deposition. The sealing layer SE13 can be formed, for example, by CVD. The multilayer film FL3 is divided into multiple parts by overhanging partitions 6. The sealing layer SE13 continuously covers each divided part of the multilayer film FL3 and the partitions 6. By patterning the multilayer film FL3 and the sealing layer SE13, a display element DE3 is formed on the sub-pixel SP3, as shown in Figure 12J.

[0135] Above the partition wall 6 between the sub-pixels SP1 and SP3, the ends of the sealing layers SE11 and SE13 are in contact. If the sealing layer SE13 is formed to be in contact with the sealing layer SE11, a protrusion 131a may be formed on the superimposed portion SE131 of the sealing layer SE13, which is formed in a later step than the sealing layer SE11. Furthermore, an extension 131b may be formed on the sealing layer SE13, extending toward the gap G1 formed between the sealing layer SE11 and the upper part 62 of the partition wall 6.

[0136] As shown in Figure 12J, a laminated film FL3 is formed in the gap between the partition wall 6 and the sealing layer SE13. Because the edges of the sealing layer SE11 and the sealing layer SE13 are in contact with each other, the penetration of the etching solution from near the edge of the sealing layer SE13 downwards is suppressed during wet etching. As a result, the laminated film FL3 remains in the gap.

[0137] Furthermore, the laminated film FL3 is surrounded not only by the partition wall 6 and the overlapping portion SE131, but also by the extension portion 131b. This further suppresses the penetration of etching solution from above into the gap.

[0138] Furthermore, if the sealing layer SE13 is formed above the partition wall 6 between the sub-pixels SP2 and SP3 so as to be in contact with the sealing layer SE12, the sealing layer SE13 formed in a later step than the sealing layer SE12 may have a protruding portion 131a on the overlapping portion SE131 and an extended portion 131b extending toward the gap formed between the sealing layer SE11 and the upper part 62 of the partition wall 6.

[0139] Furthermore, focusing on the dummy pixel region DMY and the outer peripheral region OP, the dummy sub-pixel DP3 and the stacked film FL3 and sealing layer SE13, which are placed in the outer peripheral region OP, remain. Through steps PR6 to PR8 in Figure 11, the sealing layers SE11, SE12, and SE13 shown in Figure 7 are formed in the dummy pixel region DMY and the outer peripheral region OP.

[0140] In the dummy pixel region DMY and the outer peripheral region OP, if the sealing layer SE13 is formed in contact with the sealing layers SE11 and SE12, as shown in Figures 9 and 10, the sealing layer SE13, which is formed in a later step than the sealing layers SE11 and SE12, may have protruding portions 131a and extended portions 131b formed on the superimposed portion SE131.

[0141] Furthermore, in the examples shown in Figures 12I and 12J, the portions 121c of the sealing layer SE12 and 131c of the sealing layer SE13 that overlap with the sealing layer SE11 shown in Figure 4 have been removed, but the patterning may be done so that portions 121c and 131c remain. Also, in the sealing layers SE12 and SE13 placed in the dummy pixel region DMY and the outer peripheral region OP, the patterning may be done so that portions 121c and 131c remain, as shown by the dashed lines in Figures 9 and 10.

[0142] After step PR8, resin layer RS1, encapsulation layer SE2, and resin layer RS2 are formed in sequence (step PR9 in Figure 11). For the formation of resin layers RS1 and RS2, for example, an inkjet method can be used. For the formation of encapsulation layer SE2, for example, CVD can be used.

[0143] In this embodiment, it is assumed that the display elements DE1, DE2, and DE3 are formed in this order. In this case, display element DE1 corresponds to the first color display element, display element DE2 corresponds to the second color display element, and display element DE3 corresponds to the third color display element. Note that the display elements DE1, DE2, and DE3 may be formed in any other order.

[0144] Figure 13 is a schematic plan view showing a display device according to a comparative example of this embodiment. Figure 14 is a schematic cross-sectional view of the display device along the line XIV-XIV in Figure 13.

[0145] In the comparative example's display device DSP, as shown in Figure 13, a slit SL is further provided between the dummy pixel region DMY and the outer peripheral region OP. In other words, the partition wall 6 located in the outer peripheral region OP is separated from the partition wall 6 located in the dummy pixel region DMY.

[0146] Focusing on the sealing layers 13A and 13B, as shown in Figure 13, sealing layer 13B is separated from sealing layer 13A. That is, the edge of sealing layer 13B is not in contact with the edge of sealing layer 13A. Although not shown, sealing layer 13B is also not in contact with sealing layer SE11, which is placed on the dummy sub-pixel DP1 of the dummy pixel DPA.

[0147] As shown in Figure 14, the gap formed between the end of the sealing layer SE13 and the upper part 62 of the partition wall 6A opens toward the slit SL. Similarly, the gap formed between the sealing layer SE13 and the upper part 62 of the partition wall 6B opens toward the slit SL.

[0148] In such cases, as indicated by the arrows in step PR8 of Figure 11, the etching solution penetrates the gap from the slit SL and above, causing the laminated film FL3 located in the gap to disappear. However, the degree to which the laminated film FL3 disappears may vary depending on the position of the boundary B2. As shown in the example in Figure 14, the laminated film FL3 may remain above the partition wall 6 located in the outer peripheral region OP. In Figure 14, the remaining laminated film FL3 is shown as the remaining portion P1.

[0149] Thus, variations in the degree of disappearance of the laminated film FL3 above the partition wall 6 can cause a decrease in the appearance of the outer peripheral region OP. For example, the remaining portion P1 can cause a rainbow-like pattern (discoloration) near the boundary B2, reducing the appearance of the outer peripheral region OP.

[0150] When such patterns occur, the alignment marks formed in the outer peripheral region OP become difficult to see when placing the cover glass above the resin layer RS2 in the processes from PR9 onward in Figure 11. Such defects can reduce the yield of the display device DSP.

[0151] In the DSP display device according to this embodiment, the partition wall 6 located in the outer peripheral region OP is formed continuously with the partition wall 6 located in the dummy pixel region DMY. In other words, there is no slit SL between the dummy pixel region DMY and the outer peripheral region OP. This prevents etching solution from entering through the slit SL.

[0152] Furthermore, at boundary B3 (shown in Figure 8), the edges of the sealing layer located in the dummy pixel region DMY and the sealing layer located in the outer peripheral region OP are in contact above the partition wall 6. By having the edges of the sealing layers in contact above the partition wall 6, the intrusion of etching solution from above can be suppressed.

[0153] As described above, by providing partition wall 6 and ensuring that the ends of the sealing layers are in contact above partition wall 6, the intrusion of etching solution that would erase the laminated film FL3 located above partition wall 6C is suppressed, and the laminated film FL3 can be left above partition wall 6C.

[0154] In other words, the degree to which the laminated film FL3 disappears above the partition wall 6 can be suppressed depending on the position of boundary B2. For example, by leaving the laminated film FL3 entirely above the partition wall 6C, the occurrence of rainbow-like patterns becomes less likely, improving the appearance of the outer peripheral region OP.

[0155] This eliminates problems such as the alignment marks becoming difficult to see. As a result, the yield of the display device DSP can be improved in this embodiment.

[0156] Furthermore, in this embodiment, the sealing layer SE13 has an extension portion 131b. Specifically, when the sealing layer SE13 is formed in contact with the sealing layers SE11 and SE12, the extension portion 131b can be formed continuously along the boundary B3 of the sealing layer SE13.

[0157] As shown in Figures 9 and 10, the laminated film FL3 positioned above the partition wall 6C is also surrounded by the extension portion 131b. In other words, the extension portion 131b functions as a wall that suppresses the penetration of etching solution into the laminated film FL3. Because the extension portion 131b makes it more difficult for the etching solution to reach the laminated film FL3 from above, the unwanted disappearance of the laminated film FL3 can be further suppressed. As a result, the appearance of the outer peripheral region OP in the display device DSP can be improved.

[0158] In this embodiment, the organic layer OR3 is an example of the first organic layer and the second organic layer, the multilayer film FL3 is an example of the first multilayer film and the second multilayer film, the organic layer OR1 is an example of the third organic layer, the multilayer film FL1 is an example of the third multilayer film, the dummy sub-pixel DP3 of the dummy pixel DPA is an example of the first dummy sub-pixel, the dummy sub-pixel DP1 of the dummy pixel DPA is an example of the second dummy sub-pixel, the sealing layer 13A is an example of the first sealing layer, the sealing layer 13B is an example of the second sealing layer, and the sealing layer SE11 is an example of the third sealing layer. The organic layer OR3 of the multilayer film FL3 located in the outer peripheral region OP includes the same light-emitting layer as the organic layer OR3 of the multilayer film FL3 located in the dummy sub-pixel DP3.

[0159] Next, other embodiments will be described. In the other embodiments described below, components similar to those in the first embodiment described above will be given the same reference numerals as in the first embodiment, and their detailed descriptions may be omitted or simplified.

[0160] [Second Embodiment] Figure 15 is a schematic plan view of the display device DSP according to this embodiment. Figure 16 is a schematic enlarged view of section XVI in Figure 15. In Figure 16, the focus is mainly on the sealing layers SE11, SE12, and SE13, and other elements are omitted. In this embodiment, the configuration of the dummy pixel area DMY differs from that of the first embodiment.

[0161] As shown in Figures 15 and 16, the sealing layer 13A is arranged across the dummy subpixels DP1 and DP3 of the dummy pixel DPA. Focusing on multiple dummy pixel DPAs, the sealing layer 13A is arranged across the dummy subpixels DP1 and DP3 of multiple dummy pixel DPAs aligned in the second direction Y. That is, the sealing layer 13A is arranged across the dummy subpixels DP1 and DP3 of at least two adjacent dummy pixel DPAs.

[0162] The sealing layer 13B is formed continuously with the sealing layer 13A above the partition wall 6 (partition wall 6C in Figure 17) located between the dummy pixel region DMY and the outer peripheral region OP. In other words, the sealing layer 13B is connected to the sealing layer 13A. Focusing on boundary B2, the sealing layer SE13 is formed so as to overlap (span) boundary B2.

[0163] Focusing on the left side of the display device DSP, boundary B3 is formed between the sealing layer 13A and the sealing layer SE12 placed on the dummy pixel DPA. In this case, boundary B3 is formed in a straight line.

[0164] Furthermore, the sealing layer 13A is in contact with the sealing layer SE12 located on the dummy sub-pixel DP2 of the dummy pixel DPA. In other words, the sealing layers located on the dummy pixel DPA and the outer peripheral region OP are in close contact with each other, and no gaps are formed between the sealing layers.

[0165] Figure 17 is a schematic cross-sectional view of the dummy pixel region DMY and the outer region OP along the line XVII-XVII in Figure 15. In this figure, the substrate 10, circuit layer 11, organic insulating layer 12, sealing layer SE2, and resin layers RS1 and RS2 are omitted.

[0166] In this embodiment, the dummy sub-pixel DP1 has a laminated film FL3 and a sealing layer 13A. The sealing layer SE13 is positioned above the laminated film FL3. Although not shown, the dummy sub-pixel DP3 also has a laminated film FL3 and a sealing layer 13A.

[0167] The laminated film FL3 is positioned on the upper part 62 of partition wall 6C, which is located between partition wall 6B and the dummy sub-pixels DP1, DP3 and the outer peripheral region OP, as well as on the openings 81, 83, and 91. The sealing layer SE13 (sealing layer 13A and sealing layer 13B) continuously covers these laminated film FL3, as well as partition walls 6B and 6C. In other words, sealing layer 13A is connected to sealing layer 13B above partition wall 6C.

[0168] The ends of the sealing layers SE12 and SE13 are in contact with each other on the partition wall 6A between the dummy sub-pixels DP1 and DP2. The sealing layer SE13 has an overlapping portion SE131 located above the partition wall 6A. The overlapping portion SE131 is in contact with the end of the sealing layer SE12. The overlapping portion SE131 may include a projection 131a that protrudes upward. Above the partition wall 6A, the projection 131a is located above the sealing layer SE12.

[0169] Furthermore, the superimposed portion SE131 may further include an extension portion 131b that extends toward the gap formed between the sealing layer SE12 and the upper part 62 of the partition wall 6A. For example, the extension portion 131b is formed along the second direction Y. A laminated film FL3 is disposed between the partition wall 6A and the superimposed portion SE131.

[0170] Furthermore, the protruding portion 131a may include a portion 131c (shown by a dashed line in Figure 17) that overlaps with the sealing layer SE12. In this case, in the third direction Z, the partition wall 6A, the sealing layer SE12, and the protruding portion 131a of the sealing layer SE13 are arranged in this order. Note that the above partition wall 6A between the dummy sub-pixels DP2 and DP3 is configured in the same way as in Figure 17.

[0171] In this embodiment as well, the same effects as in the first embodiment can be obtained. In this embodiment, the extension portion 131b (shown in Figure 17) can be formed linearly along the second direction Y. By forming the extension portion 131b linearly, it becomes easier to suppress the penetration of etching solution from above compared to the first embodiment.

[0172] Furthermore, in step PR8 of Figure 11, when applying the resist for processing the multilayer film FL3 and the encapsulation layer SE13, air bubbles may form at the bent portion of boundary B3. If the process for forming the display element DE3 is carried out with air bubbles present in this location, the bubbles may burst during the reduced-pressure drying of the resist for patterning the multilayer film FL3 and the encapsulation layer SE13, potentially exposing areas that should be covered by the resist.

[0173] As in this embodiment, by forming the boundary B3 in a straight line, the number of bent sections of boundary B3 can be reduced compared to the first embodiment. This suppresses the generation of air bubbles when applying the resist. With this embodiment, the yield of the display device DSP can be further improved.

[0174] In this embodiment, the organic layer OR3 is an example of the first organic layer and the second organic layer, the multilayer film FL3 is an example of the first multilayer film and the second multilayer film, the dummy sub-pixel DP3 of the dummy pixel DPA is an example of the first dummy sub-pixel, the dummy sub-pixel DP1 of the dummy pixel DPA is an example of the second dummy sub-pixel, the sealing layer 13A is an example of the first sealing layer, and the sealing layer 13B is an example of the second sealing layer.

[0175] [Third Embodiment] Figure 18 is a schematic plan view of the display device DSP according to this embodiment. In Figure 18, we mainly focus on the sealing layers SE11, SE12, and SE13, and other elements are omitted. In this embodiment, the configuration of the dummy sub-pixels DP1 and DP3 of the dummy pixel DPA differs from that of the second embodiment.

[0176] In this embodiment, the dummy sub-pixels DP1 and DP3 are provided with a laminated film FL1 and a sealing layer SE11. In other words, the sealing layer SE11 is provided across the dummy sub-pixels DP1 and DP3. The sealing layer SE11 is provided above the laminated film FL1. Here, the sealing layer SE11 provided on the dummy pixel DPA is referred to as sealing layer 11A.

[0177] In the example shown in Figure 18, the sealing layer 11A is arranged across the dummy subpixels DP1 and DP3 of multiple dummy pixels DPA aligned in the second direction Y. That is, the sealing layer 11A is arranged across the dummy subpixels DP1 and DP3 of at least two adjacent dummy pixels DPA.

[0178] Focusing on the left side of the display device DSP, boundary B3 is formed between the sealing layer 13B and the sealing layer 11A placed on the dummy pixel DPA. In the example in Figure 18, boundary B3 overlaps with boundary B2. The sealing layer 13B is in contact with the sealing layer 11A placed on the dummy sub-pixels DP1 and DP3 of the dummy pixel DPA.

[0179] In this embodiment, the cross-section including the boundary B2 between the dummy pixel region DMY and the outer peripheral region OP is configured similarly to, for example, Figure 9 in the first embodiment. Specifically, the sealing layer SE11 (11A) is in contact with the sealing layer 13B above the partition wall 6C. Furthermore, the sealing layer SE11 is in contact with the sealing layer SE12 located on the dummy sub-pixel DP2 above the partition wall 6A.

[0180] In other words, the sealing layer SE11 is not separated from the other sealing layers SE12,13B that are aligned in the first direction X. In this embodiment, the boundary B3 is formed in a straight line. In this case, the extension 131b of the sealing layer 13B is formed in a straight line along the second direction Y.

[0181] In this embodiment as well, the same effects as those of the embodiments described above can be obtained.

[0182] Here, we will describe an example of applying the configuration of this embodiment to other locations on the display device DSP.

[0183] Figure 19 is a schematic plan view, enlarged, of the area enclosed by frame XIX in Figure 5. The area enclosed by frame XIX corresponds to, for example, a part of the upper side of a circular display device DSP.

[0184] As shown in Figure 19, sealing layers 11A are placed on the dummy sub-pixels DP1 and DP3 of the dummy pixel DPA. Focusing on the outer peripheral region OP, sealing layer 11A is in contact with sealing layer 13B. Furthermore, sealing layer 13B is also in contact with sealing layer SE12 placed on the dummy pixel DPA. In the region shown in Figure 19, sealing layer 13B placed on the outer peripheral region OP is not separated from sealing layers SE11 and SE12 placed on the dummy pixel region DMY.

[0185] As shown in Figure 19, the partition wall 6 may have connecting parts CT that connect the partition walls 6 separated by the slit SL. The connecting parts CT are arranged at predetermined intervals in the second direction Y. Note that the arrangement of the connecting parts CT is not limited to the example in Figure 19.

[0186] Figure 20 is a schematic plan view, enlarged, of the area enclosed by frame XX in Figure 5. The area enclosed by frame XX corresponds, for example, to a part of the right side of a circular display device (DSP).

[0187] In Figure 20, we focus on the dummy pixel DPA located in the bent region (bending point) of the stepped boundary B2. The sealing layer 11A is placed on these dummy sub-pixels DP1 and DP3.

[0188] This sealing layer 11A is in contact with sealing layer 13B. Furthermore, sealing layer 13B is also in contact with sealing layer SE12 located on the dummy pixel DPA. In the region shown in Figure 20, sealing layer 13B located in the outer peripheral region OP is not separated from sealing layers 11A and SE12 aligned in the second direction Y, and sealing layer SE12 aligned in the first direction X.

[0189] In the examples shown in Figures 19 and 20, the sealing layers SE11 and SE12 placed on the dummy pixel DPA and the sealing layer SE13 placed on the outer peripheral region OP are in contact above the partition wall 6. By these edges being in contact, it is possible to suppress the etching solution from penetrating into the outer peripheral region OP.

[0190] Furthermore, a slit SL is formed on the side of the dummy pixel DPA. If the edge of the sealing layer placed on the dummy sub-pixel DP3 of the dummy pixel DPA overlaps with the slit SL, there is a risk that the etching solution may penetrate from the slit SL to the dummy sub-pixel DP3.

[0191] As shown in the examples in Figures 19 and 20, by placing a different sealing layer on the dummy sub-pixel DP3 than the sealing layer SE13 placed on the outer peripheral region OP, it is possible to suppress the intrusion of etching solution from the slit SL into the outer peripheral region OP via the dummy sub-pixel DP3. As a result, the unwanted disappearance of the laminated film FL3 placed on the partition wall 6C can be suppressed, and the appearance is less likely to deteriorate.

[0192] In this embodiment, organic layer OR1 is an example of a first organic layer, organic layer OR3 is an example of a second organic layer, multilayer film FL1 is an example of a first multilayer film, multilayer film FL3 is an example of a second multilayer film, dummy sub-pixel DP1 of dummy pixel DPA is an example of a first dummy sub-pixel, dummy sub-pixel DP3 of dummy pixel DPA is an example of a second dummy sub-pixel, sealing layer SE11 is an example of a first sealing layer, and sealing layer SE13 is an example of a second sealing layer.

[0193] The configurations in the first to third embodiments described above are applied to at least one of the multiple dummy pixel DPAs in the dummy pixel region DMY. For example, they may be applied to some of the multiple dummy pixel DPAs in the dummy pixel region DMY, or to all of the multiple dummy pixel DPAs.

[0194] Furthermore, one of the configurations in the first to third embodiments described above may be applied to one display device, or two or more different configurations may be applied to one display device depending on the position of the dummy pixel region DMY. Also, the CT of the partition wall 6 shown in Figure 19 is applicable to the other embodiments described above.

[0195] [Fourth Embodiment] Figure 21 is a schematic plan view of the display device DSP according to this embodiment. In Figure 21, we mainly focus on the sealing layers SE11, SE12, and SE13, and other elements are omitted.

[0196] As shown in Figure 21, the outer region OP includes region A1 and region A2. Here, the boundary between region A1 and region A2 is defined as boundary B4. Region A1 surrounds the dummy pixel region DMY, and region A2 is formed between the dummy pixel region DMY and region A1.

[0197] For example, region A2 surrounds the dummy pixel region DMY, and region A1 surrounds region A2. In other words, region A1 surrounds the dummy pixel region DMY from the outside, rather than region A2. The sealing layer placed in region A2 is different from the sealing layer placed in region A1.

[0198] A sealing layer SE13 is placed in region A1, and a sealing layer SE12 is placed in region A2. In other words, multiple sealing layers (sealing layers SE12, SE13) are placed in the outer peripheral region OP. Hereafter, the sealing layer SE12 placed in region A2 will be referred to as sealing layer 12B.

[0199] The sealing layer located in region A2 is not separated from the sealing layer located in dummy pixel region DMY and the sealing layer located in outer region OP. Focusing on boundary B2, the sealing layer 12B is in contact with the sealing layer SE11 located in dummy sub-pixel DP1 and with the sealing layer SE13 located in dummy sub-pixel DP3, above the partition wall 6 located between dummy pixel region DMY and outer region OP.

[0200] Focusing on boundary B4, the sealing layer 12B is in contact with the sealing layer 13B located in region A1, above the partition wall 6 situated between region A1 and region A2. In other words, the sealing layer 12B is not separated from the other sealing layers SE11 and SE13 aligned in the first direction X.

[0201] Figure 22 is a schematic cross-sectional view of the dummy pixel region DMY and the outer peripheral region OP along the line XXII-XXII in Figure 21. In this figure, the substrate 10, circuit layer 11, organic insulating layer 12, sealing layer SE2, and resin layers RS1 and RS2 are omitted.

[0202] The ends of the sealing layers SE11 and SE12B are in contact with each other on the partition wall 6C. The sealing layer SE12 has an overlapping portion SE121 located above the partition wall 6C. The overlapping portion SE121 is in contact with the end of the sealing layer SE11. Similarly, the overlapping portion SE121 is also in contact with the end of the sealing layer SE13 located on the dummy sub-pixel DP3.

[0203] The superimposed portion SE121 may include a projection 121a that protrudes upward. Above the partition wall 6C, the projection 121a is located above the sealing layer SE11. The superimposed portion SE121 may further include an extension 121b that extends toward the gap formed between the sealing layer SE11 and the upper part 62 of the partition wall 6C.

[0204] Furthermore, the protruding portion 121a of the sealing layer SE12 may overlap with the sealing layer SE11. Specifically, the protruding portion 121a may include a portion 121c (shown by a dashed line in Figure 22) that overlaps with the sealing layer SE11. In this case, in the third direction Z, the partition wall 6C, the sealing layer SE11, and the protruding portion 121a of the sealing layer SE12 are arranged in this order.

[0205] The sealing layer SE13 has an overlapping portion SE131 located above the partition wall 6B situated between region A1 and region A2. The overlapping portion SE131 is in contact with the end of the sealing layer SE12 (sealing layer 12B) above the partition wall 6B. The overlapping portion SE131 may include a projection 131a that protrudes upward. Above the partition wall 6B, the projection 131a is located above the sealing layer SE12.

[0206] Furthermore, the superimposed portion SE131 may further include an extension portion 131b that extends toward the gap formed between the sealing layer SE12 and the upper part 62 of the partition wall 6B. A laminated film FL3 is positioned between the partition wall 6B and the superimposed portion SE131. The laminated film FL3 is surrounded by the partition wall 6B, the superimposed portion SE131, and the extension portion 131b.

[0207] Furthermore, the protruding portion 131a of the sealing layer SE13 may overlap with the sealing layer SE12. Specifically, the protruding portion 131a may include a portion 131c (shown by a dashed line in Figure 22) that overlaps with the sealing layer SE12. In this case, in the third direction Z, the partition wall 6B, the sealing layer SE12, and the protruding portion 131a of the sealing layer SE13 are arranged in this order.

[0208] Figure 23 is a schematic plan view of another example of the DSP display device according to this embodiment. In Figure 23, the configuration of region A2 differs from the example shown in Figure 21.

[0209] In region A2, the sealing layer SE11 is located. Hereafter, the sealing layer SE11 located in region A2 will be referred to as sealing layer 11B. In other words, multiple sealing layers (sealing layers SE11, SE13) are located in the outer peripheral region OP.

[0210] The sealing layer 11B is formed in continuity with the sealing layer SE11 located on the dummy sub-pixel DP1 of the dummy pixel DPA. In other words, the sealing layer 11B is connected to the sealing layer SE11 located on the dummy sub-pixel DP1 of the dummy pixel DPA.

[0211] Focusing on boundary B2, the sealing layer 11B is in contact with the sealing layer SE13 located on the dummy sub-pixel DP3, above the partition 6 situated between the dummy pixel region DMY and the outer peripheral region OP. Focusing on boundary B4, the sealing layer 11B is in contact with the sealing layer 13B located in region A1, above the partition 6 situated between region A1 and region A2.

[0212] Figure 24 is a schematic cross-sectional view of the dummy pixel region DMY and the outer peripheral region OP along the line XXIV-XXIV in Figure 23. In this figure, the substrate 10, circuit layer 11, organic insulating layer 12, sealing layer SE2, and resin layers RS1 and RS2 are omitted.

[0213] As shown in Figure 24, the sealing layer SE11, including the sealing layer 11B, continuously covers a portion of the partition walls 6A and 6B, and partition wall 6C.

[0214] Focusing on the sealing layer SE13, the sealing layer SE13 has an overlapping portion SE131 located above the partition wall 6B. The overlapping portion SE131 is in contact with the end of the sealing layer SE11. The overlapping portion SE131 may include a projection 131a that protrudes upward. Above the partition wall 6B, the projection 131a is located above the sealing layer SE11.

[0215] Furthermore, the superimposed portion SE131 may further include an extension portion 131b that extends toward the gap formed between the sealing layer SE11 and the upper part 62 of the partition wall 6B. A laminated film FL3 is positioned between the partition wall 6B and the superimposed portion SE131.

[0216] Furthermore, the protruding portion 131a of the sealing layer SE13 may overlap with the sealing layer SE11. Specifically, the protruding portion 131a may include a portion 131c (shown by a dashed line in Figure 24) that overlaps with the sealing layer SE11. In this case, in the third direction Z, the partition wall 6B, the sealing layer SE11, and the protruding portion 131a of the sealing layer SE13 are arranged in this order. Note that in the example shown in Figure 24, the laminated film FL1 is placed on the partition wall 6C, but the laminated film FL1 may disappear.

[0217] Even with the configuration of this embodiment, the same effects as in the first embodiment can be obtained. Specifically, the ends of the sealing layer located in region A1 and the sealing layer located in region A2 are in contact with each other above the partition wall 6. By having the ends of the sealing layers in contact with each other above the partition wall 6, the intrusion of etching solution from above is suppressed, and the laminated film FL3 can be left above the partition wall 6.

[0218] Furthermore, in this embodiment, the extension portion 131b (shown in Figures 22 and 24) can be formed in a straight line along the boundary B4. By forming the extension portion 131b in a straight line, it becomes easier to suppress the penetration of etching solution from above.

[0219] Here, we will describe an example of applying the configuration of this embodiment to other locations on the display device DSP.

[0220] Figure 25 is a schematic plan view, enlarged, of the area enclosed by frame XXV in Figure 5. The area enclosed by frame XXV corresponds, for example, to a part of the left side of a circular display device (DSP).

[0221] In the example shown in Figure 25, a sealing layer 13B is placed in region A1, and a sealing layer 12B is placed in region A2. The sealing layer 12B is in contact with the sealing layers SE11 and SE13 of the dummy pixel DPA.

[0222] Furthermore, a portion of the sealing layer 12B is connected in the second direction Y to the sealing layer SE12 located on the dummy sub-pixel DP2 of the dummy pixel DPA, which is located in the bent region (bending point) of the stepped boundary B2. In addition, the sealing layer 12B is in contact with the sealing layer 13B located in region A1.

[0223] Figure 26 is a schematic plan view of another example of a display device DSP. In the example shown in Figure 26, unlike the example in Figure 25, the sealing layer 11B is located in region A2 above the dummy pixel DPA. In the example in Figure 25, an example in which the sealing layer 12B is located in region A2 is disclosed, but the sealing layer 11B may also be located in region A2.

[0224] Figure 27 is a schematic plan view, enlarged, of the area enclosed by frame XXVII in Figure 5. In the example in Figure 27, sealing layer 13B is placed in area A1, and sealing layer 12B is placed in area A2.

[0225] The sealing layer 12B is in contact with the sealing layer SE13 located on the dummy sub-pixel DP3 of the dummy pixel DPA. Furthermore, the sealing layer 12B is connected in the second direction Y to the sealing layer SE12 located on the dummy sub-pixel DP2 of the dummy pixel DPA. In addition, the sealing layer 12B is in contact with the sealing layer 13B located in region A1.

[0226] In the example shown in Figure 27, an example is disclosed in which the sealing layer 12B is placed in region A2, but the sealing layer 11B may also be placed in region A2.

[0227] Figure 28 is a schematic plan view of another example in a display device DSP. In the example shown in Figure 28, unlike the example in Figure 27, sealing layers 11B and 12B are arranged alternately in the first direction X in region A2. These sealing layers 11B and 12B are in contact with each other in the first direction X.

[0228] The sealing layer 11B is in contact with the sealing layer SE13 located on the dummy sub-pixel DP3 of the dummy pixel DPA. The sealing layer 12B is connected in the second direction Y to the sealing layer SE12 located on the dummy sub-pixel DP2 of the dummy pixel DPA.

[0229] Figure 29 is a schematic plan view, enlarged, of the area enclosed by frame XXIX in Figure 5. In the example shown in Figure 29, area A2 is formed above the dummy pixel DPA located at the bent region (bending point) of boundary B2.

[0230] Region A2 is aligned with the dummy pixel DPA in the second direction Y. A sealing layer 12B is located in region A2. The sealing layer 12B is connected in the second direction Y to the sealing layer SE12 located on the dummy sub-pixel DP2 of the dummy pixel DPA. Furthermore, the sealing layer 12B is in contact with the sealing layer 13B located in region A1.

[0231] In the example shown in Figure 29, an example is disclosed in which the sealing layer 12B is placed in region A2, but the sealing layer 11B may also be placed in region A2.

[0232] Figure 30 is a schematic plan view of another example in a display device DSP. In the example shown in Figure 30, unlike the example in Figure 29, in region A2, the sealing layer 11B is arranged adjacent to the sealing layer 12B in the first direction X. These sealing layers 11B and 12B are in contact with each other. The sealing layer 11B is in contact with the sealing layer 13B located in region A1.

[0233] In the example shown in Figure 21 of this embodiment, organic layer OR2 is an example of the first organic layer, organic layer OR3 is an example of the second organic layer, multilayer film FL2 is an example of the first multilayer film, multilayer film FL3 is an example of the second multilayer film, dummy subpixel DP2 of dummy pixel DPA is an example of the first dummy subpixel, dummy subpixel DP3 of dummy pixel DPA is an example of the second dummy subpixel, sealing layer SE12 is an example of the first sealing layer, sealing layer SE13 is an example of the second sealing layer, region A1 is an example of the first region, and region A2 is an example of the second region.

[0234] In the example shown in Figure 22 of this embodiment, organic layer OR1 is an example of the first organic layer, organic layer OR3 is an example of the second organic layer, multilayer film FL1 is an example of the first multilayer film, multilayer film FL3 is an example of the second multilayer film, dummy subpixel DP1 of dummy pixel DPA is an example of the first dummy subpixel, dummy subpixel DP3 of dummy pixel DPA is an example of the second dummy subpixel, sealing layer SE11 is an example of the first sealing layer, sealing layer SE13 is an example of the second sealing layer, region A1 is an example of the first region, and region A2 is an example of the second region.

[0235] Furthermore, each configuration in this embodiment may be applied to a part of the outer peripheral region OP, or to the entire circumference of the outer peripheral region OP.

[0236] With a display device DSP configured as described above, yield can be improved. In addition, various other desirable effects can be obtained from each of the embodiments described above.

[0237] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention. Within the scope of the idea of ​​the present invention, a person skilled in the art can conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or modify components, or to add, omit, or change the conditions of the above-described embodiments, are also included within the scope of the present invention insofar as they retain the gist of the present invention.

[0238] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0239] 1...Pixel circuit, 2...Pixel switch, 5...Rib layer, 6...Partition, 10...Substrate, 11...Circuit layer, 12...Organic insulating layer, 61...Lower part, 62...Upper part, 121a...Protrusion, 121b...Extension, 121c...Part, 131a...Protrusion, 131b...Extension, 131c...Part, A1, A2...Region, B1, B2, B3, B4...Boundary, DA...Display area, DE, DE1, DE2, DE3...Display element, DMY...Dummy pixel area, DP1, DP2, DP3...Dummy sub-pixel, DPX...Dummy pixel, DSP...Display device, FL1, FL2, FL3...Laminated film, OP...Outer peripheral area, OR1, OR2, OR3...Organic layer, PX...Pixel, SA...Peripheral area, SE11, SE12, SE13...Sealing layer, SP1, SP2, SP3...Sub-pixel.

Claims

1. A display area containing multiple pixels for displaying an image, It has multiple dummy pixels, including a first dummy subpixel that does not display an image, and a dummy pixel region surrounding the display area, The outer region surrounding the dummy pixel region, Displaced in the display area, the dummy pixel area, and the outer peripheral area, the partition wall includes a conductive lower part and an upper part having an end protruding from the side surface of the lower part, The first dummy subpixel is arranged in the first stacked film which includes a first organic layer, A first sealing layer formed of an inorganic insulating material and positioned above the first laminated film, Displaced in the outer peripheral region, a second laminated film including a second organic layer, A second sealing layer, formed of an inorganic insulating material and positioned above the second laminated film, is provided. The partition wall is formed continuously from the dummy pixel region to the outer peripheral region. Display device.

2. The second organic layer includes the same light-emitting layer as the first organic layer. The second sealing layer is formed continuously with the first sealing layer above the partition wall located between the dummy pixel region and the outer peripheral region. The display device according to claim 1.

3. The first sealing layer and the second sealing layer are formed to cover the partition wall located between the dummy pixel region and the outer peripheral region. The display device according to claim 2.

4. Further comprising a third sealing layer, The dummy pixel further includes a second dummy subpixel, The second dummy subpixel is provided with a third laminated film including a third organic layer that contains a light-emitting layer different from the first organic layer. The third sealing layer is Located above the third multilayer film, The first sealing layer and the second sealing layer are in contact with each other, The display device according to claim 3.

5. The dummy pixel further includes a second dummy subpixel on which the first stacked film is arranged. The first sealing layer is further positioned above the first stacked film arranged on the second dummy subpixel. Both the first dummy subpixel and the first sealing layer disposed on the second dummy subpixel are formed continuously with the second sealing layer above the partition wall located between the dummy pixel region and the outer peripheral region. The display device according to claim 2.

6. The first sealing layer is disposed on the first dummy subpixel and the second dummy subpixel of at least two adjacent dummy pixels. The display device according to claim 5.

7. The second organic layer includes a light-emitting layer different from the first organic layer. The second sealing layer is in contact with the first sealing layer above the partition wall located between the dummy pixel region and the outer peripheral region. The display device according to claim 1.

8. The dummy pixel further includes a second dummy subpixel on which the first stacked film is arranged. The first sealing layer is further positioned above the first stacked film arranged on the second dummy subpixel. Both the first dummy subpixel and the first sealing layer disposed on the second dummy subpixel are in contact with the second sealing layer above the partition wall located between the dummy pixel region and the outer peripheral region. The display device according to claim 7.

9. The first sealing layer is disposed on the first dummy subpixel and the second dummy subpixel of at least two adjacent dummy pixels. The display device according to claim 8.

10. The second sealing layer has a projection located above the partition wall between the dummy pixel region and the outer peripheral region, and above the first sealing layer. The display device according to claim 1.

11. The protruding portion has a portion that overlaps with the first sealing layer. The display device according to claim 10.

12. The second sealing layer further has an extension that extends toward the gap formed between the first sealing layer and the partition wall. The display device according to claim 10.

13. The second laminated film is further disposed between the partition wall located between the dummy pixel region and the outer peripheral region, the second sealing layer, and the extension portion. The display device according to claim 12.

14. A display area containing multiple pixels for displaying an image, It has multiple dummy pixels, including a first dummy subpixel and a second dummy subpixel that do not display an image, and a dummy pixel region surrounding the display area, The outer region surrounding the dummy pixel region, Displaced in the display area, the dummy pixel area, and the outer peripheral area, the partition wall includes a conductive lower part and an upper part having an end protruding from the side surface of the lower part, The first dummy subpixel is arranged in the first stacked film which includes a first organic layer, A first sealing layer formed of an inorganic insulating material and positioned above the first laminated film, The second laminated film includes a second organic layer arranged in the second dummy subpixel and containing a second organic layer that is different from the first organic layer, A second sealing layer, formed of an inorganic insulating material and positioned above the second laminated film, is provided. The partition wall is formed continuously from the dummy pixel region to the outer peripheral region, The aforementioned outer peripheral region is A first region enclosing the dummy pixel region, A second region is located between the first region and the dummy pixel region, The second sealing layer is further disposed in the first region. The first sealing layer is further disposed in the second region, The first sealing layer located in the second region is in contact with the second sealing layer located in the first region above the partition wall situated between the first region and the second region. Display device.

15. The first sealing layer located in the second region is in further contact with the second sealing layer located in the second dummy sub-pixel above the partition wall located between the dummy pixel region and the outer peripheral region. The display device according to claim 14.

16. The first sealing layer located in the second region is formed in continuity with the first sealing layer located in the first dummy subpixel. The display device according to claim 15.

17. The second sealing layer has a projection located above the partition wall between the first region and the second region, and positioned above the first sealing layer. The display device according to claim 14.

18. The protruding portion has a portion that overlaps with the first sealing layer. The display device according to claim 17.

19. The second sealing layer further has an extension that extends toward the gap formed between the first sealing layer and the partition wall. The display device according to claim 17.

20. The second laminated film is further disposed between the partition wall located between the first region and the second region, the second sealing layer, and the extension portion. The display device according to claim 19.

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