Method for manufacturing heat-treated semiconductor wafers
By correlating statistical quality parameters with lift operation parameters in single-wafer heat treatment furnaces, the method addresses the imbalance between quality and productivity, achieving efficient and sustainable heat treatment processes.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- SUMCO CORP
- Filing Date
- 2024-12-19
- Publication Date
- 2026-07-01
Smart Images
Figure 2026109390000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a heat-treated semiconductor wafer.
Background Art
[0002] As an example of the processes performed during the manufacture of semiconductor wafers such as silicon wafers, various heat treatments such as epitaxial layer formation, annealing, and thermal oxide film formation can be mentioned (see, for example, Patent Document 1).
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] For the heat treatment of semiconductor wafers, single-wafer heat treatment furnaces are widely used. The heat treatment of semiconductor wafers in a single-wafer heat treatment furnace (also simply referred to as a "heat treatment furnace") is usually performed as follows. When a semiconductor wafer is carried into the process chamber of the heat treatment furnace by a transfer means, a lift pin that can move up and down rises above the through-hole of a wafer placement member such as a susceptor to receive the semiconductor wafer, and then descends downward to place the semiconductor wafer on the placement member. When the heat treatment is completed, the lift pin rises again above the through-hole of the wafer placement member to lift the semiconductor wafer. The lifted semiconductor wafer is transferred onto the transfer means and discharged out of the process chamber.
[0005] In recent years, single-wafer heat treatment furnaces have been used that allow for variable setting of the lift speed (more specifically, the upward and downward speeds of the lift pins and / or wafer transport members) (see Patent Document 1). Patent Document 1 proposes reducing the lift speed (referred to as "movement speed" in Patent Document 1) just before the semiconductor wafer (referred to as "substrate" in Patent Document 1) and the lift pins come into contact. Paragraph 0042 of Patent Document 1 describes a preferred range for the lift speed, and paragraph 0043 states that the lift speed may be determined in more detail by factors such as the weight of the substrate, surface shape, and pressure inside the deposition chamber. However, since the lift speed set in this way is not based on quality performance, it cannot be said to be an appropriate lift speed that takes productivity into account for each quality standard. Furthermore, the lift speed control described in Patent Document 1 only targets the lift speed just before the semiconductor wafer and the lift pins come into contact, and does not consider the lift speed at other stages.
[0006] In view of the above, one aspect of the present invention aims to enable the appropriate control of the lift speed in a single-wafer heat treatment furnace, taking into consideration both quality standards and productivity, to perform heat treatment on semiconductor wafers. [Means for solving the problem]
[0007] One aspect of the present invention is as follows: [1] Create a database of relationships between one or more statistical quality parameters selected from the group consisting of flatness, LPD (Light Point Defect), lift pin mark area, and lift pin mark height, and lift operation parameters. The process capability parameters for multiple lift operation parameter combinations are calculated based on one or more quality specification information selected from the group consisting of flatness, LPD, lift pin mark area, and lift pin mark height, and the above database. Based on the results of the above calculation, a pass / fail determination is made for the above combination of lift operation parameters. In the above pass / fail judgment, among the lift operation parameter combinations that were judged to pass, a lift operation parameter combination with a total lift operation time less than or equal to a threshold is selected, and the selected lift operation parameter combination is set in a single-wafer heat treatment furnace in which the lift speed can be set variably, and Heat treatment of semiconductor wafers in the above-mentioned single-wafer heat treatment furnace, A method for manufacturing heat-treated semiconductor wafers, including [the specified component]. [2] The method for manufacturing a heat-treated semiconductor wafer according to [1], wherein the single-wafer heat treatment furnace is an epitaxial growth furnace and the heat treatment is the formation of an epitaxial layer. [3] The single-wafer heat treatment furnace comprises a lift pin and a susceptor having a through hole through which the lift pin can be inserted into the semiconductor wafer mounting area, A method for manufacturing a heat-treated semiconductor wafer according to [1] or [2], wherein the lift operation parameters include one or more lift operation parameters selected from the group consisting of the lift speed before contact between the lift pin and the back surface of the semiconductor wafer, the waiting time before contact between the lift pin and the back surface of the semiconductor wafer, the lift speed before contact between the susceptor and the semiconductor wafer, and the waiting time before contact between the susceptor and the semiconductor wafer. [4] A method for manufacturing a heat-treated semiconductor wafer according to [1] or [2], wherein, among the lift operation parameter combinations that are judged to pass in the above pass / fail judgment, the lift operation parameter combination that has the shortest total lift operation time is selected. [5] The method for manufacturing a heat-treated semiconductor wafer as described in [3], wherein among the lift operation parameter combinations that are judged to pass in the above pass / fail judgment, the lift operation parameter combination that has the shortest total lift operation time is selected. [Effects of the Invention]
[0008] According to one aspect of the present invention, a method for manufacturing a semiconductor wafer can be provided, which includes performing heat treatment of a semiconductor wafer in a single-wafer heat treatment furnace by appropriately controlling the lift speed while considering both quality standards and productivity. [Brief explanation of the drawing]
[0009] [Figure 1] This is a schematic diagram showing an example of a single-wafer epitaxial growth furnace. [Figure 2] Figure 1 is a flowchart illustrating a specific example of the lift operation of a single-wafer epitaxial growth furnace. [Figure 3] This is a flowchart of an example of a semiconductor wafer manufacturing method according to one aspect of the present invention. [Modes for carrying out the invention]
[0010] The above manufacturing method will be explained in more detail below.
[0011] <Semiconductor wafers> Examples of semiconductor wafers (also simply referred to as "wafers") that are heat-treated in a single-wafer heat treatment furnace include various types of semiconductor wafers, such as silicon wafers. For example, a wafer cut from an ingot of semiconductor material grown by a known method (for example, a silicon single-crystal wafer cut from a silicon single-crystal ingot) can be subjected to one or more processing treatments, such as planarization, polishing such as mirror polishing, chamfering, and cleaning, before being placed in a heat treatment furnace for heat treatment. The conductivity type of the semiconductor wafer may be p-type or n-type.
[0012] <Single-wafer heat treatment furnace> Examples of single-wafer heat treatment furnaces include epitaxial growth furnaces for forming an epitaxial layer on a semiconductor wafer, annealing furnaces for annealing a semiconductor wafer, and thermal oxidation furnaces for forming a thermal oxide film on a semiconductor wafer. The configurations of these heat treatment furnaces are well known.
[0013] In a single-wafer heat treatment furnace, a semiconductor wafer is placed on a placement member provided in the heat treatment furnace, and heat treatment is performed in the furnace. Examples of the placement member include a susceptor, a heat treatment boat, and the like.
[0014] FIG. 1 is a schematic diagram showing an example of a single-wafer epitaxial growth furnace. The epitaxial growth furnace 1 shown in FIG. 1 includes a process chamber 10 in which an epitaxial layer is formed. A reaction gas is introduced into the process chamber 10 made of quartz glass, and the susceptor 12 and the preheat ring 17 are heated by a lamp 19 from the outside of the process chamber 10 to form an epitaxial layer on the surface of the semiconductor wafer W. The semiconductor wafer W is carried into the process chamber 10 by a transfer blade 18 which is a transfer means, and after the formation of the epitaxial layer is completed, it is carried out of the process chamber 10 by the transfer blade 18. The susceptor 12 has through-holes through which lift pins 11 can be inserted in the semiconductor wafer placement region, and the lift pins 11 are inserted into such through-holes. The lift pins 11 are connected to a lift assembly 16 via a lift shaft 14 and a lift arm 15. The susceptor 12 is connected to the lift assembly 16 via a susceptor support shaft 13.
[0015] <Lift operation> FIG. 2 is a flowchart showing a specific example of the lift operation of the single-wafer epitaxial growth furnace shown in FIG. 1. In FIG. 2, S1 to S7 indicate the start and end positions of sections. T1 to T12 are the section operation times, and D1 to D12 are the standby times at the start and end of the sections. Hereinafter, the lift operation shown in FIG. 2 will be described. The semiconductor wafer W is carried into the process chamber 10 by the transfer blade 18 (S1). The lift pin 11 receives the semiconductor wafer W on the transfer blade 18 by the vertical movement of the lift assembly 16 (S2 to S4). After the lift pin 11 receives the semiconductor wafer W, the transfer blade 18 returns outside the process chamber 10. After the transfer blade 18 returns outside the process chamber 10, the susceptor 12 receives the semiconductor wafer W on the lift pin 11 by the vertical movement of the susceptor support shaft 13 (S6) and moves to the film formation position (S7). After forming an epitaxial layer at the film formation position, after performing S1 to S6 in reverse order, that is, after performing in the order of S6, S5, S4, S3, S2, S1, the semiconductor wafer W is carried out of the process chamber 10.
[0016] FIG. 3 is a flowchart of an example of a method for manufacturing a semiconductor wafer according to an aspect of the present invention. Hereinafter, the method for manufacturing a semiconductor wafer according to an aspect of the present invention will be further described with appropriate reference to FIG. 3.
[0017] <Creation of Database> In the above manufacturing method, a database of the relationship between one or more statistical parameters of quality selected from the group consisting of flatness, LPD, lift pin mark area, and lift pin mark height and the lift operation parameters is created (S1 in FIG. 3).
[0018] ? Lift operation parameters include the lift speed before contact between the lift pin and the back surface of the semiconductor wafer, the waiting time before contact between the lift pin and the back surface of the semiconductor wafer, the lift speed before contact between the susceptor and the semiconductor wafer, and the waiting time before contact between the susceptor and the semiconductor wafer. Furthermore, lift operation parameters can also include the lift speed after contact between the lift pin and the back surface of the semiconductor wafer, the waiting time after contact between the lift pin and the back surface of the semiconductor wafer, the lift speed after contact between the susceptor and the semiconductor wafer, and the waiting time after contact between the susceptor and the semiconductor wafer. "Lift operation" includes raising, lowering, and waiting. Lift speed can be expressed as interval operation time. Specific examples of lift operation parameters include interval operation times such as T1 to T12 in Figure 2 and waiting times at the beginning and end of intervals such as D1 to D12 in Figure 2.
[0019] The above statistical parameters can be, for example, the mean, standard deviation, etc. In one form, for each of the multiple lift motion parameters, the statistical parameters can be determined as measured values by performing heat treatment according to that lift motion parameter. In another form, some or all of the statistical parameters can be calculated values rather than measured values. Calculated values can be obtained, for example, by performing parameter allocation using an orthogonal array in experimental design, deriving a formula for determining the statistical parameters from the lift motion parameters using the least squares method, and then calculating them from this formula.
[0020] When flatness is adopted as the quality, its statistical parameters can be, for example, the flatness parameter ESFQR (Edge site front least squares range)max, i.e., the batch-unit mean value and batch-unit standard deviation of the maximum value of ESFQR within the wafer.
[0021] When LPD is adopted as the quality standard, its statistical parameters can be, for example, the average value and standard deviation of the number of LPDs of a predetermined size or larger measured on the semiconductor wafer surface by a surface defect inspection device.
[0022] Lift pin marks are contact marks on the back surface of a semiconductor wafer caused by contact with lift pins, such as scratches or deposits. When using lift pin mark area as a quality indicator, its statistical parameters can be the average value and standard deviation of the lift pin mark area on the back surface of the semiconductor wafer. When using lift pin mark height as a quality indicator, its statistical parameters can be the average value and standard deviation of the lift pin mark height on the back surface of the semiconductor wafer. Lift pin marks can be convex contact marks, and lift pin mark height is the height of the convex contact mark. The area and height of lift pin marks can be measured, for example, using a laser microscope.
[0023] The database shown in Table 1 below is a database of the relationship between statistical quality parameters and lift operation parameters, created for the lift operation shown in Figure 2. In this database, the statistical quality parameters are the batch-unit mean Ave. and batch-unit standard deviation σ of ESFQR max. For each condition ID (identification), the batch-unit mean Ave. and batch-unit standard deviation σ of ESFQR max are measured values obtained after actually forming an epitaxial layer on a silicon single-crystal wafer in an epitaxial growth furnace with the lift operation parameters for each condition ID. From the database shown in Table 1, it can be confirmed that increasing the waiting time of D2 and D5 contributes to decreasing the values of the batch-unit mean Ave. and batch-unit standard deviation σ of ESFQR max (i.e., improving quality). It is inferred that increasing the waiting time of D5 immediately before contact between the susceptor and the wafer contributes to reducing the temperature difference between the front and back sides of the wafer, thereby suppressing the occurrence of wafer warping caused by the temperature difference between the front and back sides. Increasing the waiting time of D2 immediately before contact between the lift pin and the wafer contributes to bringing the lift pin into contact with the target position on the back surface of the wafer, which in turn allows the wafer to be placed at the target position on the wafer mounting surface of the susceptor. Heat-treating the wafer after placing it at the target position on the wafer mounting surface of the susceptor can suppress localized gas flow rate or temperature distribution fluctuations caused by the positional relationship of each component in the heat treatment furnace during heat treatment, and may contribute to suppressing quality variations after heat treatment.
[0024] [Table 1]
[0025] <Calculation of process capability parameters, pass / fail determination> (Calculation of process capability parameters) In the above manufacturing method, process capability parameters for multiple lift operation parameter combinations are calculated based on one or more quality specification information selected from the group consisting of flatness, LPD, lift pin mark area, and lift pin mark height, and the above database (S2 in Figure 3). For example, condition IDs A to P shown in Table 1 are specific examples of lift operation parameter combinations. The lift operation parameter combinations may be selected and combined by the operator, or random combinations may be generated by simulation using simulation software, etc.
[0026] In the present invention and this specification, "process capability parameters" include the process capability index and the defect rate.
[0027] As an example, for condition IDs A to P shown in Table 1, the process capability parameters can be calculated as follows. Obtain the ESFQR standard information for two products (referred to as "USL_PN1" and "USL_PN2" in Table 2 below). The products from which standard information is obtained can be arbitrarily selected according to the required quality. For each of the two products, the predicted process capability values ("Cpu_PN1" and "Cpu_PN2") are calculated using the following formulas from the registered values (mean Ave. and standard deviation σ) registered in the database for each condition ID. Since ESFQR is a small-scale characteristic, there is no lower specification. Therefore, for ESFQR, it is preferable to use the process capability index Cpu as the process capability parameter. Process capability index Cpu=(Specification upper limit-Ave.) / 3σ
[0028] On the other hand, for quality that has both upper and lower specifications, the process capability index Cpk, calculated by the following formula, can be adopted as the process capability parameter. Cpk=Min{(Ave.-Specification lower limit) / 3σ,(Specification upper limit-Ave.) / 3σ}
[0029] Alternatively, the defect rate may be used as a process capability parameter.
[0030] (Pass / Fail judgment) After the above calculation, a pass / fail determination is made for the combination of the multiple lift operation parameters based on the calculation results (S3 in Figure 3). For example, if the CPU calculated by the formula described above is 1.00 or higher (CPU ≥ 1.00), it is considered a pass (OK), and if the CPU is less than 1.00, it is considered a fail (NG). Then, the pass / fail determination results for condition IDs A to P shown in Table 1 are as shown in Table 2 below ("PN1 Pass / Fail", "PN2 Pass / Fail").
[0031] [Table 2]
[0032] <Selection of lift operation parameter combinations, implementation of heat treatment> (Selection of lift operation parameter combinations) In the above manufacturing method, among the lift operation parameter combinations that were judged to pass in the above pass / fail judgment, a lift operation parameter combination in which the total lift operation time is less than or equal to a threshold is selected (S4 in Figure 3), and the selected lift operation parameter combination is set in a single-wafer heat treatment furnace in which the lift speed can be set to be variable (S5 in Figure 3). Then, heat treatment of the semiconductor wafer is performed in the single-wafer heat treatment furnace set in this manner (S6 in Figure 3).
[0033] The threshold for the total operating time of the above lift operation can be arbitrarily set with productivity in mind. A shorter total operating time is preferable from the standpoint of improving productivity. From this standpoint, in selecting the above lift operation parameter combination (S4 in Figure 3), it is preferable to select the lift operation parameter combination that has the shortest total operating time among the lift operation parameter combinations that have been judged as passing in the pass / fail judgment.
[0034] Table 3 below summarizes the pass / fail judgment results and total operating time for conditions ID: A to P shown in the table above.
[0035] [Table 3]
[0036] For each product (PN1, PN2), if we select the lift operation parameter combination with the shortest total operating time among the condition IDs that have been judged as acceptable (OK), then for product PN1, the lift operation parameter combination of condition ID:J will be selected, and for product PN2, the lift operation parameter combination of condition ID:B will be selected.
[0037] (Heat treatment) The heat treatment of semiconductor wafers in the above manufacturing method is carried out by setting the selected lift operation parameter combination in the heat treatment furnace. The lift operation parameters may be input by the operator to the control unit of the heat treatment furnace, the parameter set may be downloaded to the control unit of the heat treatment furnace via Ethernet (LAN: Local Area Network), or heat treatment furnace-specific commands may be used.
[0038] Conventionally, the lift operation parameters of a heat treatment furnace were set without considering the influence of each lift operation parameter on quality standards (see, for example, Patent Document 1). For example, if the lift operation parameter combination for condition ID: B (selected for PN2 production) is set the same for both the epitaxial growth furnace for PN1 production and the epitaxial growth furnace for PN2 production, and an epitaxial layer is formed, the lift operation parameters will be set to be inferior in quality compared to the specifications for PN1, resulting in a deterioration of quality and defect rate (in Table 4 below, for product PN1 in (1), the CPU is 0.41). On the other hand, if the lift operation parameter combination for condition ID:J (selected for PN1 production) is set the same for both the epitaxial growth furnace for PN1 production and the epitaxial growth furnace for PN2 production to form the epitaxial layer, productivity for PN2 deteriorates (in Table 4 below, product PN2 (2) has a total operating time of 63 seconds), and the quality becomes over-engineered compared to the specifications for PN2 (in Table 4 below, product PN2 (2) has a CPU of 2.54). In contrast, if the lift operation parameter combination for condition ID:J (selected for PN1 production) is set in the epitaxial growth furnace for PN1 production, and the lift operation parameter combination for condition ID:B (selected for PN2 production) is set in the epitaxial growth furnace for PN2 production, and the epitaxial layer is formed, the epitaxial layer is formed for both PN1 and PN2 with a lift operation parameter combination that does not result in inferior or excessive quality, thereby minimizing the deterioration of productivity (see (3) in Table 4 below).
[0039] [Table 4]
[0040] In the example above, the mean and standard deviation of the flatness parameter ESFQR were used as statistical parameters for quality. However, even when using the various statistical parameters for quality described earlier, heat treatment can be performed by selecting a combination of lift operation parameters to set in the heat treatment furnace, for example, in accordance with the example above. This allows heat treatment to be performed with a lift operation parameter combination that does not result in inferior or excessive quality, thereby suppressing a decline in productivity. [Industrial applicability]
[0041] One aspect of the present invention is useful in the manufacturing field of various semiconductor wafers. According to one aspect of the present invention, it is possible to perform heat treatment efficiently by improving the productivity and production yield of the heat treatment process, thereby reducing energy consumption in the heat treatment process. Reducing energy consumption leads to a reduction in environmental impact and contributes to society by contributing to the achievement of the SDGs (Sustainable Development Goals).
Claims
1. To create a database of relationships between one or more statistical quality parameters selected from the group consisting of flatness, LPD, lift pin mark area, and lift pin mark height, and lift operation parameters. The process capability parameters for a combination of lift operation parameters are calculated for multiple combinations of lift operation parameters based on one or more quality specification information selected from the group consisting of flatness, LPD, lift pin mark area, and lift pin mark height, and the database. Based on the results of the above calculation, a pass / fail determination is made for the combination of the multiple lift operation parameters. In the aforementioned pass / fail judgment, among the lift operation parameter combinations that were judged to pass, a lift operation parameter combination with a total lift operation time less than or equal to a threshold is selected, and the selected lift operation parameter combination is set in a single-wafer heat treatment furnace in which the lift speed can be set variably, and Heat treatment of semiconductor wafers in the aforementioned single-wafer heat treatment furnace, A method for manufacturing heat-treated semiconductor wafers, including [the specified component].
2. The method for manufacturing a heat-treated semiconductor wafer according to claim 1, wherein the single-wafer heat treatment furnace is an epitaxial growth furnace, and the heat treatment is the formation of an epitaxial layer.
3. The single-wafer heat treatment furnace comprises a lift pin and a susceptor having a through hole through which the lift pin can be inserted into the semiconductor wafer mounting area, and A method for manufacturing a heat-treated semiconductor wafer according to claim 1 or 2, wherein the lift operation parameters include one or more lift operation parameters selected from the group consisting of the lift speed before contact between the lift pin and the back surface of the semiconductor wafer, the waiting time before contact between the lift pin and the back surface of the semiconductor wafer, the lift speed before contact between the susceptor and the semiconductor wafer, and the waiting time before contact between the susceptor and the semiconductor wafer.
4. A method for manufacturing a heat-treated semiconductor wafer according to claim 1 or 2, wherein, among the lift operation parameter combinations that are judged to pass in the pass / fail judgment, the lift operation parameter combination that has the shortest total lift operation time is selected.
5. A method for manufacturing a heat-treated semiconductor wafer according to claim 3, wherein, among the lift operation parameter combinations that are judged to pass in the pass / fail judgment, the lift operation parameter combination that has the shortest total lift operation time is selected.