Bonding apparatus, bonding method, and method for manufacturing semiconductor device

Abstract

To improve the yield of semiconductor devices. [Solution] The bonding apparatus of the embodiment includes first and second stages and a processor. The first stage has a main body, a heater for heating the main body, and a plurality of stage pins on the main body, and is configured to hold a first substrate. The second stage is configured to hold a second substrate. The processor performs a bonding process to bond the first substrate and the second substrate. Of the plurality of stage pins, the plurality of first pins arranged in a first direction have at least one of the area and length differ between the first pin located in the center of the first stage and the first pin located on the outer periphery. Of the plurality of stage pins, the plurality of second pins arranged in a second direction different from the first direction have at least one of the area and length being substantially the same between the second pin located in the center of the first stage and the second pin located on the outer periphery.

Description

Technical Field

[0001] Embodiments relate to a bonding apparatus, a bonding method, and a method of manufacturing a semiconductor device.

Background Art

[0002] Three-dimensional stacking technology for stacking semiconductor circuit boards three-dimensionally is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the yield of semiconductor devices.

Means for Solving the Problems

[0005] The bonding apparatus according to the embodiment includes a first stage, a second stage, and a processor. The first stage has a main body portion, a plurality of stage pins provided on the upper portion of the main body portion, and a heater for heating the main body portion, and is configured to be able to hold a first substrate using each of the plurality of stage pins. The second stage is configured to be able to hold a second substrate. The processor is configured to execute a bonding process for bonding the first substrate and the second substrate by controlling the first stage and the second stage. The first stage has a central portion including the center of the first stage and an outer peripheral portion located on the outer periphery of the central portion in a plan view. Among the plurality of stage pins, a plurality of first pins arranged in a first direction have at least one of the area and the length different between a first pin located in the central portion of the first stage and a first pin located in the outer peripheral portion. Among the plurality of stage pins, a plurality of second pins arranged in a second direction different from the first direction have at least one of the area and the length substantially the same between a second pin located in the central portion of the first stage and the second pin located in the outer peripheral portion. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic diagram illustrating the general method for manufacturing a semiconductor device. [Figure 2] A schematic diagram showing an example of the placement of alignment marks used in the manufacturing process of semiconductor devices. [Figure 3] A table showing an example of the correction performance of the exposure apparatus and bonding apparatus for overlapping components that may remain on the wafer surface after bonding overlay. [Figure 4] A block diagram showing an example of the configuration of a semiconductor manufacturing system according to the first embodiment. [Figure 5] A block diagram showing an example of the configuration of an exposure apparatus included in a semiconductor manufacturing system according to the first embodiment. [Figure 6] A block diagram showing an example of the configuration of a bonding apparatus included in a semiconductor manufacturing system according to the first embodiment. [Figure 7] A schematic diagram showing an example of the configuration of the lower stage of the joining device according to the first embodiment. [Figure 8] A plan view showing an example of the planar layout of the lower stage in a first configuration example of the bonding apparatus according to the first embodiment. [Figure 9] A cross-sectional view along the line IX-IX in Figure 8 shows an example of the cross-sectional structure of the lower stage along the X direction in the first configuration example of the joining device according to the first embodiment. [Figure 10] A cross-sectional view along line XX in Figure 8, showing an example of the cross-sectional structure along the Y direction of the lower stage in the first configuration example of the joining device according to the first embodiment. [Figure 11] A plan view showing an example of the planar layout of the lower stage in a second configuration example of the bonding apparatus according to the first embodiment. [Figure 12] A cross-sectional view along line XII-XII in Figure 11, showing an example of the cross-sectional structure of the lower stage along the X direction in a second configuration example of the joining device according to the first embodiment. [Figure 13]Cross-sectional view taken along line XIII-XIII of FIG. 11 showing an example of the cross-sectional structure along the Y direction of the lower stage in the second configuration example of the bonding apparatus according to the first embodiment. [Figure 14] Plan view showing an example of the planar layout of the lower stage in the third configuration example of the bonding apparatus according to the first embodiment. [Figure 15] Cross-sectional view taken along line XV-XV of FIG. 14 showing an example of the cross-sectional structure along the X direction of the lower stage in the third configuration example of the bonding apparatus according to the first embodiment. [Figure 16] Cross-sectional view taken along line XVI-XVI of FIG. 14 showing an example of the cross-sectional structure along the Y direction of the lower stage in the third configuration example of the bonding apparatus according to the first embodiment. [Figure 17] Block diagram showing an example of the configuration of the server included in the semiconductor manufacturing system according to the first embodiment. [Figure 18] Schematic diagram showing an overview of the bonding process in the bonding apparatus according to the first embodiment. [Figure 19] Schematic diagram showing how heat is transferred to the lower wafer held on the lower stage of the bonding apparatus according to the first embodiment. [Figure 20] Graph showing a first example of the temperature change of the lower wafer held on the lower stage of the bonding apparatus according to the first embodiment. [Figure 21] Graph showing a second example of the temperature change of the lower wafer held on the lower stage of the bonding apparatus according to the first embodiment. [Figure 22] Diagram explaining the influence of thermal expansion of the lower stage in the bonding apparatus according to the first embodiment. [Figure 23] Flowchart showing an example of the learning method of the wafer magnification correction value in the semiconductor manufacturing system according to the first embodiment. [Figure 24] Graph showing an example of the learning result of the wafer magnification correction value in the semiconductor manufacturing system according to the first embodiment. [Figure 25] Flowchart showing a first example of the bonding method of the bonding apparatus according to the first embodiment. [Figure 26] Flowchart showing a second example of the bonding method of the bonding apparatus according to the first embodiment. [Figure 27] A flowchart showing an example of a method for learning a wafer magnification correction value in a semiconductor manufacturing system according to the second embodiment. [Figure 28] A graph showing an example of the learning result of the wafer magnification correction value in a semiconductor manufacturing system according to the second embodiment. [Figure 29] A block diagram showing an example of the overall configuration of a memory device according to the third embodiment. [Figure 30] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a memory device according to the third embodiment. [Figure 31] A perspective view showing an example of the structure of a memory device according to the third embodiment. [Figure 32] A plan view showing an example of the planar layout of a memory cell array included in a memory device according to the third embodiment. [Figure 33] A cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in a memory device according to the third embodiment. [Figure 34] A cross-sectional view taken along line XXXIV-XXXIV of FIG. 33 showing an example of the cross-sectional structure of a memory pillar included in a memory device according to the third embodiment. [Figure 35] A cross-sectional view showing an example of the cross-sectional structure of a memory device according to the third embodiment.

MODE FOR CARRYING OUT THE INVENTION

[0007] Hereinafter, each embodiment will be described with reference to the drawings. Each embodiment illustrates an apparatus and a method for embodying the technical idea of the invention. The drawings are schematic or conceptual. Dimensions, ratios, etc. in each drawing are not necessarily the same as those in reality. Illustrations of the configuration are appropriately omitted. Components having substantially the same function and configuration are denoted by the same reference numerals. Numbers added to the reference signs are referred to by the same reference signs and are used to distinguish similar elements from each other.

[0008] In the following, two intersecting directions will be referred to as the "X direction" and the "Y direction," respectively, and the plane parallel to the X and Y directions will be referred to as the "XY plane." In the following explanation, the direction perpendicular to the XY plane will be referred to as the "Z direction." In this specification, "above" means perpendicularly above the reference component. In this specification, "below" means perpendicularly below the reference component. In this specification, "planar view" means viewing a component, such as a horizontally placed layer, from above. "Viewing" includes observing an object using a microscope, camera, etc.

[0009] The semiconductor device described herein is formed by joining two semiconductor circuit boards, each having a semiconductor circuit formed on it, and then separating the joined semiconductor circuit boards into individual chips. Hereinafter, a semiconductor circuit board is referred to as a "wafer." The process of joining two wafers is referred to as the "joining process." The apparatus used to perform the joining process is referred to as the "joining apparatus." The wafers placed on the upper and lower sides during the joining process are referred to as the "upper wafer UW" and the "lower wafer LW," respectively. The joined pair of upper wafer UW and lower wafer LW is referred to as the "joined wafer BW." The "front side of the wafer" corresponds to the side on which the semiconductor circuit is formed by the previous process. The "back side of the wafer" corresponds to the side of the wafer opposite to the front side.

[0010] <0> Overview of Semiconductor Device Manufacturing Method Figure 1 is a schematic diagram showing an overview of the manufacturing method for a semiconductor device. The general process flow in the manufacturing method of a semiconductor device will be explained below with reference to Figure 1.

[0011] First, wafers are assigned to a lot ("lot assignment"). A lot may contain multiple wafers. Lots can be classified, for example, into lots containing upper wafers UW and lots containing lower wafers LW. Each upper wafer UW is associated with one lower wafer LW.

[0012] Then, a front-end process is performed on each lot, including the upper wafer (UW) and the lower wafer (LW). The front-end process includes a combination of "exposure," "exposure overlay measurement," and "etching." Although not described in this specification, the front-end process may also include heating, cleaning, and film deposition processes.

[0013] Exposure is the process of transferring the pattern of a mask (reticle) onto the resist material on a wafer in shot units. A "shot" corresponds to the exposure area in the exposure process. The shot arrangement on the upper wafer UW and the shot arrangement on the lower wafer LW are set to be the same. In the exposure process, one exposure shot is performed repeatedly with a shift in position. In other words, the exposure apparatus exposes the wafer using a step-and-repeat method. After that, a portion of the resist material is removed by the development process, and the desired pattern is transferred to the resist material. In the exposure process, the arrangement and shape of each shot are corrected based on the measurement results of alignment marks and various correction values. This adjusts (aligns) the overlapping position between the underlying pattern and the pattern formed by the exposure process.

[0014] Exposure OL measurement is a process that measures the amount of misalignment between the pattern of the substrate and the pattern of the resist material formed by the exposure process. The measurement results obtained from exposure OL measurement are used, for example, to determine whether the exposure process requires rework or to calculate alignment correction values ​​to be applied to subsequent lots.

[0015] Etching is a process that uses a resist material formed by exposure as a mask to process components on a wafer. Through etching, the components on the wafer are shaped according to the pattern of the resist material. Layer-by-layer circuit patterns can be formed by a combination of exposure and etching processes.

[0016] The front-end processing of the upper wafer UW is performed to form the desired semiconductor circuit on the front surface of the upper wafer UW. The front-end processing of the lower wafer LW is performed to form the desired semiconductor circuit on the front surface of the lower wafer LW ("front-end processing complete"). Subsequently, a bonding process is performed using the associated upper wafer UW and lower wafer LW pair.

[0017] In the bonding process, the bonding apparatus holds the front surfaces of the upper wafer UW and the lower wafer LW facing each other. The bonding apparatus then adjusts (aligns) the overlapping position of the pattern formed on the front surface of the upper wafer UW and the pattern formed on the front surface of the lower wafer LW based on the measurement results of the alignment marks. Next, the bonding apparatus brings the front surfaces of the upper wafer UW and the lower wafer LW into contact. This bonds the front surfaces of the upper wafer UW and the lower wafer LW, forming a bonded wafer BW. Subsequently, a bonding OL (overlay) measurement is performed on the bonded wafer BW.

[0018] Bonding OL measurement is a process that measures the amount of misalignment between the pattern formed on the bonding surface of the upper wafer UW and the pattern formed on the bonding surface of the lower wafer LW. The "bonding layer" corresponds to the layer in contact with the boundary portion of the upper wafer UW and the lower wafer LW. Both the upper wafer UW and the lower wafer LW have a bonding layer. The measurement results obtained from bonding OL measurement can be used to calculate alignment correction values ​​to be applied to the exposure process of subsequent lots.

[0019] Subsequently, a wiring process is performed on the bonded wafer BW to form wiring and pads used for external connections to circuits provided on the bonded wafer BW. Then, the bonded wafer BW is separated into individual chips through a dicing process, thereby forming multiple semiconductor devices from a single bonded wafer BW.

[0020] In this specification, alignment corresponds to the shape of the wafer relative to the exposure or bonding apparatus. The amount of overlap misalignment corresponds to the positional misalignment between the original pattern and the pattern to be overlapped. In other words, the component that cannot be corrected by the exposure or bonding process based on the alignment measurement results constitutes the overlap misalignment. Hereinafter, the correction value used for alignment of the overlap position will be referred to as the “alignment correction value.” When a polynomial is used for alignment correction, the coefficient of each term will be referred to as the “alignment correction coefficient.” The alignment correction value can be calculated based on the alignment correction coefficient of each term and the exposure position.

[0021] The amount of superposition misalignment that may occur in both the exposure and bonding processes can be expressed by a combination of various components. For example, the measurement results of superposition (alignment) can be decomposed into K values ​​by polynomial regression. The superposition components expressed by K values ​​include offset (shift) components, magnification components, and orthogonality components. The formulas corresponding to each component are listed below. In the following formulas, "x" and "y" correspond to the coordinates in the X direction (X coordinate) and the Y direction (Y coordinate), respectively. "dx" and "dy" correspond to the amount of superposition misalignment in the X and Y directions, respectively. "K1" to "K6" each correspond to an alignment correction coefficient (polynomial regression coefficient).

[0022] X-direction offset (shift) component: dx = K1 Y-direction offset (shift) component: dy = K2 Magnification component in the X direction: dx = K3 * x Y-axis magnification component: dy = K4*y Orthogonality component in the X direction: dx = K5 * y The orthogonality component in the Y direction is dy = K6 * x.

[0023] In this example, the overlap misalignment amount Ex in the X direction is calculated by "Ex = K1 + K3*x + K5*y". The overlap misalignment amount Ey in the Y direction is calculated by "Ey = K2 + K4*y + K6*x". Note that when the overlap component is expressed by polynomial regression, coefficients assigned to higher-order overlap components, not just K1 to K6, may be used as polynomial regression coefficients. Furthermore, the overlap misalignment amounts described above can be calculated both on a shot-by-shot basis and within the wafer plane. Hereafter, the overlap component of the magnification component that occurs within the wafer plane will also be called the "wafer magnification component". The wafer magnification component corresponds to the size of the wafer. The overlap component that occurs randomly within the wafer plane will be called the "random component".

[0024] Figure 2 is a schematic diagram showing an example of the arrangement of alignment marks AM used in the manufacturing process of semiconductor devices. Figure 2(A) illustrates the arrangement of multiple alignment marks AM on a wafer WF measured during exposure processing. Figure 2(B) illustrates the arrangement of multiple alignment marks AM on a wafer WF measured during bonding processing.

[0025] As shown in Figure 2(A), during the exposure process, the exposure apparatus measures multiple alignment marks AM placed on the wafer WF (i.e., the upper wafer UW or the lower wafer LW). Preferably, three or more alignment marks AM are measured. The exposure apparatus can calculate alignment correction values ​​such as shift components, magnification components, and orthogonality components in the X and Y directions by approximating the measurement results of the multiple alignment marks AM as functions in a Cartesian coordinate system. Furthermore, the exposure apparatus can correct both shot-level superposition and in-plane superposition of the wafer based on the measurement results of the multiple alignment marks AM.

[0026] As shown in Figure 2(B), during the bonding process, the bonding apparatus measures, for example, three alignment marks AM_C, AM_L, and AM_R located on the upper wafer UW and the lower wafer LW, respectively. Alignment mark AM_C is located at the center of the wafer. Alignment marks AM_L and AM_R are located on one and the other side of the outer periphery of the wafer WF, respectively. Based on the measurement results of the alignment marks AM_C, AM_L, and AM_R on the upper wafer UW and the lower wafer LW, the bonding apparatus can calculate alignment correction values ​​for the shift and rotation components. The bonding apparatus may also be configured to measure multiple alignment marks AM, similar to an exposure apparatus, and to calculate the wafer magnification component.

[0027] Figure 3 is a table showing an example of the correction performance of the exposure apparatus and bonding apparatus for overlapping components that may remain on the wafer surface in bonding overlays. As shown in Figure 3, the XY difference of the wafer magnification component can be corrected in the exposure apparatus, but is difficult to correct in the bonding apparatus.

[0028] <1> First Embodiment The first embodiment relates to a bonding apparatus, a bonding method, and a method for manufacturing a semiconductor device that can improve the XY difference of the wafer magnification component between the upper wafer UW and the lower wafer LW during bonding processing.

[0029] <1-1> Composition The configuration of the semiconductor manufacturing system PS according to the first embodiment will be described below.

[0030] <1-1-1> Configuration of a semiconductor manufacturing system PS Figure 4 is a block diagram showing an example of the configuration of a semiconductor manufacturing system PS according to the first embodiment. As shown in Figure 4, the semiconductor manufacturing system PS includes, for example, an exposure apparatus 1, a bonding apparatus 2, and a server 3. The exposure apparatus 1, the bonding apparatus 2, and the server 3 are configured to communicate with each other via a network NW. The network NW may be wired communication or wireless communication. The bonding apparatus 2 performs bonding processing using the upper wafer UW and lower wafer LW used by the exposure apparatus 1 in the previous process to create a bonded wafer BW. The server 3 is, for example, a computer that controls the entire semiconductor device manufacturing process. The server 3 manages lot processing steps and correction values ​​used in each manufacturing process. The semiconductor manufacturing system PS may also include an overlay measurement device.

[0031] <1-1-2> Configuration of exposure apparatus 1 Figure 5 is a block diagram showing an example of the configuration of an exposure apparatus 1 included in a semiconductor manufacturing system PS according to the first embodiment. As shown in Figure 5, the exposure apparatus 1 includes, for example, a control device 10, a storage device 11, a transport device 12, an exposure unit 13, and a communication device 14.

[0032] The control device 10 is a computer or similar device that controls the overall operation of the exposure apparatus 1. The control device 10 controls the storage device 11, the transport device 12, the exposure unit 13, and the communication device 14. Although not shown in the diagram, the control device 10 includes a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), etc. The CPU is a processor that executes various programs related to the control of the apparatus. ROM is a non-volatile storage medium that stores the control programs of the apparatus. RAM is a volatile storage medium used as the CPU's workspace.

[0033] The storage device 11 is a storage medium used to store data, programs, and the like. The storage device 11 stores, for example, an exposure recipe 110 and correction value information 111. The exposure recipe 110 is a table in which the settings for the exposure process are recorded. The exposure recipe 110 includes information such as the shape and layout of the shot, the amount of exposure, the focus setting, and the alignment setting. The exposure recipe 110 may be prepared for each processing step or processing lot. The correction value information 111 is a log that records the alignment correction values ​​(i.e., alignment results) used when the exposure process was performed.

[0034] The transport device 12 is equipped with a transport arm capable of transporting wafers and a transition for temporarily placing multiple wafers. For example, the transport device 12 transports wafers WF received from an external coating and developing device to the exposure unit 13. After the exposure process, the transport device 12 transports the wafers WF received from the exposure unit 13 to the outside of the exposure device 1. The "coating and developing device" is an apparatus that performs pre-processing and post-processing of the exposure process. Pre-processing of the exposure process includes the process of coating the wafer with a resist material (photosensitive material). Post-processing of the exposure process includes the process of developing the pattern exposed on the wafer. Multiple semiconductor manufacturing apparatuses may be used as the apparatus for pre-processing and post-processing of the exposure process.

[0035] The exposure unit 13 is a set of components used in the exposure process. The exposure unit 13 includes, for example, a wafer stage 130, a reticle stage 131, a light source 132, a projection optical system 133, and a camera 134. The wafer stage 130 has the function of holding the wafer WF. The reticle stage 131 has the function of holding the reticle 135 (mask). The respective stage positions of the wafer stage 130 and the reticle stage 131 can be controlled based on the control of the control device 10. The light source 132 irradiates the reticle 135 with the light it generates. The projection optical system 133 focuses the light that has passed through the reticle 135 onto the surface of the wafer WF. The camera 134 is an imaging mechanism used to measure alignment marks AM.

[0036] The communication device 14 is a communication interface that can connect to a network. The exposure device 1 may operate based on operations performed by a terminal on the network, or it may store the exposure recipe 110 and correction value information 111 on a server on the network.

[0037] <1-1-3> Configuration of Joining Device 2 Figure 6 is a block diagram showing an example of the configuration of a bonding apparatus 2 included in a semiconductor manufacturing system PS according to the first embodiment. As shown in Figure 6, the bonding apparatus 2 includes, for example, a control device 20, a storage device 21, a transport device 22, a bonding unit 23, and a communication device 24.

[0038] The control device 20 is a computer or similar device that controls the overall operation of the bonding device 2. The control device 20 controls the storage device 21, the transport device 22, the bonding unit 23, and the communication device 24. Although not shown in the illustration, the control device 20 includes a CPU, ROM, RAM, etc. The control device 20 may also be called a processor.

[0039] The storage device 21 is a storage medium used to store data, programs, and the like. For example, the storage device 21 stores relational equation 211. Relational equation 211 is a mathematical formula used to correct the XY difference of the wafer magnification component between the lower wafer LW and the upper wafer UW during the bonding process of the lower wafer LW and the upper wafer UW. Details of relational equation 211 will be described later.

[0040] The transport device 22 is a device equipped with a transport arm capable of transporting wafers and a transition for temporarily placing multiple wafers. For example, the transport device 22 transports the upper wafer UW and lower wafer LW received from the pre-processing device for bonding to the bonding unit 23. After the bonding process, the transport device 22 transports the bonded wafer BW received from the bonding unit 23 to the outside of the bonding device 2. The transport device 22 may also be equipped with a mechanism for inverting the wafers.

[0041] The bonding unit 23 is a set of components used in the bonding process. The bonding unit 23 includes, for example, a lower stage 230, a stress device 231, a camera 232, an upper stage 233, a pressing pin 234, and a camera 235. The lower stage 230 is a wafer stage that functions as a wafer chuck, for example, to hold the lower wafer LW by vacuum suction. The stress device 231 has the function of applying stress to the lower stage 230 and deforming the lower wafer LW through the lower stage 230. Depending on the amount of deformation of the lower stage 230 by the stress device 231, the amount of expansion (scaling) of the lower wafer LW held in the lower stage 230 changes. The camera 232 is located on the lower stage 230 side and is an imaging mechanism used to measure the alignment mark AM of the upper wafer UW. The upper stage 233 is a wafer stage that functions as a wafer chuck, for example, to hold the upper wafer UW by vacuum suction. The pressing pin 234 is a pin that is driven vertically based on the control of the control device 20 and can press the upper surface of the center of the upper wafer UW held on the upper stage 233. The camera 235 is an imaging mechanism located on the upper stage 233 side and used to measure the alignment mark AM of the lower wafer LW. The bonding apparatus 2 may have a vacuum pump used for vacuum adsorption of the lower stage 230 and the upper stage 233.

[0042] The lower stage 230 and the upper stage 233 are configured to allow the lower wafer LW held on the lower stage 230 and the upper wafer UW held on the upper stage 233 to be positioned opposite each other. During the bonding process, the upper surface of the upper wafer UW is the back surface of the upper wafer UW and is held on the upper stage 233 of the bonding apparatus 2. During the bonding process, the lower surface of the upper wafer UW is the front surface of the upper wafer UW and corresponds to the bonding surface. The upper surface of the lower wafer LW is the front surface of the lower wafer LW and corresponds to the bonding surface. The lower surface of the lower wafer LW is the back surface of the lower wafer LW and is held on the lower stage 230 of the bonding apparatus 2. The bonding apparatus 2 can adjust the shift and rotation components of the overlap misalignment by adjusting the relative positions of the lower stage 230 and the upper stage 233. Furthermore, the bonding apparatus 2 can adjust the XY common wafer magnification component of the lower wafer LW held on the deformed lower stage 230 by deforming the lower stage 230 with the stress device 231. Furthermore, the bonding apparatus 2 can adjust the XY difference of the wafer magnification component of the lower wafer LW by adjusting the temperature of the lower stage 230.

[0043] The communication device 24 is a communication interface that can be connected to a network NW. The connecting device 2 may operate based on the control of a terminal on the network NW, or it may store operation logs on a server 3 on the network NW, or it may calculate alignment correction values ​​based on the information stored on the server 3.

[0044] The “pre-treatment device for bonding” described above is a device that modifies and hydrophilizes the bonding surfaces of the upper wafer UW and lower wafer LW before the bonding process of the bonding device 2. Briefly, the pre-treatment device first performs plasma treatment on the surfaces of the upper wafer UW and lower wafer LW to modify their surfaces. In the plasma treatment, oxygen ions or nitrogen ions are generated from oxygen gas or nitrogen gas, which are the processing gases, under a predetermined reduced-pressure atmosphere, and the generated oxygen ions or nitrogen ions are irradiated onto the bonding surfaces of each wafer. After that, the pre-treatment device supplies pure water to the surfaces of the upper wafer UW and lower wafer LW. As a result, hydroxyl groups adhere to the surfaces of the upper wafer UW and lower wafer LW, making the surfaces hydrophilic. In the bonding process, the upper wafer UW and lower wafer LW, whose bonding surfaces have been modified and hydrophilized in this way, are used. The bonding device 2 may be combined with the pre-treatment device and the like to constitute a bonding system.

[0045] (Overview of the structure of lower stage 230) Figure 7 is a schematic diagram showing an example of the configuration of the lower stage 230 provided in the joining device 2 according to the first embodiment. Figure 7(A) shows the planar layout of the lower stage 230 in the first embodiment. Figure 7(B) shows the cross-sectional structure of the lower stage 230 in the first embodiment. As shown in Figure 7, the lower stage 230 has a main body 40, ribs 41, a plurality of stage pins 42, a plurality of suction ports 43, and a heater 44.

[0046] The diameter of the main body 40 is at least larger than that of the lower wafer LW in a plan view. The ribs 41 and the multiple stage pins 42 are provided on the upper surface of the main body 40. The upper surface of the main body 40 corresponds to the suction surface of the wafer chuck. The heights of the ribs 41 and the multiple stage pins 42 are approximately uniform. In other words, the positions (heights) of the upper surfaces of the ribs 41 and the multiple stage pins 42 are aligned. The ribs 41 are provided in an annular shape and are positioned on the outer circumference of the wafer chuck portion of the lower stage 230. The multiple stage pins 42 are positioned apart from each other inside the ribs 41 in a plan view.

[0047] The multiple suction ports 43 are arranged spaced apart from each other inside the ribs 41 in a plan view. Each suction port 43 is connected to a vacuum pump (not shown). When a wafer WF is placed on the lower stage 230, the vacuum pump can reduce the pressure in the space enclosed by the upper surface of the main body 40, the ribs 41, and the wafer WF via the multiple suction ports 43. When the pressure in the space enclosed by the upper surface of the main body 40, the ribs 41, and the wafer WF is reduced, the lower wafer LW is attracted to and held on the lower stage 230 side, depending on the external atmosphere, for example, atmospheric pressure. When the lower wafer LW is attracted, the ribs 41 support the outer periphery of the lower surface of the lower wafer LW, and each of the multiple stage pins 42 supports a portion of the lower surface of the lower wafer LW. By supporting the lower surface of the lower wafer LW with the multiple stage pins 42, the lower wafer LW is held in a flat shape, and distortion (warping) of the lower wafer LW in the Z direction can be suppressed.

[0048] The heater 44 has the function of heating the main body 40 based on the control of the control device 20. It is desirable that the heater 44 be positioned inside the main body 40 so as to heat each stage pin 42 located on the upper surface of the main body 40 substantially uniformly. The heater 44 may be positioned in sections within the main body 40. When the main body 40 is heated by the heater 44, the heat from the main body 40 is transferred to the adsorbed lower wafer LW via the multiple stage pins 42.

[0049] Furthermore, the shape of the lower stage 230 can deform in accordance with the temperature of the lower stage 230 and the stress applied by the stress device 231. In this case, the lower wafer LW adsorbed by the lower stage 230 deforms in accordance with the deformation of the lower stage 230. In addition, by supporting the lower wafer LW using the stage pins 42, the lower stage 230 can suppress the influence of particles remaining on the lower surface of the lower wafer LW on the flatness of the adsorbed lower wafer LW. Moreover, because the contact area between the lower stage 230 and the lower wafer LW is reduced by the use of the stage pins 42, the lower wafer LW becomes easier to peel off from the lower stage 230 when the adsorption of the lower wafer LW by the lower stage 230 is released.

[0050] In the bonding apparatus 2 according to the first embodiment, the lower stage 230 is further configured such that the heat transfer to the adsorbed lower wafer LW is non-uniform across the wafer surface, utilizing the arrangement and shape of the multiple stage pins 42 and the shape of the main body 40. The first to third configuration examples of the lower stage 230 in the bonding apparatus 2 according to the first embodiment are described below. Note that in the drawings of the lower stage 230 used in the description of the first to third configuration examples, the suction port 43 and heater 44 are omitted, and characteristic parts are emphasized as examples.

[0051] (Example configuration 1) Figure 8 is a plan view showing an example of the planar layout of the lower stage 230 in a first configuration example of the joining device 2 according to the first embodiment. As shown in Figure 8, in the lower stage 230 of the first configuration example, the density of the multiple stage pins 42 is arranged to vary in one direction. For example, the multiple stage pins 42 are arranged such that the density decreases in the X direction from the center to the outer periphery of the lower stage 230 (main body 40). On the other hand, the multiple stage pins 42 are arranged at equal intervals in the Y direction, for example. Although Figure 8 illustrates a case where the multiple stage pins 42 are arranged in a grid pattern, the multiple stage pins 42 do not have to be arranged in a grid pattern. In the first configuration example, the width and size of each of the multiple stage pins 42 are approximately equal.

[0052] Figure 9 is a cross-sectional view along the line IX-IX in Figure 8, showing an example of the cross-sectional structure of the lower stage 230 along the X direction in a first configuration example of the bonding apparatus 2 according to the first embodiment. In the first configuration example, the pitch of the multiple stage pins 42 aligned in the X direction is, for example, in the range of 2000 to 20000 μm. Specifically, as shown in Figure 9, the pitch D1 of two adjacent stage pins 42 in the X direction at the center of the lower stage 230 is, for example, 2000 μm. The pitch D2 of two adjacent stage pins 42 in the X direction at the outer periphery of the lower stage 230 is, for example, 20000 μm.

[0053] Figure 10 is a cross-sectional view along line XX in Figure 8, showing an example of the cross-sectional structure of the lower stage 230 along the Y direction in a first configuration example of the bonding apparatus 2 according to the first embodiment. In the first configuration example, the pitch of the multiple stage pins 42 aligned in the Y direction is, for example, a fixed value. Specifically, as shown in Figure 10, the pitch D3 of two adjacent stage pins 42 in the Y direction at the center of the lower stage 230 is approximately equal to the pitch D4 of two adjacent stage pins 42 in the Y direction at the outer periphery of the lower stage 230. The pitches D3 and D4 are, for example, 10,000 μm. Therefore, the pitch of the stage pins 42 is in the relationship D2 > D3 = D4 > D1.

[0054] In the lower stage 230 of the first configuration example, it is sufficient that the ratio of the area where the lower wafer LW and the stage pins 42 come into contact decreases in the X direction from the center to the outer periphery of the lower stage 230. In the lower stage 230 of the first configuration example, it is more preferable that the ratio of the area where the lower wafer LW and the stage pins 42 come into contact is within the range of 1 to 25%. For example, the ratio of the area of ​​the upper surface of the stage pins 42 at the center of the lower stage 230 (i.e., the area where the stage pins 42 and the lower wafer LW come into contact) is 25%, and the ratio of the area of ​​the upper surface of the stage pins 42 at the outer periphery of the lower stage 230 is 1%. In other words, in the lower stage 230 of the first configuration example, when the lower wafer LW is adsorbed, 1 cm 2The contact area between the lower wafer LW and the stage pin 42 within the region is 0.25 cm² at the center. 2 (That is, the contact ratio = 25%, and 0.01 cm at the outer circumference) 2 (That is, the contact ratio is 1%).

[0055] (Second configuration example) Figure 11 is a plan view showing an example of the planar layout of the lower stage 230a in a second configuration example of the bonding apparatus 2 according to the first embodiment. As shown in Figure 11, in the lower stage 230a of the second configuration example, the sizes of the multiple stage pins 42 are arranged to vary in one direction. Here, the “size of the stage pins 42” corresponds to the area of ​​the upper surface of the stage pins 42, that is, the area of ​​the contact portion between the stage pins 42 and the lower wafer LW when the lower wafer LW is attracted to the lower stage 230a.

[0056] For example, the size of each stage pin 42 included in a group of stage pins 42 aligned in the X direction decreases as you move from the center to the outer periphery of the lower stage 230 (main body 40). On the other hand, the size of each stage pin 42 included in a group of stage pins 42 aligned in the Y direction is, for example, approximately the same. Specifically, the X-direction diameter R1 of each stage pin 42 decreases as you move from the center to the outer periphery of the lower stage 230a, and the Y-direction diameter R2 of each stage pin 42 is approximately the same. Here, "approximately the same" includes, for example, an error of a few micrometers. Note that Figure 11 illustrates a case where multiple stage pins 42 are arranged in a grid, but the multiple stage pins 42 do not have to be arranged in a strict grid. The fact that the diameter of the stage pins 42 decreases as you move from the center to the outer periphery of the lower stage 230a may also include the arrangement of stage pins 42 with approximately the same diameter in a continuous sequence.

[0057] Figure 12 is a cross-sectional view along line XII-XII in Figure 11, showing an example of the cross-sectional structure of the lower stage 230a along the X direction in a second configuration example of the bonding apparatus 2 according to the first embodiment. As shown in Figure 12, in the second configuration example, among the multiple stage pins 42 arranged in the X direction, the X-direction diameter R1e of the stage pins 42 located on the outer periphery of the lower stage 230a is smaller than the X-direction diameter R1c of the stage pins 42 located in the center of the lower stage 230a. In the lower stage 230a, the X-direction diameter R1 of the multiple stage pins 42 is, for example, in the range of 100 to 1000 μm. Specifically, the X-direction diameter R1c of the central stage pin 42 is, for example, 1000 μm. The X-direction diameter R1e of the outer periphery stage pins 42 is, for example, 100 μm.

[0058] Figure 13 is a cross-sectional view along line XIII-XIII in Figure 11, showing an example of the cross-sectional structure of the lower stage 230a along the Y direction in a second configuration example of the bonding apparatus 2 according to the first embodiment. In the second configuration example, among the multiple stage pins 42 arranged in the Y direction, the X-direction diameter R2e of the stage pin 42 located on the outer periphery of the lower stage 230 is approximately the same as the X-direction diameter R2c of the stage pin 42 located in the center of the lower stage 230. In the lower stage 230a, the Y-direction diameter R2 of the multiple stage pins 42 is, for example, in the range of 100 to 1000 μm. Specifically, the Y-direction diameter R2c of the stage pin 42 in the center of the lower stage 230a and the Y-direction diameter R2e of the stage pin 42 on the outer periphery are, for example, 500 μm each. Therefore, the diameters of the stage pins 42 satisfy the relationship R1c > R2c = R2e > R1e.

[0059] In the second configuration example, the size of the stage pin 42 may be adjusted by changing the diameter R2 in the Y direction. In the second configuration example, the lower stage 230a should be designed such that the ratio of the area where the lower wafer LW and the stage pin 42 make contact decreases in the X direction from the center to the outer periphery of the lower stage 230. In the lower stage 230a of the second configuration example, it is more preferable that the ratio of the diameter R1 in the X direction to the diameter R2 in the Y direction is within the range of 0.3 to 3.0. Furthermore, in the lower stage 230a of the second configuration example, it is more preferable that the ratio of the area where the lower wafer LW and the stage pin 42 make contact is within the range of 1 to 25%. In this case, the ratio of the area of ​​the upper surface of the stage pin 42 at the center of the lower stage 230a (i.e., the area where the stage pin 42 and the lower wafer LW make contact) is 25%, and the ratio of the area of ​​the upper surface of the stage pin 42 at the outer periphery of the lower stage 230a is 1%. In other words, in the lower stage 230a of the second configuration example, when the lower wafer LW is adsorbed, 1 cm 2 The contact area between the lower wafer LW and the stage pin 42 within the region is 0.25 cm² at the center. 2 (That is, the contact ratio = 25%, and 0.01 cm at the outer circumference) 2 (That is, the contact ratio is 1%).

[0060] (Example of configuration 3) Figure 14 is a plan view showing an example of the planar layout of the lower stage 230b in a third configuration example of the joining device 2 according to the first embodiment. As shown in Figure 14, in the lower stage 230b of the third configuration example, stage pins 42 of the same size are arranged in a grid pattern. Although Figure 14 illustrates a case where multiple stage pins 42 are arranged in a grid pattern, the multiple stage pins 42 do not necessarily have to be arranged in a strict grid pattern.

[0061] Figure 15 is a cross-sectional view along the line XV-XV in Figure 14, showing an example of the cross-sectional structure of the lower stage 230b along the X direction in a third configuration example of the joining apparatus 2 according to the first embodiment. As shown in Figure 15, in the lower stage 230b of the third configuration example, the heights of the multiple stage pins 42 are arranged to vary in the X direction. Here, “height of stage pin 42” corresponds to the length along the Z direction between the bottom and top surface of the stage pin 42.

[0062] For example, the height of each stage pin 42 included in a plurality of stage pins 42 aligned in the X direction increases from the center to the outer periphery of the lower stage 230b (main body 40). In this example, among the plurality of stage pins 42 aligned in the X direction, the height HPc of the stage pin 42 at the center of the lower stage 230b is lower than the height HPe of the stage pin 42 at the outer periphery of the lower stage 230b. In the lower stage 230b, the heights HP of the plurality of stage pins 42 are, for example, in the range of 100 to 2000 μm. Specifically, the height HPc of the stage pin 42 at the center is, for example, 100 μm. The height HPe of the stage pin 42 at the outer periphery is, for example, 2000 μm.

[0063] In the third configuration example, the lower stage 230b may be represented by the thickness of the main body portion 40. In this case, the thickness of the main body portion 40 of the lower stage 230b decreases from the center to the outer periphery in a cross-section along the X direction. That is, the thickness HBc at the center of the lower stage 230b is thicker than the thickness HBe at the outer periphery of the lower stage 230b. Note that the fact that the height of the stage pins 42 increases from the center to the outer periphery of the lower stage 230a may also include the arrangement of stage pins 42 of approximately the same height in succession.

[0064] Figure 16 is a cross-sectional view along line XVI-XVI in Figure 14, showing an example of the cross-sectional structure of the lower stage 230b along the Y direction in a third configuration example of the joining device 2 according to the first embodiment. As shown in Figure 16, in the lower stage 230b of the third configuration example, the multiple stage pins 42 arranged in the Y direction are provided at approximately the same height. For example, in a cross-section along the Y direction including the center of the lower stage 230b, the height of the stage pins 42 is HPc, and the thickness of the main body portion 40 of the lower stage 230b is HBc.

[0065] In the above explanation, the example given was the case where the height of the stage pins 42 arranged in the X direction is changed, but the explanation is not limited to this. In the third configuration example, the lower stage 230b may be configured such that the height of each stage pin 42 included in the plurality of stage pins 42 arranged in the Y direction increases from the center of the lower stage 230b (main body 40) toward the outer periphery.

[0066] <1-1-4>Server 3 Configuration Figure 17 is a block diagram showing an example of the configuration of a server 3 in a semiconductor manufacturing system PS according to the first embodiment. As shown in Figure 17, the server 3 includes, for example, a CPU 30, a ROM 31, a RAM 32, a storage device 33, and a communication device 34. The CPU 30 is a processor that executes various programs related to the control of the server 3. The ROM 31 is a non-volatile storage device that stores the control programs of the server 3. The RAM 32 is a volatile storage device used as a workspace for the CPU 30. The storage device 33 is a non-volatile storage medium capable of storing information received from an exposure apparatus 1, a bonding apparatus 2, etc. The communication device 34 is a communication interface that can be connected to a network NW.

[0067] <1-2> Manufacturing method Below, we will describe a specific example of a semiconductor device manufacturing method according to the first embodiment, using an exposure apparatus 1, a bonding apparatus 2, and a server 3. That is, a semiconductor device can be manufactured using the bonding method (bonding process) of the first embodiment described below.

[0068] <1-2-1> Overview of the joining process Figure 18 is a schematic diagram showing an overview of the joining process in the joining apparatus 2 according to the first embodiment. Figures (1) to (8) in Figure 18 each show the state of the joining unit 23 during the joining process. In the following description, the alignment of the shift component will be referred to as "shift alignment," and the alignment of the rotational component will be referred to as "rotational alignment."

[0069] Figure 18(1) shows the state of the joining unit 23 before the joining process.

[0070] When the bonding process begins, the control device 20 controls the heater 44 based on the difference in the XY difference of the wafer magnification components of the upper wafer UW and lower wafer LW that are to be bonded, as shown in Figure 18(2), to adjust the temperature of the lower stage 240. The bonding apparatus 2 may obtain information on the XY difference of the wafer magnification components from the server 3, or it may calculate it based on alignment correction values ​​obtained from the exposure apparatus 1 or the server 3. After the process in Figure 18(2), the control device 20 may control the stress device 241 based on alignment correction values ​​of the wafer magnification components common to the X and Y directions to deform the lower stage 240.

[0071] Next, the control device 20 instructs the transport device 22 to transport the lower wafer LW to the lower stage 230 and the upper wafer UW to the upper stage 233. Then, as shown in (3) of Figure 18, the control device 20 causes the lower stage 230 to hold the lower wafer LW and the upper stage 233 to hold the upper wafer UW. The surfaces of the upper wafer UW and lower wafer LW that are transported to the bonding device 2 have been modified and hydrophilized by a pre-treatment device for the bonding process.

[0072] Next, the control device 20 performs rotational alignment. Specifically, as shown in (4) of Figure 18, the control device 20 first controls the positions of the lower stage 230 and the upper stage 233 to align the optical axis of the camera 232 on the lower stage 230 with the alignment mark AM_L on the upper wafer UW, and align the optical axis of the camera 235 on the upper stage 233 with the alignment mark AM_L on the lower wafer LW. Then, the control device 20 measures the alignment mark AM_L on the upper wafer UW using the camera 232 and measures the alignment mark AM_L on the lower wafer LW using the camera 235.

[0073] Next, as shown in (5) of Figure 18, the control device 20 controls the positions of the lower stage 230 and the upper stage 233 to align the optical axis of the camera 232 on the lower stage 230 with the alignment mark AM_R on the upper wafer UW, and align the optical axis of the camera 235 on the upper stage 233 with the alignment mark AM_R on the lower wafer LW. Then, the control device 20 measures the alignment mark AM_R on the upper wafer UW using camera 232 and measures the alignment mark AM_R on the lower wafer LW using camera 235. After that, the control device 20 calculates the correction amount for the rotational component superposition misalignment based on the measurement results of the alignment marks AM_L and AM_R obtained by cameras 232 and 235 through the processes in (4) and (5) of Figure 18.

[0074] Next, the control device 20 performs camera origin alignment. Specifically, as shown in (6) of Figure 18, the control device 20 controls the positions of the lower stage 230 and the upper stage 233 to insert a common target TG between the optical axis of camera 232 on the lower stage 230 and the optical axis of camera 235 on the upper stage 233. Then, based on the measurement results of the common target TG by cameras 232 and 235, the control device 20 aligns the origins of cameras 232 and 235, respectively.

[0075] Next, the control device 20 performs shift alignment. Specifically, as shown in (7) of Figure 18, the control device 20 first controls the positions of the lower stage 230 and the upper stage 233 to align the optical axis of the camera 232 on the lower stage 230 with the alignment mark AM_C on the upper wafer UW, and align the optical axis of the camera 235 on the upper stage 233 with the alignment mark AM_C on the lower wafer LW. Then, the control device 20 measures the alignment mark AM_C on the upper wafer UW using the camera 232 and the alignment mark AM_C on the lower wafer LW using the camera 235. After that, the control device 20 calculates the alignment correction value of the shift component based on the measurement results of the alignment marks AM_C on the lower wafer LW and the upper wafer UW.

[0076] Next, the control device 20 executes the bonding sequence as shown in (8) of Figure 18. Specifically, first, the control device 20 performs horizontal alignment based on the alignment correction values ​​calculated from rotational alignment and shift alignment, respectively, and the calibration result of the camera origin, and adjusts the relative position of the lower stage 230 and the upper stage 233. Then, the control device 20 moves the upper stage 233 closer to the lower stage 230 to adjust the distance between the upper wafer UW and the lower wafer LW. After that, the control device 20 pushes down the center of the upper wafer UW by lowering the pressing pin 244, bringing the surface of the upper wafer UW into contact with the surface of the lower wafer LW.

[0077] Subsequently, the control device 20 sequentially releases the upper wafer UW from the upper stage 243 (vacuum adsorption) from the inside outwards. As a result, the upper wafer UW falls onto the lower wafer LW, and the surfaces of the upper wafer UW and the lower wafer LW are joined together. Specifically, van der Waals forces (intermolecular forces) are generated between the modified bonding surface of the upper wafer UW and the modified bonding surface of the lower wafer LW, and the contact portions of the upper wafer UW and the lower wafer LW are joined together. Furthermore, since the bonding surfaces of the upper wafer UW and the lower wafer LW are hydrophilic, the hydrophilic groups in the contact portions of the upper wafer UW and the lower wafer LW form hydrogen bonds (intermolecular forces), and the contact portions of the upper wafer UW and the lower wafer LW are joined together more firmly.

[0078] (Temperature change of the lower wafer LW) The temperature change of the lower wafer LW held in the lower stage 230 is described below.

[0079] Figure 19 is a schematic diagram showing how heat is transferred to the lower wafer LW held on the lower stage 230 of the bonding apparatus 2 according to the first embodiment. As shown in Figure 19, the temperature of the air inside the bonding unit 23 corresponds to the room temperature (RT). The initial temperature of the lower wafer LW is, for example, room temperature. When the lower wafer LW is held on the lower stage 230, the space surrounded by the bottom surface of the lower wafer LW, the multiple stage pins 42, and the main body 40 becomes a vacuum. When the main body 40 is heated by the heater 44, the heat from the main body 40 is transferred to the bottom of the lower wafer LW via the multiple stage pins 42. On the other hand, the parts of the lower wafer LW not held by the stage pins 42 do not receive heat from the main body 40 because of the vacuum.

[0080] In the first configuration example, the lower stage 230 and in the second configuration example, the lower stage 230a can change the thermal conductivity from the lower stage 230 to the lower wafer LW within the wafer surface depending on the ratio of the area of ​​contact between the lower wafer LW and the stage pins 42. In the third configuration example, the lower stage 230 can change the thermal conductivity from the lower stage 230 to the lower wafer LW within the wafer surface depending on the length of the stage pins 42 that pass through it. The effects obtained are the same in all of the first to third configuration examples of the lower stage 230. Below, we will mainly describe the case in which the lower stage 230 of the first configuration example, as shown in Figure 8, is used.

[0081] Figures 20 and 21 are graphs showing two examples, the first and second examples, of the temperature change of the lower wafer LW held in the lower stage 230 of the bonding apparatus 2 according to the first embodiment. In the graphs shown in Figures 20 and 21, the horizontal axis represents time, and the vertical axis represents the temperature at the central part CP and the outer peripheral part EP of the lower wafer LW, respectively. The temperature of the lower stage 230 differs between the first and second examples. Specifically, the lower stage 230 in the second example is adjusted to a higher temperature than the lower stage 230 in the first example. When the lower wafer LW is held in the lower stage 230, heat is transferred from the main body 40 of the lower stage 230 to the lower wafer LW via a plurality of stage pins 42, and the temperature of the lower wafer LW rises from room temperature RT.

[0082] As shown in Figure 20, in the first example, at time t1, the temperature of the central CP of the lower wafer LW rises to TCP1, and the temperature of the outer peripheral EP of the lower wafer LW rises to TEP1. Subsequently, the temperatures of the central CP and outer peripheral EP of the lower wafer LW reach equilibrium based on the heat transmitted through the multiple stage pins 42 and the room temperature of the bonding unit 23. At this time, since the thermal conductivity of the central CP is higher than that of the outer peripheral EP, the temperature TCP1 becomes higher than the temperature TEP1.

[0083] On the other hand, as shown in Figure 21, in the second example, at time t2, the temperature of the central CP of the lower wafer LW rises to TCP2, and the temperature of the outer peripheral EP of the lower wafer LW rises to TEP2. Subsequently, the temperatures of the central CP and outer peripheral EP of the lower wafer LW reach equilibrium based on the heat transmitted through the multiple stage pins 42 and the room temperature of the bonding unit 23. At this time, since the thermal conductivity of the central CP is higher than that of the outer peripheral EP, the temperature TCP2 becomes higher than the temperature TEP2.

[0084] The bonding of the lower wafer LW and the upper wafer UW is preferably performed after the temperature of the lower wafer LW has reached equilibrium. The temperature difference between the central part CP and the outer peripheral part EP after equilibrium is reached is larger in the second example than in the first example, based on the fact that the temperature of the lower stage 230 is higher in the second example than in the first example. Thus, the bonding apparatus 2 according to the first embodiment can adjust the temperature difference within the wafer surface in the X direction of the lower wafer LW by adjusting the temperature of the lower stage 230. As a result, the XY difference of the wafer magnification component of the lower wafer LW can be adjusted based on the temperature difference within the wafer surface and the thermal expansion coefficient of the lower wafer LW. On the other hand, by adjusting the temperature of the lower stage 230, the lower wafer LW is heated in the Y direction, and the temperature difference within the wafer surface is suppressed. Therefore, the change in the wafer magnification component in the Y direction is suppressed. Accordingly, the bonding apparatus 2 can adjust the XY difference of the wafer magnification component by adjusting the temperature of the lower stage 230. Note that the timing at which the temperature of the lower wafer LW reaches equilibrium by adjusting the temperature of the lower stage 230 may differ between the central part CP and the outer peripheral part EP. For example, when a lower wafer LW is placed on the lower stage 230 of the first to third configurations, and heat is transferred to the lower wafer LW via the multiple stage pins 42, the temperature of the central CP in the X direction of the lower wafer LW becomes higher along the Y direction, while the temperature of the outer peripheral EP in the X direction of the lower wafer LW becomes lower. For example, since semiconductor substrates (wafers) expand when their temperature rises, the lower wafer LW placed on the lower stage 230 of the first to third configurations expands more in the Y direction than in the X direction. If it is desired that the lower wafer LW expands more in the X direction than in the Y direction, for example, the lower wafer LW can be placed on the lower stage 230 after being rotated 90 degrees.

[0085] (Effect of thermal expansion in the lower stage 230) Figure 22 illustrates the effect of thermal expansion on the lower stage 230 in the bonding apparatus 2 according to the first embodiment. Figures 22(A) and (B) show the position of the lower stage 230 when measuring the alignment mark AM_L located on the outer periphery and the alignment mark AM_C located in the center, respectively, and show the side and top surfaces of the lower stage 230. Figures 22(A) and (B) also show some of the configuration used for position control of the lower stage 230.

[0086] The bonding unit 23 further includes, for example, movable mirrors 236 and 237, and interferometers 238 and 239. The movable mirrors 236 and 237 are mounted on the lower stage 230 so as to reflect light irradiated from the X and Y directions, respectively. The interferometers 238 and 239 calculate the movement distance of the stage from the difference between the light waves of the fixed beam and the moving beam. Specifically, the interferometer 238 uses the reflected light from the movable mirror 236 to calculate the movement distance of the lower stage 230 in the X direction. The interferometer 239 uses the reflected light from the movable mirror 237 to calculate the movement distance of the lower stage 230 in the Y direction. As a result, the control device 20 can control the position of the lower stage 230 based on the measurement results of the interferometers 238 and 239.

[0087] When the lower stage 230 is heated by the heater 44 (see Figure 7), the lower stage 230 undergoes thermal expansion. Figure 22 shows the thermal expansion of the lower stage 230 only in the Y direction. Note that thermal expansion of the lower stage 230 occurs in both the X and Y directions, but Figure 22 only shows thermal expansion in the Y direction. Since the heater 44 is configured to control the temperature of the entire lower stage 230 substantially uniformly, the amount of thermal expansion of the lower stage 230 in the Y direction due to temperature changes in the lower stage 230 can be substantially uniform between the center and the edges of the lower stage 230 in the X direction. For this reason, in the bonding apparatus according to the first embodiment, when measuring the alignment of the lower wafer LW with the interferometer 239 as a reference, the difference in the measurement results of the wafer position in the Y direction can be suppressed between measuring the alignment mark AM_L at the center and measuring the alignment mark AM_L at the edges.

[0088] <1-2-2> Learning Method Figure 23 is a flowchart showing an example of a method for learning the wafer magnification correction value in the semiconductor manufacturing system PS according to the first embodiment. The wafer magnification correction value is a correction value for the wafer magnification component, which will be described later. Below, with reference to Figure 23, an example of a sequence for generating relational equation 211 as a method for learning the wafer magnification correction value will be described.

[0089] First, multiple upper wafers UW having approximately the same XY difference in the wafer magnification components of the bonding surface are prepared (step S101), and multiple lower wafers LW having approximately the same XY difference in the wafer magnification components of the bonding surface are prepared (step S102). In this specification, the “wafer magnification component of the bonding surface” is based, for example, on the alignment result measured by the exposure apparatus 1 in the lithography process which is the last step performed in the preceding process. The “wafer magnification component of the bonding surface” may also be a numerical value of the wafer magnification component measured in another process, if it can be used to adjust the overlap of the upper wafers UW and lower wafers LW in the bonding process. The prepared multiple upper wafers UW and multiple lower wafers LW are transported to the bonding apparatus 2 according to the first embodiment. The bonding apparatus 2 has a lower stage 230 in any of the first to third configuration examples.

[0090] Next, the bonding process between the prepared lower wafer LW and upper wafer UW is performed (step S103). In step S103, the temperature of the lower stage 230 is adjusted to a predetermined temperature among the temperatures to be learned, and at least one pair of lower wafer LW and upper wafer UW are bonded. The predetermined temperature may be, for example, the temperature of the heater 44. Once the bonding process of at least one pair of lower wafer LW and upper wafer UW using the predetermined temperature is completed, the bonding apparatus 2 checks whether the bonding process at all temperatures to be learned has been completed (step S104).

[0091] If the bonding process at all the temperatures to be learned has not been completed (step S104: NO), the bonding apparatus 2 changes the temperature (step S105) and proceeds to step S103. That is, the bonding apparatus 2 uses a different temperature than the previous time to perform the bonding process on at least one pair of lower wafers LW and upper wafers UW. If the bonding process at all the temperatures to be learned has been completed (step S104: YES), the semiconductor manufacturing system PS proceeds to step S106.

[0092] In step S106, the superposition of multiple bonded wafers BW created in step S103 is measured using a superposition inspection device. The superposition measurement results are transferred to, for example, server 3. Server 3 then calculates the difference in the XY difference of the wafer magnification component between the lower wafer LW and the upper wafer UW at each of the multiple temperatures used (this is defined as the XY difference of the wafer magnification component of bonded wafer BW) from the measurement results of the superposition of multiple bonded wafers BW (step S107). Server 3 then creates a relationship equation 211 between the XY difference of the wafer magnification component of bonded wafer BW and the temperature of the lower stage 230 (step S108). The temperature of the lower stage 230 in step S108 may be the temperature of the heater 44. After that, server 3 transfers the created relationship equation 211 to the bonding device 2, and the bonding device 2 saves the relationship equation 211 transferred from server 3 to the storage device 21. Steps S107 and S108 may be performed by the bonding device 2.

[0093] Figure 24 is a graph showing an example of the learning result of the wafer magnification correction value in the semiconductor manufacturing system PS according to the first embodiment. In the graph shown in Figure 24, the horizontal axis represents the XY difference of the wafer magnification component of the bonded wafer BW, and the vertical axis represents the temperature of the lower stage 230. As shown in Figure 24, the XY difference of the wafer magnification component of the bonded wafer BW and the temperature of the lower stage 230 can be expressed, for example, by a linear function relation 211. In other words, the XY difference of the wafer magnification component of the bonded wafer BW in the bonding process increases as the temperature of the lower stage 230 increases. By using relation 211, which is the learning result of such a wafer magnification correction value, the bonding apparatus 2 can select a temperature for the lower stage 230 such that the XY difference of the wafer magnification component of the bonded wafer BW in the bonding overlay measurement approaches zero, based on the wafer magnification information of the lower wafer LW and upper wafer UW to be bonded.

[0094] <1-2-3>Joining method Below, an example of a joining process sequence using relational equation 211 as a joining method using the joining apparatus 2 according to the first embodiment will be described.

[0095] (Example 1) Figure 25 is a flowchart showing a first example of a bonding method using the bonding apparatus 2 according to the first embodiment. Below, with reference to Figure 25, an example of a sequence in which the bonding apparatus 2 performs the bonding process using the calculation result of the XY difference of the wafer magnification component of the bonding wafer BW by the server 3 will be described.

[0096] First, server 3 acquires the alignment result of the upper wafer UW (step S111). This alignment result of the upper wafer UW corresponds to the alignment measurement result in the exposure process, which serves as the basis for overlay adjustment during the bonding process. Alternatively, the overlay inspection result from the overlay inspection device may be used instead of the alignment result of the upper wafer UW.

[0097] Next, server 3 acquires the alignment result of the lower wafer LW (step S112). This alignment result of the lower wafer LW corresponds to the alignment measurement result in the exposure process, which serves as the basis for overlay adjustment during the bonding process. Alternatively, the overlay inspection result from the overlay inspection device may be used instead of the alignment result of the lower wafer LW.

[0098] Next, Server 3 calculates the XY difference of the wafer magnification components of the upper wafer UW and lower wafer LW that are to be combined (Step S113). Then, Server 3 transfers the calculated information of the XY difference of the wafer magnification components to Bonding Apparatus 2 (Step S114). Bonding Apparatus 2 stores the information of the XY difference of the wafer magnification components transferred from Server 3 in, for example, a storage device 21.

[0099] Next, the bonding apparatus 2 calculates (or selects) the optimal temperature for the lower stage 230 based on the relational expression 211 (step S115). The calculation of the optimal temperature for the lower stage 230 is performed, for example, for each combination of upper wafer UW and lower wafer LW. Then, the bonding apparatus 2 uses the calculated optimal temperature to perform the bonding process for the associated lower wafer LW and upper wafer UW combination (step 116).

[0100] (Example 2) Figure 26 is a flowchart showing a second example of a bonding method for a bonding apparatus according to the first embodiment. Below, with reference to Figure 26, an example of a sequence in which the bonding apparatus 2 calculates the XY difference of the wafer magnification component itself and performs the bonding process will be described.

[0101] First, the bonding apparatus 2 performs alignment measurements on the upper wafer UW and the lower wafer LW (step S121). That is, in the second example, the processes corresponding to (4) to (7) in Figure 18 are performed before the process in (2) in Figure 18. Then, the bonding apparatus 2 calculates the XY difference of the wafer magnification components of the upper wafer UW and lower wafer LW to be combined based on the alignment measurement results (step S122). After that, the bonding apparatus 2 calculates the optimal temperature of the lower stage 230 based on relational equation 211, similar to the first example of the bonding method (step S115), and uses the calculated optimal temperature to perform the bonding process for the associated lower wafer LW and upper wafer UW combination (step 116).

[0102] <1-3> Effects of the First Embodiment The semiconductor manufacturing system PS according to the first embodiment can improve the yield of semiconductor devices. The effects of the first embodiment are described in detail below.

[0103] In a semiconductor device having a bonded structure, the difference in the XY difference of the wafer magnification components of the upper wafer UW and the lower wafer LW can be a factor in the deterioration of the bonded overlay of the bonded wafer BW. In the bonding apparatus 2, the wafer magnification component common to the upper wafer UW and the lower wafer LW in the X and Y directions can be corrected, for example, by deforming the lower stage 230 with the stress device 231. On the other hand, the stress device 231 cannot correct the XY difference of the wafer magnification component.

[0104] In contrast, in the lower stage 230 of the bonding apparatus 2 according to the first embodiment, the arrangement density, shape, or height of the multiple stage pins 42 of the lower stage 230 is configured such that the thermal conductivity differs between the X direction and the Y direction within the wafer surface. In other words, the multiple stage pins 42 arranged in one direction (for example, the X direction) are configured such that at least one of the area and length differs between the central part and the outer periphery of the lower stage 230.

[0105] As a result, the bonding apparatus 2 according to the first embodiment can generate a desired temperature difference within the wafer surface of the lower wafer LW. The bonding apparatus 2 according to the first embodiment can generate a temperature difference (thermal expansion difference) in the X and Y directions of the lower wafer LW, and can adjust the XY difference of the wafer magnification component between the lower wafer LW and the upper wafer UW. As a result, the bonding apparatus 2 according to the first embodiment can equalize the XY difference of the wafer magnification component between the lower wafer LW and the upper wafer UW, and can suppress overlapping misalignment in the bonding overlay of the bonded wafer BW. Therefore, the semiconductor manufacturing system PS according to the first embodiment can improve the accuracy of the bonding overlay and improve the yield of semiconductor devices having a bonded structure.

[0106] <2> Second Embodiment In the semiconductor manufacturing system PS according to the second embodiment, the bonding apparatus 2 is configured to create relational expression 211 using one bonding wafer BW. Below, the differences between the semiconductor manufacturing system PS according to the second embodiment and the first embodiment will be mainly described.

[0107] <2-1> Composition The configuration of the semiconductor manufacturing system PS according to the second embodiment is the same as that of the first embodiment.

[0108] <2-2> Manufacturing method Figure 27 is a flowchart showing an example of a method for learning wafer magnification correction values ​​in a semiconductor manufacturing system PS according to the second embodiment. Below, with reference to Figure 27, an example of a sequence for generating relational expression 211 as a method for learning wafer magnification correction values ​​will be described.

[0109] First, the lower wafer LW before bonding is prepared (step S201). In this specification, “lower wafer LW before bonding” corresponds to the lower wafer LW after the preceding process has been completed. The prepared lower wafer LW is transported to the bonding apparatus 2 and held on the lower stage 230.

[0110] Next, the temperature of the lower stage 230 is adjusted (step S202). A predetermined temperature, which is the learning target, is used as the temperature of the lower stage 230. Then, after the temperature of the lower stage 230, which has been adjusted, and the temperature of the lower wafer LW have reached equilibrium, the bonding apparatus 2 performs alignment measurement using the camera 235 on the upper stage 233 side (step S203). The object to be measured for alignment in step S203 is the bonding layer formed in the previous process or a layer near the bonding layer. The results of the alignment measurement are stored, for example, in the storage device 21. Once the alignment measurement is complete, the bonding apparatus 2 checks whether the alignment measurement has been completed at all the learning target temperatures (step S204).

[0111] If alignment measurements at all temperatures of the learning target have not been completed (step S204: NO), the bonding apparatus 2 changes the temperature (step S205) and proceeds to step S202. That is, the bonding apparatus 2 uses a different temperature than last time to adjust the temperature of the lower stage 230 and perform alignment measurements of the lower wafer LW. If alignment measurements at all temperatures of the learning target have been completed (step S204: YES), the bonding apparatus 2 proceeds to step S206.

[0112] In step S206, the bonding apparatus 2 calculates the XY difference of the wafer magnification component of the lower wafer LW at each of the multiple temperatures used, based on the alignment measurement results. Then, the bonding apparatus 2 creates a relational expression 211 between the XY difference of the wafer magnification component of the lower wafer LW and the temperature of the lower stage 230 (step S207). The temperature of the lower stage 230 in step S207 may be the temperature of the heater 44. After that, the bonding apparatus 2 stores the created relational expression 211 in the storage device 21.

[0113] Figure 28 is a graph showing an example of the learning results of the wafer magnification correction value in the semiconductor manufacturing system PS according to the second embodiment. In the graph shown in Figure 28, the horizontal axis represents the XY difference of the wafer magnification component of the lower wafer LW before bonding, and the vertical axis represents the temperature of the lower stage 230. As shown in Figure 28, the XY difference of the wafer magnification component of the lower wafer LW and the temperature of the lower stage 230 can be expressed, for example, by a linear function relation 211. In this case, the amount of correction for the XY difference of the wafer magnification component in the bonding process increases as the temperature of the lower stage 230 increases. The bonding apparatus 2 can use relation 211, which is the learning result of the wafer magnification correction value, to select a temperature for the lower stage 230 that results in an XY difference of the wafer magnification component of the lower wafer LW such that the difference in the XY difference of the wafer magnification component of the lower wafer LW and the upper wafer UW in the bonding overlay measurement approaches zero, based on the information of the XY difference of the wafer magnification components of the lower wafer LW and the upper wafer UW to be bonded, which was obtained in another process.

[0114] <2-3> Effects of the second embodiment The semiconductor manufacturing system PS according to the second embodiment can create a correction formula 211 used to correct the XY difference of the wafer magnification component with fewer resources than the first embodiment. Therefore, the semiconductor manufacturing system PS according to the second embodiment can obtain the same effects as the first embodiment, and can reduce the cost required to create the correction formula 211 compared to the first embodiment.

[0115] <3> Third Embodiment The third embodiment relates to a specific example of a semiconductor device manufactured using the bonding method described in the above embodiment. Below, a memory device having a bonding structure will be described as a specific example of a semiconductor device.

[0116] <3-1> Overall configuration of memory device 500 Figure 29 is a block diagram showing an example of the overall configuration of the memory device 500 according to the third embodiment. As shown in Figure 29, the memory device 500 includes a memory interface (memory I / F) 501, a sequencer 502, a memory cell array 503, a driver module 504, a raw decoder module 505, and a sense amplifier module 506.

[0117] The memory I / F501 is connected to an external memory controller via channel CH and communicates according to the interface standard. The memory I / F501 supports, for example, the NAND interface standard.

[0118] The sequencer 502 is a control circuit that controls the overall operation of the memory device 500. Based on commands received via the memory interface 501, the sequencer 502 controls the driver module 504, the row decoder module 505, the sense amplifier module 506, etc., to perform read operations, write operations, erase operations, etc.

[0119] The memory cell array 503 is a memory circuit that includes a collection of multiple memory cells. The memory cell array 503 includes multiple blocks BLK0 to BLKn (where n is an integer of 1 or more). The memory cell array 503 is provided with multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line BL and one word line WL.

[0120] The driver module 504 is a driver circuit that generates voltages used in read, write, and erase operations. The driver module 504 applies the generated voltages to multiple signal lines connected to the raw decoder module 505.

[0121] The row decoder module 505 decodes the row address received via the memory interface 501 and selects one block BLK based on the decoding result. The row decoder module 505 then transfers the voltages applied to multiple signal lines to multiple wirings (such as word lines WL) located in the selected block BLK.

[0122] In read operations, the sense amplifier module 506 determines the data read from the selected memory cell based on the voltage of the bit line BL and transmits it to the memory controller via the memory I / F 501. In write operations, the sense amplifier module 506 applies a voltage to each bit line BL corresponding to the data to be written to the memory cell.

[0123] <3-2> Circuit configuration of the memory cell array 503 Figure 30 is a circuit diagram showing an example of the circuit configuration of a memory cell array 503 included in the memory device 500 according to the third embodiment. Figure 30 shows one of several block BLKs included in the memory cell array 503. As shown in Figure 30, the block BLK includes, for example, four string units SU0 to SU3.

[0124] Each string unit SU contains multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each bit line BL is shared by NAND strings NS, each assigned the same column address across multiple blocks BLK. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, as well as selection transistors STD and STS.

[0125] Each memory cell transistor MT includes a control gate and a charge storage layer, and stores data nonvolatilically. The memory cell transistors MT0 to MT7 of each NAND string NS are connected in series. The control gates of the memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. Each of the word lines WL0 to WL7 is provided for each block BLK. A collection of multiple memory cell transistors MT connected to a common word line WL in the same string unit SU is called, for example, a "cell unit CU". A cell unit CU may have a storage capacity of two pages or more of data, depending on the number of bits of data stored by the memory cell transistors MT.

[0126] The selection transistors STD and STS are used for selecting string unit SU, respectively. The drain of selection transistor STD is connected to the associated bit line BL. Memory cell transistors MT0 to MT7 are connected in series between the source of selection transistor STD and the drain of selection transistor STS. The gates of selection transistor STD included in string units SU0 to SU3 are connected to selection gate lines SGD0 to SGD3, respectively. The source of selection transistor STS is connected to source line SL. The gate of selection transistor STS is connected to selection gate line SGS. Source line SL is shared, for example, by multiple blocks BLK.

[0127] In addition, the number of word lines WL, selection gate lines SGD and SGS, and the number of memory cell transistors MT, selection transistors ST1 and ST2 in the memory cell array 503 may be other numbers.

[0128] <3-3> Structure of Memory Device 500 An example of the structure of the memory device 500 according to the third embodiment is described below. In the fourth embodiment, the X direction corresponds to, for example, the extension direction of the word line WL. The Y direction corresponds to, for example, the extension direction of the bit line BL. The Z direction corresponds to the direction perpendicular to the front surface of the semiconductor substrate (wafer) used to form the memory device 500.

[0129] Figure 31 is a perspective view showing an example of the structure of a memory device 500 according to the third embodiment. As shown in Figure 31, the memory device 500 includes a memory chip MC and a CMOS chip CC. The memory chip MC includes a memory area MR, draw areas HR1 and HR2, and a pad area PR1. The CMOS chip CC includes a sense amplifier area SR, a peripheral circuit area PERI, transfer areas XR1 and XR2, and a pad area PR2.

[0130] The memory area MR includes the memory cell array 503. The lead areas HR1 and HR2 include wiring used for connecting the stacked wiring provided on the memory chip MC and the low decoder module 505 provided on the CMOS chip CC. The pad area PR1 includes pads used for connecting the memory device 500 and the memory controller. The lead areas HR1 and HR2 sandwich the memory area MR in the X direction. The pad area PR1 is adjacent to the memory area MR and the lead areas HR1 and HR2 in the Y direction.

[0131] The sense amplifier area SR includes the sense amplifier module 506. The peripheral circuit area PERI includes the sequencer 502 and the driver module 504, etc. The transfer areas XR1 and XR2 include the row decoder module 505. The pad area PR2 includes the memory I / F 501. The sense amplifier area SR and the peripheral circuit area PERI are located adjacent to each other in the Y direction and overlap with the memory area MR in the Z direction. The transfer areas XR1 and XR2 sandwich the sense amplifier area SR and peripheral circuit area PERI in the X direction and overlap with the lead areas HR1 and HR2, respectively. The pad area PR2 overlaps with the pad area PR1 of the memory chip MC in the Z direction.

[0132] The memory chip MC has multiple bonding pads BP at the bottom of each of the following areas: the memory area MR, the lead areas HR1 and HR2, and the pad area PR1. The bonding pads BP of the memory area MR are connected to the associated bit lines BL. The bonding pads BP of the lead area HR are connected to the associated wiring (e.g., word lines WL) among the stacked wiring provided in the memory area MR. The bonding pads BP of the pad area PR1 are connected to pads (not shown) provided on the top surface of the memory chip MC. The pads provided on the top surface of the memory chip MC are used, for example, for connections between the memory device 500 and the memory controller.

[0133] The CMOS chip CC has multiple junction pads BP above the sense amplifier region SR, the peripheral circuit region PERI, the transfer regions XR1 and XR2, and the pad region PR2. The junction pads BP of the sense amplifier region SR overlap with the junction pads BP of the memory region MR in the Z direction. The junction pads BP of the transfer regions XR1 and XR2 overlap with the junction pads BP of the lead regions HR1 and HR2, respectively, in the Z direction. The junction pads BP of the pad region PR1 overlap with the junction pads BP of the pad region PR2 in the Z direction.

[0134] The memory device 500 has a structure in which the lower surface of the memory chip MC (the front surface of the semiconductor substrate on which the memory chip MC is formed) and the upper surface of the CMOS chip CC (the front surface of the semiconductor substrate on which the CMOS chip CC is formed) are joined together. Of the multiple bonding pads BP provided on the memory device 500, two bonding pads BP facing each other between the memory chip MC and the CMOS chip CC are electrically connected by bonding. As a result, the circuits within the memory chip MC and the circuits within the CMOS chip CC are electrically connected via the bonding pads BP. The pair of bonding pads BP facing each other between the memory chip MC and the CMOS chip CC may have a boundary or may be integrated.

[0135] <3-3-1> Structure of the memory cell array 503 The structure of the memory cell array 503 is described below.

[0136] (Planar layout of memory cell array 503) Figure 32 is a plan view showing an example of the planar layout of a memory cell array 503 provided in a memory device 500 according to the third embodiment. Figure 32 shows a region containing one block BLK of the memory region MR. As shown in Figure 32, the memory device 100 includes a plurality of slits SLT, a plurality of slits SHE, a plurality of memory pillars MP, a plurality of bit lines BL, and a plurality of contacts CV. In the memory region MR, the planar layout described below is repeatedly arranged in the Y direction.

[0137] Each slit SLT has a structure in which, for example, an insulating material is embedded. Each slit SLT insulates adjacent wiring (word lines WL0 to WL7, and selection gate lines SGD and SGS) through it. Each slit SLT has a portion that extends along the X direction and crosses the memory area MR and the lead areas HR1 and HR2 along the X direction. Multiple slit SLTs are arranged in the Y direction. The areas separated by the slit SLTs correspond to blocks BLK.

[0138] Each slit SHE has a structure in which, for example, an insulating material is embedded. Each slit SHE insulates adjacent selected gate lines SGD through the slit SHE. Each slit SHE has a portion that extends along the X direction and crosses the memory area MR. Multiple slit SHEs are aligned in the Y direction. In this example, three slit SHEs are positioned between adjacent slits SLT. Multiple regions separated by slits SLT and SHE correspond to string units SU0 to SU3, respectively.

[0139] Each memory pillar MP functions, for example, as a single NAND string NS. Multiple memory pillar MPs are arranged in a staggered pattern, for example, 19 rows, in the region between two adjacent slits SLT. Then, counting from the top of the paper, one slit SHE overlaps each of the 5th, 10th, and 15th memory pillar MPs.

[0140] Each bit line BL has a portion that extends along the Y direction and traverses the region where multiple block BLKs are provided along the Y direction. Multiple bit lines BLs are aligned in the X direction. Each bit line BL is positioned to overlap with at least one memory pillar MP for each string unit SU. In this example, two bit lines BL overlap with each memory pillar MP.

[0141] Each contact CV is placed between one of the multiple bit lines BL that overlap the memory pillar MP and the memory pillar MP in question. The contact CV electrically connects the memory pillar MP and the bit line BL. Note that the contact CV between the memory pillar MP that overlaps with the slit SHE and the bit line BL is omitted.

[0142] (Cross-sectional structure of memory cell array 503) Figure 33 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array 503 provided in a memory device 500 according to the third embodiment. Figure 33 shows a cross-section along the Y direction, including a memory pillar MP and a slit SLT within the memory region MR. As shown in Figure 33, the memory device 500 includes insulating layers 510-518, conductive layers 520-526, and contacts V1 and V2.

[0143] The insulating layer 510 is located, for example, at the bottom layer of the memory chip MC. Wiring used for connecting the conductive layer 520 and the pad PD may be provided on the layer on which the insulating layer 510 is formed. The conductive layer 520 and the insulating layer 511 are provided in order on the insulating layer 510. The conductive layer 521 and the insulating layer 512 are provided alternately on the insulating layer 511. The insulating layer 513 is provided on the uppermost conductive layer 521. The conductive layer 522 and the insulating layer 514 are provided alternately on the insulating layer 513. The insulating layer 515 is provided on the uppermost conductive layer 522. The conductive layer 523 and the insulating layer 516 are provided alternately on the insulating layer 515. The insulating layer 517, the conductive layer 524, and the insulating layer 518 are provided in order on the uppermost conductive layer 523. The insulating layer 518 includes contacts V1 and V2, and conductive layers 525 and 526. Contact V1 connects conductive layer 524 and conductive layer 525. Contact V2 connects conductive layer 525 and conductive layer 526.

[0144] Each of the conductive layers 520, 521, 522, and 523 has, for example, a portion formed in the shape of a plate extending along the XY plane. Conductive layer 524 has, for example, a portion formed in the shape of a line extending in the Y direction. Conductive layers 520, 521, and 523 are used as source line SL, selection gate line SGS, and selection gate line SGD, respectively. Multiple conductive layers 523 are used, in order from bottom to top, as word lines WL0 to WL7, respectively. Conductive layer 524 is used as bit line BL. Conductive layer 526 is used as bonding pad BP of the memory chip MC. Conductive layer 526 contains, for example, copper.

[0145] The slit SLT has a portion that extends along the XZ plane and separates the insulating layers 511-516 and the conductive layers 521-523. Each memory pillar MP is provided extending along the Z direction and penetrates the insulating layers 511-516 and the conductive layers 521-523. Each memory pillar MP includes, for example, a core member 530, a semiconductor layer 531, and a laminated film 532. The core member 530 is an insulator provided extending along the Z direction. The semiconductor layer 531 covers the core member 530. The lower part of the semiconductor layer 531 is in contact with the conductive layer 520. The laminated film 532 covers the side surface of the semiconductor layer 531. A contact CV is provided on the semiconductor layer 531. The semiconductor layer 531 is electrically connected to the conductive layer 524 via the contact CV. Furthermore, the portion where the memory pillar MP intersects with the multiple conductive layers 521 functions as a selection transistor STS. The portion where the memory pillar MP intersects with the conductive layer 522 functions as a memory cell transistor MT. The portion where the memory pillar MP intersects with the multiple conductive layers 523 functions as a selection transistor STD.

[0146] (Cross-sectional structure of memory pillar MP) Figure 34 is a cross-sectional view along the line XXXIV-XXXIV in Figure 33, showing an example of the cross-sectional structure of a memory pillar MP in a memory device 500 according to the third embodiment. Figure 34 shows a cross-section including the memory pillar MP and the conductive layer 522, and parallel to the X and Y directions, respectively. As shown in Figure 34, the laminated film 532 includes a tunnel insulating film 533, an insulating film 534, and a block insulating film 535. The core member 530 is provided in the center of the memory pillar MP. The semiconductor layer 531 surrounds the sides of the core member 530. The tunnel insulating film 533 surrounds the sides of the semiconductor layer 531. The insulating film 534 surrounds the sides of the tunnel insulating film 533. The block insulating film 535 surrounds the sides of the insulating film 534. The conductive layer 522 surrounds the sides of the block insulating film 535. The semiconductor layer 531 is used as the channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors STD and STS. The tunnel insulating film 533 and the block insulating film 535 each contain, for example, silicon dioxide (SiO2). The insulating film 534 is used as a charge storage layer for the memory cell transistor MT and contains, for example, silicon nitride (SiN).

[0147] <3-3-2> Cross-sectional structure of memory device 500 Figure 35 is a cross-sectional view showing an example of the cross-sectional structure of a memory device 500 according to the third embodiment. Figure 35 shows a cross-section including the memory region MR and the sense amplifier region SR, that is, a cross-section including the memory chip MC and the CMOS chip CC. As shown in Figure 35, the memory device 500 includes, for example, a semiconductor substrate 540, conductive layers GC and 541-544, and contacts CS and C0-C3 in the sense amplifier region SR.

[0148] The semiconductor substrate 540 is a substrate used for forming a CMOS chip CC. The semiconductor substrate 540 includes a plurality of well regions (not shown). A transistor TR is formed in each of the plurality of well regions, for example. A conductive layer GC is provided on the semiconductor substrate 540 via a gate insulating film. The conductive layer GC in the sense amplifier region SR is used as the gate electrode of the transistor TR included in the sense amplifier module 506. A contact C0 is provided on the conductive layer GC. Two contacts CS are provided on the semiconductor substrate 540 corresponding to the source and drain of the transistor TR.

[0149] Each contact CS is connected to its corresponding conductive layer 541. Contact C0 is connected to its corresponding conductive layer 541. A conductive layer 541 is connected to the bonding pad BP (conductive layer 544) of the CMOS chip CC via contacts C1, 542, C2, 543, and C3. Conductive layers 544 in the sense amplifier region SR are bonded to conductive layer 526 (i.e., the bonding pad BP of the memory chip MC) in the memory region MR which is located opposite. Each conductive layer 544 in the sense amplifier region SR is electrically connected to a single bit line BL. Conductive layers 544 include, for example, copper. The number of wiring layers in the memory chip MC and CMOS chip CC can be appropriately changed depending on the configuration of the memory device 500.

[0150] <3-4> Effects of the third embodiment As described above, in the memory device 500, the memory chip MC includes a memory cell array 503, and the CMOS chip CC includes a CMOS circuit. For example, the memory chip MC is used as the upper wafer UW in the bonding process, and the CMOS chip CC is used as the lower wafer LW in the bonding process. As mentioned above, the circuit structures formed in the memory chip MC and the CMOS chip are significantly different. In particular, the memory chip MC tends to have a larger XY difference in the wafer magnification component as the memory cell array 503 is formed. Therefore, the yield may decrease due to the influence of the XY difference in the wafer magnification component at the bonding surface between the memory chip MC and the CMOS chip CC.

[0151] Therefore, it is conceivable to apply the bonding method and semiconductor device manufacturing method described in the first and second embodiments to the manufacturing of the memory device 500 according to the third embodiment. In other words, by applying a correction of the XY difference of the wafer magnification component by adjusting the temperature of the lower stage 230 during the bonding process between the memory chip MC and the CMOS chip CC in the memory device 500 according to the third embodiment, the superposition accuracy of the memory chip MC and the CMOS chip CC can be improved. As a result, the yield of the memory device 500 according to the third embodiment can be improved by applying the semiconductor device manufacturing method according to the first or second embodiment.

[0152] It should be noted that the bonding exposure and semiconductor device manufacturing methods described in the first and second embodiments are not limited to the memory device 500. The bonding methods and semiconductor device manufacturing methods described in the first and second embodiments are applicable to any semiconductor device having a bonding structure.

[0153] <4> Variations, etc. In the above embodiment, an example was given in which a heater 44 is provided on the lower stage 230 of the bonding apparatus 2, but the apparatus is not limited thereto. The lower stage 230 only needs to be configured to be temperature-adjustable. The lower stage 230 may also be configured to be adjustable to a temperature lower than the room temperature RT. Even in such a case, the bonding apparatus 2 can correct the XY difference of the wafer magnification component in the lower wafer LW and upper wafer UW to be bonded by adjusting the temperature of the lower stage 230 (main body 40). In the second embodiment, an example was given in which the bonding apparatus 2 performs the process shown in Figure 27, but the apparatus is not limited thereto. The process shown in Figure 27 can be performed by any apparatus that has a temperature-adjustable wafer stage and is capable of alignment measurement. In this case, it is more preferable that the wafer stage of the apparatus that performs the process shown in Figure 27 has the same configuration as the lower stage 230 of the bonding apparatus 2 (stage pins 42, heater 44, etc.).

[0154] The flowcharts used to describe the bonding method and semiconductor device manufacturing method in the above embodiments are merely examples. The order of each operation described using the flowchart may be rearranged as much as possible, other processes may be added, or some processes may be omitted. Instead of a CPU, an MPU (Micro Processing Unit), ASIC (Application Specific Integrated Circuit), or FPGA (field-programmable gate array) may be used as the control devices 10 and 20. Each of the processes described in the above embodiments may be implemented by dedicated hardware. The processes described in the above embodiments may be a mixture of processes executed by software and processes executed by hardware, or may consist of only one or the other.

[0155] The circuit configuration, planar layout, and cross-sectional structure of the memory device 500 described in the third embodiment may be modified as appropriate depending on the design of the memory device 500. For example, the third embodiment illustrates a case where the memory chip MC is provided on a CMOS chip CC, but the CMOS chip CC may be provided on top of the memory chip MC. That is, the CMOS chip CC may be assigned to the upper wafer UW and the memory chip MC may be assigned to the lower wafer LW. In this specification, “connected” means electrically connected and does not exclude the use of another element. “Electrically connected” may be via an insulator, as long as it is possible to operate as if electrically connected.

[0156] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0157] 1... Exposure apparatus, 10... Control device, 11... Memory device, 12... Transport device, 13... Exposure unit, 14... Communication device, 110... Exposure recipe, 111... Correction value information, 130... Wafer stage, 131... Reticle stage, 132... Light source, 133... Projection optical system, 134... Camera, 2... Bonding apparatus, 20... Control device, 21... Memory device, 22... Transport device, 23... Bonding unit, 24... Communication device, 211... Relationship formula, 230... Lower stage, 231... Stress Device, 232...Camera, 233...Upper stage, 234...Pressure pin, 235...Camera, 236,237...Moving mirror, 238,239...Interferometer, 3...Server, 40...Main unit, 41...Rib, 42...Stage pin, 43...Suction port, 44...Heater, 500...Memory device, 501...Memory interface, 502...Programmable logic controller, 503...Memory cell array, 504...Driver module, 505...Raw decoder module, 506... Sense amplifier module, 510-518...insulator layer, 520-526...conductor layer, 530...core component, 531...semiconductor layer, 532...multilayer film, 533...tunnel insulating film, 534...insulating film, 535...block insulating film, 540...semiconductor substrate, GC, 541-544...conductor layer, MP...memory pillar, SLT, SHE...slit, TR...transistor, BLK...block, SU...string unit, NS...NAND string, MT...memory cell transistor, STD, STS...selection transistor, BL...bit line, WL...word line, SGD, SGS...selection gate line, SL...source line, MC...memory chip, CC...CMOS chip, C0-C3, V1, V2, CV...contact, BP...bonding pad, MR...memory area, HR1, HR2...draw-out area, XR1, XR2...transfer area, SR...sense amplifier area, PR1, PR2...pad area, PERI...peripheral circuit area

Claims

1. A first stage comprising a main body, a plurality of stage pins provided on the upper part of the main body, and a heater for heating the main body, wherein each of the plurality of stage pins is configured to hold the first substrate, A second stage configured to hold the second substrate, A processor configured to control the first stage and the second stage to perform a bonding process to bond the first substrate and the second substrate, The first stage, in a plan view, has a central part that includes the center of the first stage and an outer peripheral part located on the outer periphery of the central part. Of the plurality of stage pins, the plurality of first pins arranged in a first direction have at least one of their area and length differ between the first pin located in the center of the first stage and the first pin located in the outer periphery, and of the plurality of second pins arranged in a second direction different from the first direction, the plurality of second pins located in the center of the first stage and the second pin located in the outer periphery have at least one of their area and length being substantially the same. Bonding equipment.

2. The processor is further configured to adjust the heater temperature in the bonding process based on a third difference between a first difference in the magnification components of the first substrate in the first and second directions and a second difference in the magnification components of the second substrate in the first and second directions. The joining device according to claim 1.

3. The first stage is configured such that the ratio of the area of ​​the contact points between the first substrate and the plurality of stage pins decreases in the first direction from the center to the outer periphery of the first stage. The joining device according to claim 1.

4. The first stage is further configured such that the pitch between two adjacent stage pins among the multiple stage pins arranged in the first direction widens from the center of the first stage towards the outer periphery. The joining device according to claim 3.

5. The pitch between two adjacent stage pins among the multiple stage pins arranged in the first direction is in the range of 2000 to 20000 μm. The joining device according to claim 4.

6. The first stage is further configured such that the diameter of the upper surface of each of the multiple stage pins arranged in the first direction decreases from the center of the first stage towards the outer periphery. The joining device according to claim 3.

7. The diameter of each of the multiple stage pins arranged in the first direction is in the range of 100 to 1000 μm. The joining device according to claim 6.

8. The first stage is further configured such that the height of each of the multiple stage pins arranged in the first direction increases from the center of the first stage towards the outer periphery. The joining device according to claim 1.

9. The height of each of the multiple stage pins arranged in the first direction is in the range of 100 to 2000 μm. The joining apparatus according to claim 8.

10. A first measuring instrument capable of measuring a plurality of first alignment marks placed on the first substrate held in the first stage, The system further comprises a second measuring instrument capable of measuring a plurality of second alignment marks placed on the second substrate held in the second stage, The processor is further configured to calculate the first difference based on the measurement results of the plurality of first alignment marks by the first measuring instrument, and to calculate the second difference based on the measurement results of the plurality of second alignment marks by the second measuring instrument. The joining device according to claim 2.

11. The system further comprises a first measuring instrument capable of measuring a plurality of first alignment marks placed on the first substrate held in the first stage, The aforementioned processor further, The combination of adjusting the temperature of the heater and measuring the multiple first alignment marks is performed at multiple temperatures. In relation to each of the aforementioned multiple temperatures, the first difference of the magnification components of the first substrate in the first direction and the second direction is calculated based on the measurement results of the aforementioned multiple first alignment marks. Based on the calculation results of the first difference for each of the aforementioned multiple temperatures, a relationship formula between the first difference and the heater temperature is created. The heater is configured to select the optimal temperature based on the aforementioned relational expression. The joining device according to claim 2.

12. A bonding device comprising a main body, a plurality of stage pins provided on the upper part of the main body, and a heater for heating the main body, wherein the device comprises a first stage configured to hold a first substrate using each of the plurality of stage pins, and a second stage configured to hold a second substrate, wherein the plurality of stage pins arranged in a first direction have at least one of the area and length different at the center and outer periphery of the first stage, and the plurality of stage pins arranged in a second direction different from the first direction have substantially the same area and length at the center and outer periphery of the first stage, and a bonding method using such a bonding device, To calculate the first difference of the magnification components of the first substrate in the first direction and the second direction, To calculate the second difference of the magnification components of the second substrate in the first and second directions, The temperature of the main body is adjusted based on the third difference between the first difference and the second difference, and the first substrate is held in the first stage. The second stage holds the second substrate, The method comprises controlling the first stage and the second stage to bond the first substrate and the second substrate, Joining method.

13. Multiple bonded substrates are created by adjusting the heaters to multiple different temperatures and bonding multiple first substrates to multiple second substrates, respectively. In each of the plurality of bonded substrates, the overlap between the first substrate and the second substrate is measured, and the fourth difference of the magnification component of the bonded substrate in the first direction and the second direction is calculated. Based on the calculation results of the fourth difference for each of the aforementioned multiple temperatures, a relationship formula between the fourth difference and the heater temperature is created. The system further comprises adjusting the temperature of the heater based on the aforementioned relational expression. The joining method according to claim 12.

14. The combination of adjusting the temperature of the heater and measuring the multiple alignment marks placed on the first substrate held in the first stage is performed at multiple temperatures. In accordance with each of the aforementioned multiple temperatures, the first difference of the magnification components of the first substrate in the first and second directions is calculated based on the measurement results of the aforementioned multiple alignment marks, Based on the calculation results of the first difference for each of the aforementioned multiple temperatures, a relationship formula between the first difference and the heater temperature is created. The system further comprises adjusting the temperature of the heater based on the aforementioned relational expression. The joining method according to claim 12.

15. A method for manufacturing a semiconductor device using a bonding apparatus, comprising: a main body; a plurality of stage pins provided on the upper part of the main body; a heater for heating the main body; a first stage configured to hold a first substrate using each of the plurality of stage pins; and a second stage configured to hold a second substrate, wherein, in a plan view, the first stage has a central part including the center of the first stage and an outer peripheral part located on the outer periphery of the central part; and of the plurality of stage pins, a plurality of first pins arranged in a first direction have at least one of the area and length differ between the first pins located in the central part of the first stage and the first pins located in the outer peripheral part; and of the plurality of stage pins, a plurality of second pins arranged in a second direction different from the first direction have substantially the same area and length between the second pins located in the central part of the first stage and the second pins located in the outer peripheral part, To calculate the first difference of the magnification components of the first substrate in the first direction and the second direction, To calculate the second difference of the magnification components of the second substrate in the first and second directions, The heater temperature is adjusted based on the third difference between the first difference and the second difference, and the first substrate is held in the first stage. The second stage holds the second substrate, The method comprises controlling the first stage and the second stage to bond the first substrate and the second substrate, A method for manufacturing a semiconductor device.

16. Multiple bonded substrates are created by adjusting the heaters to multiple different temperatures and bonding multiple first substrates to multiple second substrates, respectively. In each of the plurality of bonded substrates, the overlap between the first substrate and the second substrate is measured, and the fourth difference of the magnification component of the bonded substrate in the first direction and the second direction is calculated. Based on the calculation results of the fourth difference for each of the aforementioned multiple temperatures, a relationship formula between the fourth difference and the heater temperature is created. The system further comprises adjusting the temperature of the heater based on the aforementioned relational expression. The method for manufacturing a semiconductor device according to claim 15.

17. The combination of adjusting the temperature of the heater and measuring the multiple alignment marks placed on the first substrate held in the first stage is performed at multiple temperatures. In accordance with each of the aforementioned multiple temperatures, the first difference of the magnification components of the first substrate in the first and second directions is calculated based on the measurement results of the aforementioned multiple alignment marks, Based on the calculation results of the first difference for each of the aforementioned multiple temperatures, a relationship formula between the first difference and the heater temperature is created. The system further comprises adjusting the temperature of the heater based on the aforementioned relational expression. The method for manufacturing a semiconductor device according to claim 15.

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