Voltage generation circuit, semiconductor memory device

Abstract

To provide a voltage generation circuit capable of improving voltage resistance. [Solution] The voltage generation circuit comprises a variable resistor, a reference resistor, a detection circuit, and a voltage adjustment unit. The variable resistor is connected to the voltage output line. The reference resistor is connected in series with the low-voltage side of the variable resistor. The detection circuit detects the voltage at the first connection point between the variable resistor and the reference resistor. The voltage adjustment unit adjusts the voltage applied to the voltage output line based on the voltage detected by the detection circuit. The variable resistor has a plurality of resistive elements connected in series, a plurality of switching elements provided between the second and first connection points of each of the plurality of resistive elements, and a diode connected in parallel with at least one of the plurality of resistive elements.

Description

Technical Field

[0001] Embodiments relate to a voltage generation circuit and a semiconductor memory device.

Background Art

[0002] A voltage generation circuit used in a semiconductor memory device such as a NAND type flash memory is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] According to the disclosed embodiments, a voltage generation circuit and a semiconductor memory device capable of improving withstand voltage performance are provided.

Means for Solving the Problems

[0005] The voltage generation circuit of the embodiment includes a variable resistor, a reference resistor, a detection circuit, and a voltage adjustment unit. The variable resistor is connected to a voltage output line. The reference resistor is connected in series to the low voltage side of the variable resistor. The detection circuit detects the voltage at a first connection point between the variable resistor and the reference resistor. The voltage adjustment unit adjusts the voltage applied to the voltage output line based on the voltage detected by the detection circuit. The variable resistor has a plurality of resistance elements connected in series, a plurality of switching elements provided between a second connection point and the first connection point of each of the plurality of resistance elements, and a diode connected in parallel to at least one of the plurality of resistance elements.

Brief Description of the Drawings

[0006] [Figure 1] A block diagram showing a schematic configuration of a memory system according to the first embodiment. [Figure 2] A block diagram showing the schematic configuration of a semiconductor memory device according to the first embodiment. [Figure 3] A circuit diagram showing the configuration of a semiconductor memory device according to the first embodiment. [Figure 4] A cross-sectional view showing the cross-sectional structure of the semiconductor memory device according to the first embodiment. [Figure 5] A figure showing an example of the threshold voltage distribution of a memory cell transistor in the first embodiment. [Figure 6] This figure shows the potential change of each wire during the programmed operation of the memory cell transistor in the first embodiment. [Figure 7] This figure shows the potential change of each wire during the read operation of the memory cell transistor in the first embodiment. [Figure 8] A diagram showing the potential change of the word line during the writing operation of the first embodiment. [Figure 9] This figure shows the relationship between the number of loops during the write operation and the verify operation in the first embodiment. [Figure 10] This figure shows the relationship between the number of loops and program operation during the write operation in the first embodiment. [Figure 11] A block diagram showing the schematic configuration of the low decoder of the first embodiment. [Figure 12] A block diagram showing the schematic configuration of the voltage supply circuit of the first embodiment. [Figure 13] A circuit diagram showing the configuration of the first voltage generation unit of the first embodiment. [Figure 14] A circuit diagram showing the configuration of the charge pump circuit of the first embodiment. [Figure 15] A circuit diagram showing the configuration of the detection circuit of the first embodiment. [Figure 16] A circuit diagram showing an example of the operation of the detection circuit of the first embodiment. [Figure 17] A circuit diagram showing the configuration of a sample detection circuit. [Figure 18] A circuit diagram showing the configuration of a detection circuit in a first modified example of the first embodiment. [Figure 19] A circuit diagram showing the configuration of a detection circuit in a second modified example of the first embodiment. [Figure 20] Circuit diagram showing the configuration of the detection circuit according to the third modification of the first embodiment. [Figure 21] Circuit diagram showing the configuration of the detection circuit according to the second embodiment. [Figure 22] Circuit diagram showing the configuration of the detection circuit according to other embodiments. [Figure 23] Circuit diagram showing the configuration of the detection circuit according to other embodiments. [Figure 24] Circuit diagram showing the configuration of the detection circuit according to other embodiments. [Figure 25] Circuit diagram showing the configuration of the detection circuit according to other embodiments. [Figure 26] Cross-sectional view showing the cross-sectional structure of a semiconductor memory device according to other embodiments.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. For ease of understanding the description, the same reference numerals are given to the same components in each drawing as much as possible, and redundant descriptions are omitted.

[0008] 1 First Embodiment The semiconductor memory device according to the first embodiment will be described. The semiconductor memory device according to the present embodiment is a non-volatile memory device configured as a NAND-type flash memory.

[0009] 1.1 Configuration of Memory System First, the configuration of the memory system of the present embodiment will be described.

[0010] As shown in FIG. 1, the memory system 3 of the present embodiment includes a memory controller 1 and a semiconductor memory device 2. The memory system 3 can be connected to a host. The host is an electronic device such as a personal computer or a mobile terminal.

[0011] The memory controller 1 controls the writing of data to the semiconductor storage device 2 in accordance with write requests from the host. The memory controller 1 also controls the reading of data from the semiconductor storage device 2 in accordance with read requests from the host.

[0012] The following signals are transmitted and received between the memory controller 1 and the semiconductor storage device 2: chip enable signal / CE, ready busy signal R / B, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals / RE,RE, write protect signal / WP, signal DQ<7:0>, and data strobe signals DQS, / DQS.

[0013] The chip enable signal / CE is transmitted from the memory controller 1 to the semiconductor memory device 2. The chip enable signal / CE is a signal to enable the semiconductor memory device 2. The ready / busy signal R / B is transmitted from the semiconductor memory device 2 to the memory controller 1. The ready / busy signal R / B is a signal to indicate whether the semiconductor memory device 2 is in a ready state or a busy state. "Ready state" means, for example, a state in which it is ready to accept commands from an external source. "Busy state" means, for example, a state in which it is not ready to accept commands from an external source.

[0014] The command latch enable signal CLE is transmitted from memory controller 1 to semiconductor storage device 2. The command latch enable signal CLE indicates that signal DQ<7:0> is a command. The address latch enable signal ALE is transmitted from memory controller 1 to semiconductor storage device 2. The address latch enable signal ALE indicates that signal DQ<7:0> is an address. The write enable signal / WE is transmitted from memory controller 1 to semiconductor storage device 2. The write enable signal / WE is a signal for inputting the received signal into the semiconductor memory device 2, and is asserted by the memory controller 1 each time it receives a command, address, and data. The memory controller 1 instructs the semiconductor memory device 2 to input the signal DQ<7:0> while the write enable signal / WE is at the "L (Low)" level.

[0015] The read enable signal / RE is transmitted from the memory controller 1 to the semiconductor memory device 2. Signal RE is the complementary signal to signal / RE. The read enable signals / RE and RE are signals for the memory controller 1 to read data from the semiconductor memory device 2. The read enable signals / RE and RE are used to control the operating timing of the semiconductor memory device 2 when, for example, outputting signal DQ<7:0>. Signal DQ<7:0> is the data entity transmitted and received between the semiconductor memory device 2 and the memory controller 1, and includes commands, addresses, and data. The data strobe signal DQS is a timing control signal transmitted and received between the semiconductor memory device 2 and the memory controller 1 in conjunction with signal DQ<7:0>. Signal / DQS is the complementary signal to signal DQS. The data strobe signals DQS and / DQS are signals for controlling the input and output timing of signal DQ<7:0>.

[0016] The memory controller 1 comprises RAM 11, a processor 12, a host interface 13, an ECC circuit 14, and a memory interface 15. These are connected to each other by an internal bus 16.

[0017] The host interface 13 outputs requests and user data (write data), etc., received from the host to the internal bus 16. The host interface 13 also sends user data read from the semiconductor memory device 2 and responses from the processor 12, etc., to the host.

[0018] The memory interface 15 controls the process of writing user data, etc., to the semiconductor storage device 2 and the process of reading data from the semiconductor storage device 2, based on instructions from the processor 12.

[0019] The processor 12 comprehensively controls the memory controller 1. The processor 12 is a CPU, MPU, etc. When the processor 12 receives a request from the host via the host interface 13, it performs control according to that request. For example, the processor 12 instructs the memory interface 15 to write user data and parity to the semiconductor storage device 2 according to a request from the host. The processor 12 also instructs the memory interface 15 to read user data and parity from the semiconductor storage device 2 according to a request from the host.

[0020] The processor 12 determines the storage area (memory area) on the semiconductor memory device 2 for the user data stored in the RAM 11. The user data is stored in the RAM 11 via the internal bus 16. The processor 12 determines the memory area for data in page units (page data), which are the writing units. User data stored in one page of the semiconductor memory device 2 will also be referred to as "unit data" below. Unit data is generally encoded and stored in the semiconductor memory device 2 as a codeword. In this embodiment, encoding is not mandatory. The memory controller 1 may store the unit data in the semiconductor memory device 2 without encoding, but Figure 1 shows a configuration in which encoding is performed as an example.

[0021] The processor 12 determines the memory area of ​​the semiconductor storage device 2 to which each unit data should be written. Each memory area of ​​the semiconductor storage device 2 is assigned a physical address. The processor 12 manages the memory area to which the unit data should be written using the physical address. The processor 12 instructs the memory interface 15 to write the user data to the semiconductor storage device 2 by specifying the determined memory area (physical address). 12 manages the correspondence between the logical address (logical address managed by the host) and the physical address of user data. When processor 12 receives a read request from the host that includes a logical address, it identifies the physical address corresponding to the logical address and instructs the memory interface 15 to read the user data by specifying the physical address.

[0022] The ECC circuit 14 encodes user data stored in the RAM 11 to generate codewords. The ECC circuit 14 also decodes codewords read from the semiconductor memory device 2.

[0023] RAM11 temporarily stores user data received from the host before storing it in the semiconductor memory device 2, and also temporarily stores data read from the semiconductor memory device 2 before sending it to the host. RAM11 is a general-purpose memory such as SRAM or DRAM.

[0024] Figure 1 shows an example configuration in which the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 may be integrated into the memory interface 15. Alternatively, the ECC circuit 14 may be integrated into the semiconductor memory device 2. The specific configuration and arrangement of each element shown in Figure 1 are not particularly limited.

[0025] When a write request is received from the host, the memory system 3 in Figure 1 operates as follows: The processor 12 temporarily stores the data to be written in the RAM 11. The processor 12 reads the data stored in the RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and inputs the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the semiconductor memory device 2.

[0026] When a read request is received from the host, the memory system 3 in Figure 1 operates as follows: The memory interface 15 inputs the codeword read from the semiconductor memory device 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 transmits the data stored in the RAM 11 to the host via the host interface 13.

[0027] 1.2 Schematic Configuration of Semiconductor Memory Devices As shown in Figure 2, the semiconductor memory device 2 includes a memory cell array 21, an input / output circuit 22, a logic control circuit 23, a register 24, a sequencer 25, a voltage supply circuit 26, a row decoder 27, a sense amplifier 28, a group of input / output pads 30, a group of logic control pads 31, and a group of power input terminals 32.

[0028] The memory cell array 21 is the part that stores data. The memory cell array 21 is composed of multiple memory cell transistors associated with multiple bit lines and multiple word lines.

[0029] The input / output circuit 22 transmits and receives signals DQ<7:0> and data strobe signals DQS, / DQS to and from the memory controller 1. The input / output circuit 22 also transfers the command and address within signal DQ<7:0> to register 24. Furthermore, the input / output circuit 22 transmits and receives write data and read data to and from the sense amplifier 28.

[0030] The logic control circuit 23 receives the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals RE, / RE, and write protect signal / WP from the memory controller 1. The logic control circuit 23 also receives the ready busy signal / RB from the memory controller 1. The data is transferred to Troller 1 to notify the external system of the state of semiconductor memory device 2.

[0031] Register 24 temporarily holds various types of data. For example, register 24 holds commands that instruct write, read, and erase operations. These commands are input from the memory controller 1 to the input / output circuit 22, and then transferred from the input / output circuit 22 to register 24 for storage. Register 24 also holds the addresses corresponding to the above commands. These addresses are input from the memory controller 1 to the input / output circuit 22, and then transferred from the input / output circuit 22 to register 24 for storage. Furthermore, register 24 also holds status information indicating the operating state of the semiconductor memory device 2. This status information is updated by the sequencer 25 as needed, according to the operating state of the memory cell array 21, etc. The status information is output to the memory controller 1 from the input / output circuit 22 as a status signal in response to a request from the memory controller 1.

[0032] The sequencer 25 controls the operation of each part, including the memory cell array 21, based on control signals input from the memory controller 1 to the input / output circuit 22 and the logic control circuit 23. In this embodiment, the sequencer 25 is an example of a control unit.

[0033] The voltage supply circuit 26 is the part that generates the voltages necessary for the data writing, reading, and erasing operations in the memory cell array 21. These voltages include, for example, the voltages applied to multiple word lines and multiple bit lines of the memory cell array 21. The operation of the voltage supply circuit 26 is controlled by the sequencer 25.

[0034] The row decoder 27 is a circuit composed of a group of switches for applying voltage to multiple word lines of the memory cell array 21. The row decoder 27 receives a block address and a row address from the register 24, selects a block based on the block address, and selects a word line based on the row address. The row decoder 27 switches the open / closed state of the group of switches so that voltage from the voltage supply circuit 26 is applied to the selected word line. The operation of the row decoder 27 is controlled by the sequencer 25.

[0035] The sense amplifier 28 is a circuit for adjusting the voltage applied to the bit lines of the memory cell array 21 and for reading the voltage from the bit lines and converting it into data. When reading data, the sense amplifier 28 acquires the data read from the memory cell transistors of the memory cell array 21 onto the bit lines and transfers the acquired read data to the input / output circuit 22. When writing data, the sense amplifier 28 transfers the data to be written to the memory cell transistors via the bit lines. The operation of the sense amplifier 28 is controlled by the sequencer 25.

[0036] The input / output pad group 30 is a section provided with multiple terminals (pads) for sending and receiving signals between the memory controller 1 and the input / output circuit 22. Each terminal is individually provided to correspond to the signal DQ<7:0> and the data strobe signals DQS, / DQS, respectively.

[0037] The logic control pad group 31 is a section provided with multiple terminals for sending and receiving signals between the memory controller 1 and the logic control circuit 23. Each terminal is individually provided to correspond to the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals RE, / RE, write protect signal / WP, and ready busy signal / RB.

[0038] The power input terminal group 32 is a section provided with multiple terminals for receiving the voltages necessary for the operation of the semiconductor memory device 2. The voltages applied to each terminal include the power supply voltage Vcc, VccQ, Vpp, and the ground voltage Vss. The power supply voltage Vcc is the circuit power supply voltage supplied externally as the operating power supply, and is, for example, a voltage of about 2.5V. The power supply voltage Vcc is the voltage used to generate the internal power supply voltage Vdd of the semiconductor memory device 2, for example. The power supply voltage Vdd is, for example, a voltage of about 1.5V. The power supply voltage VccQ is a power supply voltage lower than the power supply voltage Vcc, for example, a voltage of 1.2V. The power supply voltage VccQ is the input / output power supply voltage used when sending and receiving signals between the memory controller 1 and the semiconductor memory device 2. The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, for example, a voltage of 12V.

[0039] 1.3 Circuit configuration of memory cell array Next, the configuration of the memory cell array 21 will be described.

[0040] As shown in Figure 3, the memory cell array 21 is composed of multiple block blocks (BLKs). In Figure 3, only one of the block blocks is shown. The configuration of the other block blocks in the memory cell array 21 is the same as that shown in Figure 3.

[0041] As shown in Figure 3, block BLK includes, for example, four string units SU (SU0 to SU3). Each string unit SU also includes multiple NAND strings NS. Each NAND string NS includes, for example, eight memory cell transistors MT (MT0 to MT7) and selection transistors ST1 and ST2.

[0042] The memory cell transistor MT is arranged in series between the selection transistors ST1 and ST2. One end of the memory cell transistor MT7 is connected to the source of the selection transistor ST1, and the other end of the memory cell transistor MT0 is connected to the drain of the selection transistor ST2.

[0043] The gates of the selection transistors ST1 in each of the string units SU0 to SU3 are commonly connected to the select gate lines SGD0 to SGD3, respectively. The gate of the selection transistor ST2 is commonly connected to the same select gate line SGS among multiple string units SU within the same block BLK. The gates of the memory cell transistors MT0 to MT7 within the same block BLK are commonly connected to the word lines WL0 to WL7, respectively. In other words, the word lines WL0 to WL7 and the select gate line SGS are common among multiple string units SU0 to SU3 within the same block BLK, whereas the select gate line SGD is provided individually for each string unit SU0 to SU3, even within the same block BLK.

[0044] The memory cell array 21 is provided with m bit lines BL(BL0, BL1, ..., BL(m-1)). "m" is an integer corresponding to the number of NAND strings NS contained in one string unit SU. The drain of each selection transistor ST1 of the NAND string NS is connected to the corresponding bit line BL. The source of each selection transistor ST2 of the NAND string NS is connected to the source line SL. The source line SL is common to the sources of multiple selection transistors ST2 in block BLK.

[0045] Data stored in multiple memory cell transistors MT within the same block BLK is erased collectively. On the other hand, data reading and writing are performed collectively on multiple memory cell transistors MT connected to a single word line WL and belonging to a single string unit SU.

[0046] Each memory cell transistor MT can hold 3 bits of data consisting of a high-order bit, a middle-order bit, and a low-order bit. In other words, the semiconductor memory device 2 according to this embodiment employs a TLC method as the method for writing data to the memory cell transistors MT, which allows 3 bits of data to be stored in one memory cell transistor MT. Alternatively, the method for writing data to the memory cell transistors MT may be an MLC method that stores 2 bits of data in one memory cell transistor MT, or an SLC method that stores 1 bit of data in one memory cell transistor MT, etc.

[0047] In the following explanation, a "page" refers to a set of 1-bit data stored by multiple memory cell transistors MT connected to a single word line WL and belonging to a single string unit SU. In Figure 3, one of the sets of multiple memory cell transistors MT described above is denoted with the code "MG".

[0048] As in this embodiment, when 3 bits of data are stored in one memory cell transistor MT, a set of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU can store 3 pages of data.

[0049] 1.4 Cross-sectional structure of semiconductor memory devices Next, the structure of the memory cell array 21 and its surrounding area will be described.

[0050] As shown in Figure 4, in the memory cell array 21, multiple NAND strings NS are formed on the conductive layer 320. The conductive layer 320 is also called the embedded source line (BSL) and corresponds to the source line SL shown in Figure 3.

[0051] Above the conductive layer 320, multiple wiring layers 333 functioning as select gate lines (SGS), multiple wiring layers 332 functioning as word lines (WL), and multiple wiring layers 331 functioning as select gate lines (SGD) are stacked. An insulating layer (not shown) is placed between each of the stacked wiring layers 333, 332, and 331.

[0052] Multiple memory holes 334 are formed in the memory cell array 21. The memory holes 334 penetrate vertically through the wiring layers 333, 332, 331 and the insulating layer (not shown) between them, and reach the conductive layer 320. Block insulating film 335, charge storage layer 336, and gate insulating film 337 are sequentially formed on the side surface of the memory hole 334, and a conductive column 338 is embedded further inside. The conductive column 338 is made of polysilicon, for example, and functions as a region where a channel is formed when the memory cell transistor MT and selection transistors ST1, ST2 included in the NAND string NS are in operation. Hereinafter, the columnar body formed by the block insulating film 335, charge storage layer 336, gate insulating film 337, and conductive column 338 inside the memory hole 334 will also be referred to as a memory pillar MP.

[0053] Of the memory pillar MP, each portion that intersects with the stacked wiring layers 333, 332, and 331 functions as a transistor. Of these multiple transistors, the portion that intersects with wiring layer 331 functions as a selection transistor ST1. Of these multiple transistors, the portions that intersect with wiring layer 332 function as memory cell transistors MT (MT0 to MT7). Of these multiple transistors, the portion that intersects with wiring layer 333 functions as a selection transistor ST2. With this configuration, the memory pillar MP functions as a NAND string NS as shown in Figure 3. The conductive pillar 338 inside the memory pillar MP functions as a selection transistor for memory cell transistors MT and selection transistors. This is the part that functions as the channel for selector transistors ST1 and ST2.

[0054] Above the conductive column 338, a wiring layer that functions as a bit line BL is formed. At the upper end of the conductive column 338, a contact plug 339 is formed to connect the conductive column 338 and the bit line BL.

[0055] Multiple configurations similar to the one shown in Figure 4 are arranged along the depth direction of the page in Figure 4. A single string unit SU is formed by a collection of multiple NAND strings NS arranged in a line along the depth direction of the page in Figure 4.

[0056] In the semiconductor memory device 2 of this embodiment, a peripheral circuit PER is provided below the memory cell array 21, that is, at a position between the memory cell array 21 and the semiconductor substrate 300. The peripheral circuit PER is a circuit provided to realize data writing, reading, and erasing operations in the memory cell array 21. The sense amplifier 28, row decoder 27, and voltage supply circuit 26 shown in Figure 2 are part of the peripheral circuit PER. The peripheral circuit PER includes various transistors and RC circuits. In the example shown in Figure 4, a transistor TR formed on the semiconductor substrate 300 and a bit line BL located above the memory cell array 21 are electrically connected via a contact 924.

[0057] 1.5 Threshold voltage distribution of memory cell transistors Next, we will explain the threshold voltage distribution of memory cell transistors (MTs). Figure 5 is a schematic diagram showing the threshold voltage distribution of memory cell transistors (MTs). The diagram in the middle of Figure 5 shows the correspondence between the threshold voltage of a memory cell transistor (horizontal axis) and the number of memory cell transistors (vertical axis).

[0058] In the case where the TLC method is adopted as in this embodiment, the multiple memory cell transistors MT form eight threshold voltage distributions, as shown in the middle section of Figure 5. These eight threshold voltage distributions (write levels) are referred to as "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, in order from the lowest threshold voltage.

[0059] The table in the upper part of Figure 5 shows examples of data assigned to each of the threshold voltage levels mentioned above. As shown in the table, each level is assigned different 3-bit data, such as shown below.

[0060] "ER" level: "111" ("Lower bit / Middle bit / Upper bit") "A" Level: "011" "B" Level: "001" "C" level: "000" "D" Level: "010" "E" level: "110" "F" level: "100" "G" level: "101" Thus, the threshold voltage of the memory cell transistor MT in this embodiment can take one of eight preset candidate levels, and data is assigned to each candidate level as described above.

[0061] Between pairs of adjacent threshold voltage distributions, a verify voltage used in the write operation is set. Specifically, the verify voltage corresponds to multiple levels. Pressures VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set.

[0062] The verify voltage VfyA is set between the maximum threshold voltage at the "ER" level and the minimum threshold voltage at the "A" level. When the verify voltage VfyA is applied to the word line WL, memory cell transistors MT connected to the word line WL whose threshold voltage is included in the "ER" level turn ON, and memory cell transistors MT whose threshold voltage is included in the threshold voltage distribution of "A" level or higher turn OFF.

[0063] Other verify voltages VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set in the same way as the verify voltage VfyA described above. The verify voltage VfyB is set between the "A" level and the "B" level, the verify voltage VfyC is set between the "B" level and the "C" level, the verify voltage VfyD is set between the "C" level and the "D" level, the verify voltage VfyE is set between the "D" level and the "E" level, the verify voltage VfyF is set between the "E" level and the "F" level, and the verify voltage VfyG is set between the "F" level and the "G" level.

[0064] For example, the verify voltages VfyA, VfyB, VfyC, VfyC, VfyF, and VfyG may be set to 0.8V, VfyB, VfyE, VfyF, VfyG, and VfyG, respectively. However, the system is not limited to these values, and each of the verify voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG may be set in steps as appropriate, for example, within the range of 0V to 7.0V.

[0065] Furthermore, a read voltage used in the read operation is set between adjacent threshold voltage distributions. The "read voltage" is the voltage applied to the word line WL connected to the memory cell transistor MT to be read, i.e., the selected word line, during the read operation. In the read operation, the data is determined based on whether or not the threshold voltage of the memory cell transistor MT to be read is higher than the applied read voltage.

[0066] As schematically shown in the lower part of Figure 5, the read voltage VrA, which determines whether the threshold voltage of the memory cell transistor MT falls within the "ER" level or above the "A" level, is set between the maximum threshold voltage at the "ER" level and the minimum threshold voltage at the "A" level.

[0067] Other read voltages VrB, VrC, VrD, VrE, VrF, and VrG are set in the same way as read voltage VrA above. Read voltage VrB is set between level "A" and level "B", read voltage VrC is set between level "B" and level "C", read voltage VrD is set between level "C" and level "D", read voltage VrE is set between level "D" and level "E", read voltage VrF is set between level "E" and level "F", and read voltage VrG is set between level "F" and level "G".

[0068] Then, the read path voltage VPASS_READ is set to a voltage higher than the maximum threshold voltage of the highest threshold voltage distribution (for example, the "G" level). When the read path voltage VPASS_READ is applied to the gate of a memory cell transistor MT, it turns ON regardless of the data to be stored.

[0069] Furthermore, the verify voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set to higher voltages than, for example, the read voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG. In other words, the verify voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set near the lower tail of the threshold voltage distributions for the "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, respectively.

[0070] When the data allocation described above is applied, the lower-order bit page data (lower page data) can be determined in the read operation by the read results using read voltages VrA and VrE. The middle-order bit page data (middle page data) can be determined by the read results using read voltages VrB, VrD, and VrF. The upper-order bit page data (upper page data) can be determined by the read results using read voltages VrC and VrG. Thus, since the lower-order, middle-order, and upper-order page data are determined by 2, 3, and 2 read operations, respectively, this type of data allocation is called a "2-3-2 code".

[0071] 1.6 Potential changes in each wiring during the writing operation of semiconductor memory devices Next, the writing operation of the semiconductor memory device 2 will be explained. The writing operation involves a program operation and a verify operation. The "program operation" is an operation that changes the threshold voltage of some memory cell transistors MT by injecting electrons into the charge storage layer 336 of those memory cell transistors MT. The "verification operation" is an operation that, after the above program operation, reads the data to determine and verify whether the threshold voltage of the memory cell transistors MT has reached the target level. Memory cell transistors MT whose threshold voltage has reached the target level are then disabled for writing. The "target level" here refers to a specific candidate level set as the target level from among the eight candidate levels mentioned earlier.

[0072] During the write operation, the above program and verification operations are repeatedly performed. This causes the threshold voltage of the memory cell transistor MT to rise to the target level.

[0073] Among the multiple word lines WL, the word line WL connected to the memory cell transistor MT that is the target of the write operation (i.e., the target whose threshold voltage is changed) will be referred to as the "selected word line" below. Similarly, the word line WL connected to the memory cell transistor MT that is not the target of the write operation will be referred to as the "unselected word line" below. The memory cell transistor MT that is the target of the write operation will also be referred to as the "selected memory transistor" below.

[0074] Among multiple string units SU, the string unit SU that is the target of the write operation will be referred to as the "selected string unit" below. Conversely, the string unit SU that is not the target of the write operation will be referred to as the "unselected string unit" below.

[0075] In the following, the conductive column 338 of each NAND string NS included in the selection string unit, that is, each channel in the selection string unit, will also be referred to as the "selection channel." Similarly, the conductive column 338 of each NAND string NS included in the non-selection string unit, that is, each channel in the non-selection string unit, will also be referred to as the "non-selection channel."

[0076] Of the multiple bit lines BL, the bit line BL connected to the selected memory transistor... These will also be referred to as "selection bit lines" below. Furthermore, bit lines BL that are not connected to selection memory transistors will also be referred to as "non-selection bit lines" below.

[0077] Figure 6 shows the potential changes of each wire during program operation. During program operation, the sense amplifier 28 changes the potential of each bit line BL in accordance with the program data. For bit lines BL connected to memory cell transistors MT that are the target of the program (where the threshold voltage should be increased), an "L" level voltage, such as the ground voltage Vss (0V), is applied. For bit lines BL connected to memory cell transistors MT that are not the target of the program (where the threshold voltage should be maintained), an "H" level voltage, such as 2.5V, is applied. The former bit line BL is labeled "BL(0)" in Figure 6. The latter bit line BL is labeled "BL(1)" in Figure 6.

[0078] The row decoder 27 selects one of the blocks BLK as the target for the writing operation, and then selects one of the string units SU. More specifically, a voltage of, for example, 5V is applied from the voltage supply circuit 26 to the select gate line SGD (selection select gate line SGDsel) of the selected string unit SU via the row decoder 27. This turns on the selection transistor ST1. On the other hand, a voltage of, for example, Vss is applied to the select gate line SGS from the voltage supply circuit 26 to the row decoder 27. This turns off the selection transistor ST2.

[0079] Furthermore, a voltage of, for example, 5V is applied from the voltage supply circuit 26 to the select gate line SGD (non-select select gate line SGDusel) of the non-select string unit SU in the selection block BLK via the low decoder 27. This turns on the selection transistor ST1. Note that the select gate line SGS is commonly connected in the string unit SU included in each block BLK. Therefore, the selection transistor ST2 is also in the off state in the non-select string unit SU.

[0080] The source line SL is set to a higher potential than the select gate line SGS. This potential is, for example, 1V.

[0081] Next, the potential of the selection gate line SGDsel in the selection block BLK is set to, for example, 2.5V. This potential turns on the selection transistor ST1 corresponding to bit line BL(0) which is given 0V in the above example, but cuts off the selection transistor ST1 corresponding to bit line BL(1) which is given 2.5V. As a result, in the selection string unit SU, the selection transistor ST1 corresponding to bit line BL(0) is turned on, and the selection transistor ST1 corresponding to bit line BL(1) which is given 2.5V is cut off. On the other hand, the potential of the non-selection gate line SGDusel is set to, for example, voltage Vss. As a result, in the non-selection string unit SU, the selection transistor ST1 is cut off regardless of the potentials of bit line BL(0) and bit line BL(1).

[0082] The row decoder 27 then selects one of the word lines WL as the target for the write operation in the selection block BLK. The program voltage VPGM is applied to the word line WL that is the target of the write operation (selected word line WLsel) from the voltage supply circuit 26 via the row decoder 27. On the other hand, the program path voltage VPASS_PGM is applied to the other word lines WL (unselected word line WLusel) from the voltage supply circuit 26 via the row decoder 27. The program voltage VPGM is a high voltage for injecting electrons into the charge storage layer 336 by tunneling. The program path voltage VPASS_PGM is a voltage that turns on the memory cell transistor MT connected to the word line WL, but does not change the threshold voltage. VPGM is a higher voltage than VPASS_PGM.

[0083] In the NAND string NS corresponding to the programmable bit line BL(0), the selection transistor ST1 is turned ON. As a result, the channel potential of the memory cell transistor MT connected to the selection word line WLsel becomes 0V. The potential difference between the control gate and the channel increases, and as a result, electrons are injected into the charge storage layer 336, causing the threshold voltage of the memory cell transistor MT to rise.

[0084] In the NAND string NS corresponding to the bit line BL(1), which is not programmed, the selection transistor ST1 is cut off. As a result, the channel of the memory cell transistor MT connected to the selection word line WLsel becomes electrically floating, and the channel potential is raised to near the program voltage VPGM due to capacitive coupling with the word line WL, etc. The potential difference between the control gate and the channel becomes small, and as a result, electrons are not injected into the charge storage layer 336, so the threshold voltage of the memory cell transistor MT is maintained. More precisely, the threshold voltage does not fluctuate to the extent that the threshold voltage distribution level transitions to a higher distribution.

[0085] In addition, the so-called pre-charge operation, which involves applying a 5V voltage to the select gate line SGDsel and the deselect gate line SGDusel during the initial stages of program operation, may be omitted.

[0086] The verification operation that follows the program execution is identical to the read operation described below, so its explanation will be omitted.

[0087] 1.7 Potential changes in each wiring during read operation of semiconductor memory device Next, the read operation of the semiconductor memory device 2 will be described. Figure 7 shows the potential change of each wiring during the read operation. In the read operation, the NAND string NS containing the memory cell transistor MT to be read is selected. Alternatively, the string unit SU containing the page to be read is selected.

[0088] First, a voltage of, for example, 5V is applied to the select gate line SGDsel, the non-select select gate line SGDusel, and the select gate line SGS from the voltage supply circuit 26 via the row decoder 27. This turns on the select transistors ST1 and ST2 included in the select block BLK. In addition, a read path voltage, for example, VPASS_READ, is applied to the select word line WLsel and the non-select word line WLusel from the voltage supply circuit 26 via the row decoder 27. The read path voltage VPASS_READ is a voltage that can turn on the memory cell transistor MT regardless of the threshold voltage of the memory cell transistor MT, and does not change the threshold voltage. As a result, current conducts in all NAND strings NS included in the select block BLK, regardless of whether they are select string units SU or non-select string units SU.

[0089] Next, a read voltage VCGRV, such as VrA, is applied from the voltage supply circuit 26 to the word line WL (selected word line WLsel) connected to the memory cell transistor MT that is the target of the read operation, via the row decoder 27. For the other word lines (non-selected word lines WLusel), the read path voltage VPASS_READ is applied.

[0090] Furthermore, while maintaining the voltage applied to the select gate line SGDsel and the select gate line SGS, a voltage Vss is applied to the non-select select gate line SGDusel from the voltage supply circuit 26 via the low decoder 27. This allows the select string unit to function as intended. The selection transistor ST1 included in the string unit SU remains in the ON state, while the selection transistor ST1 included in the non-selected string unit SU remains in the OFF state. Regardless of whether it is a selection string unit SU or a non-selected string unit SU, the selection transistor ST2 included in the selection block BLK remains in the ON state.

[0091] As a result, the NAND string NS included in the non-selected string unit SU does not form a current path because at least the selection transistor ST1 is in the off state. On the other hand, the NAND string NS included in the selected string unit SU forms or does not form a current path depending on the relationship between the read voltage VCGRV applied to the selected word line WLsel and the threshold voltage of the memory cell transistor MT.

[0092] The sense amplifier 28 applies a voltage to the bit line BL connected to the selected NAND string NS. In this state, the sense amplifier 28 reads data based on the value of the current flowing through the bit line BL. Specifically, it determines whether the threshold voltage of the memory cell transistor MT that is the target of the read operation is higher than the read voltage applied to the memory cell transistor MT. Note that data reading may be performed based on the time change of the potential in the bit line BL, rather than based on the value of the current flowing through the bit line BL. In the latter case, the bit line BL is pre-charged to a predetermined potential.

[0093] The verification operation described above is performed in the same way as the read operation described above. In the verification operation, a verification voltage, such as VfyA, is applied from the voltage supply circuit 26 to the word line WL connected to the memory cell transistor MT to be verified, via the row decoder 27.

[0094] Note that the operation of applying a 5V voltage to the non-selected select gate line SGDusel and the read path voltage VPASS_READ to the selected word line WLsel during the initial stage of the read operation (verification operation) may be omitted.

[0095] 1.8 Flow of writing operations for semiconductor memory devices Next, we will explain the specific flow of the entire write operation. In the write operation, the program operation and verification operation described above are repeated until it is confirmed that the data has been written correctly. Figure 8 shows an example where the combination of program operation and verification operation is repeated 19 times to write the data. Each of these repeated operations will be referred to as a "loop" below.

[0096] Figure 8 shows an example of the potential change of the selected word line WLsel during a write operation. As shown in the figure, the above loop is executed up to 19 times. In Figure 8, "VPGM1" refers to the VPGM applied to the selected word line WLsel in the first loop. "VPGM2" refers to the VPGM applied to the selected word line WLsel in the second loop. Similarly, the VPGM applied to the selected word line WLsel in each loop is labeled "VPGM3", "VPGM4", ..., "VPGM19" in Figure 8. As shown in the figure, with each repetition of the loop, the value of the VPGM is gradually increased in steps.

[0097] Figure 9 shows the target level of the verification operation performed in each loop. Figure 10 shows the target level of the program operation performed in each loop. In Figure 10, "1" means that no write operation is performed at that level, and "0" means that a write operation is performed at that level. Also, "0 / 1" means that the write operation at that level is basically... The write operation will proceed, but if the verification was passed during the previous write operation, the write operation will not be performed.

[0098] As shown in Figures 8, 9, and 10, in the first loop in these examples, after VPGM1 is applied to the selected word line WLsel during program operation, the verification operation is performed only on the "A" level. That is, during the verification operation, the verification voltage VfyA is applied to the selected word line WLsel, and the verification voltages VfyB to VfyG are not applied.

[0099] In the first loop, the memory cell transistors (MTs) that are programmed are all memory cell transistors (MTs) whose threshold voltage should ultimately be at or above level "A". On the other hand, in the first loop, the memory cell transistors (MTs) that are verified at level "A" are those whose threshold voltage ultimately becomes at level "A". Memory cell transistors (MTs) whose threshold voltage ultimately becomes at or above level "B" are excluded from verification at level "A".

[0100] In the second loop, after VPGM2 is applied to the selected word line WLsel, the same programming and verification operations as in the first loop are performed. However, memory cell transistors MT whose threshold voltage ultimately reaches level "A" that passed verification at level "A" in the first loop are excluded from the programming and verification operations in the second loop. In other words, in the second loop, memory cell transistors MT whose threshold voltage ultimately reaches level "B" or higher, and memory cell transistors MT that failed verification in the previous loop, are the targets of the programming operation.

[0101] In the third loop, VPGM3 is applied to the selected word line WLsel and the program operation is performed, after which the verification operation is performed on the "A" level and the "B" level. In other words, during the verification operation, the verification voltages VfyA and VfyB are sequentially applied to the selected word line WLsel, while the verification voltages VfyC to VfyG are not applied.

[0102] In the third loop, the memory cell transistors (MTs) that are programmed are all memory cell transistors (MTs) whose threshold voltage should ultimately be at or above level "B", and memory cell transistors (MTs) that failed to verify in the previous loops. In the third loop, the memory cell transistors (MTs) that are verified at level "A" are those memory cell transistors (MTs) whose threshold voltage ultimately reaches level "A", and which failed to verify in the previous loops. In the third loop, the memory cell transistors (MTs) that are verified at level "B" are those memory cell transistors (MTs) whose threshold voltage ultimately reaches level "B".

[0103] In the fourth loop, after VPGM4 is applied to the selected word line WLsel, the same programming and verification operations as in the third loop are performed. However, among the memory cell transistors MT whose threshold voltage ultimately reaches level "A", those that passed the "A" level verification in the third loop are excluded from the programming and verification operations in the second loop. Similarly, those that passed the "B" level verification in the third loop are excluded from the programming and verification operations in the fourth loop. In other words, in the fourth loop, memory cell transistors MT whose threshold voltage ultimately reaches level "C" or higher, and memory cell transistors MT that failed verification in the previous loop, are the targets of the programming operation.

[0104] Similarly, in subsequent loops, after the program execution, each predetermined loop as shown in Figure 8 Bell's verification operation is performed. Memory cell transistors MT whose threshold voltage has reached the final target level are excluded from program operation and verification operation in subsequent loops.

[0105] As the loop repeats, the number of memory cell transistors MT whose threshold voltage reaches the final target level increases, and consequently, the number of memory cell transistors MT excluded from program operation and verification operation gradually increases. This is also reflected in Figure 10, where the number of levels labeled "1" increases and the number of levels labeled "0" decreases as the number of loop iterations increases.

[0106] In the example shown in Figure 9, the verification operation targeting level "A" is completed in the 6th loop. This is because, for example, from the previously obtained characteristics of the memory cell array 21, it is known that the writing of data to level "A" is almost completed after a total of 6 loops. Similarly, in the example shown in Figure 9, the verification operation targeting level "B" is completed in the 8th loop. This is because it is known that the writing of data to level "B" is almost completed after a total of 6 loops, from the 3rd to the 8th.

[0107] 1.9 Raw Decoder Configuration Next, we will describe the general configuration of the low decoder 27.

[0108] Figure 11 is a block diagram showing an example of the connection between the row decoder 27 and the memory cell array 21. The voltage supply circuit 26 generates various voltages, including the voltages necessary for program operation and read operation of the memory cell transistor MT. The voltage supply circuit 26 supplies voltage to signal lines SG0~SG4 and CG0~CG7, respectively. These signal lines SG0~SG4 and CG0~CG7 are branched by the row decoder 27 and connected to the wiring of each physical block BLK. Specifically, signal lines SG0~SG3 function as global select gate lines and are connected to select gate lines SGD0~SGD3 as local select gate lines in each physical block BLK via the row decoder 27. Signal lines CG0~CG7 function as global word lines and are connected to word lines WL0~WL7 as local word lines in each physical block BLK via the row decoder 27. Signal line SG4 functions as a global select gate line and is connected to select gate line SGS as a local select gate line in each physical block BLK via the row decoder 27.

[0109] The row decoder 27 has a plurality of switch circuit groups 27A corresponding to each block BLK, and a plurality of block decoders 27B provided corresponding to each of the plurality of switch circuit groups 27A.

[0110] Each switch circuit group 27A includes multiple transistors TR_SG0 to TR_SG4 provided between signal lines SG0 to SG4 and select gate lines SGD0 to SGD4. Furthermore, each switch circuit group 27A includes multiple transistors TR_CG0 to TR_CG7 provided between signal lines CG0 to CG7 and word lines WL0 to WL7. Each of the transistors TR_SG0 to TR_SG4 and TR_CG0 to TR_CG7 is a high-voltage transistor.

[0111] Each block decoder 27B, if it is designated by a row address, supplies a block selection signal BLKSEL at the "H" level to the switch circuit group 27A. The block selection signal BLKSEL is a signal where the "H" level indicates the voltage VPGMH and the "L" level indicates the voltage Vss. The voltage VPGMH is a voltage greater than the program voltage VPGM. For example, if the program voltage VPGM is 20V, the voltage VPGMH is set to 25V. Hereafter, the voltage VPGMH will also be referred to as the "block selection voltage VPGMH". When a "H" level block selection signal BLKSEL is supplied to the gates of transistors TR_SG0~TR_SG4 and TR_CG0~TR_CG7 included in the switch circuit group 27A, those transistors TR_SG0~TR_SG4 and TR_CG0~TR_CG7 turn on and conduct. Therefore, the voltage generated by the voltage supply circuit 26 is supplied to the select gate lines SGD0~SGD3, SGS and word lines WL0~WL7 included in the block BLK to be operated, via the signal lines SG0~SG4 and CG0~CG7.

[0112] On the other hand, each block decoder 27B, if it is not designated by a low address, supplies an "L" level block selection signal BLKSEL to the switch circuit group 27A. As a result, the "L" level block selection signal BLKSEL is supplied to the gates of transistors TR_SG0~TR_SG4 and TR_CG0~TR_CG7 included in the switch circuit group 27A, causing these transistors TR_SG0~TR_SG4 and TR_CG0~TR_CG7 to turn off and become non-conductive. Therefore, the voltage generated by the voltage supply circuit 26 is not supplied to the select gate lines SGD0~SGD3, SGS and word lines WL0~WL7 included in the non-operating block BLK.

[0113] 1.10 Configuration of the Voltage Generation Circuit Next, the general configuration of the voltage supply circuit 26 will be described.

[0114] Figure 12 is a block diagram showing the internal configuration of the voltage supply circuit 26. As shown in Figure 12, the voltage supply circuit 26 comprises a voltage generation circuit 260 and a multiplexer 261. Note that Figure 12 only shows the configuration in which voltage is applied to signal lines CG0 to CG7 in the voltage supply circuit 26, and the configuration for applying voltage to the other signal lines SG0 to SG4 is omitted.

[0115] The voltage generation circuit 260 includes a first voltage generation unit 260a, a second voltage generation unit 260b, and a third voltage generation unit 260c. The first voltage generation unit 260a generates the program voltage VPGM and the block selection voltage VPGMH, which are applied to the selected word line WLsel during a write operation. The first voltage generation unit 260a is connected to an output node NLa that outputs the program voltage VPGM and an output node NHa that outputs the block selection voltage VPGMH. The second voltage generation unit 260b generates the program path voltage VPASS_PGM, which is applied to the unselected word line WLusel during a write operation, and the voltage VPASS_READ, which is applied to the unselected word line WLusel during a read operation. The second voltage generation unit 260b is connected to an output node NLb that outputs the program path voltage VPASS_PGM or the voltage VPASS_READ. The third voltage generation unit 260c generates the read voltage VCGRV, which is applied to the selected word line WLsel during a read operation. The third voltage generation unit 260c is connected to the output node NLc, which outputs the read voltage VCGRV.

[0116] Within the multiplexer 261, the output node NLa of the first voltage generation unit 260a is connected to signal lines CG0 to CG7 via multiple signal lines SVA0 to SVA7. Although not shown in the diagram, the output node NHa of the first voltage generation unit 260a is connected to each block decoder 27B of the row decoder 27. Furthermore, the output node NLb of the second voltage generation unit 260b is connected to signal lines CG0 to CG7 via multiple signal lines SVB0 to SVB7. In addition, the output node NLc of the third voltage generation unit 260c is connected to signal lines CG0 to CG7 via multiple signal lines SVC0 to SVC7.

[0117] Multiplexer 261 uses transistors TR_SVA0~TR_SVA7, TR_SV It has transistors B0~TR_SVB7 and TR_SVC0~TR_SVC7. Transistors TR_SVA0~TR_SVA7 are provided in the middle of multiple signal lines SVA0~SVA7, respectively. Transistors TR_SVB0~TR_SVB7 are provided in the middle of multiple signal lines SVB0~SVB7, respectively. Transistors TR_SVC0~TR_SVC7 are provided in the middle of multiple signal lines SVC0~SVC7, respectively. The operation of each of the transistors TR_SVA0~TR_SVA7, TR_SVB0~TR_SVB7, and TR_SVC0~TR_SVC7 is controlled by the sequencer 25.

[0118] The multiplexer 261 selectively applies the voltages generated by the voltage generation units 260a, 260b, and 260c to the signal lines CG0 to CG7 by switching the on / off states of the transistors TR_SVA0 to TR_SVA7, TR_SVB0 to TR_SVB7, and TR_SVC0 to TR_SVC7, respectively.

[0119] For example, when word line WL7 is set to selected word line WLsel during a write operation, the multiplexer 261 first turns on transistors TR_SVB0 to TR_SVB7 and turns off the other transistors TR_SVA0 to TR_SVA7 and TR_SVC0 to TR_SVC7, thereby supplying the program path voltage VPASS_PGM to each word line WL0 to WL7 via signal lines CG0 to CG7 from the second voltage generation unit 260b. Subsequently, when it is time to boost the voltage from the program path voltage VPASS_PGM to the program voltage VPGM, the transistor TR_SVB7 corresponding to word line WL7, which is the selected word line WLsel, is turned off and transistor TR_SVA7 is turned on, thereby boosting the voltage of word line WL7 from the program path voltage VPASS_PGM to the program voltage VPGM.

[0120] On the other hand, the first voltage generation unit 260a of this embodiment generates a preparation voltage VPGM_prep that is higher than the program path voltage VPASS_PGM before the transistor TR_SVA7 is turned on. When the transistor TR_SVA7 is turned on, the first voltage generation unit 260a outputs the preparation voltage VPGM_prep, as shown by the dashed line in Figure 6, and then outputs the program voltage VPGM. This makes it possible to smoothly boost the voltage of the word line WL7, which is the selected word line WLsel, from the program path voltage VPASS_PGM to the program voltage VPGM.

[0121] Furthermore, when word line WL7 is set to the selected word line WLsel during a read operation, the multiplexer 261 applies the read voltage VCGRV to the signal line CG7 connected to the selected word line WL7 by turning on transistor TR_SVC7 and turning off transistors TR_SVA7 and TR_SVB7. In addition, the multiplexer 261 applies the read path voltage VPASS_READ to the other signal lines CG0 to CG6 connected to the unselected word lines WL0 to WL6 by turning on transistors TR_SVB0 to TR_SVB6 and turning off transistors TR_SVA0 to TR_SVA6 and TR_SVC0 to TR_SVC6.

[0122] 1.11 Configuration of the Voltage Generation Unit Next, the general configuration of the first voltage generation unit 260a will be described.

[0123] Figure 13 is a schematic circuit diagram showing the circuit configuration of the first voltage generation unit 260a. As shown in Figure 13, the first voltage generation unit 260a includes a charge pump circuit 40, a potential difference generation circuit 41, and a detection circuit 42.

[0124] Figure 14 is a circuit diagram showing an example of the circuit configuration of the charge pump circuit 40. As shown in Figure 14, the charge pump circuit 40 consists of a clock control circuit 400 and an NMOS transistor. It has staves NTc(1) to NTc(n+1) and capacitors C(1) to C(n). Note that n is an arbitrary integer.

[0125] The clock control circuit 400 generates clock signals CLK and / CLK. The clock signal / CLK is the inverted signal of the clock signal CLK. The clock control circuit 400 supplies complementary clock signals CLK and / CLK to the charge pump circuit 40. The charge pump circuit 40 generates a block selection voltage VPGMH using the clock signals CLK and / CLK supplied from the clock control circuit 400.

[0126] The NMOS transistors NTc(1) to NTc(n+1) each function as diodes by being connected in a diode configuration, that is, by electrically connecting their drains and gates. The current paths of the NMOS transistors NTc(1) to NTc(n+1) are connected in series in the forward direction.

[0127] One end of each capacitor C(1) to C(n) is electrically connected to one end of the output side of the current path of the NMOS transistors NTc(1) to NTc(n). The other end of capacitors C1, C3, C5, ... is supplied with the clock signal CLK, and the other end of capacitors C2, C4, C6, ... is supplied with the clock signal / CLK.

[0128] A voltage VSUP (e.g., the power supply voltage Vdd) is supplied to one end of the current path input of the NMOS transistor NTc(1). Then, a clock signal CLK, / CLK having an amplitude equal to the power supply voltage Vdd causes capacitors C(1) to C(n) to repeatedly charge and discharge, and the input voltage VSUP is boosted and sequentially transferred to the subsequent stages. As a result, a block selection voltage VPGMH, which is larger than the voltage VSUP, is generated at the output side of the current path of the NMOS transistor NTc(n+1).

[0129] As shown in Figure 13, the charge pump circuit 40 outputs the generated block selection voltage VPGMH to the output node NHa.

[0130] The potential difference generation circuit 41 is provided between output node NHa and output node NLa. The potential difference generation circuit 41 generates a potential difference ΔV between output node NHa and output node NLa. The potential difference ΔV is the potential difference to be generated between the program voltage VPGM and the block selection voltage VPGMH, and is, for example, 5V. As the potential difference generation circuit 41, for example, a single diode-connected NMOS transistor as shown in Figure 13, or multiple diode-connected NMOS transistors electrically connected in series can be used. In this embodiment, output nodes NHa and NLa are examples of voltage output lines.

[0131] The detection circuit 42 includes a variable resistor Ra, a reference resistor Rb, and a comparison circuit 420.

[0132] The variable resistor Ra and the reference resistor Rb are electrically connected in series between the output node NLa and the ground voltage Vss. The connection point Pcr between the variable resistor Ra and the reference resistor Rb is connected to one input terminal of the comparator circuit 420. Therefore, a voltage VMON, generated by dividing the voltage of the output node NLa by the variable resistor Ra and the reference resistor Rb, is applied to one input terminal of the comparator circuit 420. Hereafter, this voltage VMON will also be referred to as the "monitor voltage VMON".

[0133] A reference voltage VREF is applied to the other input terminal of the comparator circuit 420. The reference voltage VREF is set to the voltage that should appear at connection point Pcr when the voltage output to output node NLa becomes the specified program voltage VPGM. If the monitor voltage VMON is higher than the reference voltage VREF, the comparator circuit 420 sends a stop signal Scp to the clock of the charge pump circuit 40. The signal is output to the control circuit 400. The clock control circuit 400 stops generating the clock signals CLK, / CLK during the period when the stop signal Scp is output from the comparator circuit 420. As a result, the charge pump circuit 40 stops. In this embodiment, the comparator circuit 420 is an example of a detection unit.

[0134] Next, an example of the operation of the first voltage generation unit 260a will be described.

[0135] For example, if the voltage appearing at output node NLa exceeds the specified program voltage VPGM, the monitor voltage VMON becomes higher than the reference voltage VREF, and the comparator circuit 420 generates a stop signal Scp. This stop signal Scp causes the clock control circuit 400 to stop generating the clock signals CLK, / CLK. As a result, the output voltage of the charge pump circuit 40 decreases, suppressing the voltage rise at output node NLa, and the voltage at output node NLa is maintained at the specified program voltage VPGM. Also, if the voltage appearing at output node NLa is lower than the specified program voltage VPGM, the comparator circuit 420 does not generate a stop signal Scp, and the charge pump circuit 40 continues to operate. As a result, the voltage at output node NLa rises, and the voltage at output node NLa is maintained at the specified program voltage VPGM.

[0136] In the first voltage generation unit 260a, a feedback loop is formed by the charge pump circuit 40, the potential difference generation circuit 41, resistors Ra and Rb, the comparator circuit 420, and the clock control circuit 400, and the program voltage VPGM is determined by controlling the resistive voltage divider of resistors Ra and Rb. The output voltage of the charge pump circuit 40 is changed so that this program voltage VPGM is obtained, and a block selection voltage VPGMH that is ΔV higher than the program voltage VPGM is obtained.

[0137] Thus, in the first voltage generation unit 260a, a voltage adjustment unit 43 is configured to adjust the voltage VPGM applied to the output node NLa based on the voltage VMON detected by the comparison circuit 420, using the charge pump circuit 40 and the potential difference generation circuit 41.

[0138] 1.12 Configuration of the detection circuit Next, we will explain the specific configuration of the detection circuit.

[0139] Figure 15 is a circuit diagram showing the schematic configuration of the detection circuit 42. As shown in Figure 15, the variable resistor Ra comprises multiple resistor elements R(1) to R(k), multiple switching elements SW(1) to SW(k-1), and NMOS transistors NT(1) to NT(k-1). Note that k is an integer of 2 or greater.

[0140] Multiple resistors R(1) to R(k) are electrically connected in series in this order. The upper end of resistor R(1), which is located on the highest voltage side, is connected to the output node NLa. The lower end of resistor R(k), which is located on the lowest voltage side, is connected to connection point Pcr. In Figure 15, the respective connection points of resistors R(1) to R(k) are indicated as Pc(1), Pc(2), ..., Pc(k-1).

[0141] Switching element SW(1) is provided between connection point Pc(1) and connection point Pcr of resistor elements R(1) and R(2) connected in series. Similarly, the other switching elements SW(2) to SW(k-1) are provided between connection points Pc(2) to Pc(k-1) and connection point Pcr of resistor elements R(2) to R(k). Each switching element SW(1) to SW(k-1) is composed of, for example, an NMOS transistor. The on / off switching of each switching element SW(1) to SW(k-1) is controlled by the sequencer 25 shown in Figure 2.

[0142] The NMOS transistors NT(1) to NT(k-1) are electrically connected in parallel to multiple resistors R(1) to R(k-1). Each of the NMOS transistors NT(1) to NT(k-1) functions as a diode through diode connection. The NMOS transistors NT(1) to NT(k-1) are arranged so that their current path is forward. For example, the drain of NMOS transistor NT(1) is connected to the high-potential side of resistor R(1), and the source of NMOS transistor NT(1) is connected to the low-potential side of resistor R(1).

[0143] Next, we will describe an example of the operation of the detection circuit 42.

[0144] The sequencer 25 turns on one of the multiple switching elements SW(1) to SW(k-1) and turns off all the other switching elements based on the magnitude of the program voltage VPGM to be generated.

[0145] For example, sequencer 25 turns on switching element SW(k-1) and turns off the other switching elements SW(1) to SW(k-2). As a result, the low-potential side of switching element SW(k-1) is connected to connection point Pcr, and a current path is created between output node NLa and connection point Pcr as shown by the dashed line Ia arrow in Figure 15. That is, a circuit is formed in which electrically series-connected resistor elements R(1) to R(k-1) are placed between output node NLa and connection point Pcr. Therefore, the resistance value of the variable resistor Ra is the sum of the resistance values ​​of resistor elements R(1) to R(k-1). Consequently, the monitor voltage VMON is set to the voltage VMONa obtained by dividing the voltage of output node NLa by the sum of the resistance values ​​of resistor elements R(1) to R(k-1) and the reference resistor Rb. As a result, a program voltage VPGMa of a magnitude corresponding to this voltage VMONa is generated at output node NLa. The program voltage VPGMa is, for example, one of the program voltages VPGM1 to VPGM19 or the preparation voltage VPGM_prep.

[0146] On the other hand, when changing the program voltage from VPGMa to VPGMb, the sequencer 25 switches, for example, switching switching element SW(4) from off to on, and switching switching element SW(k-1) from on to off. As a result, the low-potential side of switching element SW(4) is connected to connection point Pcr, and a current path is created between the output node NLa and connection point Pcr, as shown by the dashed line Ib arrow in Figure 16. That is, a circuit is formed in which electrically series-connected resistor elements R(1) to R(4) are placed between the output node NLa and connection point Pcr. Therefore, the resistance value of the variable resistor Ra is the sum of the resistance values ​​of each resistor element R(1) to R(4). Consequently, the monitor voltage VMON is changed to the voltage VMONb obtained by dividing the voltage of the output node NLa by the sum of the resistance values ​​of each resistor element R(1) to R(4) and the reference resistor Rb. As a result, a program voltage VPGMb of a magnitude corresponding to this voltage VMONb is generated at the output node NLa. The program voltage VPGMb is, for example, one of the program voltages VPGM1 to VPGM19 or the preparation voltage VPGM_prep.

[0147] In this way, the detection circuit 42 can generate various program voltages VPGM1 to VPGM19 and the preparation voltage VPGM_prep by selectively turning on one of the switching elements SW(1) to SW(k-1) and turning off the other switching elements.

[0148] Next, while describing the reference example detection circuit 44 shown in Figure 17, we will explain the operation and effects of the detection circuit 42 of this embodiment shown in Figures 15 and 16.

[0149] The detection circuit 44 in the reference example shown in Figure 17 is an NMOS transistor NT(1)~NT( Except for the points that do not have (k - 1), it has the same structure as the detection circuit 42 of the present embodiment shown in FIGS. 15 and 16. In the detection circuit 44 of the reference example shown in FIG. 17, when the switching element SW(k - 1) is turned on and the other switching elements SW(1) to SW(k - 2) are turned off, similar to the detection circuit 42 of the present embodiment shown in FIG. 15, a current path as shown by the two-dot chain line Ic1 in the figure is formed, and the monitor voltage VMON is set to the voltage VMONa. As a result, the program voltage VPGMa is output to the output node NLa. Also, at this time, when the voltage of the connection point Pc(3) of the resistance element R(3) and the resistance element R(4) is V3, the voltage of the connection point Pc(4) of the resistance element R(4) and the resistance element R(5) is V4, and the voltage V4 of the connection point Pc(5) of the resistance element R(5) and the resistance element R6 is V5, the relationship "VMONa≪V5<V4<V3" holds for their voltages Va, Vb, Vc, VMONa.

[0150] In the detection circuit 44 of the reference example, when changing the program voltage output to the output node NLa from VPGMa to VPGMb, similar to the detection circuit 42 of the present embodiment shown in FIG. 16, the switching element SW(4) is switched from off to on, and the switching element SW(k - 1) is switched from on to off. As a result, a new current path as shown by the two-dot chain line Ic2 in the figure is formed, and the voltage of the connection point Pc(4) of the resistance element R(4) and the resistance element R(5) rapidly decreases toward the voltage VMONa. Therefore, there is a possibility that a large difference ΔV1 occurs between the voltage of the connection point Pc(4) of the resistance element R(4) and the resistance element R(5) and the voltage of the connection point Pc(3) of the resistance element R(3) and the resistance element R(4). As a result, there is a possibility that a potential difference close to the breakdown voltage or a potential difference exceeding the breakdown voltage occurs across the resistance element R(4). Similarly, there is a possibility that a large difference ΔV2 occurs between the voltage of the connection point Pc(4) of the resistance element R(4) and the resistance element R(5) and the voltage of the connection point Pc(5) of the resistance element R(5) and the resistance element R6. As a result, there is also a possibility that a potential difference close to the breakdown limit or a potential difference exceeding the breakdown limit occurs across the resistance element R(5).

[0151] Such voltage breakdown violations of each resistor element R(1) to R(k) are likely to become apparent, for example, when it is necessary to switch the voltage output from the first voltage generation unit 260a to the output node NLa from the preparation voltage VPGM_prep to the program voltage VPGM in a short period of time, as shown by the dashed line in Figure 6, that is, when the on / off switching of each switching element SW(1) to SW(k-1) is performed in a short period of time.

[0152] In this respect, the detection circuit 42 of this embodiment shown in Figure 16 differs from the detection circuit 44 of the reference example in that NMOS transistors NT(1) to NT(k-1) are electrically connected in parallel to each of the resistive elements R(1) to R(k-1). According to the configuration of the detection circuit 42 of this embodiment, when the voltage at the connection point Pc(4) of resistive elements R(4) and R(5) decreases due to the switching element SW(4) being turned on, a current path as shown by the dashed line Id1 in Figure 16 is generated. That is, when the voltage at the connection point Pc(4) decreases and a potential difference greater than the threshold voltage of the NMOS transistor NT(4) is generated between the connection point Pc(4) and the connection point Pc(3) of resistive elements R(3) and R(4), the NMOS transistor NT(4) turns on. As a result, a current path is created from connection point Pc(3) through NMOS transistor NT(4) to connection point Pc(4), as shown by the dashed line Id1 in the figure, making it less likely for the voltage at connection point Pc(4) to drop. Consequently, the potential difference between connection point Pc(3) and connection point Pc(4) is less likely to become large, and the potential difference between connection point Pc(4) and connection point Pc(5) is also less likely to become large, thus making it less likely for the resistive elements R(4) and R(5) to exceed their breakdown voltage.

[0153] Furthermore, when a current path is formed as shown by the dashed line Id1 in the figure, the voltage at the connection point Pc(3) of resistors R(3) and R(4) decreases, the resistor R A large potential difference may occur between the connection point Pc(2) of resistor (2) and resistor R(3) and the connection point Pc(3) of resistor R(3) and resistor R(4). In this case, a further current path may be formed as shown by the dashed line Id2 in the figure. That is, when the voltage at connection point Pc(3) decreases and a potential difference greater than the threshold voltage of NMOS transistor NT(3) is generated between connection point Pc(3) and connection point Pc(2), NMOS transistor NT(3) turns on. As a result, a further current path is generated from connection point Pc(2) to connection point Pc(4) via NMOS transistors NT(3) and NT(4), as shown by the dashed line Id2 in the figure, making it less likely for the voltage at connection point Pc(4) to decrease further. As a result, the potential difference between connection point Pc(3) and connection point Pc(4) becomes less likely to become large, and the potential difference between connection point Pc(4) and connection point Pc(5) also becomes less likely to become large, thus reducing the likelihood of voltage breakdown violations occurring in the resistive elements R(4) and R(5).

[0154] Similarly, further current paths may be formed as shown by the dashed lines Id3 and Id4 in the figure. This makes it less likely for the voltage at connection point Pc(4) to drop further, thus making it less likely for the potential difference between connection point Pc(3) and connection point Pc(4) to become large, as well as less likely for the potential difference between connection point Pc(4) and connection point Pc(5) to become large. Therefore, voltage breakdown violations are less likely to occur in the resistive elements R(4) and R(5).

[0155] 1.13 Operation and Effects of the Voltage Generation Circuit of the First Embodiment As described above, the voltage generation circuit 260 of this embodiment comprises a variable resistor Ra, a reference resistor Rb, a comparison circuit 420 (detection unit), and a voltage adjustment unit 43. The variable resistor Ra is connected to the output node NLa (voltage output line). The reference resistor Rb is connected in series with the low-voltage side of the variable resistor Ra. The comparison circuit 420 detects the monitor voltage VMON at the connection point Pcr (first connection point) between the variable resistor Ra and the reference resistor Rb. The voltage adjustment unit 43 adjusts the program voltage VPGM applied to the output node NLa based on the monitor voltage VMON detected by the comparison circuit 420. The variable resistor Ra comprises a plurality of resistor elements R(1) to R(k), a plurality of switching elements SW(1) to SW(k-1), and a plurality of NMOS transistors NT(1) to NT(k-1). The plurality of resistor elements R(1) to R(k) are connected in series. Multiple switching elements SW(1) to SW(k-1) are placed between the connection points Pc(1), Pc(2), ..., Pc(k-1) (second connection point) and connection point Pcr of each of the multiple resistive elements R(1) to R(k). Multiple NMOS transistors NT(1) to NT(k-1) function as diodes and are connected in parallel to each of the multiple resistive elements R(1) to R(k-1).

[0156] With this configuration, when one of the multiple switching elements SW(1) to SW(k-1) is designated as SW(i), a sharp drop in voltage at the connection point Pc(i) between resistors R(i) and R(i+1) can be suppressed when the switching element SW(i) switches from off to on. Note that i = 1, 2, ..., k-1. As a result, a large potential difference is suppressed across each of the resistors R(i) and R(i+1), thereby improving the breakdown voltage performance of the voltage generation circuit 260.

[0157] The NMOS transistors NT(1) to NT(k-1) are arranged so as to be in the forward direction relative to the current path of the resistors R(1) to R(k).

[0158] With this configuration, when one of the multiple switching elements SW(1) to SW(k-1), SW(i), switches from off to on, a current path is formed from the connection points Pc(1) to Pc(i-1) through the NMOS transistors NT(1) to NT(i) to the connection point Pc(i), thereby suppressing a drop in the voltage at the connection point Pc(i).

[0159] The NMOS transistors NT(1) to NT(k-1) are provided in the same number as the switching elements SW(1) to SW(k-1).

[0160] With this configuration, since an NMOS transistor NT(1) to NT(k-1) can be placed for each of the multiple switching elements SW(1) to SW(k-1), the occurrence of voltage breakdown violations in the resistive elements R(1) to R(k) can be suppressed more reliably.

[0161] 1.14 First Variation Next, a first modified example of the voltage generation circuit 260 of the first embodiment will be described.

[0162] As shown in Figure 18, in the detection circuit 42 of this modified example, when j = 1, 3, 5, ..., k-1, one NMOS transistor NT(j) is connected in parallel to two resistors R(j) and R(j+1).

[0163] Even with this configuration, for example, when the voltage at the connection point Pc(4) of resistors R(4) and R(5) drops, the NMOS transistor NT(3) turns on, creating a current path from connection point Pc(2) through NMOS transistor NT(3) to connection point Pc(4), as shown by the dashed line If1 in the figure. Therefore, the voltage at connection point Pc(4) is less likely to drop. Furthermore, the formation of another current path, as shown by the dashed line If2 in the figure, may further reduce the likelihood of the voltage at connection point Pc(4) dropping. As a result, the potential difference between connection point Pc(3) and connection point Pc(4) is less likely to increase, and the potential difference between connection point Pc(4) and connection point Pc(5) is also less likely to increase, thus reducing the likelihood of voltage breakdown violations occurring in resistors R(4) and R(5).

[0164] 1.15 Second Variation Next, a second modified example of the voltage generation circuit 260 of the first embodiment will be described.

[0165] As shown in Figure 19, in the detection circuit 42 of this modified example, when i = 1, 2, ..., k-1, two NMOS transistors NTa(i) and NTb(i) are provided in series with respect to one resistor R(i). Even with this configuration, it is possible to obtain the same or similar operation and effects as the voltage generation circuit 260 of the above embodiment.

[0166] 1.16 Third Variation Next, a third modified example of the voltage generation circuit 260 of the first embodiment will be described.

[0167] As shown in Figure 20, the detection circuit 42 of this modified example includes resistors R(1) to R(p) in which NMOS transistors NT(1) to NT(p) are connected in parallel to multiple resistors R(1) to R(k), and resistors R(p+1) to R(k) in which NMOS transistors are not connected in parallel. Note that p is an integer satisfying "2 ≤ p ≤ k - 2". The resistors R(1) to R(p) are located on the higher voltage side than the resistors R(p+1) to R(k). In this modified example, resistors R(1) to R(p) are an example of the first resistors, and resistors R(p+1) to R(k) are an example of the second resistors.

[0168] In the detection circuit 42, the voltage drop at the connection point between the two resistive elements is greater when the high-voltage switching elements SW(1) to SW(p) switch from off to on than when the low-voltage switching elements SW(p+1) to SW(k-1) switch from off to on, making it more likely for the resistive elements to exceed their breakdown voltage. Therefore, as shown in Figure 20, by placing NMOS transistors NT(1) to NT(p) only between the high-voltage resistive elements R(1) to R(p), the breakdown voltage violation of the resistive elements R(1) to R(k) can be suppressed while also providing NMOS transistors. The detection circuit 42 can be made smaller because the transistors NT(p+1) to NT(k-1) are no longer needed.

[0169] 2. Second Embodiment Next, a second embodiment of the semiconductor memory device 2 will be described. The following description will focus on the differences from the semiconductor memory device 2 of the first embodiment.

[0170] In the detection circuit 42 of the first embodiment shown in Figure 16, it is necessary to prevent current from flowing through the NMOS transistors NT(1) to NT(k-1) during normal operation. Therefore, when i = 1, 2, ..., k-1, the threshold voltage of the NMOS transistor NT(i) must be higher than the potential difference generated across the resistor R(i) during normal operation. However, for some reason, the potential difference generated across the resistor R(i) during normal operation may become higher than the threshold voltage of the NMOS transistor NT(i). In such a situation, if an unintended current path is generated that flows through the NMOS transistor NT(i), the detection circuit 42 may malfunction.

[0171] Therefore, in the detection circuit 42 of this embodiment, as shown in Figure 21, the NMOS transistors NT(1) to NT(k-1) that function as diodes are arranged in the opposite direction to the current path of the resistors R(1) to R(k-1).

[0172] Next, the operation and effects of the detection circuit 42 of this embodiment will be described.

[0173] In the detection circuit 42 of this modified example, when the switching element SW(4) is turned on, a current path is generated as shown by the dashed line Ib arrow in Figure 16, and when the voltage at the connection point Pc(4) of the resistors R(4) and R(5) drops, a current path is generated as shown by the dashed line Ie1 in the figure. That is, when the voltage at the connection point Pc(4) drops, a potential difference greater than the threshold voltage of the NMOS transistor NT(5) is generated between the connection point Pc(4) and the connection point Pc(5) of the resistors R(5) and R(6), and the NMOS transistor NT(5) turns on. As a result, a current path is generated from the connection point Pc(5) to the connection point Pc(4) via the NMOS transistor NT(5), as shown by the dashed line Ie1 in the figure, making it difficult for the voltage at the connection point Pc(4) to drop. As a result, the potential difference between connection point Pc(3) and connection point Pc(4) becomes less likely to become large, and the potential difference between connection point Pc(4) and connection point Pc(5) also becomes less likely to become large, thus reducing the likelihood of voltage breakdown violations occurring in the resistive elements R(4) and R(5).

[0174] Furthermore, when a current path as shown by the dashed line Ie1 in the figure is formed, the voltage at the connection point Pc(5) of resistors R(5) and R(6) decreases, which can create a large potential difference between the connection point Pc(5) of resistors R(5) and R(6) and the connection point Pc(6) of resistors R(6) and R(7). In this case, a further current path as shown by the dashed line Ie2 in the figure may be formed. That is, when the voltage at connection point Pc(5) decreases, a potential difference greater than the threshold voltage of NMOS transistor NT(6) is generated between connection point Pc(5) and connection point Pc(6), causing NMOS transistor NT(6) to turn on. As a result, a further current path is generated as shown by the dashed line Ie2 in the figure, where current flows from connection point Pc(6) through NMOS transistors NT(6) and NT(5) to connection point Pc(4), making it less likely for the voltage at connection point Pc(4) to decrease. As a result, the potential difference between connection point Pc(3) and connection point Pc(4) becomes less likely to become large, and the potential difference between connection point Pc(4) and connection point Pc(5) also becomes less likely to become large, thus reducing the likelihood of voltage breakdown violations occurring in the resistive elements R(4) and R(5).

[0175] Similarly, further current paths are formed as shown by the dashed lines Ie3, Ie4, ... in the figure. This is possible. As a result, the voltage at connection point Pc(4) is less likely to drop further, making it less likely for the potential difference between connection point Pc(3) and connection point Pc(4) to become large, and also less likely for the potential difference between connection point Pc(4) and connection point Pc(5) to become large. Therefore, voltage breakdown violations are less likely to occur in the resistive elements R(4) and R(5).

[0176] Furthermore, by arranging the NMOS transistors NT(1) to NT(k-1), which function as diodes, in the opposite direction to the current path of the resistors R(1) to R(k-1), it is possible to prevent the formation of unintended current paths that would flow through the NMOS transistors NT(1) to NT(k-1) during normal operation, thereby suppressing malfunctions of the detection circuit 42.

[0177] 3 Other Embodiments This disclosure is not limited to the specific examples given above.

[0178] For example, the detection circuit 42 of the second embodiment can adopt the configuration of the first to third modified examples of the first embodiment. That is, the detection circuit 42 of the second embodiment can adopt the configuration shown in Figures 22 to 24.

[0179] In the detection circuit 42, it is sufficient that an NMOS transistor, which functions as a diode, is connected in parallel to at least one of the multiple resistors R(1) to R(k).

[0180] The resistive elements R(1) to R(k) may be, for example, three-terminal resistive elements as shown in Figure 25. As three-terminal resistive elements, for example, P-type diffusion resistive elements can be used.

[0181] The structure of the semiconductor memory device 2 is not limited to the structure shown in Figure 4 and can be modified as appropriate. For example, the semiconductor memory device 2 may have a CBA (CMOS Bonding Array) structure as shown in Figure 26. In the semiconductor memory device 2 shown in Figure 26, the memory section 80, which is provided with the memory cell array 21, and the control circuit section 90, which is provided with the peripheral circuit PER, are manufactured separately. This semiconductor memory device 2 is constructed by bonding the separately manufactured memory section 80 and control circuit section 90 together on a bonding surface B1. The memory cell array 21 and the peripheral circuit PER are electrically connected to each other via wiring layers 800, 801 and vias 810, 811 provided on the bonding surface 81.

[0182] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention and are included in the claims of the invention and its equivalents. [Explanation of Symbols]

[0183] MT: Memory cell transistor, NLa: Output node (voltage output line), NT(1)~NT(k-1): NMOS transistor (diode), Pcr: Connection point (first connection point), Ra: Variable resistor, Rb: Reference resistor, R(1)~R(p): Resistor element (first resistor element), R(p+1)~R(k): Resistor element (second resistor element), SW(1)~SW(k-1): Switching element, WL,WL0~WL7: Word lines, 40: Charge pump circuit, 43: Voltage adjustment section, 260: Voltage generation circuit, 420: Comparator circuit (detection section).

Claims

1. A variable resistor connected to the voltage output line, A reference resistor connected in series with the low-voltage side of the aforementioned variable resistor, A detection unit that detects the voltage at the first connection point between the variable resistor and the reference resistor, The system includes a voltage adjustment unit that adjusts the voltage applied to the output line of the voltage based on the voltage detected by the detection unit, The aforementioned variable resistor is Multiple resistors connected in series, A plurality of switching elements are provided between the second connection point and the first connection point of each of the plurality of resistive elements, A diode connected in parallel to at least one of the plurality of resistive elements, Voltage generation circuit.

2. The diode is positioned to be in the forward direction relative to the current path of the resistive element. The voltage generation circuit according to claim 1.

3. The diode is positioned so as to be in the opposite direction to the current path of the resistive element. The voltage generation circuit according to claim 1.

4. Multiple diodes are provided, in the same number as the multiple switching elements. The voltage generation circuit according to claim 1.

5. The aforementioned variable resistor is The diode comprises a plurality of diodes connected in parallel to one of the resistive elements and connected in series with each other. The voltage generation circuit according to claim 1.

6. The plurality of resistive elements include: The diode is connected in parallel to a first resistive element, The diode is not connected in parallel to a second resistive element, The first resistive element is positioned on the higher voltage side than the second resistive element. The voltage generation circuit according to claim 1.

7. The aforementioned resistive element is a three-terminal diffusion resistive element. The voltage generation circuit according to claim 1.

8. Multiple memory cell transistors connected in series, The word line connected to the gate of the memory cell transistor, The system includes a voltage generation circuit that generates a voltage to be supplied to the word line, The voltage generation circuit is A charge pump circuit that applies the boosted voltage to the word line via a voltage output line, A variable resistor connected to the aforementioned voltage output line, A reference resistor connected in series with the low-voltage side of the aforementioned variable resistor, A detection unit that detects the voltage at the first connection point between the variable resistor and the reference resistor, Based on the voltage detected by the detection unit, the voltage applied to the output line of the voltage is adjusted. It has a voltage adjustment unit that adjusts the voltage. The aforementioned variable resistor is Multiple resistors connected in series, A plurality of switching elements are provided between the second connection point and the first connection point of each of the plurality of resistive elements, A diode connected in parallel to at least one of the plurality of resistive elements, Semiconductor memory device.

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