Semiconductor equipment

Abstract

This suppresses differences in power supply capability to circuits that supply power voltage in areas where the density of power terminals differs from one another. [Solution] The semiconductor device comprises a first region in which first power terminals connected to a first power line are arranged at a first density, a second region in which second power terminals connected to the first power line are arranged at a second density lower than the first density, a plurality of first power switch circuits provided in the first region and connected to the first power line and the second power line, and a plurality of second power switch circuits provided in the second region and connected to the first power line and the second power line, wherein the first power switch circuit has a first fin and a first transistor having a plurality of first gate electrodes provided on the first fin, and the second power switch circuit has a second fin and a second transistor provided on the second fin and having a plurality of second gate electrodes that are more numerous than the first gate electrodes.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] There is a technique of providing a power switch circuit for switching on / off the supply of a power voltage in a standard cell region of a semiconductor device to achieve low power consumption. There is also a technique of providing a plurality of types of power switch circuits and sequentially turning on the power switch circuits to suppress a rush current (inrush current) in which the power voltage of a power supply source decreases due to a rapid supply of the power voltage.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

Summary of the Invention

Problems to be Solved by the Invention

[0004] When multiple power switch circuits are placed in a large circuit area, differences in wiring resistance from the power terminals receiving the power voltage to the multiple power switch circuits can cause IR drop at points of high resistance. Furthermore, in semiconductor devices where power terminals are provided as bumps, differences in the degree of IR drop can occur if the wiring resistance from the power terminals to the power switch circuits increases in areas with a lower density of power terminals compared to other areas. This can result in differences in the power supply capability to circuits supplying power voltage in areas with varying power terminal densities.

[0005] The present invention has been made in view of the above points, and aims to suppress differences in the power supply capability to circuits that supply power voltage in regions where the arrangement density of power terminals differs from one another. [Means for solving the problem]

[0006] In one aspect of the present invention, a semiconductor device includes a circuit region having a first power line, a second power line, a first region in which a plurality of first power terminals connected to the first power line are arranged at a first density in a plan view, and a second region in which a plurality of second power terminals connected to the first power line are arranged at a second density lower than the first density in a plan view; a plurality of first power switch circuits provided in the first region and connected to the first power line and the second power line; and a plurality of second power switch circuits provided in the second region and connected to the first power line and the second power line, wherein the first power switch circuit has a first fin and a first transistor having a plurality of first gate electrodes provided on the first fin, and the second power switch circuit has a second fin and a second transistor provided on the second fin and having a plurality of second gate electrodes that are more numerous than the first gate electrodes. [Effects of the Invention]

[0007] According to the disclosed technology, it is possible to suppress differences in the power supply capability to circuits that supply power voltage in areas where the arrangement density of power terminals differs from one another. [Brief explanation of the drawing]

[0008] [Figure 1] This figure shows an example of the layout of a semiconductor device in the first embodiment. [Figure 2] Figure 1 is a circuit block diagram showing an overview of the circuits arranged in the standard cell block. [Figure 3] Figure 1 is a plan view showing an overview of the standard cell block layout. [Figure 4] Figure 2 is a plan view showing an example of the layout of the power switch circuit (PSW). [Figure 5] This is a cross-sectional view showing a section along the line X1-X1' in Figure 4. [Figure 6] This is a cross-sectional view showing the section along the line Y1-Y1' in Figure 4. [Figure 7] Figure 2 is a plan view showing an example of the layout of the power switch circuit (LPSW). [Figure 8] This is a plan view showing an overview of the layout of the standard cell block in the second embodiment. [Figure 9] This is a plan view showing an overview of the layout of the standard cell block in the third embodiment. [Figure 10] This is a plan view showing an overview of the layout of the standard cell block in the fourth embodiment. [Figure 11] This is a plan view showing an overview of the layout of the standard cell block in the fifth embodiment. [Modes for carrying out the invention]

[0009] Embodiments will be described below with reference to the drawings. In the following, symbols indicating signals are also used to indicate signal values, signal lines, or signal terminals. Symbols indicating power supply voltage are also used to indicate power lines or power supply terminals to which the power supply voltage is supplied.

[0010] (First embodiment) FIG. 1 shows an example of the layout of a semiconductor device in the first embodiment. For example, the semiconductor device SEM shown in FIG. 1 may be a SoC (System on Chip), or a single FPGA (Field-Programmable Gate Array) or ASIC (Application Specific Integrated Circuit), etc.

[0011] The semiconductor device SEM has a plurality of I / O cells IOC and IOCP each connected to a bump BMP. The I / O cell IOC is an interface circuit for a signal SIG such as an input signal, an output signal, or an input / output signal. The I / O cell IOCP is an interface circuit for a power supply voltage or a ground voltage.

[0012] Each I / O cell IOC and IOCP is connected to an internal circuit region INTR. For example, the internal circuit region INTR has a plurality of standard cell blocks SCB where standard cells are provided. Note that a logic circuit other than the standard cell or a memory may be mounted in the internal circuit region INTR. Note that the number and ratio of the I / O cells IOC and IOCP are not limited to the example shown in FIG. 1.

[0013] The semiconductor device SEM is connected, for example, to pads (not shown) on the surface of a wiring board WBRD via a plurality of bumps BMP provided on the surface of the semiconductor device SEM. External connection terminals (for example, bumps) are provided on the back surface of the wiring board WBRD.

[0014] FIG. 2 is a circuit block diagram showing an overview of the circuit arranged in the standard cell block SCB of FIG. 1. The standard cell block SCB has a power switch circuit PSW (or a low power switch circuit LPSW) and a standard cell region SCA. The standard cell region SCA is electrically connected to a virtual power supply line VVDD and a ground line VSS, and operates by receiving a supply of a power supply voltage from the virtual power supply line VVDD.

[0015] A power switch circuit (PSW) (or power switch circuit LPSW) has a switch transistor SWT and a control circuit CNTL. The power switch circuit LPSW has the same configuration as the power switch circuit PSW, except that the switch transistor SWT is larger and has a higher power supply capacity.

[0016] The power switch circuit PSW is an example of a first power switch circuit. The power switch circuit LPSW is an example of a second power switch circuit. The switch transistor SWT of the power switch circuit PSW is an example of a first switch transistor. The switch transistor SWT of the power switch circuit LPSW is an example of a second switch transistor.

[0017] A switch transistor (SWT) is, for example, a p-channel transistor whose source is connected to the power line VSS and whose drain is connected to the virtual power line VVDD. It operates by receiving a switch control signal SWCNT from the control circuit CNTL at its gate. In Figure 2, for simplicity, one switch transistor SWT is shown, but multiple switch transistors SWT may be placed between the power line VDD and the virtual power line VVDD. Power line VDD is an example of a first power line, and virtual power line VVDD is an example of a second power line.

[0018] While the switch transistor SWT is ON, the power line VDD and the virtual power line VVDD are electrically connected, and the power supply voltage VDD is supplied to the virtual power line VVDD. While the switch transistor SWT is OFF, the electrical connection between the power line VDD and the virtual power line VVDD is broken, and the virtual power line VVDD is set to a floating state.

[0019] The control circuit CNTL is, for example, a buffer circuit. When the control circuit CNTL operates a circuit in the standard cell area SCA, it sets the switch control signal SWCNT to a low level and supplies power voltage from the power line VDD to the virtual power line VVDD. When the control circuit CNTL stops the operation of a circuit in the standard cell area SCA, it sets the switch control signal SWCNT to a high level and stops supplying power voltage from the power line VDD to the virtual power line VVDD.

[0020] Figure 3 is a plan view illustrating the layout of the standard cell block (SCB) shown in Figure 1. Figure 3 shows a portion of the standard cell block (SCB) area as seen from the surface of the semiconductor device's SEM (the surface where the bump BMPs are formed) (plan view). In Figure 3, each bump BMP is shown as a ring to make the wiring hidden by the bump BMPs more visible. For simplicity of explanation, the size of each bump BMP is smaller than its actual size. Figures 5 and 6 illustrate the actual size of the bump BMPs.

[0021] The power line VDD (GL2) and the ground line VSS (GL2) are routed along the X direction in Figure 3 using the global wiring layer GL2 closest to the bump BMP. The power line VDD (GL1) and the ground line VSS (GL1) are routed along the Y direction in Figure 3 using the global wiring layer GL1 located on the opposite side of the bump BMP from the global wiring layer GL2. Global wiring layers GL2 and GL1 are located on the surface side of the semiconductor device SEM.

[0022] Power lines VDD (GL2) and VDD (GL1) are interconnected via vias (not shown). Ground lines VSS (GL2) and VSS (GL1) are interconnected via vias (not shown). For the sake of simplicity, the signal lines SIG and power lines VDDM, which are routed using global wiring layers GL2 and GL1, are omitted from the description. Bump BMP (VDDM) and power line VDDM are used to supply power voltage to memory when memory is provided in the standard cell block SCB.

[0023] In Figure 3, the widths Wa and Wb of the power line VDD(GL1) or ground line VSS(GL1) located in regions Ra and Rb are equal. Also, the placement pitches Pa and Pb of the power line VDD(GL1) or ground line VSS(GL1) located in regions Ra and Rb are equal. Region Ra is an example of a first region, and region Rb is an example of a second region. While not particularly limited, in Figure 3, six power switch circuits PSW are located in region Ra, and six power switch circuits LPSW are located in region Rb.

[0024] For example, the power switch circuits PSW and LPSW are provided using the semiconductor layer and wiring layer on the back side of the semiconductor device SEM (opposite the front side where the bump BMP is located), but for ease of viewing, they are positioned at the very front in Figure 3.

[0025] For example, the size of the switch transistor SWT (Figure 2) of the power switch circuit LPSW is set to 2.5 times the size of the switch transistor SWT of the power switch circuit PSW. Here, the size of the switch transistor SWT represents the power supply capability of each power switch circuit LPSW and PSW to the virtual power line VVDD, without considering the placement density of the bump BMP (VDD) and the wiring resistance of the power line VDD. For example, if the switch transistor SWT is a FinFET (Fin Field Effect Transistor), the size of the switch transistor SWT and the power supply capability of each power switch circuit LPSW and PSW to the virtual power line VVDD are represented by the product of the number of gates and the number of fins.

[0026] Region Ra contains 20 bump BMPs, including 10 bump BMPs (VDD) in a plan view. Region Rb contains 15 bump BMPs, including 3 bump BMPs (VDD) in a plan view. Therefore, the arrangement density of bump BMPs (VDD) in region Rb (3 / 15=0.2) is 40% of the arrangement density of bump BMPs (VDD) in region Ra (10 / 20=0.5).

[0027] The bump BMP (VDD) located in region Ra is an example of a first power supply terminal. The bump BMP (VDD) located in region Rb is an example of a second power supply terminal. The placement density of bump BMPs (VDD) in region Ra is an example of a first density. The placement density of bump BMPs (VDD) in region Rb is an example of a second density.

[0028] In this embodiment, for example, in each region Ra and Rb, the product of the placement density of bump BMPs (VDD) and the size of the switch transistor SWT is set to be equal to each other. Therefore, even when the placement density of bump BMPs (VDD) is lower than in region Ra, the actual power supply capability to the virtual power line VVDD in region Rb can be made equal to or greater than the actual power supply capability to the virtual power line VVDD in region Ra.

[0029] Figure 4 is a plan view showing an example of the layout of the power switch circuit PSW in Figure 2. In the legend shown in Figure 4, the symbol LI indicates a local trace, and the symbol FIN indicates a fin. The symbol GT indicates the gate of the switch transistor SWT. The symbol M1 indicates the first trace layer, and the symbol M2 indicates the second trace layer. The symbol VIA1 indicates a via connecting trace layer M1 and the local trace LI.

[0030] The power switch circuit PSW includes the switch transistor SWT and the control circuit CNTL shown in Figure 2. The control circuit CNTL has inverters IV1 and IV2 connected to the power line VDD (M1) and the ground line VSS (M1). Inverters IV1 and IV2 are connected in series and operate as a buffer. Inverter IV1 inverts the level of the signal received at input terminal IN1 and outputs it as a switch control signal SWCNT to the switch control signal line SWCNT connected to output terminal OUT1.

[0031] The switch control signal SWCNT is supplied to the gate GT of the p-channel transistor P located in the switch transistor SWT and to the input terminal IN2 of the inverter IV2. The p-channel transistor P is indicated by a rectangular frame with arc-shaped corners and dashed lines. The switch control signal SWCNT controls the on and off states of the p-channel transistor P in the switch transistor SWT, thereby controlling the supply of power voltage from the power line VDD to the virtual power line VVDD. The switch transistor SWT shown in Figure 4 has 48 p-channel transistors P located at the intersections of 6 gates GT and 8 fins FIN. The p-channel transistor P located in the power switch circuit PSW is an example of a first transistor.

[0032] Inverter IV2 inverts the level of the switch control signal SWCNT received at input terminal IN2 and outputs it from output terminal OUT2. For example, the signal output from output terminal OUT2 may be supplied to input terminal IN1 of control circuit CNTL of another power switch circuit PSW (not shown) located adjacent to the power switch circuit PSW shown in Figure 4 in the Y direction.

[0033] Each of the multiple p-channel transistors P has its source electrically connected to the power line VDD(M1), its drain electrically connected to the virtual power line VVDD(M1), and its gate GT electrically connected to the switch control signal line SWCNT(M1). Here, the source of the p-channel transistor P is provided on one of the fins FIN opposite the gate. The drain of the p-channel transistor P is provided on the other fin FIN opposite the source, across the gate.

[0034] One end of the fin is connected to the power line VDD(M1) via local wiring LI, and the other end of the fin is connected to the virtual power line VVDD(M1) via local wiring LI. The virtual power line VVDD(M1), connected to the switch transistor SWT, extends along the X direction and is connected to the standard cell area SCA.

[0035] Figure 5 is a cross-sectional view showing a section along the line X1-X1' in Figure 4. The bump BMP(VDD) provided on the surface side of the semiconductor device SEM is connected to the power line VDD(GL2) via a pad PAD provided by opening in the insulating film INS1. The power line VDD(GL2) is connected to the power line VDD(GL1) via via VIA-G2.

[0036] The power line VDD(GL1) is connected to the power line VDD(M1) located on the back side of the semiconductor device SEM via via VIA-G1, which is provided by openings in the insulating film INS2, and TSVs (not shown) provided in the insulating film INS3. The power line VDD(M1) is then connected to the source of the p-channel transistor P provided on the fin FIN. In other words, the bump BMP(VDD) is electrically connected to the source of the p-channel transistor P (Figure 4) via the power line VDD of each layer. A Shallow Trench Isolation (STI) film is formed as an insulating film on the surface of the semiconductor substrate SUB.

[0037] Figure 6 is a cross-sectional view showing the cross-section along the line Y1-Y1' in Figure 4. Elements similar to those in Figure 5 are given the same reference numerals, and detailed explanations are omitted. The wiring structure from bump BMP (VDD) to via VIA-G1 is the same as in Figure 5. The virtual power line VVDD (M1) is connected to local wiring LI via via VIA1, and further connected to fin FIN provided on the switch transistor SWT. Fin FIN is provided on the semiconductor substrate SUB. The gate insulating film formed between the gate GT and fin FIN is not shown.

[0038] Figure 7 is a plan view showing an example of the layout of the power switch circuit LPSW in Figure 2. Elements similar to those in the power switch circuit PSW shown in Figure 4 are given the same reference numerals, and detailed explanations are omitted.

[0039] The power switch circuit LPSW has the same configuration as the power switch circuit PSW shown in Figure 4, except that the number of gate GTs is 9. That is, the number of gate GTs in the power switch circuit LPSW is 1.5 times the number of gate GTs in the power switch circuit PSW (6). In other words, the size of the switch transistor SWT of one power switch circuit LPSW is approximately 1.5 times the size of the switch transistor SWT of one power switch circuit PSW. The switch transistor SWT shown in Figure 7 has 72 p-channel transistors P located at the intersections of the 9 gate GTs and 8 fins FIN. The p-channel transistors P provided in the power switch circuit LPSW are an example of second-order transistors.

[0040] Therefore, if the wiring resistance of the power lines VDD is the same, the power supply capability to the virtual power line VVDD by the power switch circuit LPSW alone can be made approximately 1.5 times that of the power switch circuit PSW alone. This suppresses the increase in wiring resistance of the power wiring, reduces the IR drop of the power supply voltage VDD, and suppresses the decrease in power supply capability to the virtual power line VVDD, even when the placement density of bump BMPs (VDD) is low. As a result, the actual power supply capability to the virtual power line VVDD in region Rb, where the placement density of bump BMPs (VDD) is lower than in region Ra, can be made equivalent to the actual power supply capability to the virtual power line VVDD in region Ra.

[0041] In this embodiment and the embodiments described later, the condition for making the power supply capability to the virtual power line VVDD in region Rb equivalent to the power supply capability to the virtual power line VVDD in region Ra can be determined by equation (1). However, the threshold voltages of the p-channel transistors P of the power switch circuits PSW and LPSW are assumed to be equal. Furthermore, the widths of each power line VDD(GL2) in regions Ra and Rb are assumed to be equal, and the arrangement density of each power line VDD(GL2) in regions Ra and Rb is assumed to be equal. Ba × (Ga × Fa × Pa × Wa × Da) = Bb × (Gb × Fb × Pb × Wb × Db) ... (1)

[0042] The meanings of the symbols shown in equation (1) are as follows: Ba: Placement density of bump BMPs (VDD) in region Ra Ga: Number of gate GTs of each switch transistor SWT in region Ra Fa: Number of fins (FINs) of each switch transistor SWT in region Ra. Pa: Number of power switch circuits (PSWs) in region Ra (arrangement density) Wa: Width of each power line VDD(GL1) in region Ra Da: Arrangement pitch (arrangement density) of power lines VDD (GL1) in region Ra. Bb: Placement density of bump BMPs (VDD) in region Rb Gb: Number of gate GTs of each switch transistor SWT in region Rb Fb: Number of fins (FINs) of each switch transistor SWT in region Rb Pb: Number of power switch circuits (PSW) in region Rb (placement density) Wb: Width of each power line VDD (GL1) in region Rb Db: Arrangement pitch (arrangement density) of power lines VDD (GL1) in region Rb.

[0043] In equation (1), "Ga × Fa × Pa × Wa × Da" represents the power supply capability to the virtual power line VVDD in region Ra, without considering the placement density of bump BMPs (VDD) (the power supply capability of the circuit alone, including the power line VDD and the power switch circuit PSW). In equation (1), "Gb × Fb × Pb × Wb × Db" represents the power supply capability to the virtual power line VVDD in region Rb, without considering the placement density of bump BMPs (VDD) (the power supply capability of the circuit alone, including the power line VDD and the power switch circuit LPSW). The power supply capability of the circuit alone to the virtual power line VVDD in region Ra is an example of the first power supply capability. The power supply capability of the circuit alone to the virtual power line VVDD in region Rb is an example of the second power supply capability.

[0044] In this embodiment, "Fa = number of fins" is equal to "Fb = number of fins", and "Pa = number of power switch circuits (PSW)" is equal to "Pb = number of power switch circuits (LPSW)". Also, "Wa = width of each power line VDD(GL1)" is equal to "Wb = width of each power line VDD(GL1)", and "Da = arrangement pitch of power lines VDD(GL1)" is equal to "Db = arrangement pitch of power lines VDD(GL1)". Therefore, equation (1) can be transformed into equation (2). Ba × Ga = Bb × Gb ... (2)

[0045] In equation (2), "Ga" represents the power supply capability to the virtual power line VVDD of the circuit alone, without considering the placement density of bump BMPs (VDD) in region Ra. In equation (2), "Gb" represents the power supply capability to the virtual power line VVDD of the circuit alone, without considering the placement density of bump BMPs (VDD) in region Rb. The left side of equation (2), "Ba × Ga", represents the actual power supply capability to the virtual power line VVDD in region Ra, expressed as the product of the placement density of bump BMPs (VDD) and the power supply capability of the circuit alone. The right side of equation (2), "Bb × Gb", represents the actual power supply capability to the virtual power line VVDD in region Rb, expressed as the product of the placement density of bump BMPs (VDD) and the power supply capability. "Ba × Ga" is an example of the first parameter. "Bb × Gb" is an example of the second parameter.

[0046] The arrangement densities Ba and Bb of the bump BMP(VDD) are 0.5 and 0.2, respectively, as explained in Figure 3. The number of gates GT Ga and Gb are 6 and 9, respectively. In this case, the left side of equation (2) becomes 3, and the right side of equation (2) becomes 1.8.

[0047] Therefore, the actual power supply capacity to the virtual power line VVDD in region Rb is insufficient compared to the actual power supply capacity to the virtual power line VVDD in region Ra. For example, by setting the number of gates GT Gb of the switch transistor SWT of each power switch circuit LPSW to 15, the right-hand side of equation (2) can be changed to "3", which is equal to the left-hand side of equation (2).

[0048] Furthermore, the threshold voltage of the p-channel transistor P in the power switch circuit LPSW may be set lower than the threshold voltage of the p-channel transistor P in the power switch circuit PSW. In this case, for example, even if the number of gates GT Gb in the power switch circuit LPSW is 9, the actual power supply capability to the virtual power line VVDD in region Rb can be made equal to or greater than the actual power supply capability to the virtual power line VVDD in region Ra.

[0049] Furthermore, in one or more of the second to fifth embodiments described later (Figures 8, 9, 10, and 11), a power switch circuit LPSW may be placed in place of the power switch circuit PSW in region Rb.

[0050] In this embodiment, the power supply switch circuit LPSW, which has a higher power supply capacity than the power supply switch circuit PSW, is placed in region Rb, where the arrangement density of bump BMPs (VDD) is lower than in region Ra. Therefore, in region Rb, the increase in the wiring resistance of the power line VDD provided between the bump BMP (VDD) and the power supply switch circuit LPSW can be suppressed, and the IR drop of the power supply voltage VDD can be reduced.

[0051] As a result, the decrease in the actual power supply capacity to the virtual power line VVDD in region Rb can be suppressed, and the actual power supply capacity to the virtual power line VVDD in region Rb can be made equal to or greater than the actual power supply capacity to the virtual power line VVDD in region Ra. In other words, it is possible to suppress differences in the power supply capacity to circuits in the standard cell region SCA that supply the virtual power line VVDD in regions Ra and Rb, where the arrangement density of bump BMP (VDD) is different from that of other regions.

[0052] (Second embodiment) Figure 8 is a plan view showing an overview of the layout of the standard cell block (SCB) in the second embodiment. Elements similar to those in the standard cell block (SCB) shown in Figure 3 are given the same reference numerals and detailed explanations are omitted. The standard cell block (SCB) shown in Figure 8 is provided in the internal circuit region (INTR) of the semiconductor device SEM, similar to Figure 1, and has the same circuit configuration as in Figure 2.

[0053] In this embodiment, the arrangement densities Ba and Bb of the bump BMP (VDD) are "0.5" and "0.2", respectively, as in Figure 3. In Figure 8, multiple power switch circuits PSW are arranged in region Rb instead of the multiple power switch circuits LPSW in Figure 3. That is, power switch circuits PSW having the same circuit configuration are arranged in regions Ra and Rb.

[0054] The other configurations of the standard cell block (SCB) are the same as in Figure 3. For example, the number of power switch circuits (PSW) Pb located in region Rb is twice the number of power switch circuits (PSW) Pa located in region Ra. That is, the arrangement density Pb ​​of power switch circuits (PSW) located in region Rb is twice the arrangement density Pb ​​of power switch circuits (PSW) located in region Ra. Note that the power switch circuits (PSW) may be stacked within the semiconductor device SEM.

[0055] As a result, similar to the first embodiment, the increase in wiring resistance of the power line VDD provided between the bump BMP (VDD) and the power switch circuit PSW in region Rb can be suppressed, and the IR drop of the power supply voltage VDD can be reduced. As a result, the decrease in the actual power supply capacity to the virtual power line VVDD in region Rb can be suppressed, and the actual power supply capacity to the virtual power line VVDD in region Rb can be made equal to or greater than the actual power supply capacity to the virtual power line VVDD in region Ra.

[0056] In this embodiment as well, the condition for making the actual power supply capacity to the virtual power line VVDD in region Rb equivalent to the actual power supply capacity to the virtual power line VVDD in region Ra can be determined by equation (1) described above. In equation (1), all elements except the arrangement density Ba and Bb of the bump BMP(VDD) and the number of power switch circuits PSW Pa and Pb are the same on both the left and right sides, so equation (1) can be transformed into equation (3). Ba × Pa = Bb × Pb ... (3)

[0057] In equation (3), "Pa" represents the power supply capability of the circuit alone to the virtual power line VVDD, without considering the placement density of bump BMPs (VDD) in region Ra. In equation (3), "Pb" represents the power supply capability of the circuit alone to the virtual power line VVDD, without considering the placement density of bump BMPs (VDD) in region Rb.

[0058] The left-hand side of equation (3), "Ba × Pa," represents the actual power supply capacity to the virtual power line VVDD, which is expressed as the product of the placement density of bump BMPs (VDD) and the power supply capacity in region Ra. The right-hand side of equation (1), "Bb × Pb," represents the actual power supply capacity to the virtual power line VVDD, which is expressed as the product of the placement density of bump BMPs (VDD) and the power supply capacity in region Rb. The left-hand side of equation (3), "Ba × Pa," is an example of the first parameter. The right-hand side of equation (3), "Bb × Pb," is an example of the second parameter.

[0059] The arrangement densities Ba and Bb of the bump BMP(VDD) are 0.5 and 0.2, respectively, as explained in Figure 3. The number of power switch circuits (PSW) Pa and Pb are 8 and 12, respectively. In this case, the left side of equation (3) becomes 4, and the right side of equation (3) becomes 2.4.

[0060] Therefore, the power supply capability of the power switch circuit PSW alone in region Rb to the virtual power line VVDD is insufficient compared to the power supply capability of the power switch circuit PSW alone in region Ra to the virtual power line VVDD. Here, the power supply capability of the power switch circuit PSW alone is the power supply capability of the power switch circuit PSW alone to the virtual power line VVDD, without considering the placement density of bump BMP(VDD) and the wiring resistance of the power line VDD.

[0061] However, for example, by setting the number of power switch circuits Pb in region Rb to 20, the right-hand side of equation (3) can be changed to "4", which is equal to the left-hand side of equation (3).

[0062] Furthermore, the threshold voltage of the p-channel transistor P of the power switch circuit LPSW may be set lower than the threshold voltage of the p-channel transistor P of the power switch circuit PSW. In this case, for example, even if the number of power switch circuits Pb provided in region Rb is 12, the product of the arrangement density of bump BMP (VDD) in regions Ra and Rb and the power supply capability of the circuit alone, including the power line VDD and the power switch circuit PSW, can be made equal to each other.

[0063] Furthermore, in the first embodiment (Figure 3) and one or more of the third to fifth embodiments described later (Figures 9, 10, and 11), the number Pb of power switch circuits PSW (or LPSW) in region Rb may be greater than the number Pa of power switch circuits PSW in region Ra.

[0064] As described above, the same effects as in the first embodiment can be obtained in this embodiment as well. For example, the placement density of power switches (PSW) in region Rb, where the placement density of bump BMPs (VDD) Bb is lower than that in region Ra, is made higher than the placement density of power switch circuits (PSW) in region Ra.

[0065] This makes it possible to suppress the increase in wiring resistance of the power line VDD provided between the bump BMP (VDD) and the power switch circuit LPSW in region Rb using the existing power switch circuit PSW, thereby reducing the IR drop of the power supply voltage VDD. As a result, even when the arrangement density Bb of bump BMPs (VDD) in region Rb is relatively low, the actual power supply capability to the virtual power line VVDD in region Rb can be made equal to or greater than the actual power supply capability to the virtual power line VVDD in region Ra.

[0066] (Third embodiment) Figure 9 is a plan view showing an overview of the layout of the standard cell block (SCB) in the third embodiment. Elements similar to those in the standard cell block (SCB) shown in Figure 3 are given the same reference numerals and detailed descriptions are omitted. The standard cell block (SCB) shown in Figure 9 is provided in the internal circuit region (INTR) of the semiconductor device SEM, similar to Figure 1, and has the same circuit configuration as Figure 2.

[0067] In this embodiment, the arrangement densities Ba and Bb of the bump BMP(VDD) are "0.5" and "0.2", respectively, as in Figure 3. Furthermore, the width Wb of the power line VDD(GL1) and ground line VSS(GL1) provided in region Rb is set to be thicker than the width Wa of the power line VDD(GL1) and ground line VSS(GL1) provided in region Ra. Note that the power line VDD(GL1) may be stacked within the semiconductor device SEM.

[0068] In region Rb, multiple power switch circuits PSW are arranged instead of the multiple power switch circuits LPSW shown in Figure 3. The number of power switch circuits PSW arranged in region Rb is equal to the number of power switch circuits PSW arranged in region Ra. That is, the number of gates GT of each switch transistor SWT in regions Rb and Ra is equal to each other, and the number of fins FIN of each switch transistor SWT in regions Rb and Ra is equal to each other.

[0069] Furthermore, the arrangement densities (arrangement pitches) Db and Da of the power line VDD (GL1) and ground line VSS (GL1) in regions Rb and Ra are equal to each other. The rest of the configuration of the standard cell block SCB is the same as in Figure 3.

[0070] In this embodiment as well, the condition for making the actual power supply capacity to the virtual power line VVDD in region Rb equivalent to the actual power supply capacity to the virtual power line VVDD in region Ra can be determined by equation (1) described above. In equation (1), all elements except the arrangement density Ba and Bb of the bump BMP(VDD) and the widths Wa and Wb of each power line VDD(GL1) are the same on both the left and right sides, so equation (1) can be transformed into equation (4). Ba × Wa = Bb × Wb ... (4)

[0071] In equation (4), "Wa" represents the power supply capability of the circuit alone to the virtual power line VVDD, without considering the placement density of bump BMPs (VDD) in region Ra. In equation (4), "Wb" represents the power supply capability of the circuit alone to the virtual power line VVDD, without considering the placement density of bump BMPs (VDD) in region Rb.

[0072] The left-hand side of equation (4), "Ba × Wa," represents the actual power supply capacity to the virtual power line VVDD, which is expressed as the product of the placement density of bump BMPs (VDD) and the power supply capacity in region Ra. The right-hand side of equation (4), "Bb × Wb," represents the actual power supply capacity to the virtual power line VVDD, which is expressed as the product of the placement density of bump BMPs (VDD) and the power supply capacity in region Rb. The left-hand side of equation (4), "Ba × Wa," is an example of the first parameter. The right-hand side of equation (4), "Bb × Wb," is an example of the second parameter.

[0073] In this embodiment, by making the width Wb of each power line VDD(GL1) in region Rb wider than the width Wa of each power line VDD(GL1) in region Ra, the actual power supply capability to the virtual power line VVDD in regions Rb and Ra can be made equivalent. Alternatively, the threshold voltage of the p-channel transistor P of the power switch circuit PSW in region Rb may be set lower than the threshold voltage of the p-channel transistor P of the power switch circuit PSW in region Rb.

[0074] Furthermore, in one or more of the first embodiment (Figure 3), the second embodiment (Figure 8), the fourth embodiment (Figure 10) described later, and the fifth embodiment (Figure 11) described later, the width Wb of the power line VDD(GL1) in region Rb may be thicker than the width Wa of the power line VDD(GL1) in region Ra. Also, when regions Ra and Rb are arranged side by side in the Y direction, the width of the power line VDD(GL2) provided in region Rb may be thicker than the width of the power line VDD(GL2) provided in region Ra.

[0075] As described above, the same effects as in the above-described embodiment can be obtained in this embodiment as well. For example, the width Wb of each power line VDD(GL1) in region Rb, where the arrangement density Bb of bump BMP(VDD) is lower than that of region Ra, is made wider than the width Wa of each power line VDD(GL1) in region Ra.

[0076] This suppresses the increase in wiring resistance of the power line VDD provided between the bump BMP(VDD) and the power switch circuit LPSW in region Rb, thereby reducing the IR drop of the power supply voltage VDD. As a result, even when the arrangement density Bb of bump BMP(VDD) in region Rb is relatively low, the actual power supply capability to the virtual power line VVDD in region Rb can be made equal to or greater than the actual power supply capability to the virtual power line VVDD in region Ra.

[0077] (Fourth embodiment) Figure 10 is a plan view showing an overview of the layout of the standard cell block (SCB) in the fourth embodiment. Elements similar to those in the standard cell block (SCB) shown in Figure 3 are given the same reference numerals and detailed descriptions are omitted. The standard cell block (SCB) shown in Figure 10 is provided in the internal circuit region (INTR) of the semiconductor device SEM, similar to Figure 1, and has the same circuit configuration as in Figure 2.

[0078] In this embodiment, the placement densities Ba and Bb of the bump BMP(VDD) are "0.5" and "0.2", respectively, as in Figure 3. Furthermore, the placement densities Db of the power line VDD(GL1) and ground line VSS(GL1) provided in region Rb are set higher than the placement densities Da of the power line VDD(GL1) and ground line VSS(GL1) provided in region Ra.

[0079] In other words, the arrangement pitch Db of the power line VDD(GL1) and ground line VSS(GL1) provided in region Rb is set to be smaller than the arrangement pitch Da of the power line VDD(GL1) and ground line VSS(GL1) provided in region Ra.

[0080] For example, the number of power lines VDD(GL1) provided in region Rb is four times the number of power lines VDD(GL1) provided in region Rb in Figure 3. The number of ground lines VSS(GL1) provided in region Rb is twice the number of ground lines VSS(GL1) provided in region Rb in Figure 3. Note that the power lines VDD(GL1) may be stacked within the semiconductor device SEM.

[0081] The number of power switch circuits Pb located in region Rb is equal to the number of power switch circuits Pa located in region Ra. The number of gates Gb and Ga of each switch transistor SWT in regions Rb and Ra are equal to each other, and the number of fins Fb and Fa of each switch transistor SWT in regions Rb and Ra are equal to each other. In addition, the widths Wa and Wb of the power lines VDD(GL1) provided in regions Ra and Rb are equal to each other. The other configurations of the standard cell block SCB are the same as in Figure 3.

[0082] In this embodiment as well, the condition for making the actual power supply capacity to the virtual power line VVDD in region Rb equivalent to the actual power supply capacity to the virtual power line VVDD in region Ra can be determined by equation (1) described above. In equation (1), all elements except the arrangement densities Ba and Bb of the bump BMP(VDD) and the arrangement pitches Da and Db of the power line VDD(GL1) are the same on both the left and right sides, so equation (1) can be transformed into equation (5). Ba × Da = Bb × Db ... (5)

[0083] In equation (5), "Da" represents the power supply capability of the circuit alone to the virtual power line VVDD, without considering the placement density of bump BMPs (VDD) in region Ra. In equation (5), "Db" represents the power supply capability of the circuit alone to the virtual power line VVDD, without considering the placement density of bump BMPs (VDD) in region Rb.

[0084] The left-hand side of equation (5), "Ba × Da," represents the actual power supply capacity to the virtual power line VVDD, which is the product of the placement density of the bump BMP (VDD) and the power supply capacity. The right-hand side of equation (5), "Bb × Db," represents the actual power supply capacity to the virtual power line VVDD. The left-hand side of equation (5), "Ba × Da," is an example of the first parameter. The right-hand side of equation (5), "Bb × Db," is an example of the second parameter.

[0085] In this embodiment, by making the arrangement pitch Db of the power line VDD(GL1) in region Rb smaller than the arrangement pitch Da of the power line VDD(GL1) in region Ra, the actual power supply capability to the virtual power line VVDD in regions Rb and Ra can be made equivalent. Alternatively, the threshold voltage of the p-channel transistor P of the power switch circuit PSW in region Rb may be set lower than the threshold voltage of the p-channel transistor P of the power switch circuit PSW in region Rb.

[0086] Furthermore, in one or more of the first to third embodiments (Figures 3, 8, and 9), the wiring pitch Db of the power line VDD(GL1) provided in region Rb may be smaller than the wiring pitch Da of the power line VDD(GL1) provided in region Ra. Also, when regions Ra and Rb are arranged side by side in the Y direction, the wiring pitch of the power line VDD(GL2) provided in region Rb may be smaller than the wiring pitch of the power line VDD(GL2) provided in region Ra.

[0087] As described above, the same effects as in the above-described embodiment can be obtained in this embodiment as well. For example, the wiring pitch Db of each power line VDD(GL1) in region Rb, where the arrangement density Bb of bump BMP(VDD) is lower than that of region Ra, is made smaller than the wiring pitch Da of each power line VDD(GL1) in region Ra.

[0088] This suppresses the increase in wiring resistance of the power line VDD provided between the bump BMP(VDD) and the power switch circuit LPSW in region Rb, thereby reducing the IR drop of the power supply voltage VDD. As a result, even when the arrangement density Bb of bump BMP(VDD) in region Rb is relatively low, the actual power supply capability to the virtual power line VVDD in region Rb can be made equal to or greater than the actual power supply capability to the virtual power line VVDD in region Ra.

[0089] (Fifth embodiment) Figure 11 is a plan view showing an overview of the layout of the standard cell block (SCB) in the fifth embodiment. Elements similar to those in the standard cell block (SCB) shown in Figure 3 are given the same reference numerals and detailed descriptions are omitted. The standard cell block (SCB) shown in Figure 11 is provided in the internal circuit region (INTR) of the semiconductor device SEM, similar to Figure 1, and the circuit block is the same as in Figure 2.

[0090] In this embodiment, the placement densities Ba and Bb of the bump BMP(VDD) are "0.5" and "0.2", respectively, as in Figure 3. Furthermore, the placement densities Db of the power line VDD(GL1) and ground line VSS(GL1) provided in region Rb are set higher than the placement densities Da of the power line VDD(GL1) and ground line VSS(GL1) provided in region Ra.

[0091] This allows the number of power lines VDD(GL1) provided in region Rb to be relatively greater than the number of power lines VDD(GL1) provided in region Ra, thereby reducing wiring resistance. For example, the number of power lines VDD(GL1) provided in region Rb is six times the number of power lines VDD(GL1) provided in region Rb in Figure 3. The number of ground lines VSS(GL1) provided in region Rb is equal to the number of ground lines VSS(GL1) provided in region Rb in Figure 3. Note that the power lines VDD(GL1) may be stacked within the semiconductor device SEM.

[0092] The number of power switch circuits Pb located in region Rb is equal to the number of power switch circuits Pa located in region Ra. The number of gates Gb and Ga of each switch transistor SWT in regions Rb and Ra are equal to each other, and the number of fins Fb and Fa of each switch transistor SWT in regions Rb and Ra are equal to each other. In addition, the widths Wa and Wb of the power lines VDD(GL1) provided in regions Ra and Rb are equal to each other. The other configurations of the standard cell block SCB are the same as in Figure 3.

[0093] In this embodiment, by making the arrangement density Db of power lines VDD(GL1) in region Rb higher than the arrangement density Da of power lines VDD(GL1) in region Ra, the actual power supply capability to the virtual power line VVDD in regions Rb and Ra can be made equivalent. Alternatively, the threshold voltage of the p-channel transistor P of the power switch circuit PSW in region Rb may be set lower than the threshold voltage of the p-channel transistor P of the power switch circuit PSW in region Rb.

[0094] Furthermore, in one or more of the first to third embodiments (Figures 3, 8, and 9), the arrangement density Db of power lines VDD(GL1) provided in region Rb may be higher than the arrangement density Da of power lines VDD(GL1) provided in region Ra. Also, when regions Ra and Rb are arranged side by side in the Y direction, the arrangement density of power lines VDD(GL2) provided in region Rb may be higher than the arrangement density of power lines VDD(GL2) provided in region Ra.

[0095] As described above, the same effects as in the above-described embodiment can be obtained in this embodiment as well. For example, the arrangement density Db of each power line VDD(GL1) in region Rb, where the arrangement density Bb of bump BMP(VDD) is lower than that in region Ra, is made higher than the wiring density Da of each power line VDD(GL1) in region Ra.

[0096] This suppresses the increase in wiring resistance of the power line VDD provided between the bump BMP(VDD) and the power switch circuit LPSW in region Rb, thereby reducing the IR drop of the power supply voltage VDD. As a result, even when the arrangement density Bb of bump BMP(VDD) in region Rb is relatively low, the actual power supply capability to the virtual power line VVDD in region Rb can be made equal to or greater than the actual power supply capability to the virtual power line VVDD in region Ra.

[0097] Although the present invention has been described above based on various embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be modified as long as they do not impair the spirit of the present invention, and can be appropriately determined according to their application. [Explanation of Symbols]

[0098] BMP Bump CNTL control circuit FIN GL1, GL2 Global Wiring Layers GT Gate IN1, IN2 Input Terminals INS insulating film INTR Internal circuit area IOC, IOCP I / O cell IV1, IV2 Inverter LI local wiring M1, M2 wiring layer OUT1, OUT2 output terminals P p Channel Transistor PAD PSW, LPSW Power Switch Circuit Ra, Rb region SCA Standard Cell Area SCB Standard Cell Block SEM (Semiconductor Equipment) SIG signal STI insulating film SUB Semiconductor Substrate SWCNT Switch Control Signal SWT Switch Transistor VDD, VDDM power line VIA1, VIA2 VIA-G1, VIA-G2 VSS ground wire VVDD Virtual Power Line WBRD (Wall-Bridged Circuit Board)

Claims

1. First power line and, The second power line and A circuit region having a first region in which a plurality of first power terminals connected to the first power line are arranged at a first density in a plan view, and a second region in which a plurality of second power terminals connected to the first power line are arranged at a second density lower than the first density in a plan view, A plurality of first power switch circuits are provided in the first region and connected to the first power line and the second power line, A plurality of second power switch circuits are provided in the second region and connected to the first power line and the second power line, It has, The first power switch circuit includes a first fin and a first transistor having a plurality of first gate electrodes provided on the first fin. The second power switch circuit includes a second fin and a second transistor provided on the second fin and having a plurality of second gate electrodes, which are more numerous than the first gate electrode. Semiconductor device.

2. The second fin is longer than the first fin in a plan view. The semiconductor device according to claim 1.

3. The first transistor is connected to the first power line and the second power line, The second transistor is connected to the first power line and the second power line. The semiconductor device according to claim 1.

4. It has a third power line, The first transistor has a first portion and a second portion that are positioned on either side of the third power line in a plan view. The semiconductor device according to claim 1.

5. The first power switch circuit has a first inverter and a second inverter located on either side of the third power line in a plan view. The semiconductor device according to claim 4.

6. It has a third power line, The second transistor has a first portion and a second portion that are positioned on either side of the third power line in a plan view. The semiconductor device according to claim 1.

7. The second power switch circuit has a third inverter and a fourth inverter located on either side of the third power line in a plan view. The semiconductor device according to claim 4.

8. The first transistor is a p-channel transistor, The second transistor is a p-channel transistor. The semiconductor device according to claim 1.

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