Reduction of line bending during metal filling processes

Abstract

Methods to mitigate line bending during feature filling include depositing and / or inhibiting the amorphous layer during filling.

Description

[Technical Field]

[0001] Reference As part of this application, a PCT application is filed concurrently with this specification. Each application specified in the concurrently filed PCT application, for which this application claims interest or priority, is incorporated herein by reference in its entirety for all purposes. [Background technology]

[0002] The deposition of conductive materials is an essential part of many semiconductor fabrication processes. These materials can be used for horizontal interconnects, vias between adjacent metal layers, contacts between metal layers and devices on silicon substrates, and high aspect ratio features. In one example of a deposition process on a semiconductor substrate, the substrate is heated to process temperature in a vacuum chamber, and a very thin portion of the film, which acts as a seed or nucleation layer, is deposited. The rest of the film (bulk layer) is then deposited on top of the nucleation layer by exposing the substrate to two reactants simultaneously. The bulk layer generally deposits more rapidly than the nucleation layer. However, as devices shrink and the industry utilizes more complex patterning schemes, depositing thin films to fill features has become a challenge.

[0003] The background information provided herein is intended to provide a general overview of the contents of this disclosure. Any research by the inventors named at this time, as well as any description that is not otherwise considered prior art at the time of filing, within the scope described in this background information section, shall not be recognized as prior art to this disclosure, whether express or implied. [Overview of the Initiative]

[0004] A method for mitigating line bending during feature filling is described. This method can be used to mitigate line bending during the filling of adjacent features. In some embodiments, the method involves depositing an amorphous metal-based layer. In some embodiments, the method involves depositing a metal-based layer containing impurities. According to various embodiments, the metal-based layer can reduce stress and / or break metal-metal bonds that may cause line bending. In some embodiments, the method involves surface treatment of the layer with an inhibitory chemical. According to various embodiments, the surface treatment can roughen the surface and reduce line bending.

[0005] One aspect of the present disclosure relates to a method comprising (a) providing a substrate having a plurality of spaced features, each feature having a feature opening width, the width of which narrows from the top to the bottom of the feature, (b) conformally treating the surface by exposing the surface to a metal-containing precursor and an inhibitory chemical, and (c) depositing a bulk metal layer on the features after the surface has been treated.

[0006] In some embodiments, the width of the bottom of each feature is between 0 nm and 90% of the width at the top of the feature. In some embodiments, the metal is selected from the group consisting of tungsten, ruthenium, molybdenum, and cobalt. In some embodiments, operations (b) and (c) are repeated once or more times to fill the feature. In some embodiments, the bulk metal layer deposited in (c) completely fills the feature. In some embodiments, operation (b) is carried out without depositing a continuous film on the feature. In some embodiments, operation (b) includes heterogeneous adsorption of a metal precursor and an inhibitory compound. In some embodiments, operation (b) includes the deposition of a discontinuous film. In some embodiments, the method further includes depositing a nucleated layer on the feature such that (b) includes treating the nucleated layer surface. In some embodiments, operation (b) increases the surface roughness of the bulk metal layer. In some embodiments, operation (b) is a non-plasma thermal process. In some embodiments, operation (b) is a plasma-based process. In some embodiments, the inhibitory chemical includes nitrogen-containing compounds. In some embodiments, the inhibitory chemical is ammonia.

[0007] Another aspect of the present disclosure relates to a method comprising (a) providing a substrate having a plurality of spaced features, each feature having a feature opening width, and at least some of the widths of the features narrowing from the top to the bottom of the features, (b) depositing a conformal amorphous metal-based layer on the features, and (c) depositing a bulk metal layer on the features after depositing the conformal amorphous metal-based layer. In some embodiments, the width at the bottom of each feature is between 0 nm and 90% of the width at the top of the feature. In some embodiments, the metal is selected from the group consisting of tungsten, ruthenium, molybdenum, and cobalt. In some embodiments, operations (b) and (c) are repeated once or more times to fill the features. In some embodiments, the method further includes annealing the conformal amorphous metal-based layer.

[0008] In some embodiments, features are spaced apart at a pitch of approximately 10 nm to 60 nm between adjacent features. In some embodiments, the method further includes depositing a metallic nucleation layer on the features. In some embodiments, the metallic layer contains at least 50 atomic percent of metal. In some embodiments, the metallic layer further includes one or more of boron (B), nitrogen (N), carbon (C), silicon (Si), and germanium (Ge).

[0009] Another aspect of the present disclosure relates to a method comprising (a) providing a substrate having a plurality of spaced features, each feature having a feature opening width, the width of which narrows from the top to the bottom of the feature, (b) depositing a bulk metal layer on the features, and (c) depositing an amorphous metal-based layer on the features after depositing the bulk metal layer on the features.

[0010] In some embodiments, the width of the bottom of each feature is between 0 nm and 90% of the width of the top of each feature. In some embodiments, the metal is selected from the group consisting of tungsten, ruthenium, molybdenum, and cobalt. In some embodiments, the method further includes filling the features by repeating (b) once or more times. In some such embodiments, the method further includes filling the features by repeating (c) once or more times. In some embodiments, the method further includes annealing a conformal amorphous metal-based layer. In some embodiments, the features are spaced apart at a pitch of about 10 nm to 60 nm between adjacent features. In some embodiments, the method further includes depositing a metal nucleation layer on the features. In some embodiments, the metal-based layer contains at least 50% metal. In some embodiments, the metal-based layer further includes one or more of boron (B), nitrogen (N), carbon (C), silicon (Si), and germanium (Ge).

[0011] Another aspect of the present disclosure provides a substrate having a plurality of features spaced apart, each feature having a feature opening width, and at least some of the widths of the features narrowing from the top of the feature to the bottom of the feature, depositing a conformal metal-based layer on the features, the metal-based layer including a metal selected from tungsten (W), ruthenium (Ru), molybdenum (Mo), titanium (Ti), tantalum (Ta), and cobalt (Co), and the metal-based layer including at least 5% (atomic) of an impurity selected from boron (B), nitrogen (N), carbon (C), silicon (Si), germanium (Ge), and combinations thereof. In some embodiments, the plurality of features are filled with a film selected from titanium nitride and tantalum nitride.

[0012] These and other aspects of the present disclosure are further described below with reference to the drawings.

Brief Description of the Drawings

[0013] [Figure 1] FIG. 1 is a schematic diagram of an exemplary film on a substrate.

[0014] [Figure 2A] FIG. 2A is a schematic diagram of an example of a dynamic random access memory (DRAM) architecture including buried word lines (bWLs) in a silicon substrate.

[0015] [Figure 2B] FIG. 2B is a schematic diagram of line bending.

[0016] [Figure 2C] FIG. 2C is a schematic diagram of the dipping phenomenon.

[0017] [Figure 2D] FIG. 2D is a graph showing the interatomic force as a function of the tungsten-tungsten bond radius.

[0018] [Figure 3A] Figure 3A shows schematic examples of various structures on which metals such as tungsten can be deposited, according to certain disclosed embodiments. [Figure 3B] Figure 3B shows schematic examples of various structures in which metals such as tungsten can be deposited, according to certain disclosed embodiments. [Figure 3C] Figure 3C shows schematic examples of various structures on which metals such as tungsten can be deposited, according to certain disclosed embodiments. [Figure 3D] Figure 3D shows schematic examples of various structures in which metals such as tungsten can be deposited, according to certain disclosed embodiments. [Figure 3E] Figure 3E shows schematic examples of various structures on which metals such as tungsten can be deposited, according to certain disclosed embodiments. [Figure 3F] Figure 3F shows schematic examples of various structures in which metals such as tungsten can be deposited, according to certain disclosed embodiments. [Figure 3G] Figure 3G shows schematic examples of various structures on which metals such as tungsten can be deposited, according to certain disclosed embodiments. [Figure 3H] Figure 3H shows schematic examples of various structures in which metals such as tungsten can be deposited, according to certain disclosed embodiments. [Figure 3I] Figure 3I shows schematic examples of various structures in which metals such as tungsten can be deposited, according to certain disclosed embodiments.

[0019] [Figure 4A] Figure 4A is a process flow diagram illustrating the operation of the method being implemented according to a particular disclosed embodiment. [Figure 4B] Figure 4B is a process flow diagram illustrating the operation of the method being implemented according to a particular disclosed embodiment. [Figure 4C] Figure 4C is a process flow diagram illustrating the operation of the method being implemented according to a particular disclosed embodiment.

[0020] [Figure 5A] Figure 5A is a schematic diagram of various operations during feature filling according to a specific embodiment. [Figure 5B] Figure 5B is a schematic diagram of various operations during feature filling according to a specific embodiment. [Figure 5C] Figure 5C is a schematic diagram of various operations during feature filling according to a specific embodiment.

[0021] [Figure 6] Figure 6 is a timing sequence diagram illustrating exemplary cycles in various ways according to a particular disclosed embodiment. [Figure 7] Figure 7 is a timing sequence diagram illustrating exemplary cycles in various ways according to a particular disclosed embodiment. [Figure 8] Figure 8 is a timing sequence diagram illustrating exemplary cycles in various ways according to a particular disclosed embodiment. [Figure 9] Figure 9 is a timing sequence diagram illustrating exemplary cycles in various ways according to a particular disclosed embodiment. [Figure 10] Figure 10 is a timing sequence diagram illustrating exemplary cycles in various ways according to a particular disclosed embodiment.

[0022] [Figure 11] Figure 11 is a schematic diagram of an exemplary process tool for carrying out the disclosed embodiments.

[0023] [Figure 12] Figure 12 is a schematic diagram of an exemplary station for carrying out the disclosed embodiment. [Modes for carrying out the invention]

[0024] The following description includes many specific details to provide a complete understanding of the presented embodiments. The disclosed embodiments may be carried out without some or all of these specific details. In other examples, well-known process behaviors are not described in detail so as not to unnecessarily obscure the disclosed embodiments. The disclosed embodiments are described in conjunction with specific embodiments, but it should be understood that this is not intended to limit the disclosed embodiments.

[0025] Metal fillings, such as tungsten (W) fillings, are frequently used in semiconductor device fabrication to form electrical contacts. As devices scale to smaller technology nodes and more complex patterning structures are used, tungsten filling presents various challenges. One challenge is reducing the fluorine concentration or content in the deposited tungsten film. Smaller features with the same fluorine concentration in the tungsten film as larger features have a more substantial impact on device performance. For example, smaller features result in thinner film deposition. Consequently, fluorine in the deposited tungsten film is more likely to diffuse through the thin film, potentially causing device failure.

[0026] One method to prevent fluorine diffusion involves depositing one or more barrier layers before depositing tungsten to prevent fluorine from diffusing from tungsten to other layers of the substrate, such as oxide layers. For example, Figure 1 shows an exemplary stack of layers deposited on a substrate 190. The substrate 190 includes a silicon layer 192, an oxide layer 194 (e.g., titanium oxide (TiOx), tetraethyl orthosilicate (TEOS) oxide, etc.), a barrier layer 196 (e.g., titanium nitride (TiN)), a tungsten nucleation layer 198, and a bulk tungsten layer 199. The barrier layer 196 is deposited to prevent fluorine diffusion from the bulk tungsten layer 199 and the tungsten nucleation layer 198 to the oxide layer 194. However, as the device shrinks, the barrier layer becomes thinner, and fluorine may still diffuse from the deposited tungsten layer. Chemical vapor deposition (CVD) of bulk tungsten carried out at high temperatures reduces fluorine content, but such films have insufficient step coverage.

[0027] Another challenge is reducing the resistance of deposited tungsten films. Thinner films tend to have higher resistance than thicker films. As features become smaller, scattering effects in thinner tungsten films increase the contact or line resistance of the tungsten. Low resistivity tungsten films minimize power loss and overheating in integrated circuit designs. Tungsten nucleated layers typically have higher electrical resistivity than the bulk layer above them. Barrier layers deposited on contacts, vias, and other features can also have high resistivity. Furthermore, thin barriers and tungsten nucleated films occupy a larger percentage of smaller features, increasing the overall resistance of the features. The resistivity of a tungsten film depends on the thickness of the deposited film, so resistivity increases as the thickness decreases due to boundary effects.

[0028] Another challenge is reducing the stress on the deposited film. Thin tungsten films tend to have increased tensile stress. Conventional techniques for depositing bulk tungsten films by chemical vapor deposition result in tensile stresses exceeding 2.5 GPa for a 200 Å film. High thermal tensile stress causes the substrate to curl, making subsequent processing difficult. For example, subsequent processes may include chemomechanical planarization, material deposition, and / or clamping of the substrate to a substrate holder, with the process carried out in a chamber. However, these processes often depend on a flat substrate, and a curled substrate results in uneven processing or inability to process the substrate. While existing methods exist to reduce stress in films of other materials, such as annealing, tungsten has a high melting point and therefore does not have surface mobility that would allow for particle movement or modification once deposited.

[0029] Another challenge is reducing line bending, a phenomenon observed, for example, in substrates with multiple features having a narrow pitch, or in substrates with multiple high-aspect-ratio features adjacent to each other. Line bending in dynamic random-access memory (DRAM) embedded word-line structures (bWLs) during tungsten filling is thought to be caused by grain boundary fusion (sometimes called a "zipping" mechanism). When grain boundaries are formed, metal-metal bonds between adjacent tungsten surfaces (such as tungsten films growing on the sidewalls of features) cause strain, bending the silicon fins (lines) that separate the bWLs. Atomic layer deposition (ALD) and CVD tungsten filling techniques can result in severe bending of the bWL structure. This line bending leads to non-uniformity of tungsten recesses and contact landing problems in downstream processes, resulting in DRAM yield losses.

[0030] ALD can be used to form tungsten films that exhibit low stress, low fluorine, and low resistivity, but forms films only on surfaces that allow such growth. As devices are scaled down and features become narrower, there may be a dipping mechanism that causes tensile stress, high fluorine incorporation, and affects resistivity, resulting in a rough morphology.

[0031] Certain embodiments relate to methods and related apparatus for forming tungsten wordlines in memory devices. FIG. 2A illustrates a schematic example of a DRAM architecture including an embedded wordline (bWL) 11 within a silicon substrate 9. The bWL 11 is formed within a trench etched into the silicon substrate 9. The bWL 11 is tungsten deposited on the silicon substrate 9 and is capped by a SiN passivation 5. The trench is lined with a conformal barrier layer 12 and an insulating layer 13 disposed between the conformal barrier layer 12 and the silicon substrate 9. In the example of FIG. 2A, the insulating layer 13 can be a gate oxide layer formed from a material such as silicon oxide. Examples of conformal barrier layers include TiN and tungsten-containing barrier layers. The tungsten-containing conformal barrier layer is WB x , WSi x , WGe x , WC x , WN x and other binary compounds, and WB x N y , WSi x N y , WGe x N y , WSi x C y , WB x C y , WGe x C y , WC x N y and other ternary compounds, and WB x Ge y N z , WGe x C y N zThis can include quaternary compounds such as, and x, y, and z are numbers greater than zero.

[0032] The filling process for DRAM bWL trenches can distort them, resulting in significantly uneven final trench width and resistance Rs. Figure 2B shows an unfilled (201) and filled (205) narrow asymmetric trench structure DRAM bWL exhibiting line bending after filling. As shown, multiple features are illustrated on the substrate. These features are spaced apart, and in some embodiments, adjacent features have a pitch of approximately 5 nm to 60 nm, or 20 nm to 60 nm, or 10 nm to 30 nm, or 10 nm to 40 nm, or 20 nm to 40 nm. The pitch is defined as the distance from the central axis of one feature to the central axis of an adjacent feature. Unfilled features are generally V-shaped, as shown in feature 203, and have sloping sidewalls where the width of the feature narrows from the top to the bottom of the feature. Features widen from the bottom 213b to the top 213a of the feature. After tungsten filling, severe line bending is observed on substrate 205. Although not constrained by any particular theory, it is thought that cohesive forces between opposing surfaces of the trench pull the sides of the trench together, as illustrated by arrow 207. This phenomenon is shown in Figure 2C and can be characterized as "zipping up" the feature. When feature 203 is filled, more force is applied from the central axis 299 of feature 203, causing line bending. Thus, the tungsten 243a and 243b deposited on the sidewalls of feature 203 interact in close proximity, and because the tungsten-tungsten bonding radius r is small, cohesive interatomic forces are generated between the smoothly growing surfaces of the tungsten, pulling the sidewalls together and thereby causing line bending. Figure 2D shows the interatomic forces as a function of the tungsten-tungsten bonding radius r. As can be seen, the cohesive forces exist at a specific value of r. Even low-stress tungsten films deposited by the ALD process can experience severe line bending during filling.Although V-shaped features are described herein, the method can also be advantageously applied to features of any profile that undergo line bending during feature filling.

[0033] This specification describes a method for filling features with metal, as well as related systems and apparatus for reducing line bending. While various examples and embodiments described herein are given in relation to tungsten, it is understood that the disclosed embodiments are suitable for depositing various metals, including, but not limited to, ruthenium, molybdenum, and cobalt. Examples of applications include logic and memory contact filling, DRAM embedded word line filling, vertically integrated memory gate / word line filling, and 3D integration with through-silicon vias (TSVs). The methods described herein can be used to fill vertical features such as tungsten vias, and horizontal features such as 3D-NAND word lines. The methods may be used for conformal filling and bottom-up or inside-out filling.

[0034] The methods described herein are carried out on a substrate that can be housed in a chamber. The substrate may be a silicon wafer, for example, a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, and may include a wafer on which one or more layers of materials such as dielectric materials, conductive materials, or semiconducting materials are deposited. The substrate may have features such as via holes or contact holes that can be characterized by V-shaped sidewalls, narrow and / or reentrant openings, constrictions within features, and one or more high aspect ratios. Features may be formed in one or more of the aforementioned layers. For example, features may be formed at least partially in a dielectric layer. In some embodiments, features may have aspect ratios of at least about 2:1, at least about 4:1, at least about 6:1, at least about 10:1, or higher. An example of a feature is a hole or via in a semiconductor substrate or a layer on the substrate. Features may be spaced apart on the substrate by a pitch between adjacent features of about 20 nm to about 40 nm.

[0035] Figures 3A to 3G are schematic examples of various structures on which tungsten can be deposited according to the disclosed embodiments. Figure 3A shows an example of a cross-sectional view of a vertical feature 301 filled with tungsten. Feature 301 may include a feature hole 305 in the substrate 303. Hole 305 or other features may have dimensions close to the opening, e.g., an opening diameter or line width of about 10 nm to 500 nm, e.g., about 25 nm to about 300 nm. Feature hole 305 may be called an unfilled feature or simply a feature. Feature 301, and any feature, may be partially characterized by an axis 318 extending through the center of the hole 305 over the length of the feature, with vertical features having a vertical axis and horizontal features having a horizontal axis.

[0036] In some embodiments, the feature is a trench in the 3D NAND structure. For example, the substrate may include a word-line structure having at least 60 lines, 18 to 48 layers or several hundred layers, and trenches with a depth of at least 200 Å or several microns. Another example is a trench in the substrate or layer. The feature may be of any depth. In various embodiments, the feature may have an underlying layer such as a barrier layer or adhesive layer. Non-limiting examples of underlying layers include dielectric layers and conductive layers, e.g., silicon oxide, silicon nitride, silicon carbide, metal oxides, metal nitrides, metal carbides, and metal layers.

[0037] Figure 3B shows an example of a feature 301 having a reentrant profile. A reentrant profile is a profile that narrows from the bottom, closed end, or interior of the feature to the feature opening. According to various embodiments, the profile narrows gradually and / or may include an overhang at the feature opening. Figure 3B shows an example of the latter, where the underlayer 313 backs the sidewall or inner surface of the feature hole 305 of the feature 301. The underlayer 313 may be, for example, a diffusion barrier layer, an adhesive layer, a nucleating layer, a combination thereof, or any other applicable material. Non-limiting examples of underlayers may include dielectric and conductive layers, e.g., silicon oxide, silicon nitride, silicon carbide, metal oxides, metal nitrides, metal carbides, and metal layers. In certain embodiments, the underlayer may be one or more of Ti, TiN, WN, TiAl, and W. The lower layer 313 forms an overhang 315, which makes the lower layer 313 thicker near the opening of feature 301 than inside feature 301.

[0038] In some embodiments, features may be filled with one or more constrictions within the feature. Figure 3C shows examples of various filled features with constrictions. Each of examples (a), (b), and (c) in Figure 3C includes a constriction 309 at the midpoint within the feature. The constriction 309 may be, for example, about 15 nm to 20 nm wide. The constriction can cause pinch-off when depositing tungsten into the feature using conventional techniques, and the deposited tungsten blocks further deposits through the constriction before that portion of the feature is filled, resulting in a void in the feature. Example (b) further includes a liner / barrier overhang 315 at the feature opening. Such an overhang may also be a potential pinch-off point. Example (c) includes a constriction 312 that is further from the field area than the overhang 315 in example (b).

[0039] Horizontal features, such as 3D memory structures, can also be filled. Figure 3D shows an example of a horizontal feature 350 including a constriction 351. For example, the horizontal feature 350 could be a word line of a 3D NAND structure.

[0040] In some embodiments, the presence of pillars in 3D NAND or other structures can result in constrictions. For example, Figure 3E shows a plan view of a pillar 325 within a 3D NAND or vertically integrated memory (VIM) structure 348, and Figure 3F shows a simplified schematic cross-sectional view of the pillar 325. The arrows in Figure 3E represent deposited material. Because the pillar 325 is located between area 327 and a gas inlet or other deposit source, adjacent pillars may result in constrictions 351, which present challenges to void-free filling in area 327.

[0041] Structure 348 can be formed, for example, by depositing a stack of alternating interlayer dielectric layers 329 and a sacrificial layer (not shown) on a substrate 300 and selectively etching the sacrificial layer. The interlayer dielectric layers may be, for example, silicon oxide and / or silicon nitride layers, and the sacrificial layer is a material that can be selectively etched with an etchant. Subsequently, etching and deposition processes can be carried out to form pillars 325 that may contain the channel region of the completed memory device.

[0042] The main surface of the substrate 300 can extend in the x and y directions, and the pillars 325 are oriented in the z direction. In the examples of Figures 3E and 3F, the pillars 325 are arranged in an offset manner such that directly adjacent pillars 325 in the x direction are offset from each other in the y direction, and vice versa. According to various embodiments, the pillars (and the corresponding constrictions formed by adjacent pillars) can be arranged in any number of ways. Furthermore, the pillars 325 can be any shape, including circular, square, etc. The pillars 325 can include annular semiconducting material or circular (or square) semiconducting material. A gate dielectric may surround the semiconducting material. The areas between each interlayer dielectric layer 329 can be filled with tungsten. Thus, the structure 348 has a plurality of stacked horizontal features extending in the x and / or y directions that are filled.

[0043] Figure 3G provides another example of a diagram of a 3D NAND or other structure including a horizontal feature, e.g., a pillar constriction 351. The example in Figure 3G is open-ended, allowing the material to be deposited to enter horizontally from both sides, as indicated by the arrows. (Note that the example in Figure 3G can be viewed as a 2D rendering of the structure as a 3D feature, and Figure 3G is a cross-sectional view of the area to be filled, and the pillar constriction shown in the figure represents a constriction as seen in a plan view, not a cross-sectional view.) In some embodiments, a 3D structure can be characterized by an area to be filled that extends along two or three dimensions (e.g., in the x and y directions, or in the x, y, and z directions, as in the example in Figure 3F), which can present more challenges to filling than filling a hole or trench that extends along one or two dimensions. For example, controlling the filling of a 3D structure can be difficult because the depositing gas may enter the feature from multiple dimensions.

[0044] Figure 3H provides an example of a cross-sectional view of a V-shaped feature. Figure 3H includes a tungsten-filled feature 301 containing a feature hole 305 in a substrate 303. The hole has dimensions close to the opening (e.g., the opening diameter or line width w, which may be about 10 nm to about 20 nm, or about 15 nm). The width is measured by the distance between the side walls of the feature. The width may vary from the top of the feature (opening diameter or line width w) to the bottom of the feature at the feature opening. The feature hole 305 is partially characterized by an axis 318. The V-shaped feature 301 contains a depth 350 which may be about 80 nm to about 120 nm, or about 100 nm. In various embodiments, the sidewalls intersect at the bottom of the feature, or in some embodiments, at point 395 where the bottom of the feature lies on a flat bottom surface, where the distance from one sidewall to the other may be about 0.1w to about 0.9w, or the percentage of the line width w at the opening may be about 10% to about 90% of the width w. The feature may have an aspect ratio of 2:1 to about 10:1, or about 6:1 to about 8:1, or about 6:1, or about 8:1. The line pitch may be about 20nm to about 40nm. The bottom of the feature, characterized as a region at 50% to 70% of the depth of the feature, may have a sidewall width of 0nm to about 20nm.

[0045] Figure 3I provides another example of a cross-sectional view of a V-shaped feature. A V-shaped feature as described herein refers to a feature that narrows in width from the top field level of the substrate to the bottom of the feature. Figure 3I includes a feature 301 filled with a metal such as tungsten, which contains a feature hole 305 in the substrate 303. The hole has dimensions close to the opening (e.g., the opening diameter or line width w, which may be about 10 nm to about 20 nm or about 15 nm). The bottom of the feature 396 has a width narrower than the width w. For example, the bottom of the feature 396 may have a width of 1% to 90% of the width w, or 1% to 50% of the width w, or 10% to 20% of the width w.

[0046] In various disclosed embodiments, such as those shown in Figure 2B, multiple V-shaped features are present on the substrate. These multiple features on the substrate are defined as adjacent features having a distance of 20 nm to 40 nm or less from each other. In various embodiments, such multiple features include all V-shaped features that may have the shapes shown in Figure 3H or Figure 3I.

[0047] Examples of feature filling for horizontal and vertical features are described below. Note that the examples are applicable to both horizontal and vertical features. Furthermore, note that in the following description, the term “lateral” may be used to refer to a direction generally perpendicular to the feature axis, and the term “vertical” may be used to refer to a direction generally along the feature axis.

[0048] While the following description focuses on tungsten feature filling, embodiments of this disclosure can also be implemented for filling features with other materials. For example, feature filling using one or more techniques described herein can be used to fill features with other materials including Mo, Co, and Ru. Furthermore, it can also be used to fill features with any material that undergoes grain growth in a vapor deposition process.

[0049] Some embodiments involve the deposition of an amorphous layer during the filling of adjacent trenches. The amorphous layer may be deposited with a thickness of 10 Å to 1 nm in certain embodiments. According to various embodiments, the amorphous layer is deposited conformally to the feature. The amorphous layer blocks the aforementioned zipping mechanism and reduces stress propagation to the dielectric within the feature.

[0050] Amorphous films contain metals (e.g., W, Mo, Co, Ru, etc.) and some amount of impurities. Examples of such impurities include boron (B), nitrogen (N), carbon (C), silicon (Si), and germanium (Ge). The presence of impurities makes the metal film amorphous, preventing the zipping mechanism and / or preventing stress propagation from the bulk layer to the dielectric. Exemplary impurity levels include 5% to 50% atoms, with the remainder of the film being metal. In some embodiments, the amorphous layer contains at least 50 atomic% metal, at least 60 atomic%, at least 70 atomic%, at least 80 atomic%, or at least 90 atomic% metal.

[0051] Amorphous films may contain mixtures of metals and metal compounds. For example, an amorphous layer may have a mixture of tungsten (W) and tungsten nitride (WN), where the total amount of W in the amorphous layer is at least 50 atomic%, and the total amount of N in the amorphous layer is 5 atomic% to 50 atomic%. In another example, the amorphous film is a mixture of W and B and / or N, where the total amount of B and / or N in the film is 5 atomic% to 50 atomic%.

[0052] Amorphous layers can be deposited at various stages of the filling process according to different embodiments. Figure 4A provides an example of a process flow for filling adjacent trenches. The process begins with depositing a conformal nucleation layer in adjacent trenches (402). A conformal amorphous metal-based film is then deposited in the trenches (404). In this example, the amorphous layer is relatively thin, for example, 10 Å–50 Å, 10 Å–40 Å, or 10 Å–20 Å. Next, a bulk metal layer is deposited on top of the amorphous layer (406). In some embodiments, the bulk metal layer can be deposited to fill the trenches. In other embodiments, operations 404 and 406 may be repeated once or more times to fill the trenches (408). Operations 404 and 406 can be advantageously repeated if a zipping mechanism occurs when conformal bulk deposition is performed. The bulk layer may be, for example, a high-purity layer having an atomic purity of at least 97% or 99% of the elemental metal.

[0053] In the example shown in Figure 4A, one or more annealing operations can be performed to reduce the resistivity of the amorphous layer. According to various embodiments, thermal annealing can be performed after the features have been filled (e.g., after operation 408, if performed), optionally after the deposition of the amorphous layer (e.g., between operations 404 and 406), or optionally after the deposition of part or all of the bulk layer (e.g., during or after operation 406).

[0054] The process described with respect to Figure 4A may be modified according to various embodiments. In some embodiments, operation 406 is not performed. For example, in some embodiments, the entire feature is filled with an amorphous layer so that only operation 404 is performed. In some embodiments, a nucleation layer is deposited, followed by an amorphous layer, to fill the feature so that only operations 402 and 404 are performed. Furthermore, in some embodiments, the nucleation layer is not deposited, and only operations 404 and 406 (and optionally 408) are performed.

[0055] Figure 4B provides another example of a process flow for filling adjacent trenches. The process begins with depositing a conformal nucleation layer in adjacent trenches, as in the example in Figure 4A (402). However, in this example, the bulk metal layer is deposited on top of the underlying layer (e.g., the nucleation layer) (414). This is followed by the deposition of an amorphous layer (416). Operations 414 and 416 may be repeated once or more times to fill the trenches (418). The bulk layer may be, for example, a high-purity layer having an atomic purity of at least 97% or 99% of the elemental metal. In some embodiments, after the first instance of operation 416, the deposition of the amorphous layer is stopped and operation 414 is repeated to complete the filling of the trenches.

[0056] In the example shown in Figure 4B, one or more annealing operations can be performed to reduce the resistivity of the amorphous layer. According to various embodiments, thermal annealing can be performed only after the features have been filled (e.g., after operation 418, if performed) or, optionally, only after the amorphous layer has been deposited (e.g., after operation 416).

[0057] The process described with respect to Figure 4B may be modified according to various embodiments. In some embodiments, the nucleation layer is not deposited, and only operations 414 and 416 are performed. In some embodiments, where the deposition of bulk metal occurs after the deposition of the amorphous layer, a treatment to remove or reduce inhibitory effects may be performed before bulk deposition. Such a treatment may involve one or more immersion steps of a reducing agent (e.g., diborane and / or silane and / or hydrogen) and a metal precursor. In some embodiments, the deposition of the bulk layer on the amorphous layer may be preceded by the deposition of the nucleation layer. For example, one sequence may involve metal nucleation / metal bulk / amorphous layer / metal nucleation / bulk metal.

[0058] Figures 5A and 5B show schematic examples of adjacent trenches filled by the methods shown in Figures 4A and 4B, respectively. In Figure 5A, the trench is lined with a barrier layer 501, e.g., TiN, and includes a conformal nucleation layer 505 (e.g., a nucleation layer with a thickness of 2 nm), a conformal amorphous layer 503 (e.g., about 10 nm), and is filled with a bulk layer 507.

[0059] In Figure 5B, the trench is lined with a barrier layer 501, e.g., TiN, and includes a conformal nucleation layer 503 (e.g., a nucleation layer with a thickness of 2 nm), a conformal bulk layer 507, and is filled with an amorphous layer 505. The method in Figure 4B reduces the zipping effect when closing the seam, while the method in Figure 4A can be understood as preventing stress transfer from the bulk layer to the nucleation layer, barrier layer, and dielectric by inserting an amorphous layer between the bulk layer and the dielectric. Both effects may be advantageously observed in embodiments in which operations 408 and 418 are performed.

[0060] The presence of an amorphous film reduces line bending, but it is a film with higher resistivity than the bulk metal film. The reduction of line bending and resistivity can be appropriately controlled by controlling the thickness of each film, as well as the amount of impurities in the amorphous film. In the method shown in Figure 4B, the amorphous layer can be deposited at or near the location where a zip-up mechanism would occur, in order to prevent the zip-up mechanism from occurring. This can be determined experimentally, by modeling, or theoretically. In the method shown in Figure 4A, the thickness of the central amorphous film can be controlled to mitigate the increase in resistivity.

[0061] A reduction in line bending was observed from two processes used to fill adjacent trenches and form lines by using a filling process that included an amorphous film. Process A is the reference process (without amorphous film). Process A: Nucleation + W-CVD (WF6 / H2CVD) Process B: Nucleation + Amorphous film deposited from WF6 and NH3. The temperature was approximately 300°C, and the chamber pressure was approximately 10 Torr. [Table 1]

[0062] In the embodiments described above, the layer containing the metal and one or more impurities (e.g., nitrogen, boron, etc.) is described as amorphous. In other embodiments, a layer containing impurities but not necessarily amorphous may be used in the manner described above for the amorphous layer.

[0063] In some embodiments, the entire feature may be filled with a layer containing impurities. For example, a tungsten nitride (WN) film can be used as the lead material in the trench. Other examples of such layers include other metal nitrides, including titanium nitride (TiN) and tantalum nitride (TaN).

[0064] In certain embodiments, the method involves conformally treating the feature with a metal-containing precursor and an inhibitory chemical before depositing the bulk layer. Figure 4C provides an example of the process flow for filling adjacent trenches. The process begins with depositing an initial amount of metal in the adjacent trenches (452). This may be a conformal nucleating layer in some embodiments, or it may consist of a nucleating layer and some amount of bulk layer. Thus, after this step, the feature has a generally conformal metal layer backing the sidewalls and bottom of the feature. In one example, a 15 nm feature is backed with a 2 nm nucleating layer. The deposited layer is then conformally treated with a metal-containing precursor and an inhibitory chemical (454). In one example, the feature is exposed to a tungsten-containing precursor and ammonia (NH3). The treatment in block 454 may involve the deposition of a film and / or adsorbed species of the tungsten-containing precursor and the inhibitory chemical. In certain embodiments, the treatment is carried out so that it is conformal but discontinuous. For example, a discontinuous film may be deposited across the entire depth of the feature. In another example, tungsten-containing and nitrogen-containing species are non-uniformly adsorbed across the entire depth of the feature. This has the effect of providing non-uniform passivation across the entire depth of the feature, so that in the subsequent bulk layering process, the film may be deposited conformally but with increased roughness.

[0065] Next, a bulk metal layer is deposited on the treated metal (456). In some embodiments, the bulk metal layer can be deposited to fill the trench. In other embodiments, operations 454 and 456 may be repeated once or more times to fill the trench (458). If a zipping mechanism occurs when conformal bulk deposition is performed, operations 454 and 456 can be advantageously repeated. The bulk layer may be, for example, a high-purity layer having an atomic purity of at least 97% or 99% of the elemental metal.

[0066] In the example in Figure 4C, one or more annealing operations can be performed to reduce the resistivity of the amorphous layer. According to various embodiments, thermal annealing can be performed after the features have been filled (e.g., after operation 458 if performed), optionally after processing (e.g., between operations 454 and 456), or optionally after some or all of the bulk layer has been deposited (e.g., during or after operation 456).

[0067] The process described with respect to Figure 4C may be modified according to various embodiments. For example, in some embodiments, operation 452 is not performed, and only operations 454 and 456 (and optionally 458) are performed. This may be appropriate in some embodiments if the feature has a liner layer (e.g., WCN) that can be processed as described above.

[0068] In some embodiments, the processing operation may involve only inhibitory chemicals that are non-uniformly adsorbed across the entire feature and / or react non-uniformly with the underlying metal, forming a discontinuously passivated surface throughout the entire depth of the feature.

[0069] Figure 5C shows an example of a substrate having a V-shaped feature 553, where seeds 570 on the surface of tungsten 580 deposited along the sidewall of feature 553 prevent tungsten-tungsten bonding, thereby reducing line bending. The seeds are adsorbed discontinuously across the entire feature.

[0070] The disclosed embodiments are suitable for reducing line bending. Line bending analysis can be performed by measuring the line width and roughness of a trench filled with tungsten or other metal. Line bending analysis involves imaging the metal at the top of the device aperture using a plane microscope and measuring the metal width at multiple points on multiple lines. For each line, the line width is measured over 100 points. From each line, the average line width and the variation in line width are then calculated, which can also be defined as roughness. "Average line width" is the average of the average line widths of all individual lines measured during the analysis.

[0071] In line bending, two main metrics are defined as follows: (i) Line-to-Line (LTL) variation is the standard deviation of the average line width, thereby capturing the variation in line width change across various lines on the image; (ii) Line Width Roughness (LWR) is the average of the line roughness (variation in line width within each line) from all measured lines, thereby capturing the average line width variation within a single line. These two metrics, LTL and LWR, are given by σ = (σ1 2 +σ2 2 ) 1 / 2 It is combined with a single variation metric, σtotal, as determined by [the formula / method]. Furthermore, LTL and σtotal are normalized with respect to the line width mean and described as LTL% and σtotal%.

[0072] In various embodiments, the method yields a substrate with a total dispersion of less than approximately 5 nm, or less than approximately 1.5 nm, or less than approximately 7.2% in percentage, where the total dispersion percentage is calculated by normalizing the total dispersion by the average line width.

[0073] In any of the filling processes described herein, inhibitory treatments may be preferentially applied to the tops of features to facilitate improved filling. Such inhibitory treatments may involve heat treatment or plasma treatment using inhibitory chemicals. For example, N2 plasma or NH3 heat treatment can be used to inhibit nucleation at the tops of features at any point during the filling process.

[0074] Inhibitory chemicals refer to atoms, compounds, or other species that interact with a surface and inhibit the subsequent nucleation of a metal. Nitrogen, for example, can inhibit tungsten nucleation and can be supplied thermally (e.g., in ammonia) or in a plasma (e.g., in an N2 plasma).

[0075] Deposition of amorphous layers With respect to Figures 4A and 4B, the deposition of amorphous layers as described above can be carried out using CVD or ALD techniques. Figures 6 and 7 provide timing sequence diagrams illustrating exemplary cycles for depositing amorphous W-based layers from tungsten-containing precursor WF6 and reducing agent NH3. In Figure 6, the reactants are carried out in parallel with purges between consecutive doses. In Figure 7, the reactants are carried out with purges between each reactant.

[0076] The reaction conditions during the deposition of amorphous layers are such that impurities are incorporated into the film. This differs from the deposition of nucleating and bulk layers, where high-purity metal films can be deposited. In some embodiments, such as those shown in Figures 6 and 7, impurities are supplied by a reducing agent. In these examples, nitrogen is incorporated from NH3. Similarly, boron can be incorporated from a diborane reducing agent.

[0077] In other examples, impurities may be present in the metal-containing precursor or supplied separately from the metal-containing precursor and reducing agent. For example, N2 may be used to supply nitrogen in the WF6 / H2 reaction to form an amorphous film.

[0078] Examples of such reducing agents include boron-containing reducing agents, silicon-containing reducing agents, and germanium-containing reducing agents. An example of a boron-containing reducing agent is B n H n+4 B n H n+6 B n H n+8 B n H m Examples of boranes include those listed above, where n is an integer from 1 to 10 and m is an integer different from m. In certain cases, diborane can be used. Other boron-containing compounds include alkylboranes, alkylborons, aminoboranes (CH3)2NB(CH2)2, and C2B n H n+2 Carboranes such as can also be used. Examples of silicon-containing compounds include silanes such as SiH4 and Si2H6. Examples of germanium-containing compounds include Ge n H n+4 , Ge n H n+6 , Ge n H n+8 , and Ge n H m Examples of germanium compounds include those listed above, where n is an integer between 1 and 10, and n is an integer different from m. Other germanium-containing compounds, such as alkylgermanes, alkylgermanium, aminogermanes, and carbogermanes, can also be used. Examples of nitrogen-containing reducing agents are NH3 and N2H4. Examples of carbon-containing reactants are CH4 and C2H2.

[0079] Depending on the reactants, the temperature may need to be relatively high to allow for the incorporation of impurities. The amount of reducing agent or other impurity carriers may also need to be increased to facilitate this incorporation.

[0080] Amorphous film deposition processes may involve exposing the substrate to more impurity-containing reactants than metal-containing reactants, allowing for the incorporation of impurities into the film. In some embodiments, the ALD process involves a ratio of at least 2:1 between impurity-containing reactant pulses and metal-containing reactant pulses. This ratio may be at least 3:1, 4:1, or higher, depending on the various embodiments. In the processes described herein, pulses may be a single injection of gas or several short, consecutive injections. In some embodiments, the process involves a ratio of at least 2:1, 3:1, or higher between impurity-containing reactant injections and metal-containing reactant injections.

[0081] In some embodiments, the relative flow rate of the reactants can also be varied to adjust the concentrations of metals and impurities. Exemplary flow rates may range from about 60 sccm to about 300 sccm for a 300 mm wafer, with the flow rate scaling linearly with respect to area. The dosing time can also be varied, with a greater number of short pulses of impurity-containing reactants providing more efficient uptake than fewer, longer pulses. Furthermore, in some embodiments, a relatively long purge time follows at least the pulses of impurity-containing reactants.

[0082] In some embodiments, the amount of impurities may be limited to improve resistivity. For example, this may involve a ratio of the number of impurity-containing reactant pulses to the number of metal-containing reactant pulses being less than 2:1, or even less than 1:1. The flow rate ratio, as well as the exposure time, can be adjusted. The total exposure time may be such that the exposure time for the metal-containing gas is longer than that for the impurity-containing reactant gas.

[0083] In some embodiments, the amount of impurities can change through the deposition of the amorphous film. For example, the amount of NH3 may increase when the zip-up mechanism is observed and then decrease thereafter. In this way, the amount of impurities can be varied. The flow rate and / or exposure time may also be varied.

[0084] Treatment using metal-containing precursors and inhibitory chemicals In some embodiments, the method includes a process to inhibit metal nucleation at least along the sidewalls of the feature. In some embodiments, the inhibition involves a chemical reaction between an inhibiting species and a metal-containing precursor or the feature surface, which can form small islands of compound material such as tungsten nitride (WN) or tungsten carbide (WC). In some embodiments, the inhibition may involve surface effects such as adsorption, which passivates the surface without forming a layer of compound material. The metal-containing precursor adsorbs to sites that can provide seed metal nucleation during subsequent deposition operations.

[0085] The inhibiting chemical may be a nitrogen-containing compound such as N2 or NH3. Other chemicals that can be used to inhibit tungsten and other metal surfaces include oxygen-based and hydrocarbon-based chemicals. For example, molecular oxygen or methane can be introduced into the plasma generator. Inert components such as argon, xenon, or krypton can be used as carrier gases. In some embodiments, there are no other non-inert components in the gas from which the plasma is generated, except in trace amounts. In some embodiments, the inhibiting chemical may be nitrogen-containing, hydrogen-containing, oxygen-containing, and / or carbon-containing, accompanied by one or more additional reactive species present in the plasma.

[0086] Operation 454 in Figure 4C can be a thermal or plasma-assisted process. If thermal, the metal-containing precursor can be flowed with an inhibitory chemical or introduced into the feature sequentially. If plasma-assisted, the plasma may be ignited while the inhibitory chemical is in the chamber. The co-reactants to the metal-containing precursor (e.g., H2) may or may not flow.

[0087] Figures 8–10 provide timing sequence diagrams illustrating exemplary cycles for treating a surface using a tungsten-containing precursor WF6 and a reducing agent NH3. In these figures, WF6 is shown as the metal-containing precursor, NH3 or N2 as the inhibitory chemical, and H2 as the co-reactant. However, examples show other metal-containing precursors that may be used (e.g., WCl x It is understood that this is applicable to other inhibitory chemicals (such as MoCl4), and other co-reactants.

[0088] In Figure 8, the metal-containing precursor and inhibitory chemical are co-administered in doses with purging between successive doses. Alternatively, the compounds can be co-administered in a single dose without purging until the process is complete. In Figure 9, the metal-containing precursor and inhibitory chemical are alternated with purging between each reactant. In Figures 8-10, a carrier gas is shown. This may be, for example, argon (Ar) or any other inert gas. In some embodiments, the carrier gas may not be used and / or may be used only for a specific flow. The processing cycle can begin with either the inhibitory chemical or the metal-containing precursor. The metal-containing precursor or inhibitory chemical can be introduced with a compound such as a reducing agent. In the examples in Figures 8 and 9, no additional reducing agent is used, but hydrogen in ammonia may act as one. The examples in Figures 8 and 9 are thermal processes. Figure 10 shows an example of a plasma-assisted process, where the metal-containing precursor is administered alternately with plasma generated from N2 gas. Either a remote or in-situ plasma generator may be used. In other embodiments, the metal-containing precursor and the inhibitory chemical may be introduced together or sequentially without plasma, after which plasma generated from an inert gas (e.g., Ar) is applied.

[0089] As shown above, the process is discontinuous but conformal. Process parameters that can be adjusted to achieve this include exposure time, number of cycles, reactant concentration, and chamber pressure. Temperature can also be used to achieve conformality and discontinuity. Lower temperatures allow the compound to diffuse to the bottom of the feature (rather than reacting at the top), and may also allow the process to be stopped while the film and / or adsorbed species are discontinuously deposited and / or adsorbed.

[0090] In plasma-based processes, tuning the inhibition profile can involve appropriately controlling inhibitory chemicals, substrate bias power, plasma power, process pressure, exposure time, and other process parameters. In in-situ plasma processes (or other processes where ionic species are present), a bias can be applied to the substrate. Substrate bias can have a significant impact on the inhibition profile in some embodiments, with increased bias power leading to deeper active species within vertical features. Inhibitory chemicals can also be used to tune the inhibition profile by varying the ratio of active inhibitory species used. For example, when inhibiting W and other metal surfaces, nitrogen can have a stronger inhibitory effect than hydrogen, and the profile can be tuned by adjusting the ratio of N2 and H2 gases in the forming gas-based plasma. Plasma power can also be used to tune the inhibition profile by varying the ratio of active species tuned by the plasma power.

[0091] Process pressure can be used to adjust the inhibition profile because pressure not only causes more recombination (inactivation of active species), but can also push active species further into the feature. Process time can also be used to adjust the inhibition profile; longer processing times cause inhibition to occur deeper within the feature.

[0092] In some embodiments, the inhibition rate depends on the concentrations of various components at different locations within the feature. In conformal processing, large quantities of inhibitory species can be supplied to avoid species consumption at feature openings (e.g., by increasing the number of cycles, dosing time, flow rate, and concentration). In addition to variations in the overall inhibitory concentration within the feature, inhibition may be influenced by the relative concentrations of different inhibitory species across the feature. These relative concentrations may then depend on the relative dynamics of the dissociation and recombination processes of the inhibitory species. Initial inhibitory materials, such as molecular nitrogen, can be passed through a remote plasma generator and / or subjected to an in-situ plasma to generate activated species (e.g., atomic nitrogen, nitrogen ions). However, activated species may recombine with less reactive recombining species (e.g., nitrogen molecules) and / or react with W, WN, TiN, or other feature surfaces along their diffusion pathways. Thus, different parts of a feature may be exposed to different inhibitory materials at different concentrations, e.g., initial inhibitory gas, activated inhibitory species, and recombining inhibitory species. Activated species are generally more reactive than initial inhibitory gas and recombining inhibitory species. Furthermore, in some cases, the activated species may be less sensitive to temperature changes than the recombining species. Process conditions can be controlled so that inhibition is primarily due to the inactive species (e.g., in non-plasma thermal processes).

[0093] The timing sequence diagram is similar to that for the deposition described above. However, as mentioned above, only discontinuous layers are deposited at most. To limit the process accordingly, one or more of the temperature, dosing time, and total exposure time can be controlled.

[0094] Deposition of nucleation layers The nucleation layer is deposited according to certain disclosed embodiments by alternating between a metal-containing precursor and a reducing agent such as silane (SiH4), disilane (Si2H6), trisilane (Si3H8), germane (GeH4), or diborane (B2H6). In some embodiments, the nucleation layer is deposited by exposing the substrate to alternating pulses of a tungsten-containing precursor and silane. In some embodiments, the nucleation layer is deposited by exposing the substrate to alternating pulses of a tungsten-containing precursor and diborane. In some embodiments, the nucleation layer is deposited by exposing the substrate to alternating pulses of a tungsten-containing precursor and silane, and then exposing the substrate to alternating pulses of a tungsten-containing precursor and diborane. In some embodiments, the nucleation layer is deposited by exposing the substrate to alternating pulses of a tungsten-containing precursor and diborane, and then exposing the substrate to alternating pulses of a tungsten-containing precursor and silane. In some embodiments, the nucleating layer is deposited by exposing the substrate to alternating pulses of a tungsten-containing precursor and silane, then to alternating pulses of a tungsten-containing precursor and diborane, and then to alternating pulses of a tungsten-containing precursor and silane. In some embodiments, the nucleating layer is deposited by exposing the substrate to alternating pulses of a tungsten-containing precursor and diborane, then to alternating pulses of a tungsten-containing precursor and silane, and then to alternating pulses of a tungsten-containing precursor and diborane. In any of the disclosed embodiments, the chamber containing the substrate may be purged during one or more dosing operations for depositing the nucleating layer. Purging can be carried out by flowing an inert gas, such as argon, through the chamber. Any suitable inert gas may be used for purging. For example, in some embodiments, the substrate may be exposed to pulses of a tungsten-containing precursor, the chamber may be purged, the substrate may then be exposed to pulses of silane, the chamber may be purged again, and such operations may be repeated in cycles.

[0095] The nucleation layer deposition that can be used in any of the embodiments described above may involve co-circulating hydrogen (H2), argon (Ar), nitrogen (N2), or any combination thereof, throughout the entire nucleation deposition process, or during silane administration, or diborane administration, or tungsten-containing precursor administration such as WF6 administration, or during any purging time. In some embodiments, surface treatment operations may be performed during or after nucleation growth by exposing the substrate to any of silane, disilane, trisilane, germane, diborane, hydrogen, tungsten hexafluoride, nitrogen, argon, or any combination thereof. For example, during nucleation layer deposition, the substrate may be exposed to alternating pulses of silane and WF6, then the substrate may be exposed to silane immersion, and then the substrate may begin to be exposed to alternating pulses of silane and WF6. Such operations may be performed in cycles. For example, in some embodiments, the following cycle may be repeated once or more times to deposit a nucleation layer: alternating pulses of SiH4 and WF6 and exposure to surface treatment.

[0096] In some embodiments, the nucleating layer can be deposited by exposing the substrate to a tungsten-containing precursor and one or more combinations of the following gases in any sequence and order for one or more cycles. For example, in some embodiments, the nucleating layer can be deposited by exposing the substrate to diborane, then to tungsten hexafluoride, then to silane, and then to hydrogen. Such operation can be repeated for one or more cycles. In another example, in some embodiments, the nucleating layer can be deposited by exposing the substrate to silane, then to tungsten hexafluoride, and then to hydrogen. Such operation can be repeated for one or more cycles. In yet another example, in some embodiments, the nucleating layer can be deposited by exposing the substrate to diborane, then to hydrogen, and then to tungsten hexafluoride. Such operation can be repeated for one or more cycles. In other examples, in some embodiments, the nucleating layer can be deposited by exposing the substrate to nitrogen, the substrate to diborane, and the substrate to tungsten hexafluoride. Such operations can be repeated in one or more cycles. In other examples, in some embodiments, the nucleating layer can be deposited by exposing the substrate to silane, the substrate to nitrogen, and the substrate to tungsten hexafluoride. Such operations can be repeated in one or more cycles. In any of the embodiments described, the substrate may be exposed to surface treatment and / or immersion operations before, during, or after the deposition of a nucleation cycle using any available gas. In some embodiments, additional gases may be flowed in parallel with any of the gases described above during one or more exposures in the nucleation deposition process. In any of the disclosed embodiments, the chamber containing the substrate may be purged during one or more dosing operations for depositing the nucleating layer.Purge can be carried out by passing an inert gas, such as argon, through the chamber. Any suitable inert gas may be used for purging. In some embodiments, it is understood that the substrate may be periodically exposed to nitrogen during the deposition of the tungsten nucleation layer.

[0097] During any of the above-described exposures, the gas may be continuously pulsed or flowed. For example, in some embodiments, during WF6 administration in a continuous CVD operation, WF6 may be pulsed once or multiple times during a single administration. Similarly, in some embodiments, during purging, the inert gas may be pulsed once or multiple times during a single purge operation. Such pulsed operation can be performed during any operation of nucleation deposition or any operation of bulk deposition or any combination thereof. In some embodiments, one or more changes to one or more parameters such as pressure, flow rate, and temperature may be used. In some embodiments, the pedestal may be moved during any operation of nucleation deposition or bulk deposition, or both, thereby adjusting the gap between the substrate on the pedestal and the showerhead. Movement of the pedestal may be used in combination with changing one or more parameters such as pressure, temperature, or flow rate. Adjusting the gap between the substrate and the showerhead may affect the pressure, temperature, or flow rate that may be used according to certain disclosed embodiments. It is understood that any of the processes described herein may be applicable to techniques involving ALD.

[0098] Bulk layer deposition The bulk deposition described herein can involve simultaneous exposure of two reactants, allowing both reactants to flow simultaneously during deposition. For example, bulk tungsten can be deposited by simultaneously exposing a substrate to hydrogen (H2) and tungsten hexafluoride (WF6) for a period sufficient to fill the features. The hydrogen and WF6 react during exposure to deposit tungsten on the features. In a pulsed CVD process, one reactant flows continuously while the other is pulsed, but the substrate is exposed to both reactants during deposition, with material deposited during each pulse. For example, while WF6 is pulsed, the substrate may be exposed to a continuous flow of H2, and the WF6 and H2 react during the pulse to deposit tungsten.

[0099] In some embodiments, bulk deposition may involve separate exposures to each reactant so that the reactants do not flow into the chamber simultaneously during deposition. Rather, the flow of each reactant is introduced into the chamber containing the substrate in sequentially time-separated pulses, and this is repeated once or multiple times in a cycle.

[0100] Metal-containing precursors While the above description primarily concerns tungsten layers, the method can be implemented to fill features using other metals, including molybdenum, cobalt, and ruthenium.

[0101] Examples of Mo precursors for ALD in molybdenum materials include molybdenum halides such as MoF6 and MoCl6, molybdenum oxyhalides such as molybdenum dichloride (MoO2Cl2) and molybdenum tetrachloride (MoOCl4), and hexacarbonylmolybdenum (Mo(CO)6). Formula Mo xOther Mo oxyhalides of OyHaly include Hal, where Hal is a halogen (fluorine (F), chlorine (Cl), bromine (Br), or iodine (I)), and x, y, and z are any numbers greater than zero that can form a stable molecule. These include molybdenum tetrafluoride (MoOF4), molybdenum dibromide (MoO2Br2), and molybdenum iodide (MoO2I and Mo4O) 11 Includes I.

[0102] In certain embodiments, organometallic precursors may also be used in conjunction with examples that include Mo precursors having cyclopentadienyl ligands. Further examples include precursors of the formula Mo2Ln, where each L is independently selected from amidate ligand, amidinate ligand, and guanidinate ligand, and n is 2–5. Mo2Ln precursors contain multiple molybdenum-molybdenum bonds (such as double bonds or any multiple bonds with bond order 2–5). Further examples include halide-containing heteroreptic molybdenum compounds (i.e., compounds having different types of ligands). A particular example of such precursors is a compound containing molybdenum, at least one halide that forms a bond with molybdenum, and at least one organoligand having one of the elements N, O, and S, where an atom of any of these elements forms a bond with molybdenum. Suitable organic ligands that provide a nitrogen or oxygen bond include amidinates, amidates, iminopyrrolidineates, diazadienes, betaiminoamides, alphaiminoalkoxides, betaaminoalkoxides, beta-diketiminates, beta-ketoimiminates, beta-diketonates, amines, and pyrazolates. Suitable organic ligands that provide a sulfur bond include thioethers, thiolates, dithiolenes, dithiolates, and α-iminothiolenes. These ligands may be substituted or unsubstituted. In some embodiments, these ligands include one or more substituents independently selected from the group consisting of H, alkyl, fluoroalkyl, alkylsilyl, alkylamino, and alkoxy substituents. The organic ligands may be neutral or anionic (e.g., monoanionic or dianionic), and molybdenum may be in various oxidation states such as +1, +2, +3, +4, +5, and +6.

[0103] Ruthenium (Ru) precursors can be used to deposit ruthenium (Ru). Examples of ruthenium precursors that can be used in oxidation reactions include (ethylbenzyl)(1-ethyl-1,4-cyclohexadienyl)Ru(0), (1-isopropyl-4-methylbenzyl)(1,3-cyclohexadienyl)Ru(0), (2,3-dimethyl-1,3-butadienyl)Ru(0) tricarbonyl, (1,3-cyclohexadienyl)Ru(0) tricarbonyl, and (cyclopentadienyl)(ethyl)Ru(II) dicarbonyl. Examples of ruthenium precursors that react with non-oxidizing reactants are bis(5-methyl-2,4-hexanediketonate)Ru(II) dicarbonyl and bis(ethylcyclopentadienyl)Ru(II).

[0104] To deposit cobalt (Co), cobalt-containing precursors can be used, including dicarbonylcyclopentadienylcobalt(I), cobalt carbonyl, various cobalt amidinate precursors, cobalt diazadienyl complexes, cobalt amidinate / guanidinate precursors, and combinations thereof.

[0105] While WF6 is used as an example of a tungsten-containing precursor, it should be understood that other tungsten-containing precursors may be suitable for carrying out the disclosed embodiments. For example, organometallic tungsten-containing precursors can be used. Organometallic precursors such as MDNOW (methylcyclopentadienyl-dicarbonylnitrosyl-tungsten) and EDNOW (ethylcyclopentadienyl-dicarbonylnitrosyl-tungsten), as well as fluorine-free precursors, can also be used. Chlorine-containing tungsten precursors such as tungsten pentachloride (WCl5) and tungsten hexachloride (WCl6) can also be used. x ) may be used.

[0106] The metal-containing precursor can be reacted with a reducing agent as described above. In some embodiments, H2 is used as a reducing agent for bulk layer deposition to deposit a high-purity film.

[0107] In some embodiments, the bulk layer is deposited using CVD filling of features and is carried out at low temperatures. According to various embodiments, the low temperature (substrate temperature) is one of the following ranges: about 250-350°C, about 250-340°C, about 250-330°C, about 250-325°C, about 250-320°C, about 250-315°C, about 250-310°C, about 250-305°C, or about 250-300°C. Also according to various embodiments, the substrate temperature is about 260-310°C, about 270-310°C, about 280-310°C, or about 290-310°C. In certain embodiments, the process and / or substrate temperature is about 300°C. Using low-temperature CVD, high-quality filling can be obtained with narrow, high-aspect-ratio features.

[0108] Device The disclosed embodiments can be carried out using any suitable chamber. Exemplary deposition systems include any of the various systems, e.g., ALTUS® and ALTUS® Max, available from Lam Research, Fremont, California, or various other commercially available processing systems. In some embodiments, continuous chemical vapor deposition (CVD) may be carried out in a first station, which is one of two, five, or more deposition stations positioned within a single deposition chamber. Thus, for example, diborane (B2H6) and tungsten hexafluoride (WF6) can be alternately introduced onto the surface of a semiconductor substrate in the first station using individual gas supply systems that create a local atmosphere on the substrate surface for depositing nucleation layers. Another station may be used for the deposition of amorphous layers. Another station may also be used to deposit bulk metal layers at low pressure. In some embodiments, the temperature is controlled individually. For example, the temperature may be increased in the amorphous layer station to increase impurity incorporation.

[0109] In embodiments where inhibition treatment is performed, one station may be used for processing the nucleated layer. Another station may be used to deposit the bulk metal layer. In some embodiments, the temperature is controlled individually. For example, the temperature can be lowered in the processing station to enable discontinuous conformal processing.

[0110] Tungsten can be deposited in parallel using two or more stations. Alternatively, the wafer can be indexed, and the deposition operation can be performed consecutively on two or more stations.

[0111] Figure 11 is a block diagram of a processing system suitable for carrying out a tungsten thin film deposition process according to an embodiment. System 1000 includes a transfer module 1003. Transfer module 1103 provides a clean pressurized environment to minimize the risk of substrate contamination as the substrate moves between various reactor modules during processing. Transfer module 1103 is fitted with a multi-station reactor 1109 capable of carrying out ALD and CVD according to the embodiment. Reactor 1109 may include a plurality of stations 1111, 1113, 1115, and 1117 that can carry out operations according to the disclosed embodiment in succession. For example, reactor 1109 may be configured so that station 1111 carries out nucleation layer deposition by ALD, station 1113 carries out amorphous layer deposition, and stations 1115 and 1117 carry out bulk layer deposition by CVD or ALD.

[0112] In another example, the reactor 1109 can be configured such that station 1111 performs nucleation layer deposition by ALD, station 1113 performs nucleation layer processing, and stations 1115 and 1117 perform bulk metal layer deposition by ALD or CVD.

[0113] The station may include a heated base or substrate support, and one or more gas inlets or showerheads or dispersion plates. An example of a deposition station 1200 including a substrate support 1202 and a showerhead 1203 is illustrated in Figure 12. A heater may be provided in the base portion 1201.

[0114] Furthermore, the transfer module 1103 may be fitted with one or more single or multi-station modules 1107 capable of performing plasma pre-cleaning or chemical (non-plasma) pre-cleaning. The modules may also be used for various processes, for example, to prepare substrates for deposition processes. In some embodiments, module 1107 may be used, for example, for plasma inhibition processing.

[0115] System 1100 also includes one or more wafer source modules 1201 for storing wafers before and after processing. An atmospheric robot (not shown) in an atmospheric transfer chamber 1119 can first remove the wafers from the source modules 1101 and transfer them to the load lock 1121. A wafer transfer device (typically a robotic arm unit) in a transfer module 1103 moves the wafers from the load lock 1121 to modules attached to the transfer module 1103, and moves them between modules.

[0116] In various embodiments, a system controller 1129 is used to control process conditions during deposition. The controller 1129 typically includes one or more memory devices and one or more processors. The processors may include a CPU or computer, analog and / or digital input / output connections, a stepping motor controller board, and the like.

[0117] The controller 1129 can control all the activities of the deposition apparatus. The system controller 1129 runs system control software that includes a set of instructions for controlling timing, gas mixing, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power level, wafer chuck position or pedestal position, and other parameters of a particular process. In some embodiments, other computer programs stored in a memory device associated with the controller 1129 can be used.

[0118] Typically, a user interface is associated with the controller 1129. The user interface may include a display screen, a graphical software display of the device and / or process conditions, and user input devices such as a pointing device, keyboard, touchscreen, or microphone.

[0119] System control logic can be configured in any suitable way. Generally, logic can be designed or configured in hardware and / or software. Instructions for controlling drive circuits may be hardcoded or provided as software. Instructions may also be provided by “programming.” Such programming is understood to include all forms of logic, including hardcoded logic of digital signal processors, application-specific integrated circuits, and other devices with specific algorithms implemented as hardware. Programming is also understood to include software or firmware instructions that can be executed on a general-purpose processor. System control software can be coded in any suitable computer-readable programming language.

[0120] Computer program code for controlling germanium-containing reducing agent pulses, hydrogen flow, and tungsten-containing precursor pulses in a process sequence, as well as other processes, can be written in any conventional computer-readable programming language (e.g., assembly language, C, C++, Pascal, Fortran, etc.). The compiled object code or script is executed by the processor to perform the tasks identified by the program. Alternatively, as shown, the program code may be hardcoded.

[0121] Controller parameters relate to process conditions such as process gas composition and flow rate, temperature, pressure, cooling gas pressure, substrate temperature, and chamber wall temperature. These parameters are provided to the user in the form of a recipe and can be entered using the user interface.

[0122] Signals for monitoring the process may be provided by the analog and / or digital input connections of the system controller 1129. Signals for controlling the process are output by the analog and digital output connections of the deposition unit 1100.

[0123] System software can be designed or configured in many different ways. For example, various chamber component subroutines or control objects may be written to control the operation of the chamber components necessary to perform the deposition process according to the disclosed embodiments. Examples of programs or sections of programs for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code.

[0124] In some embodiments, the controller 1129 is part of a system, and such a system may be part of the examples described above. Such a system may include a semiconductor processing apparatus comprising one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as a wafer pedestal, gas flow system, etc.). These systems may be integrated with electronic equipment for controlling system operation before, during, and after processing of semiconductor wafers or substrates. Such electronic equipment may be referred to as a “controller” and may control various components or sub-components of one or more systems. The controller 1229 may be programmed to control any of the processes disclosed herein, depending on the processing requirements and / or the type of system. Such processes may include supplying processing gases, setting temperature (e.g., heating and / or cooling), setting pressure, setting vacuum, setting power, setting radio frequency (RF) generators in some systems, setting RF matching circuits, setting frequency, setting flow rates, setting fluid supply, setting position and operation, loading and unloading wafers to and from tools, and loading and unloading wafers to and from other transport tools and / or load locks connected to or interlocked with a particular system.

[0125] In a broad sense, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive and issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, chips defined as digital signal processors (DSPs), application-specific integrated circuits (ASICs), and / or one or more microprocessors, i.e., microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that may define operating parameters for performing a particular process on or for a semiconductor wafer or for a system. In some embodiments, operating parameters may be part of a recipe defined by a process engineer to realize one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0126] In some embodiments, the controller 1129 may be part of a computer integrated with or coupled to the system, or otherwise networked to the system, or coupled to such a computer, or a combination thereof. For example, the controller 1129 may be in the “cloud,” or all or part of the fab host computer system. This enables remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of fabrication operations, review the history of past fabrication operations, review trends or performance criteria from multiple fabrication operations, modify parameters of the current process, set processing steps following the current process, or start a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system over a network. Such a network may include a local network or the internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data. Such data identifies parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tools to which the controller is configured to interact or control. Therefore, as described above, the controller may be distributed by including, for example, one or more separate controllers that are networked together and cooperate toward a common purpose (such as the processes and controls described herein).An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber that communicate with one or more integrated circuits that are remotely located (for example, at the platform level or as part of a remote computer) and combined to control processes in the chamber.

[0127] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, CVD chambers or modules, ALD chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, tracking chambers or modules, and any other semiconductor processing systems that may be used in connection with or for the fabrication and / or manufacture of semiconductor wafers.

[0128] As described above, depending on one or more process steps performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used for material handling to load and unload wafer containers to and from tool locations and / or load ports within the semiconductor manufacturing plant.

[0129] The controller 1129 may include various programs. A substrate positioning program may include program code for controlling chamber components used to load the substrate onto a pedestal or chuck and to control the distance between the substrate and other parts of the chamber, such as the gas inlet and / or target. A process gas control program may include code for controlling the gas composition, flow rate, pulse time, and optionally code for supplying gas to the chamber before deposition in order to stabilize the pressure in the chamber. A pressure control program may include code for controlling the pressure in the chamber, for example, by adjusting the throttle valve of the chamber's exhaust system. A heater control program may include code for controlling the current to a heating unit used to heat the substrate. Alternatively, the heater control program can control the supply of a heat transfer gas (such as helium) to the wafer chuck.

[0130] Examples of chamber sensors that can be monitored during deposition include mass flow controllers, pressure sensors (such as pressure gauges), and thermocouples located in a pedestal or chuck. Appropriately programmed feedback and control algorithms can be used in conjunction with data from these sensors to maintain desired process conditions.

[0131] The above describes the implementation of the disclosed embodiments in single or multi-chamber semiconductor processing tools. The apparatus and processes described herein may be used in conjunction with lithography patterning tools or processes for, for example, the fabrication or manufacture of semiconductor devices, displays, LEDs, solar panels, etc. Typically, although not essential, such tools / processes are used or performed together in a common fabrication facility. Film lithography patterning typically involves some or all of the following steps, each made possible by a variety of available tools: (1) applying photoresist to a workpiece (i.e., substrate) using a spin-on or spray-on tool; (2) curing the photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist with visible light, UV light, or X-ray light using a tool such as a wafer stepper; (4) developing the resist and selectively removing it using a tool such as a wet bench, thereby patterning the resist; (5) transferring the resist pattern to the underlying film or workpiece by using a dry etching tool or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

[0132] conclusion While the embodiments described above have been described in some detail for clearer understanding, it will be apparent that certain changes and modifications may be implemented within the scope of the appended claims. It should be noted that there are many other ways of carrying out the processes, systems, and apparatus of these embodiments. Therefore, these embodiments should be considered illustrative rather than restrictive, and their embodiments should not be limited to the details described herein.

Claims

1. It is a method, (a) Provide a substrate having a plurality of features arranged at intervals, each feature having a feature opening width, the width of the feature narrowing from the top of the feature to the bottom of the feature, (b) Conformally treat the surface by exposing it to a metal-containing precursor and an inhibitory compound. (c) After treating the surface, deposit a bulk metal layer on the feature. A method that includes [a certain feature].

2. The method according to claim 1, A method wherein the width of the bottom of each feature is between 0 nm and 90% of the width of the top of the feature.

3. A method according to claim 1 or 2, The method wherein the metal is selected from the group consisting of tungsten, ruthenium, molybdenum, and cobalt.

4. A method according to any one of claims 1 to 3, A method further comprising filling the feature by repeating (b) and (c) once or more times.

5. A method according to any one of claims 1 to 4, (b) A method that is carried out without depositing a continuous film on the feature.

6. A method according to any one of claims 1 to 5, (b) A method comprising heterogeneous adsorption of the metal precursor and the inhibitory compound.

7. A method according to any one of claims 1 to 5, (b) A method comprising the deposition of a discontinuous film.

8. A method according to any one of claims 1 to 7, A method further comprising depositing a nucleation layer on the feature, such that (b) includes treating the surface of the nucleation layer.

9. A method according to any one of claims 1 to 8, (b) A method for increasing the surface roughness of the bulk metal layer.

10. A method according to any one of claims 1 to 9, (b) is a method that is a non-plasma thermal process.

11. A method according to any one of claims 1 to 9, (b) is a plasma-based process, method.

12. A method according to any one of claims 1 to 11, The method wherein the inhibitory chemical substance includes a nitrogen-containing compound.

13. A method according to any one of claims 1 to 11, The method wherein the inhibitory chemical is ammonia.

14. It is a method, (a) Provide a substrate having a plurality of features spaced apart, each feature having a feature opening width, and at least some of the widths of the features narrow from the top of the feature to the bottom of the feature. (b) A conformal amorphous metal-based layer is deposited on the feature, (c) After depositing the conformal amorphous metal-based layer, deposit a bulk metal layer on the feature. A method that includes [a certain feature].

15. The method according to claim 14, A method wherein the width of the bottom of each feature is between 0 nm and 90% of the width of the top of the feature.

16. The method according to claim 14 or 15, The method wherein the metal is selected from the group consisting of tungsten, ruthenium, molybdenum, and cobalt.

17. A method according to any one of claims 14 to 16, A method further comprising filling the feature by repeating (b) and (c) once or more times.

18. A method according to any one of claims 14 to 17, A method further comprising annealing the conformal amorphous metal base layer.

19. A method according to any one of claims 14 to 18, The aforementioned features are arranged with a spacing of approximately 10 nm to 60 nm between adjacent features.

20. A method according to any one of claims 14 to 19, A method further comprising depositing a metallic nucleation layer on the feature.

21. A method according to any one of claims 14 to 20, The method wherein the metal-based layer contains at least 50 atomic percent of metal.

22. A method according to any one of claims 14 to 21, The method wherein the metal-based layer further comprises one or more of boron (B), nitrogen (N), carbon (C), silicon (Si), and germanium (Ge).

23. It is a method, (a) Provide a substrate having a plurality of features arranged at intervals, each feature having a feature opening width, the width of the feature narrowing from the top of the feature to the bottom of the feature, (b) A bulk metal layer is deposited on the feature, (c) After depositing the bulk metal layer on the feature, deposit an amorphous metal-based layer on the feature. A method that includes [a certain feature].

24. The method according to claim 23, A method wherein the width of the bottom of each feature is between 0 nm and 90% of the width of the top of each feature.

25. The method according to claim 23 or 24, The method wherein the metal is selected from the group consisting of tungsten, ruthenium, molybdenum, and cobalt.

26. A method according to any one of claims 23 to 25, A method further comprising repeating (b) once or more times to fill the features.

27. The method according to claim 26, A method further comprising filling the features by repeating (c) once or more times.

28. A method according to any one of claims 23 to 27, A method further comprising annealing the conformal amorphous metal base layer.

29. A method according to any one of claims 23 to 28, The aforementioned features are arranged with a spacing of approximately 10 nm to 60 nm between adjacent features.

30. A method according to any one of claims 23 to 29, A method further comprising depositing a metallic nucleation layer on the aforementioned feature.

31. A method according to any one of claims 23 to 30, The method wherein the metal-based layer contains at least 50% metal.

32. The method according to claim 31, The method wherein the metal-based layer further comprises one or more of boron (B), nitrogen (N), carbon (C), silicon (Si), and germanium (Ge).

33. It is a method, A substrate is provided having multiple features arranged at intervals, each feature having a feature opening width, and at least some of the widths of the features narrow from the top of the feature to the bottom of the feature. A conformal metal-based layer is deposited on the feature, the metal-based layer comprising a metal selected from tungsten (W), ruthenium (Ru), molybdenum (Mo), titanium (Ti), tantalum (Ta), and cobalt (Co), and the metal-based layer comprising at least 5% (atoms) of impurities selected from boron (B), nitrogen (N), carbon (C), silicon (Si), germanium (Ge), and combinations thereof. A method that includes [a certain feature].

34. The method according to claim 33, A method wherein the aforementioned features are filled with a film selected from titanium nitride and tantalum nitride.

Images