A TEG device and a low-temperature intrinsic characteristic analysis method for evaluating the quantitative effect of a high-k-based passivation layer on the electrical characteristics of a 2D FET structure.

Abstract

This invention provides a TEG device and a low-temperature intrinsic characteristic analysis method for evaluating the quantitative effect of the passivation layer on the electrical characteristics of a 2D FET structure. [Solution] A first FET element in which the passivation layer is positioned in a first direction relative to the channel and a second FET element in which the passivation layer is positioned in a second direction different from the first direction relative to the channel can be prepared. By comparing the amount of first charge trapped in the passivation layer in the first FET element and the amount of second charge trapped in the passivation layer in the second FET element, the quantitative effect of the shape of the passivation layer on the FET element can be evaluated. For the first and second FET elements, the resistance value in the passivation layer can be detected from the drain voltage and drain current measured at low temperatures using an equivalent circuit based on the shape of the passivation layer, and the change in mobility in the channel can be quantitatively analyzed based on the rate of increase of the resistance value.

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