Analysis method and apparatus for evaluating the electrical properties of vertical sidewalls in a three-dimensional semiconductor gate stack structure.

Abstract

This disclosure relates to an analytical method and apparatus for evaluating the electrical properties of vertical sidewalls in a semiconductor gate stack structure having a three-dimensional structure. [Solution] Multiple three-dimensional semiconductor gate stacked structures are provided, each having a different area and each containing the same vertical sidewall within its area. The electrical characteristics of each three-dimensional semiconductor gate stacked structure are measured, and the electrical characteristics of the vertical sidewall are detected from the relationship between the area and the electrical characteristics using an extrapolation method.

Description

Technical Field

[0001] The present disclosure relates to a technique for analyzing the electrical characteristics of general memory elements, and more particularly, to an analysis method and apparatus for evaluating the electrical characteristics of vertical sidewalls in a three-dimensional semiconductor gate stack structure. This patent was supported by the funds of the Ministry of Science and ICT and received support from the Korea Research Foundation (RS-2023-00280841).

Background Art

[0002] In the three-dimensional gate stack structure of a semiconductor element, various physical structures such as vertical sidewalls, planar regions, and corners have a complex influence on electrical characteristics. As the semiconductor element is miniaturized, the influence of the vertical sidewalls is increasing, but it is difficult to measure this individually.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present disclosure proposes a technique for analyzing the electrical characteristics of the entire area of a three-dimensional semiconductor gate stack structure and separating only the characteristics of the vertical sidewalls by an extrapolation method. Thereby, the characteristics of the vertical sidewalls can be accurately grasped, and the performance and reliability of the element can be improved by optimizing the gate insulating film and the structure.

Means for Solving the Problems

[0004] The present disclosure provides an analysis method and apparatus for evaluating the electrical characteristics of vertical sidewalls in a three-dimensional semiconductor gate stack structure.

[0005] In the present disclosure, an operating method of a computing device may include steps of providing a plurality of three-dimensional semiconductor gate stack structures each having a different area and each including the same vertical sidewall within the area, measuring the electrical characteristics of each of the three-dimensional semiconductor gate stack structures, and detecting the electrical characteristics of the vertical sidewall from the relationship between the area and the electrical characteristics by an extrapolation method.

[0006] In this disclosure, the computing device includes a memory and a processor connected to the memory and configured to execute at least one instruction word stored in the memory, wherein the processor is provided with a plurality of three-dimensional semiconductor gate stack structures, each having a different area and each containing the same vertical sidewall within its area, and the electrical properties of each three-dimensional semiconductor gate stack structure are measured, and the electrical properties of the vertical sidewalls are detected by extrapolation from the relationship between the area and the electrical properties. [Effects of the Invention]

[0007] According to this disclosure, it is possible to precisely detect only the electrical characteristics of the vertical sidewalls of a small three-dimensional semiconductor gate stack structure. Therefore, the electrical characteristics of the vertical sidewalls can be used to optimize semiconductor devices realized as three-dimensional semiconductor gate stack structures. Specifically, it is possible to accurately grasp the changes in leakage current and EOT (effective oxide thickness) in the vertical sidewalls, and to derive an optimal gate insulating film with stable electrical characteristics. This makes it possible to present semiconductor devices with improved CET (capacitive effective thickness), thereby improving the overall performance and reliability of the semiconductor device. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view showing a three-dimensional semiconductor gate stack structure to which various embodiments are applied. [Figure 2] This diagram schematically illustrates computing devices in various embodiments. [Figure 3] This figure illustrates the operating characteristics of the processor shown in Figure 2. [Figure 4] This diagram schematically illustrates the operation methods of a computing device in various embodiments. [Figure 5] Figure 4 is a diagram that shows in detail the steps for detecting the electrical characteristics of the vertical side wall. [Figure 6]This figure illustrates the steps involved in detecting the electrical characteristics of the vertical side wall shown in Figure 4. [Modes for carrying out the invention]

[0009] In the following, this disclosure provides an analysis method and apparatus for evaluating the electrical properties of vertical sidewalls in a three-dimensional semiconductor gate stack structure.

[0010] Various embodiments of this disclosure will be described below with reference to the accompanying drawings.

[0011] Figure 1 is a cross-sectional view showing a three-dimensional semiconductor gate stack structure to which various embodiments are applied.

[0012] Referring to Figure 1, a three-dimensional semiconductor gate stack structure may be realized as a stacked structure comprising a substrate, a channel, a gate insulating film, and a gate metal. In some embodiments, although not shown in the figure, additional components may be stacked between two of the substrate, channel, gate insulating film, or gate metal. For example, a three-dimensional semiconductor gate stack structure may include a FinFET as shown in Figure 1(a) or a nano-sheet FET as shown in Figure 1(b). Such a three-dimensional semiconductor gate stack structure may have vertical sidewalls. Vertical sidewalls represent the lateral surfaces of the three-dimensional semiconductor gate stack structure and may represent regions that extend vertically from the channel to the gate metal.

[0013] Here, three directions may be defined for a three-dimensional semiconductor gate stack structure: a first direction (x-direction), a second direction (y-direction), and a third direction (z-direction). The first direction may define the length of the three-dimensional semiconductor gate stack structure and the thickness of the vertical sidewalls, particularly the oxide layer of the vertical sidewalls, for example, from the channel to the gate metal. That is, the first direction may correspond to the horizontal stacking direction of the three-dimensional semiconductor gate stack structure, or in other words, the stacking direction of the oxide layer of the vertical sidewalls. The second direction may define the width of the three-dimensional semiconductor gate stack structure. The third direction may define the height of the three-dimensional semiconductor gate stack structure. That is, the third direction may correspond to the vertical stacking direction of the three-dimensional semiconductor gate stack structure.

[0014] Figure 2 is a schematic diagram showing the computing device 200 in various embodiments. Figure 3 is a diagram illustrating the operating characteristics of the processor 270 in Figure 2. Here, Figure 3 shows a three-dimensional semiconductor gate stack structure with different areas.

[0015] Referring to Figure 2, the computing device 200 is for evaluating the electrical characteristics of vertical sidewalls in a three-dimensional semiconductor gate stack structure and may include at least one of the following: a camera module 210, a communication module 220, an input module 230, an output module 240, a measurement module 250, a memory 260, or a processor 270. In some embodiments, at least one of the components of the computing device 200 (e.g., the camera module 210, the communication module 220) may be omitted, or at least one other component may be added. In some embodiments, at least two of the components of the computing device 200 may be implemented as a single integrated circuit. In some embodiments, the components of the computing device 200 may be distributed across at least two devices, which may be connected to each other in a communicative manner.

[0016] The camera module 210 may capture images with the computing device 200. Here, the camera module 210 may be, but is not limited to, an RGB camera. For example, the camera module 210 may include at least one of a lens, an image sensor, an image signal processor, or a flash.

[0017] The communication module 220 may perform communication with an external device (not shown) on the computing device 200. The communication module 220 may establish a communication channel between the computing device 200 and the external device and communicate with the external device via the communication channel. For example, the external device may include at least one of an electronic device, a base station, a server, or a satellite. The communication module 220 may include at least one of a wired communication module or a wireless communication module. For example, the wireless communication module may communicate with the external device via at least one of a telecommunications network or a short-range communication network.

[0018] The input module 230 may input instructions to be used for at least one component of the computing device 200. The input module 230 may include at least one of the following: an input unit configured for a user to directly input instructions or data to the computing device 200, or a sensor unit configured to detect the surrounding environment and generate data. For example, the input unit may include at least one of the following: a microphone, a mouse, or a keyboard. In some embodiments, the input unit may include at least one of the following: a touch circuitry configured to detect touches, or a sensor circuitry configured to measure the intensity of the force generated by a touch.

[0019] The output module 240 may output information outside the computing device 200. The output module 240 may include at least one of a display module that visually outputs information or an audio module that aurally outputs information. For example, the display module may include at least any one of a display, a hologram device, or a projector. In one embodiment, the display module may be combined with at least one of the touch circuit or the sensor circuit of the input module 230 and may be implemented as a touch screen. For example, the audio module may include at least one of a speaker or a receiver.

[0020] The measurement module 250 may measure the three-dimensional semiconductor gate structure. Specifically, the measurement module 250 may apply a voltage to the gate electrode of the three-dimensional semiconductor gate structure to measure at least one of current-voltage (I-V) characteristics or capacitance-voltage (C-V) characteristics.

[0021] The memory 260 may store various data used by at least one component of the computing device 200. For example, the memory 260 may include at least any one of volatile memory or non-volatile memory. The data may include a program or input data or output data for instructions related thereto. The program may be stored as software in the memory 260 and may include at least any one of an operating system, middleware, or an application.

[0022] The processor 270 may execute the program in the memory 260 to control at least one component of the computing device 200. Thereby, the processor 270 can execute data processing or operations. At this time, the processor 270 may execute the instructions stored in the memory 260.

[0023] In various embodiments, the processor 270 may evaluate the electrical characteristics of the vertical sidewalls in a three-dimensional semiconductor gate stack structure. Specifically, the processor 270 may analyze the electrical characteristics of the entire area of the three-dimensional semiconductor gate stack structure and separate only the electrical characteristics of the vertical sidewalls by extrapolation. The area may be defined as the first direction and the second direction (e.g., x-direction and y-direction) (i.e., length × width). The vertical sidewalls represent the cross-section of the three-dimensional semiconductor gate stack structure and mean the region vertically extended from the channel to the gate metal. The thickness of the vertical sidewalls, especially the oxide layer of the vertical sidewalls, may be defined as the first direction. Here, the electrical characteristics may include at least one of leakage current, capacitance, or dielectric constant.

[0024] More specifically, the processor 270 may measure, for example, as shown in FIG. 2, the change in the electrical characteristics of the three-dimensional semiconductor gate stack structure with the decrease in area. By such a method, the processor 270 may extract the electrical characteristics when the area is 0 for the three-dimensional semiconductor stack structure by extrapolation and then detect the electrical characteristics of the vertical sidewalls. The processor 270 may derive the slope showing the relationship between the area and the electrical characteristics of the three-dimensional semiconductor gate stack structure by extrapolation as in the following formula (1), and detect the electrical characteristics of the vertical sidewalls by the intercept of the slope as in the following formula (2).

[0025]

Equation

[0026]

Equation

[0027] Here, m represents the slope, n represents the number of data points, i.e., the number of areas or electrical characteristics, x represents the area at each data point, y represents the electrical characteristics at each data point, and y0 represents the electrical characteristics of the vertical sidewalls as the y-intercept of the gradient.

[0028] Therefore, the electrical characteristics of the vertical sidewalls can be utilized to optimize semiconductor devices realized in a three-dimensional semiconductor gate stack structure. This can improve the performance and reliability of the semiconductor devices.

[0029] Figure 4 is a schematic diagram illustrating the operation methods of the computing device 200 in various embodiments.

[0030] Referring to Figure 4, first, in step 410, a plurality of three-dimensional semiconductor gate stack structures may be provided, each having a different area and each containing the same vertical sidewall within its area. The area may be defined as the direction perpendicular to the stacking direction of the three-dimensional semiconductor gate stack structure (e.g., z-direction) (i.e., height) (e.g., x-direction and y-direction) (i.e., length × width). The vertical sidewall is defined as the stacking direction of the three-dimensional semiconductor gate stack structure (e.g., z-direction) (i.e., height), represents the side surface of the three-dimensional semiconductor gate stack structure, and may mean a region that extends vertically from the channel to the gate metal. Here, a three-dimensional semiconductor gate stack structure with a relatively small area may be identical to a part of a three-dimensional semiconductor gate stack structure with a relatively large area.

[0031] Next, in step 420, the computing device 200 may measure the electrical properties of each of the three-dimensional semiconductor gate stack structures. Specifically, the processor 270 may measure the electrical properties of each of the three-dimensional semiconductor gate stack structures via the measurement module 250. Here, the electrical properties may include at least one of leakage current, capacitance, or dielectric constant. In one embodiment, with the source electrode and drain electrode combined, the processor 270 may apply a voltage to the gate electrode to measure the current-voltage (IV) characteristics and, based on this, measure the voltage-dependent leakage current. In another embodiment, with the source electrode and drain electrode combined, the processor 270 may apply a voltage to the gate electrode to measure the capacitance-voltage (CV) characteristics and, based on this, measure the voltage-dependent capacitance. In yet another embodiment, for each of the three-dimensional semiconductor gate stack structures, the processor 270 may use the measured capacitance to derive the dielectric constant. In this case, the processor 270 may calculate the dielectric constant as shown in equation (3) below.

[0032]

number

[0033] Here, ε may represent the dielectric constant, C the capacitance, A the area, and t the thickness of the oxide layer on the vertical sidewall.

[0034] Next, in step 430, the computing device 200 may detect the electrical characteristics of the vertical sidewalls from the relationship between the area and electrical characteristics of the three-dimensional semiconductor gate stack structure by extrapolation. Specifically, the processor 270 may detect the electrical characteristics of the vertical sidewalls as the electrical characteristics when the area is 0, from the relationship between the area and electrical characteristics by extrapolation. Here, the electrical characteristics may include at least one of leakage current, capacitance, or dielectric constant. In one embodiment, the processor 270 may detect the leakage current of the vertical sidewalls from the relationship between the area and leakage current of the three-dimensional semiconductor gate stack structure. In another embodiment, the processor 270 may detect the capacitance of the vertical sidewalls from the relationship between the area and capacitance of the three-dimensional semiconductor gate stack structure. In yet another embodiment, the processor 270 may detect the dielectric constant of the vertical sidewalls from the relationship between the area and dielectric constant of the three-dimensional semiconductor gate stack structure. This will be explained in more detail with reference to Figure 4.

[0035] Figure 5 is a detailed diagram illustrating the step (step 430) of detecting the electrical characteristics of the vertical side wall in Figure 4. Figure 6 is a diagram illustrating the step (step 430) of detecting the electrical characteristics of the vertical side wall in Figure 4.

[0036] Referring to Figures 5 and 6, first, in step 531, the processor 270 may set the area and electrical characteristics of the three-dimensional semiconductor gate stack structure on the x and y axes, respectively. Specifically, the processor 270 may set the area on the x axis and the electrical characteristics on the y axis. Next, in step 533, the processor 270 may extract the electrical characteristics when the area is 0 by the y-intercept using extrapolation. Specifically, the processor 270 may derive a slope showing the relationship between the area and electrical characteristics of the three-dimensional semiconductor gate stack structure using extrapolation similar to equation (1) above, and detect the electrical characteristics of the vertical sidewall by the intercept of the slope, i.e., the y-intercept, as shown in equation (2) above. Next, in step 535, the processor 270 may detect the electrical characteristics of the vertical sidewall by the electrical characteristics when the area is 0. Here, Figure 6 shows an example of detecting leakage current by electrical characteristics, but is not limited to this. In other words, the processor 270 may detect the capacitance or dielectric constant of the vertical sidewall using the same method as described with reference to Figure 6.

[0037] Therefore, the electrical characteristics of the vertical sidewalls can be utilized to optimize semiconductor devices realized in a three-dimensional semiconductor gate stack structure. This can improve the performance and reliability of the semiconductor devices.

[0038] According to this disclosure, the electrical characteristics of only the vertical sidewalls of a small three-dimensional semiconductor gate stack structure can be precisely detected. Therefore, the electrical characteristics of the vertical sidewalls can be used to optimize semiconductor devices realized in a three-dimensional semiconductor gate stack structure. Specifically, the changes in leakage current and EOT in the vertical sidewalls can be accurately grasped, and an optimal gate insulating film with stable electrical characteristics can be derived. This makes it possible to present semiconductor devices with improved CET, thereby enhancing the overall performance and reliability of the semiconductor device.

[0039] In short, this disclosure provides an analytical method and apparatus for evaluating the electrical properties of vertical sidewalls in a three-dimensional semiconductor gate stacked structure.

[0040] In this disclosure, the operation method of the computing device 200 may include the steps of providing a plurality of three-dimensional semiconductor gate stack structures, each having a different area and each containing the same vertical sidewall within its area (step 410), measuring the electrical characteristics of each three-dimensional semiconductor gate stack structure (step 420), and detecting the electrical characteristics of the vertical sidewall from the relationship between the area and the electrical characteristics by extrapolation (step 430).

[0041] In this disclosure, the vertical sidewall refers to the lateral surface of a three-dimensional semiconductor gate stack structure and may mean a region that extends vertically from the channel to the gate metal within the three-dimensional semiconductor gate stack structure.

[0042] In this disclosure, the electrical properties of the three-dimensional semiconductor gate stack structure and the electrical properties of the vertical sidewalls may include at least one of leakage current, capacitance, or dielectric constant.

[0043] In this disclosure, the step of detecting the electrical properties of a vertical side wall (step 430) may include the steps of extracting the electrical properties when the area is 0 from the relationship between the area and the electrical properties by extrapolation (steps 531 and 533), and detecting the electrical properties of the vertical side wall by the electrical properties when the area is 0 (step 535).

[0044] In this disclosure, the step of extracting electrical characteristics when the area is 0 (steps 531 and 533) may include the step of setting the area on the x-axis and the electrical characteristics on the y-axis (step 531), and the step of extracting electrical characteristics when the area is 0 by the y-intercept (step 533).

[0045] In this disclosure, the step of measuring the electrical properties of each of the three-dimensional semiconductor gate stack structures (step 420) may include at least one of the following steps for each of the three-dimensional semiconductor gate stack structures: measuring at least one of leakage current or capacitance, or deriving the dielectric constant using the measured capacitance for each of the three-dimensional semiconductor gate stack structures.

[0046] In this disclosure, the computing device 200 includes a memory 260 and a processor 270 connected to the memory 260 and configured to execute at least one instruction word stored in the memory 260, wherein the processor 270 may be provided with a plurality of three-dimensional semiconductor gate stack structures, each having a different area and each containing the same vertical sidewall within its area, and the electrical characteristics of each three-dimensional semiconductor gate stack structure may be measured, and the electrical characteristics of the vertical sidewall may be detected from the relationship between the area and the electrical characteristics by extrapolation.

[0047] In this disclosure, the vertical sidewall refers to the lateral surface of a three-dimensional semiconductor gate stack structure and may mean a region that extends vertically from the channel to the gate metal within the three-dimensional semiconductor gate stack structure.

[0048] In this disclosure, the electrical properties of the three-dimensional semiconductor gate stack structure and the electrical properties of the vertical sidewalls may include at least one of leakage current, capacitance, or dielectric constant.

[0049] In this disclosure, the processor 270 may be configured to extract the electrical characteristics when the area is 0 from the relationship between the area and the electrical characteristics by extrapolation, and to detect the electrical characteristics of the vertical side wall by the electrical characteristics when the area is 0.

[0050] The above-described apparatus may be implemented by hardware components, software components, and / or combinations of hardware and software components. For example, the apparatus and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as processors, controllers, ALUs (arithmetic logic units), digital signal processors, microcomputers, FPGAs (field programmable gate arrays), PLUs (programmable logic units), microprocessors, or various devices capable of executing and responding to instructions. The processing unit may execute an operating system (OS) and one or more software applications running on the OS. The processing unit may also respond to software execution, access data, record, manipulate, process, and generate data. For convenience of understanding, it may be described as if a single processing unit is used, but those skilled in the art will understand that the processing unit may include multiple processing elements and / or multiple types of processing elements. For example, the processing unit may include multiple processors or one processor and one controller. Other processing configurations, such as parallel processors, are also possible.

[0051] Software may include computer programs, code, instructions, or a combination of one or more of these, which may configure a processing unit to operate as desired, or which may instruct the processing unit independently or collectively. Software and / or data may be embodied in any kind of machine, component, physical device, computer recording medium, or device for interpretation based on the processing unit or for providing instructions or data to the processing unit. Software may be distributed across a networked computer system, and may be recorded or executed in a distributed manner. Software and data may be recorded on one or more computer-readable recording media.

[0052] Methods according to various embodiments may be implemented in the form of program instructions executable by various computer means and recorded on a computer-readable medium. In this case, the medium may continuously record computer-executable programs or may temporarily record them for execution or download. Furthermore, the medium may be various recording or storage means in the form of a combination of one or more hardware components, and may be a medium directly connected to a computer system or distributed on a network. Examples of media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and media configured to record program instructions such as ROM, RAM, and flash memory. Other examples of media include recording media and storage media managed by app stores that distribute applications, and sites and servers that supply and distribute various other software.

[0053] The various embodiments described herein and the terminology used herein should be understood not to limit the technology described herein to any particular embodiment, but to include various modifications, equivalents, and / or substitutes of the applicable embodiments. In connection with the description of the drawings, similar reference numerals have been used for similar components. Singular expressions may also include plural expressions unless the context clearly indicates otherwise. In this specification, expressions such as “A or B,” “A and / or B,” “A, B or C,” or “A, B, and / or C” may include all possible combinations of the items listed together. Expressions such as “first,” “second,” “first,” or “second” modify the applicable component regardless of order or importance, and are used only to distinguish one component from another, and not to limit the applicable component. When it is stated that a component (e.g., component 1) is "connected (functionally or communicatively)" or "linked" to another component (e.g., component 2), such component may be directly connected to such other component, or it may be connected via another component (e.g., component 3).

[0054] According to various embodiments, each component of the above-described components (e.g., a module or program) may include one or more individuals. According to various embodiments, one or more components or steps of the above-described components may be omitted, or one or more other components or steps may be added. Alternatively or additionally, multiple components (e.g., a module or program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in the same or similar manner as those performed by the respective components among the multiple components before integration. According to various embodiments, steps performed by a module, program, or other component may be performed sequentially, in parallel, iteratively, or heuristically, or one or more steps may be performed in a different order, or omitted, or one or more other steps may be added. [Explanation of Symbols]

[0055] 200 computing devices 210 Camera Module 220 Communication Module 230 Input Modules 240 Output Modules 250 measurement modules 260 memory 270 processors

Claims

1. A method for operating a computing device, The steps include providing a plurality of three-dimensional semiconductor gate stacked structures, each having a different area and each containing the same vertical side wall within that area, The steps include measuring the electrical characteristics of each of the three-dimensional semiconductor gate stacked structures, The steps include detecting the electrical characteristics of the vertical side wall from the relationship between the area and the electrical characteristics using an extrapolation method, including, How computing devices operate.

2. The aforementioned vertical sidewall represents the lateral surface of the three-dimensional semiconductor gate stack structure and signifies the region that extends vertically from the channel to the gate metal within the three-dimensional semiconductor gate stack structure. A method for operating the computing device according to claim 1.

3. The electrical properties of the three-dimensional semiconductor gate stack structure and the electrical properties of the vertical sidewalls include at least one of leakage current, capacitance, or dielectric constant. A method for operating the computing device according to claim 1.

4. The step of detecting the electrical characteristics of the vertical side wall is: The extrapolation method involves extracting the electrical characteristics when the area is 0 from the relationship between the area and the electrical characteristics, A step of detecting the electrical characteristics of the vertical side wall based on the electrical characteristics when the area is 0, including, A method for operating the computing device according to claim 1.

5. The step of extracting the electrical characteristics when the area is 0 is: The steps include setting the area on the x-axis and the electrical characteristics on the y-axis, A step of extracting the electrical characteristics when the area is 0 using the y-intercept, including, A method for operating the computing device according to claim 4.

6. The step of measuring the electrical characteristics of each of the three-dimensional semiconductor gate stacked structures is as follows: A step of measuring at least one of leakage current or capacitance for each of the three-dimensional semiconductor gate stacked structures, or A step of deriving the dielectric constant using the capacitance measured for each of the three-dimensional semiconductor gate stacked structures. Including at least one of the following: A method for operating the computing device according to claim 3.

7. A computing device, Memory and A processor connected to the memory and configured to execute at least one instruction word stored in the memory, Includes, The aforementioned processor, Multiple three-dimensional semiconductor gate stacked structures are provided, each having a different area and each containing the same vertical side wall within that area. The electrical characteristics of each of the three-dimensional semiconductor gate stacked structures were measured. The system is configured to detect the electrical characteristics of the vertical side wall from the relationship between the area and the electrical characteristics using an extrapolation method. Computing device.

8. The aforementioned vertical sidewall represents the lateral surface of the three-dimensional semiconductor gate stack structure and signifies the region that extends vertically from the channel to the gate metal within the three-dimensional semiconductor gate stack structure. The computing device according to claim 7.

9. The electrical properties of the three-dimensional semiconductor gate stack structure and the electrical properties of the vertical sidewalls include at least one of leakage current, capacitance, or dielectric constant. The computing device according to claim 7.

10. The aforementioned processor, By the above extrapolation method, the electrical characteristics when the area is 0 are extracted from the relationship between the area and the electrical characteristics. The system is configured to detect the electrical characteristics of the vertical side wall based on the electrical characteristics when the area is 0. The computing device according to claim 7.

Images