Self-aligned core pattern

Abstract

The present invention provides an IC device structure having a glass core substrate or interposer that can accommodate more IC dies than substrates made from organic materials. [Solution] The apparatus comprises a glass panel 204 having a first surface 206, a trench 212 within the first surface, and a routing structure on the first surface. The conductive trace 228 comprises a first portion 236 within the trench and a second portion 234 above the first surface, extending laterally for a length greater than the width of the conductive trace. The first portion extends to a depth below the first surface, and the second portion extends to a height above the first surface, with the depth being at least 10 percent or at least 20 percent of the height. The second portion comprises side walls having a concave or planar profile. The glass panel comprises a second surface opposite to the first surface. Through-glass vias (TGVs) extend between the first and second surfaces and are coupled to the conductive trace.

Description

Background Art

[0001] In the manufacture of electronic devices, integrated circuit (IC) packaging is a stage of semiconductor device fabrication in which an IC fabricated monolithically on a chip (or die) is assembled into a "package" that can protect the IC chip from physical damage. The package connects the IC chip to other packaged IC chips and / or scaled host components such as a package substrate or printed circuit board. Multiple IC chips can be assembled to form a multi-die package. Some IC packages include an interposer, which is a substrate used to connect multiple chips or dies within an integrated circuit (IC) package.

[0002] Conventionally, package substrates and interposers have been made from organic materials. More recently, package substrates and interposers having a glass core between layers of organic material have been introduced. Substrates having a glass core have advantages over conventional substrates having an organic core, including small total thickness variation (TTV), high plated-through-hole (PTH) density, high dimensional stability, and high strength.

[0003] The layer of organic material on the surface of a package substrate or interposer with a glass core generally includes a redistribution structure having one or more redistribution layers (RDLs), as well as interconnect features on the upper and bottom surfaces of the redistribution structure. Package substrates and interposers having a glass core generally also include through-glass vias (TGVs). The redistribution structure and TGVs couple the upper and bottom interconnect features, and thus the package substrate or interposer can couple IC dies to each other and to a circuit board.

[0004] The subjects described herein are shown in the accompanying drawings as examples, not as limitations. For the sake of brevity and clarity of the examples, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. The drawings referred to as “section,” “side,” and “plan” correspond to orthogonal planes in the Cartesian coordinate system. Thus, section and side views are taken in the xz plane, and plan views are taken in the xy plane. Typically, a side view in the xz plane is a section. Where appropriate, the drawings are marked with axes to indicate the orientation of the drawing. Furthermore, where appropriate, reference numerals are repeated between drawings to indicate corresponding or similar elements. The drawings are as follows: [Brief explanation of the drawing]

[0005] [Figure 1] The flowchart shows a method for forming an IC device structure having a glass core substrate or interposer according to several embodiments, wherein the glass core includes a conductive trace having a portion in a trench on the glass surface and a portion above the surface.

[0006] [Figure 2] These are cross-sectional views of glass panels received in the initial fabrication stage according to several embodiments.

[0007] [Figure 3-1] Figures 3A and 3B are cross-sectional views of a glass panel unfolding as the operation in the method shown in Figure 1 is put into practice, according to several embodiments. [Figure 3-2] Figure 3C is a cross-sectional view of a glass panel as it unfolds in several embodiments as the operation in the method shown in Figure 1 is put into practice. [Figure 3-3] Figures 3D and 3E are cross-sectional views of a glass panel unfolding as the operation in the method shown in Figure 1 is put into practice, according to several embodiments. [Figure 3-4]Figure 3F is a cross-sectional view of a glass panel as it unfolds in several embodiments as the operation in the method shown in Figure 1 is put into practice. [Figure 3-5] Figures 3G and 3H are cross-sectional views of a glass panel unfolding as the operation in the method shown in Figure 1 is put into practice, according to several embodiments. [Figure 3-6] Figure 3I is a cross-sectional view of a glass panel as it unfolds in several embodiments as the operation in the method shown in Figure 1 is put into practice. [Figure 3-7] Figures 3J and 3K are cross-sectional views of a glass panel unfolding as the operation in the method shown in Figure 1 is put into practice, according to several embodiments. [Figure 3-8] Figure 3L is a cross-sectional view of a glass panel as it unfolds in several embodiments as the operation in the method shown in Figure 1 is put into practice. [Figure 3-9] Figure 3M is a cross-sectional view of a glass panel as it unfolds in several embodiments as the operation in the method shown in Figure 1 is put into practice.

[0008] [Figure 4] This is a cross-sectional view of a glass core package substrate or interposer in a fabrication stage of the method shown in Figure 1, according to several embodiments.

[0009] [Figure 5] This figure shows a system in a fabrication stage according to the method shown in Figure 1, after one or more IC dies and host components have been mounted on the package substrate shown in Figure 4, according to several embodiments.

[0010] [Figure 6-1] Figures 6A and 6B are cross-sectional views of a glass panel unfolding as the operation in the method shown in Figure 1 is put into practice, according to several alternative embodiments. [Figure 6-2]Figures 6C and 6D are cross-sectional views of the glass panel as it unfolds in several alternative embodiments as the operation in the method shown in Figure 1 is put into practice. [Figure 6-3] Figures 6E and 6F are cross-sectional views of the glass panel as it unfolds in several alternative embodiments as the operation in the method shown in Figure 1 is put into practice. [Figure 6-4] Figures 6G and 6H are cross-sectional views of the glass panel as it unfolds in several alternative embodiments as the operation in the method shown in Figure 1 is put into practice.

[0011] [Figure 7] The present invention illustrates several embodiments of a data server machine employing a mobile computing platform and one or more devices comprising an IC package having a substrate or interposer having a glass core, wherein the glass core includes conductive traces having a portion inside a trench within the glass and a portion above the surface of the glass.

[0012] [Figure 8] This is a functional block diagram of an electronic computing device according to several embodiments. [Modes for carrying out the invention]

[0013] Embodiments will be described with reference to the attached figures. Specific configurations and arrangements are illustrated and discussed in detail, but this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of this specification. Those skilled in the art will also see that the techniques and / or arrangements described herein can be employed in a variety of other systems and applications not described in detail herein.

[0014] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. Also, for the sake of facilitating the description of features within the drawings, it should be noted that directions and references such as up, down, upper, bottom, and the like may be used. Accordingly, the following detailed description should not be taken in a limiting sense, and the scope of the claimed subject matter is defined only by the appended claims and their equivalents.

[0015] In the following description, numerous details are set forth. However, it will be apparent to those skilled in the art that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments. Throughout this specification, references to "an embodiment", "one embodiment", or "some embodiments" mean that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in an embodiment", "in one embodiment", or "in some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment. Further, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment if the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0016] As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Also, the term "and / or" as used herein is to be understood to refer to and encompass any and all possible combinations of one or more of the associated listed items.

[0017] The terms "coupled" and "connected" along with their derivatives may be used herein to describe a functional or structural relationship between components. These terms are not intended to be synonymous with each other. Rather, in a particular embodiment, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in physical or electrical contact with each other either directly or indirectly (having other intervening elements between them), and / or that two or more elements cooperate or interact with each other (such as being in a causal relationship).

[0018] The terms "over", "under", "between", and "on" as used herein refer to the relative position of one component or material with respect to another component or material when such physical relationships are of interest. A "vertical" orientation is in the z - direction. A "lateral" orientation is in the x or y - direction. For example, in the context of materials, one material or layer that is over or under another may be in direct contact or may have one or more intervening materials or layers. Further, one material that is between two materials or layers may be in direct contact with the two materials / layers or may have one or more intervening materials / layers. In contrast, a first material or layer "on" a second material or layer is in direct physical contact with that second material / layer. Similar distinctions will be made in the context of component assemblies.

[0019] As used throughout this description and in the claims, a list of items connected by the terms “at least one of” or “one or more of” may mean any combination of the listed terms. For example, the phrase “at least one of A, B, or C” may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0020] Unless otherwise specified in the context of specific use, the term “majority” means more than 50% or more than half. For example, a composition that is predominantly the first component means that more than half of the composition is the first component (e.g., <50 atomic%). The term “primarily” means the most abundant or largest portion. For example, a composition that is primarily the first component means that the composition has more of the first component than any other component. A composition that is primarily the first and second components means that the composition has more of the first and second components than any other component. The term “substantially” means that only accidental variation exists. For example, a composition that is substantially the first component means that the composition may further contain <1% of any other component. A composition that is substantially the first and second components means that the composition may further contain <1% of any other component used in place of either the first or second component.

[0021] As the miniaturization of circuits within IC dies coupled to package substrates or interposers progresses, the desired number of connections between the IC die and the package substrate or interposer may increase. It may be desirable to provide a large number of conductive traces on the surface of the glass core. Furthermore, it may be necessary to supply a significant amount of power to the IC die, which may require connections capable of carrying relatively large currents. Electrical resistance is inversely proportional to the cross-sectional area of ​​a wire. A conductive trace with a particular cross-sectional area will have lower resistance than another conductive trace with a smaller cross-sectional area. It may be desirable to provide conductive traces with relatively large cross-sectional areas.

[0022] More conductive traces can be placed on the surface of the glass core, and they can be wider and taller. However, one challenge with this method is that conductive traces on the surface of the glass core must be separated by a certain distance according to the design rules. As the height above the surface increases, the design rules may require larger spacing distances. Another challenge is that making the conductive traces wider limits the number of conductive traces that can be placed on the surface of the glass core.

[0023] The embodiments relate to IC device structures having a glass core substrate or interposer, the glass core including conductive traces having portions in trenches on the glass surface and portions above the surface. The embodiments also relate to self-aligning core patterning processes. An advantage of the embodiments described herein is that the conductive traces having portions in trenches and portions above the glass may have a higher aspect ratio than other conductive traces that exist only on the glass surface. Another advantage of the conductive traces described herein is that they may have a larger cross-sectional area than conductive traces that exist only on the glass surface, and the increased thickness provided by the portions in trenches of the conductive traces gives the conductive traces described herein a lower electrical resistance than conductive traces that exist only on the glass surface. A further advantage of the embodiments described herein is that the package substrate or interposer having a glass core is more robust and can accommodate more IC dies than substrates made from organic materials.

[0024] As shown in Figure 1, various fabrication methods can be employed to form an IC device package structure having one or more of the features described herein. Figure 1 shows a flowchart of a method for forming an IC device structure having a glass core substrate or interposer according to several embodiments, wherein the glass core includes conductive traces having portions in trenches on the glass surface and portions above the surface. Method 101 begins at input 110, where a workpiece containing glass of a certain thickness is received. The workpiece may be prepared upstream of Method 101 and may be in the form of a large panel, a wafer, or similar. The workpiece received at input 110 may be patterned with a plurality of holes and trenches, or the workpiece may not be patterned, as shown, for example, in Figure 2.

[0025] Figure 2 is a cross-sectional view of a glass panel 204 received in an initial fabrication stage 202 according to several embodiments. The advantages of fabricating IC device package structures on glass are that the flatness and / or thickness control of the glass preform is superior to that of an initial substrate based on an organic material (e.g., epoxy), and the cost can be significantly lower than that of a single-crystal material (e.g., silicon). The glass 204 is a solid bulk material layer which may be preformed into any shape suitable for a packaging workpiece, such as a rectangle. The glass 204 includes a first surface 206 and a second surface 208 opposite to the first surface. The glass 204 has a thickness T1 which may vary by the mounting, while limiting warping while remaining thin enough to allow the formation of through vias and trenches at pitches as small as possible, for example, made possible by the surface flatness of the glass 204. In exemplary embodiments, the thickness T1 is advantageously 0.1 mm to 3.0 mm.

[0026] Although not shown, one or more material layers may coat either or both of the first surface 206 or the second surface 208 of the glass 204, thereby making the glass 204 a bulk or core layer of a multilayer substrate. Exemplary coating materials include inorganic materials such as silicon nitride (SiNx) or silicon oxynitride (SiOxNy). In other embodiments, a silicon layer (polycrystalline or monocrystalline) may coat one or both sides of the glass 204. An organic material layer, such as a polymer dielectric material, may also coat one or more sides of the glass 204. Thus, the glass 204 is advantageously substantially free of organic materials (e.g., without adhesives), although the workpiece in the fabrication stage 202 may contain organic materials within the substrate stack containing the glass 204.

[0027] Glass 204 is advantageously composed of mostly silicon and oxygen. In some embodiments, glass 204 contains at least 23 percent silicon and at least 26 percent oxygen by weight (i.e., wt%). Glass 204 may further contain one or more additives such as aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, or zinc. In some embodiments where glass 204 contains at least 23 wt% Si and at least 26 wt% O, glass 204 further contains at least 5 wt% Al. Additives in glass 204 may form suboxides (A2O), monooxides (AO), binary oxides (AO2), ternary oxides (ABO3), and mixtures thereof. For example, glass 204 may contain AlOx (e.g., Al2O3), BOx (e.g., B2O3), MgOx (e.g., MgO), CaOx (e.g., CaO), SrOx (e.g., SrO), BaOx (e.g., BaO), SnOx (e.g., SnO2), NaOx (e.g., Na2O), KOx (e.g., K2O), POx (e.g., P2O3), ZrOx (e.g., ZrO2), LiOx (e.g., Li2O), TiOx (e.g., TiO2), or ZnOx (e.g., ZnO2). Therefore, depending on the chemical composition, glass 204 may be called, for example, silica, fused silica, aluminosilicate, borosilicate, or aluminoborosilicate.

[0028] Glass 204 is advantageously a bulk material with a substantially homogeneous composition, in contrast to composite materials that may simply contain glass fillers and / or fibers. In some embodiments, glass 204 is substantially amorphous, but glass 204 may also have other forms or microstructures, such as polycrystalline (e.g., nanocrystalline).

[0029] Returning to Figure 1, Method 101 proceeds to Block 115, where features are formed within the unpatterned glass 204. Exemplary features include through holes or openings within the glass, and trenches or channels on one or both surfaces of the glass. Features may be fabricated by any process known to be suitable for bulk glass. In some embodiments, Block 115 requires laser ablation, a glass etching process (laser-assisted or otherwise), or any other technique known to be suitable for forming features within or through a certain thickness of glass with desired xy size (diameter, or width and length), z size (depth), and feature pitch.

[0030] Figures 3A and 3B are cross-sectional views of a glass panel 204 in fabrication stage 210 after features have been drawn in the glass panel using laser irradiation, according to several embodiments. Figure 3C is a plan view of the glass panel 204 in fabrication stage 210. The cross-sectional view in Figure 3A is taken along line A-A' (shown in Figure 3C). The cross-sectional view in Figure 3B is taken along line B-B' (shown in Figure 3A). In the examples shown in Figures 3A-3C, the locations 211 of the trenches 212 and 213 of the through-holes 214 are drawn using laser irradiation that alters one or more properties of the glass 204. In some embodiments, the laser irradiation is pulsed (e.g., at a femtosecond rate), which makes the portion of the glass 204 exposed to the irradiation more susceptible to etching by a chemical etchant. Thus, the laser patterning process in 210 can define both the location and dimensions of the trenches 212 and through-holes 214.

[0031] Figures 3D and 3E are cross-sectional views of the glass panel 204 in the fabrication stage 216 after features have been etched into the glass panel, according to several embodiments. Figure 3F is a plan view of the glass panel 204 in the fabrication stage 216. As shown in Figures 3D, 3E, and 3F, the etching process forms trenches 212 and through-holes 214. In the examples shown, the trenches 212 are formed on both the first surface 206 and the second surface 208, but in other examples, the trenches 212 may be formed on only one of the surfaces. The dimensions of the through-holes 214 and trenches 212 may vary depending on the implementation, as will be described below. Any suitable wet or dry etching process known in the art may be employed in the fabrication stage 216.

[0032] The trench 212 includes side walls 218. In some embodiments, the side walls 218 are substantially linear or planar. In some examples, as shown in Figure 3E, the side walls 218 are substantially perpendicular to the surfaces 206, 208. In other examples, the side walls 218 may have a positive taper with respect to one of the surfaces 206, 208, for example, the trench is wider on that surface than at the bottom surface 219 of the trench. In yet another example, the side walls 218 may have a negative taper with respect to one of the surfaces 206, 208, for example, the trench is narrower on that surface than at the bottom of the trench.

[0033] Returning to Figure 1, Method 101 proceeds to Block 120, where conductive features are formed on one or both surfaces of the glass panel, and the TGV is formed. The conductive features may include traces or lines. The conductive features and TGV may be formed using subtractive etching, semi-additive etching, or any other suitable process. Figures 3G to 3L show subtractive etching methods for fabricating conductive features and TGV according to several embodiments. Figures 6A to 6H show semi-additive etching methods for fabricating conductive features and TGV according to several embodiments.

[0034] Figures 3G and 3H are cross-sectional views of the glass panel 204 in the fabrication stage 220 after the conductive material 222 has been deposited and after the photoresist 224 has been applied over the conductive material 222, according to several embodiments. Figure 3I is a plan view of the glass panel 204 in the fabrication stage 220. As shown in Figures 3G to 3I, the conductive material 222 covers both surfaces 206 and 208 and fills the through holes 214 and trenches 212. The conductive material 222 can be any conductive material, including, but not limited to, metals such as copper, aluminum, gold, titanium, nickel, tungsten, silver, zirconium, cobalt, and alloys thereof. The conductive material 222 can be deposited by any suitable process known in the art. In some examples, the conductive material 222 is formed by sputtering copper or another suitable metal onto surfaces 206 and 208.

[0035] In Figures 3G to 3I, the photoresist 224 is applied on and at selected locations on the conductive material 222 on surfaces 206, 208. Any suitable photoresist can be used. In some embodiments, the photoresist 224 is a dry film resist. The photoresist 224 can be formed using any suitable technique. For example, the photoresist 224 may be applied using vacuum lamination or hot lamination techniques. Furthermore, in Figures 3G to 3I, the photoresist 224 may be applied to the entire surface and then patterned by a photolithography process to form openings in which the conductive material 222 is removed in a subsequent operation to form conductive features, such as conductive traces 228, at specific locations on surfaces 206, 208.

[0036] Figures 3J, 3K, and 3M are cross-sectional views of the glass panel 204 in the fabrication stage 226 after the unmasked portions of the conductive material 222 and the photoresist 224 have been removed to expose the conductive trace 228 and conductive features 230, according to several embodiments. Figure 3L is a plan view of the glass panel 204 in the fabrication stage 226. A cross-section of TGV229 can be seen in Figure 3J. The conductive trace 228 comprises a first portion 236 within the trench 212 and a second portion 234 above the surface of the glass 204, for example, the first surface 206 or the second surface 208. The conductive trace 228 and conductive features 230 have an upper surface 231 and side walls 232 extending above surface 206. In the examples shown in Figures 2J-L, the conductive trace 228 and conductive features 230 are formed using a subtractive etching method, which etches the conductive material 222 through an etching mask of photoresist defined by lithography. In alternative embodiments, the conductive trace 228 and conductive feature 230 may be formed using, for example, a semi-additive method as described elsewhere in this specification.

[0037] The conductive trace 228 is generally located within the trench 212, but a segment 233 (also called a portion) of the conductive trace 228 may extend laterally for a length L3 away from the trench 212 or TGV 229. For example, segment 233 may be above the first surface 206 but not above the trench or TGV. Thus, the conductive trace 228 may have a first thickness T2 away from the trench and a second thickness T3 above the trench 212. The first thickness T2 is between the surface 206 and the upper surface 231 of the conductive trace 228. The second thickness T3 is between the bottom surface 219 of the trench and the upper surface 231. The second thickness T3 is greater than the first thickness T2. In some examples, the length L3 is greater than the width W1 of the conductive trace or the width W2 of the trench, however this is not required.

[0038] The conductive trace 228 has a laterally extending length L1, a width W1 at the upper surface 231 of the conductive trace 228, and a width W2. The width W2 may be adjacent to the glass surface, for example, the first surface 206, or at the bottom surface 219 of the trench 212. The width W1 may be at the upper surface 231 of the conductive trace 228. In embodiments, the width W1 may be between 30 and 50 microns. In some examples, the widths W1 and W2 are approximately equal. In some examples, the width W1 may be slightly narrower than W2, for example, 5 to 10 percent narrower. In some examples, the width W1 may be slightly wider than W2, for example, 5 to 10 percent wider.

[0039] In some embodiments, the conductive trace 228 extends a lateral length L1, where L1 is greater than the width W1 or W2 of the conductive trace. In some examples, the conductive trace 228 has a lateral dimension L1 of 40 microns to 10 mm or greater. As shown in Figures 3J and 3L, part of the conductive trace 228 may be over the TGV, and other parts may not be over the TGV. For example, the conductive trace 228 extends a lateral length L2 that is not over the TGV. In some examples, the length L2 of the conductive trace extends between the first and second TGVs. In some examples, the length L2 of the conductive trace extends between the TGV and conductive features other than the TGV (not shown in Figure 3J) in the routing structure on the surface of the glass 204, for example, the first surface 206 or the second surface 208. In some examples, the conductive trace 228 extends without spanning the location where the TGV (or other conductive features in the glass 204) intersects with the first surface 206. For example, the conductive trace 228 may extend between first and second features (not shown in Figure 3J or Figure 3L) on the first surface 206. As another example, the conductive trace 228 may extend between first and second features within a routing structure on the first surface 206. As mentioned, the conductive trace 228 may also extend a length L3 that is not inside or above the trench 212.

[0040] As shown in Figure 3K, the conductive trace 228 may have a height H1 (e.g., z height) above the first surface 206 (or second surface 208), which is between 5 and 75 microns. The conductive trace 228 may extend to a depth D1 (e.g., z height) below the first surface 206. The depth D1 may be between 5 microns and 40-50 percent of the glass thickness T1. In some examples, the conductive trace 228 may extend to a depth D1 between 0.05 mm and 1.5 mm. As mentioned, the conductive trace 228 may have a width W1 or W2. When two conductive traces 228 are adjacent to each other, a minimum spacing S1 is required between the conductive traces. The minimum spacing S1 required between adjacent conductive traces 228 also applies to conventional conductive traces. For example, two or more adjacent conventional conductive traces on the surface of a glass core or inside a dielectric in a redistribution structure may require a minimum spacing S1 between the traces. An advantage of the embodiments described herein is that, by adding depth within the glass panel, adjacent conductive traces 228 of a given width can be thicker than adjacent conventional conductive traces of the same width. Therefore, the conductive traces 228 can offer lower electrical resistance than conventional conductive traces. Lower electrical resistance is particularly advantageous for conductive traces 228 that transmit power signals.

[0041] In embodiments employing the subtractive etching method, the minimum spacing S1 between adjacent conductive traces 228 can be 1 to 2 times the height H1. Thus, in some examples, the height H1 is in the range of 15 to 25 microns, and S1 is in the range of 30 to 50 microns.

[0042] Depending on the process being implemented, the sidewall 232 may have a profile with a concave curve or scalloped shape indicating a subtractive etching method. The conductive trace 228 may have a first corner C1 between the upper surface 231 and the sidewall 232. Furthermore, there may be a second corner C2 where the sidewall 232 intersects with the first surface 206 (or second surface 208). According to some embodiments, the conductive trace 228a shown in Figure 3K includes a first corner C1 without significant undercut or overhang at the first corner C1. The second corner C2 of the conductive trace 228a is curved and intersects with the first surface 206.

[0043] Figure 3M shows examples of adding profiles to the sidewalls 232 of conductive traces fabricated using subtractive etching, according to several embodiments. The conductive trace 228b shown in Figure 3M includes a first corner C1 having an undercut or overhang at the first corner C1. The second corner C2 of the conductive trace 228b intersects the first surface 206 with a vertically linear or planar profile.

[0044] The conductive trace 228c shows a sidewall 232 having a concave, curved profile defined by a radius of curvature R1. In some examples, the sidewall may be curved to a greater degree, as indicated by the radius of curvature R3, or to a lesser degree, as indicated by the radius of curvature R2. In Figure 3M, the dotted lines indicate sidewall profiles with greater or less curvature. The conductive trace 228c shows varying degrees of undercut at the first corner C1.

[0045] The conductive trace 228d has a width W4 at the first surface 206 where the first portion 236 intersects with the second portion 234. The width W4 is smaller than the width W2 of the trench 212 at either the first surface 206 or the bottom surface 219. The second corner C2 of the conductive trace 228d may have a depression or valley between the vertical range of the side wall 232 and the first surface 206, indicating that a small portion of the conductive material 222 in the trench 212 has been removed, i.e., the conductive material in the first portion 236 has been removed.

[0046] The conductive trace 228e has a width W5 on the first surface 206, where the width W5 is greater than the width W2 of the trench 212. The second corner C2 of the conductive trace 228d may include a laterally extending portion that overlaps with the width W2 of the trench 212.

[0047] Referring again to Figure 1, method 101 proceeds to block 130, where the redistribution structure is formed on the surface of the glass panel 204. Figure 4 is a cross-sectional view of the glass panel 204 in a fabrication stage after the redistribution structures 404 and 406 have been formed, according to several embodiments. According to some embodiments, the structure shown in Figure 4 may be a package substrate 402. In other embodiments, the structure shown in Figure 4 may be an interposer. The package substrate 402 includes a glass panel 204 having conductive traces 228 and conductive features 230, similar to the examples shown in Figures 3J to 3L. (The orientation of the glass panel 204 is reversed from that in Figure 3J.) The redistribution structure 404 is on the first surface 206 and comprises one or more layers of package metallization, including a plurality of front line metallizations 408 and front via metallizations 410 between line metallization levels. The redistribution structure 406 on the second surface 208 comprises one or more layers of package metallization, including a plurality of back-side line metallizations 412 and back-side via metallizations 414 between line metallization levels. The via metallizations can vertically interconnect the line metallizations with the conductive traces 228 and conductive features 230. In some examples, the package substrate 402 may have only one redistribution structure on one surface.

[0048] The redistribution structures 404 and 406 comprise a first surface 405a, 405b adjacent to the glass panel 204, and a second surface 407a, 407b opposite the first surface, which may be called the “outer” surface. As shown in Figure 4, interconnects 416, 418 (also called contact pads) are formed on the outer surfaces of the redistribution structures 404 and 406. The interconnects 416, 418 may be separated by solder resist material 420. Via metallization interconnects line metallization, conductive traces 228, and conductive features 230 vertically to the interconnects 416, 418 on the outer surfaces. The conductive traces 228 and conductive features 230, along with the metallization features within the redistribution structures, may be used to route electrical signals to the interconnects 416, 418. For example, conductive traces 228 can be used as part of a network for routing power and electrical signals from interconnections on one surface to interconnections on the opposite surface, or to electrical components within the glass panel 204. Via metallizations 410, 414 and line metallizations 408, 412 within the package substrate 402 may be formed using, for example, additive or semi-additive methods. Via metallizations 410, 414 and line metallizations 408, 412 may contain copper. However, other conductive materials are also possible.

[0049] The package substrate metallization is embedded within one or more layers of the package substrate insulator 422. In exemplary embodiments, the package substrate insulator 422 comprises an organic dielectric material (e.g., a polymer). The package substrate insulator 422 may comprise an epoxy resin, phenolic glass, or a resin film such as the GX series film commercially available from Ajinomoto Fine Techno Co., Ltd. Exemplary epoxy resins include novolac acrylates such as epoxy phenol novolac (EPN) or epoxy cresol novolac (ECN). In some specific examples, the package substrate insulator 422 is a bisphenol A epoxy resin containing, for example, epichlorohydrin. In other examples, the package substrate insulator 422 comprises a bisphenol F epoxy resin (containing epichlorohydrin). In other examples, the package substrate insulator 422 comprises an aliphatic epoxy resin which may be monofunctional (e.g., dodecanol glycidyl ether), difunctional (butanediol diglycidyl ether), or have a higher number of functional groups (e.g., trimethylolpropane triglycidyl ether). In yet another example, the package substrate insulator 422 comprises a glycidylamine epoxy resin such as triglycidyl-p-aminophenol (3 functional groups) and N,N,N,N-tetraglycidyl-bis-(4-aminophenyl)-methane (4 functional groups).

[0050] Returning to Figure 1, Method 101 follows Block 140, in which the IC device package 502 is completed, according to some embodiments. Figure 5 is a cross-sectional view of the IC device package 502 in a fabrication stage after one or more IC dies and host components have been mounted on the package substrate, according to some embodiments. As shown in Figure 5, IC dies 504a and 504b are mounted on the surface of the package substrate 402, and the package substrate 402 is mounted on the host component 506.

[0051] In some embodiments, IC dies 504a and 504b may be attached to an interconnect 416 of a package substrate 402 by solder features 512. In some embodiments, the interconnect 416 is directly bonded to conductive features (not shown) of IC dies 504a and 504b using a hybrid bonding technique. When hybrid bonding is employed, surface metal features embedded within the insulator of one IC die are directly fused to surface metal features embedded within the insulator of another die (or in this case, within the redistribution structure 404). The hybrid bonding interface between dies may include both metallurgically interdiffused metals and chemically bonded insulators.

[0052] IC dies 504a and 504b may include circuits for performing any desired function. For example, either IC die 504a or 504b may be a logic circuit, a power management integrated circuit, a transmitter, a receiver, a memory controller, a communication controller, a controller, a processor, an application-specific integrated circuit (ASIC), or a memory. Either IC die 504a or 504b may be a photonic integrated circuit (PIC) or may include optical or photonic elements. The IC device package 502 may be coupled to a power supply 530. The power supply 530 may be coupled to IC dies 504a and 504b via a package substrate 402 having a host component 506 and a glass core. Power may be supplied from the power supply 530 to IC dies 504a and 504b by a network including conductive structures in the package substrate 402, e.g., conductive traces 228, conductive features 230, and metallization features in redistribution structures 404, 406.

[0053] The package substrate 402 can be attached to the host component 506 by reflowing a first-level interconnect (FLI) 511. In exemplary embodiments, the FLI interconnect 511 is a solder (e.g., SAC) microbump, but other interconnect features are also possible. In some embodiments, the host component 506 is predominantly silicon. The host component 506 may also include one or more alternative materials known to be suitable for interposers or package substrates (e.g., epoxy preforms, cored or coreless laminates). The host component 506 may include one or more metallized redistribution levels (not shown) embedded within a dielectric material. The host component 506 may also include one or more IC dies embedded therein. In embodiments where the package substrate 402 is an interposer, the interposer may be attached to one or more IC dies via the redistribution structure 406 instead of the host component 506.

[0054] In other embodiments, the host component 506 includes a second-level interconnect (SLI) 520. The SLI 520 may have any solder (balls, bumps, etc.) suitable for a given host board architecture (e.g., surface mount FR4). One or more heat spreaders and / or heat sinks 550 may be further coupled to the IC dies 504a and 504b, as shown by the dashed lines, which may be advantageous, for example, if the IC dies 504a and 504b have one or more CPU cores or other circuits of similar power density.

[0055] The IC device package 502 includes a package substrate 402. The package substrate 402 comprises a glass panel having trenches on its surface and conductive traces comprising a first portion within the trenches and a second portion above the surface. In the examples presented above, the conductive traces 228 of the package substrate 402 are fabricated using a subtractive etching method. In these examples, the sidewall profiles of the conductive traces 228 have concave curves indicating that subtractive etching was performed. However, in other examples, the conductive traces 228 may not have sidewalls 232 with inwardly curved profiles. In other examples described below, the sidewalls 232 may have substantially linear or planar profiles indicating a semi-additive method.

[0056] Returning to Figure 1, in block 120 of method 101, conductive features are formed on one or both surfaces of the glass panel to form the TGV. Figures 6A to 6H show semi-additive methods for forming conductive traces on one or both surfaces of a glass panel to form the TGV, according to several embodiments. Figures 6A and 6B show fabrication stage 602 after a seed layer 604 has been deposited on the surface of the glass panel 204. Fabrication stage 602 may occur after features have been formed within the glass panel. For example, fabrication stage 602 shown in Figures 6A and 6B may occur after fabrication stage 216 shown in Figures 3D and 3E. In some examples, the seed layer 604 is a thin film of a conductive material containing copper, gold, silver, or other suitable metal. The seed layer 604 is deposited on surfaces 206, 208, on the surface of the through-hole 214, and on the surface of the trench 212, including the side walls 218 and bottom surface 219 of the trench 212.

[0057] Figures 6C and 6D are cross-sectional views of the glass panel 204 in fabrication stage 606 after the photoresist 608 has been deposited and patterned on the surface of the glass panel 204. The patterned photoresist serves as a plating mask for subsequent fabrication stages. The photoresist 608 may be patterned by a photolithography process and may include openings at designated locations for conductive traces and other conductive features. The photoresist 608 may be any suitable photoresist material known in the art. Similarly, the photolithography process may be any suitable photolithography process known in the art.

[0058] Figures 6E and 6F are cross-sectional views of the glass panel 204 in the fabrication stage 610 after electroplating the conductive material 222 onto the exposed surfaces of the glass panel 204, including surfaces 206, 208, and the surfaces of the through holes 214 and trenches 212. The conductive material 222 is plated onto the seed layer 604 within openings in the photoresist 608 plating mask.

[0059] Figures 6G and 6H are cross-sectional views of the glass panel 204 in a fabrication stage 612 after the photoresist has been removed and a seed layer etching process has been carried out to expose the conductive trace 628 and conductive feature 630, according to several embodiments. Figures 6G and 6H show a glass core structure 614 comprising the conductive trace 628, conductive feature 630, and TGV, including portions within the trench. The exposed portions of the photoresist 608 and seed layer 604 can be removed using any suitable process known in the art. The conductive trace 628 comprises a first portion 636 within the trench 212 and a second portion 634 above the surface of the glass 204, e.g., surfaces 206 and 208. The conductive trace 628 and conductive feature 630 have an upper surface 631 and a side wall 632 extending above surface 206. The second portion 634 comprises the side wall 632. The sidewall 632 has a substantially vertical profile, or a profile with an inclination of less than 10° from the vertical, indicating a semi-additive patterning method. The conductive trace 228 has an upper corner C3 between the upper surface 631 and the sidewall 632. In some examples, the upper corner C3 may be rounded (not shown in Figure 6H), which indicates a semi-additive patterning method. Similar to the conductive trace 228, the conductive trace 628 may extend laterally for a certain length, where the length is greater than the width of the conductive trace. A cross-section of TGV629 can be seen in Figure 6G.

[0060] As shown in Figure 6H, the conductive trace 628 may have a height H2 (e.g., z height) above the first surface 206 (or second surface 208), which is between 5 and 75 microns. The conductive trace 628 may extend to a depth D2 (e.g., z height) below the first surface 206. The depth D2 may be between 5 microns and 40 to 50 percent of the glass thickness T1. In some examples, the conductive trace 628 may extend to a depth D2 between 0.05 mm and 1.5 mm. The conductive trace may have a width W3. When two conductive traces 628 are adjacent to each other, a minimum spacing S2 is required between the conductive traces. The same minimum spacing S2 required between adjacent conductive traces 628 may also apply to conventional conductive traces. An advantage of the embodiments described herein is that, by adding depth within the glass panel, adjacent conductive traces 628 of a given width W3 may be thicker than adjacent conventional conductive traces of the same width W3. Therefore, conductive traces 628 can offer lower electrical resistance than conventional conductive traces. Lower electrical resistance is particularly advantageous for conductive traces 628 that transmit power signals. In embodiments where the semi-additive method is used, the minimum spacing S2 between adjacent conductive traces 628 can be 0.25 to 0.50 times the height H2. Thus, in some examples, the height H2 is in the range of 15 to 25 microns, and S2 is in the range of 3.50 to 13 microns.

[0061] A redistribution structure can be formed on one or both of the surfaces 206, 208 of the glass core structure 614 to form a package substrate or interposer in a manner similar to that described with reference to Figure 4 and the package substrate 402. According to some embodiments, a package substrate comprising the glass core structure 614 may be contained within an IC device package, such as the IC device package 502 described with reference to Figure 5. Thus, according to some embodiments, the IC device package may include one or more IC dies and host components mounted on a package substrate comprising the glass core structure 614 with the redistribution structure. In some embodiments, the IC device package may include one or more IC dies mounted on an interposer comprising the glass core structure 614 with the redistribution structure.

[0062] Figure 7 shows a data server machine employing one or more devices comprising a mobile computing platform and an IC device package 750 (or interposer) having a substrate with a glass core, wherein the glass core includes conductive traces having a portion inside a trench within the glass and a portion above the surface of the glass, as described, for example, elsewhere in this specification. The server machine 706 may be any commercial server, for example, arranged in a rack and including any number of high-performance computing platforms networked together for electronic data processing. The mobile computing platform 705 may be any portable device configured for electronic data display, electronic data processing, wireless electronic data transmission, or the like, respectively. For example, the mobile computing platform 705 may be a tablet, smartphone, laptop computer, etc., and may include a display screen (e.g., capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 710, and a battery 715.

[0063] Whether deployed within an integrated system 710 as shown in enlarged figure 720, or as a standalone package within a server machine 706, the IC device package 750 (or interposer), as described elsewhere in this specification, comprises a substrate having a glass core, the glass core including conductive traces having portions inside trenches within the glass and portions above the surface of the glass. The IC device package 750 may further be coupled to a host board 760 together with one or more of the following: a power management integrated circuit (PMIC) 730, an RF (radio frequency) integrated circuit (RFIC) 725 including a broadband RF (radio frequency) transmitter and / or receiver (TX / RX) (e.g., including a digital baseband and an analog front-end module further comprising a power amplifier on the transmit path and a low-noise amplifier on the receive path), and a controller 735. The PMIC 730 may perform battery power regulation, DC / DC conversion, etc., and has an input coupled to a battery 715, and an output that provides current to other functional modules. As further shown, in exemplary embodiments, the RFIC725 has an output coupled to an antenna (not shown) and implements any of a number of radio standards or protocols, including but not limited to Wi-Fi® (IEEE 802.11 family), WiMAX® (IEEE 802.16 family), IEEE 802.20, Long-Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM®, GPRS, CDMA, TDMA, DECT, Bluetooth®, their derivatives, and any other radio protocols designated as 3G, 4G, 4G, and above.

[0064] Figure 8 is a functional block diagram of an electronic computing device 800 according to one embodiment of the present invention. The computing device may be found inside a mobile computing platform 705 or a server machine 706 as described elsewhere in this specification. The device 800 further includes a package substrate 802 that hosts a number of components, including, but not limited to, a processor 804 (e.g., an application processor). The processor 804 may be physically and / or electrically coupled to the package substrate 802. Generally, the terms “processor” or “microprocessor” may refer to any device or part of a device that processes electronic data from a number of registers and / or memories and converts such electronic data into other electronic data that can be further stored in the number of registers and / or memories. In some embodiments, the package substrate 802 may be an IC device package having a substrate with a glass core, the glass core including conductive traces having a portion inside a trench in the glass and a portion above the surface of the glass, as described elsewhere in this specification. In some examples, one or more components of the computing device 800 include an interposer having a substrate with a glass core, the glass core including conductive traces having a portion inside a trench within the glass and a portion above the surface of the glass, as described elsewhere herein.

[0065] In various examples, one or more communication chips 806 may also be physically and / or electrically coupled to the package substrate 802. In further implementations, the communication chip 806 may be part of the processor 804. The computing device 800 may include other components that may or may not be physically and electrically coupled to the package substrate 802, depending on its application. These other components include, but are not limited to, volatile memory (e.g., DRAM 832), non-volatile memory (e.g., ROM 835), flash memory (e.g., NAND or NOR), magnetic memory (MRAM 830), graphics processor 822, digital signal processor, cryptographic processor, chiplet 812, antenna 825, touchscreen display 815, touchscreen controller 865, battery 816, audio codec, video codec, power amplifier 821, global positioning system (GPS) device 840, compass 845, accelerometer, gyroscope, speaker 820, camera 841, and mass storage devices (such as hard disk drives, solid-state drives (SSDs), compact disks (CDs), digital versatile disks (DVDs), and the like) or the like.

[0066] The communication chip 806 may enable wireless communication for the transfer of data to and from the computing device 800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through the use of modulated electromagnetic radiation over a non-solid medium. This term does not imply that the associated device does not include any wired connections, although this may not be the case in some embodiments. The communication chip 806 may implement any of a number of wireless standards or protocols. As discussed, the computing device 800 may include multiple communication chips 806. For example, a first communication chip may be dedicated to short-range wireless communication such as Wi-Fi® and Bluetooth®, and a second communication chip may be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX®, LTE, Ev-DO, and others.

[0067] While some features described herein have been explained with reference to various implementations, this explanation is not intended to be constrained. Therefore, various modifications and other implementations of the implementations described herein, though obvious to those skilled in the art to whom this disclosure relates, are considered to be within the spirit and scope of this disclosure.

[0068] The present invention is not limited to the embodiments described, but it will be recognized that it can be put into practice with modifications and changes without departing from the scope of the appended claims. For example, the embodiments described above may include certain combinations of features further provided below.

[0069] Example 1: A glass panel having a surface, a trench within the surface, and a routing structure above the surface; and a conductive trace having a first portion within the trench and a second portion above the surface, wherein the conductive trace extends laterally for a certain length, and the length is greater than the width of the conductive trace.

[0070] Example 2: The apparatus according to Example 1, wherein the first portion extends to a certain depth below the surface, and the second portion extends to a certain height above the surface, the depth being at least 20 percent of the height.

[0071] Example 3: The apparatus according to Example 1 or Example 2, wherein the second part includes a side wall having a concave profile.

[0072] Example 4: The apparatus according to Example 1 or Example 2, wherein the second part includes a side wall having a planar profile.

[0073] Example 5: The apparatus according to any one of Examples 1 to 3, wherein the conductive trace has a third portion on the surface that extends laterally away from the trench.

[0074] Example 6: The apparatus according to any one of Examples 1 to 3 or Example 5, wherein the routing structure includes a first surface adjacent to the surface, a second surface opposite to the first surface, and metallization features that connect the conductive traces to interconnection features of the second surface.

[0075] Example 7: The apparatus according to Example 6, further comprising: the surface is a first surface; the trench is a first trench; the conductive trace is a first conductive trace; the length is a first length; the width is a first width; the glass panel is a second surface opposite to the first surface, the second surface includes a second trench; and a second conductive trace extending laterally within the second trench by a second length, the second conductive trace having a second width, the second conductive trace including a third portion within the second trench, a fourth portion above the second surface, the second length being greater than the second width.

[0076] Example 8: The apparatus according to Example 7, further comprising: the routing structure is a first routing structure; the metallization feature is a first metallization feature; the interconnection feature is a first interconnection feature; a second routing structure on the second surface, the second routing structure including a third surface adjacent to the second surface, a fourth surface opposite to the third surface, and a second metallization feature that connects the second conductive trace to the second interconnection feature on the fourth surface.

[0077] Example 9: The apparatus according to Example 8, wherein the glass panel further comprises glass through vias extending between the first conductive trace and the second conductive trace.

[0078] Example 10: The apparatus according to Example 8, further comprising an integrated circuit (IC) die coupled to the first interconnection feature.

[0079] Example 11: Apparatus comprising: a glass panel having a first surface, a second surface opposite to the first surface, and a trench in the first surface; a conductive trace having a first portion in the trench and a second portion above the first surface, the conductive trace extending laterally over a length between first and second positions on the first surface, the second position being spaced apart from the first position; and a glass through-via (TGV) extending between the first and second surfaces, wherein the TGV is coupled to the conductive trace at the first position.

[0080] Example 12: The apparatus according to Example 11, further comprising: a first routing structure on the first surface, the first routing structure having a first face adjacent to the first surface, a second face opposite to the first surface, and a first metallization feature that connects the conductive trace at the second position to a first interconnection feature on the second surface; and a second routing structure on the second surface, the second routing structure having a third face adjacent to the second surface, a fourth face opposite to the third surface, and a second metallization feature that connects the TGV to a second interconnection feature on the fourth surface.

[0081] Example 13: The apparatus according to Example 12, further comprising an integrated circuit (IC) die coupled to the first interconnection feature, and a host component coupled to the second interconnection feature.

[0082] Example 14: The apparatus according to Example 12, further comprising a power supply coupled to the second interconnection feature.

[0083] Example 15: The apparatus according to Example 11 or Example 12, wherein the first portion extends to a certain depth below the first surface, and the second portion extends to a certain height above the first surface, the depth being at least 10 percent of the height.

[0084] Example 16: The apparatus according to Example 11, Example 12, or Example 15, wherein the conductive trace has a third surface, a side wall, and a corner where the third surface and the side wall intersect, and the side wall has a profile with an overhang at the corner.

[0085] Example 17: The apparatus according to Example 11 or Example 12, wherein the first portion has a first width on the first surface; the second portion has a second width on the first surface; and the second width is greater than or less than the first width.

[0086] Example 18: A method comprising the steps of forming a trench on a first surface of a glass panel; forming a conductive trace, the step of forming the conductive trace comprising depositing a conductive material on the first surface and on a second surface within the trench; and forming a first routing structure on the first surface.

[0087] Example 19: The method according to Example 18, wherein the step of forming the conductive trace further comprises the steps of applying a mask containing a photoresist material onto the conductive material, and etching a portion of the conductive material inside an opening in the mask.

[0088] Example 20: The method of Example 18, wherein the step of forming the conductive trace further comprises the steps of applying a seed layer onto the first surface and the second surface; applying a mask containing a photoresist material onto the seed layer; and the step of depositing the conductive material further comprises the step of electroplating the conductive material at positions defined by openings in the mask. [Other possible items] [Item 1] A glass panel having a surface, trenches within the surface, and a routing structure on the surface; and A conductive trace having a first portion within the trench and a second portion above the surface, wherein the conductive trace extends laterally for a certain length, the length being greater than the width of the conductive trace. A device equipped with the following features. [Item 2] The apparatus according to item 1, wherein the first portion extends to a certain depth below the surface, and the second portion extends to a certain height above the surface, the depth being at least 20 percent of the height. [Item 3] The apparatus according to item 1, wherein the second part includes a side wall having a concave profile. [Item 4] The apparatus according to item 1, wherein the second part includes a side wall having a planar profile. [Item 5] The apparatus according to item 1, wherein the conductive trace has a third portion on the surface that extends laterally away from the trench. [Item 6] The apparatus according to item 1, wherein the routing structure includes a first surface adjacent to the surface, a second surface opposite to the first surface, and metallization features that connect the conductive traces to interconnection features of the second surface. [Item 7] The surface is a first surface, the trench is a first trench, the conductive trace is a first conductive trace, the length is a first length, the width is a first width, and the glass panel is A second surface opposite to the first surface, the second surface including a second trench; and A second conductive trace extending laterally within the second trench for a second length, the second conductive trace having a second width, the second conductive trace including a third portion within the second trench, a fourth portion above the second surface, and the second length being greater than the second width. The apparatus described in item 6, further comprising the following: [Item 8] The routing structure is a first routing structure, the metallization feature is a first metallization feature, and the interconnection feature is a first interconnection feature. A second routing structure on the second surface, the second routing structure including a third surface adjacent to the second surface, a fourth surface opposite to the third surface, and a second metallization feature that connects the second conductive trace to a second interconnection feature on the fourth surface. The apparatus described in item 7, further comprising the following: [Item 9] The apparatus according to item 8, wherein the glass panel further comprises glass through vias extending between the first conductive trace and the second conductive trace. [Item 10] The apparatus according to item 8, further comprising an integrated circuit (IC) die coupled to the first interconnection feature. [Item 11] A glass panel having a first surface, a second surface opposite to the first surface, and a trench within the first surface; A conductive trace having a first portion within the trench and a second portion above the first surface, wherein the conductive trace extends laterally over a length between the first and second positions on the first surface, and the second position is spaced apart from the first position; and Glass through vias (TGVs) extending between the first and second surfaces, wherein the TGVs are coupled to the conductive trace at the first position. A device equipped with the following features. [Item 12] A first routing structure on the first surface, the first routing structure having a first surface adjacent to the first surface, a second surface opposite to the first surface, and a first metallization feature that connects the conductive traces at the second position to a first interconnection feature on the second surface; and A second routing structure on the second surface, the second routing structure having a third surface adjacent to the second surface, a fourth surface opposite to the third surface, and a second metallization feature that connects the TGV to the second interconnection feature on the fourth surface. The apparatus described in item 11, further comprising the above. [Item 13] The apparatus according to item 12, further comprising an integrated circuit (IC) die coupled to the first interconnection feature, and a host component coupled to the second interconnection feature. [Item 14] The apparatus according to item 12, further comprising a power supply coupled to the second interconnection feature. [Item 15] The apparatus according to item 11, wherein the first portion extends to a certain depth below the first surface, and the second portion extends to a certain height above the first surface, the depth being at least 10 percent of the height. [Item 16] The apparatus according to item 11, wherein the conductive trace has a third surface, a side wall, and a corner where the third surface and the side wall intersect, and the side wall has a profile with an overhang at the corner. [Item 17] The first portion has a first width on the first surface; The second portion has a second width on the first surface; and The apparatus according to item 11, wherein the second width is greater than or less than the first width. [Item 18] A step of forming a trench on the first surface of a glass panel; The step of forming a conductive trace, the step of forming the conductive trace, includes the step of depositing a conductive material on the first surface and on the second surface in the trench; and Step of forming a first routing structure on the first surface. A method that includes [a certain feature]. [Item 19] The step of forming the conductive trace is: The step of applying a mask containing a photoresist material onto the conductive material; and The step of etching a portion of the conductive material inside the opening in the mask. The method described in item 18, further comprising: [Item 20] The step of forming the conductive trace is: A step of applying a seed layer to the first surface and the second surface; The step of applying a mask containing a photoresist material onto the seed layer; and It further possesses, The step of depositing the conductive material further includes the step of electroplating the conductive material at a position defined by the opening in the mask. The method described in item 18.

Claims

1. A glass panel having a surface, trenches within the surface, and a routing structure on the surface; and A conductive trace having a first portion within the trench and a second portion above the surface, wherein the conductive trace extends laterally for a certain length, and the length is greater than the width of the conductive trace. A device equipped with the following features.

2. The apparatus according to claim 1, wherein the first portion extends to a certain depth below the surface, and the second portion extends to a certain height above the surface, the depth being at least 20 percent of the height.

3. The apparatus according to claim 1, wherein the second portion includes a side wall having a concave profile.

4. The apparatus according to claim 1, wherein the second portion includes a side wall having a planar profile.

5. The apparatus according to claim 1, wherein the conductive trace has a third portion on the surface that extends laterally away from the trench.

6. The apparatus according to claim 1, wherein the routing structure includes a first surface adjacent to the surface, a second surface opposite to the first surface, and a metallization feature that connects the conductive traces to interconnection features of the second surface.

7. The surface is a first surface, the trench is a first trench, the conductive trace is a first conductive trace, the length is a first length, the width is a first width, and the glass panel is A second surface opposite to the first surface, the second surface including a second trench; and A second conductive trace extending laterally within the second trench for a second length, the second conductive trace having a second width, the second conductive trace including a third portion within the second trench, a fourth portion above the second surface, and the second length being greater than the second width. The apparatus according to claim 6, further comprising the above.

8. The routing structure is a first routing structure, the metallization feature is a first metallization feature, and the interconnection feature is a first interconnection feature. A second routing structure on the second surface, the second routing structure including a third surface adjacent to the second surface, a fourth surface opposite to the third surface, and a second metallization feature that connects the second conductive trace to a second interconnection feature on the fourth surface. The apparatus according to claim 7, further comprising the above.

9. The apparatus according to claim 8, wherein the glass panel further comprises glass through vias extending between the first conductive trace and the second conductive trace.

10. The apparatus according to claim 8, further comprising an integrated circuit (IC) die coupled to the first interconnection feature.

11. The first portion extends to a certain depth below the surface, the depth below the surface being in the range of 0.5 to 1.5 millimeters; and The second portion extends to a certain height above the surface, and the height above the surface is in the range of 5 to 75 microns. The apparatus according to claim 1.

12. The first portion extends to a certain depth below the surface, the depth below the surface ranging from 5 microns to 50% of the thickness of the glass panel; and The second portion extends to a certain height above the surface, and the height above the surface is in the range of 5 to 75 microns. The apparatus according to claim 1.

13. The second portion includes a side wall comprising a first corner adjacent to the surface and a second corner away from the surface, where, The first section of the side wall adjacent to the first corner is substantially perpendicular to the surface; and The second section of the side wall adjacent to the second corner protrudes above the surface. The apparatus according to claim 1 or 2, or any one of claims 4 to 12.

14. A glass panel having a first surface, a second surface opposite to the first surface, and a trench within the first surface; A conductive trace having a first portion within the trench and a second portion above the first surface, wherein the conductive trace extends laterally over a length between a first position and a second position on the first surface, the second position being spaced apart from the first position; and Glass through vias (TGVs) extending between the first surface and the second surface, wherein the TGVs are coupled to the conductive trace at the first position. A device equipped with the following features.

15. A first routing structure on the first surface, the first routing structure having a first surface adjacent to the first surface, a second surface opposite to the first surface, and a first metallization feature that connects the conductive traces at the second position to a first interconnection feature on the second surface; and A second routing structure on the second surface, the second routing structure having a third surface adjacent to the second surface, a fourth surface opposite to the third surface, and a second metallization feature that connects the TGV to the second interconnection feature of the fourth surface. The apparatus according to claim 14, further comprising:

16. The apparatus according to claim 15, further comprising an integrated circuit (IC) die coupled to the first interconnection feature, and a host component coupled to the second interconnection feature.

17. The apparatus according to claim 15, further comprising a power supply coupled to the second interconnection feature.

18. The apparatus according to claim 14 or 15, wherein the first portion extends to a certain depth below the first surface, and the second portion extends to a certain height above the first surface, the depth being at least 10 percent of the height.

19. The apparatus according to claim 14 or 15, wherein the conductive trace has a third surface, a side wall, and a corner where the third surface and the side wall intersect, and the side wall has a profile with an overhang at the corner.

20. The first portion has a first width on the first surface; The second portion has a second width on the first surface; and The apparatus according to claim 14 or 15, wherein the second width is greater than or less than the first width.

21. The step of forming a trench on the first surface of the glass panel; and The step of forming a conductive trace, the step of forming the conductive trace, includes the step of depositing a conductive material on the first surface and on the second surface in the trench. A method that includes [a certain feature].

22. The step of forming the conductive trace is: The step of applying a mask containing a photoresist material onto the conductive material; and The step of etching a portion of the conductive material inside the opening in the mask. The method according to claim 21, further comprising:

23. The step of forming the conductive trace is: Steps include applying a seed layer to the first surface and the second surface; A step of applying a mask containing a photoresist material onto the seed layer; It further possesses, The step of depositing the conductive material further includes the step of electroplating the conductive material at a position defined by the opening in the mask. The method according to claim 21.

24. The method according to any one of claims 21 to 23, further comprising the step of forming a first rewiring structure on the first surface.

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