Polymer glass through-glass via buffer layer in glass core substrate

Abstract

The stress on the glass core during high-temperature processes is relieved, providing a glass core substrate for integrated circuit packages or other applications. [Solution] In one embodiment, the substrate 200A includes a glass core layer 202 having conductive glass through vias (TGVs) 208, and an intermediate layer 210 and a polymer buffer layer 212 between the glass core layer 202 and the TGVs 208.

Description

[Background technology]

[0001] The continued growth of computing and mobile devices will drive increasing demands for higher bandwidth density and reliability within semiconductor packages. Some integrated circuit packages can incorporate glass cores, which can offer advantages over conventional packages with organic cores (for example, glass cores can be thicker and better resistant to warping throughout the manufacturing process). Through-glass vias (TGVs) can provide electrical connectivity through the glass core, for example, connecting the metallization layers on both sides of the glass core. [Brief explanation of the drawing]

[0002] [Figure 1] This is a diagram of an exemplary substrate having a glass core exhibiting stress cracking.

[0003] [Figure 2] Figures 2A and 2B show exemplary substrates in which a polymer TGV buffer layer is mounted between a glass core and glass through-vias (TGVs) according to embodiments of the present disclosure.

[0004] [Figure 3-1] Figures 3A, 3B, and 3C illustrate an exemplary process for manufacturing a glass core substrate having a polymer TGV buffer layer according to an embodiment of the present disclosure. [Figure 3-2] Figures 3D, 3E, and 3F illustrate an exemplary process for manufacturing a glass core substrate having a polymer TGV buffer layer according to an embodiment of the present disclosure. [Figure 3-3] Figures 3G and 3H illustrate an exemplary process for manufacturing a glass core substrate having a polymer TGV buffer layer according to an embodiment of the present disclosure.

[0005] [Figure 4-1]Figures 4A, 4B, and 4C illustrate another exemplary process for manufacturing a glass core substrate having a polymer TGV buffer layer according to an embodiment of the present disclosure. [Figure 4-2] Figures 4D, 4E, and 4F illustrate another exemplary process for manufacturing a glass core substrate having a polymer TGV buffer layer according to an embodiment of the present disclosure. [Figure 4-3] Figure 4G is a diagram illustrating another exemplary process for manufacturing a glass core substrate having a polymer TGV buffer layer according to an embodiment of the present disclosure.

[0006] [Figure 5] Figures 5A, 5B, and 5C illustrate exemplary processes for forming a polymer TGV buffer layer on a glass substrate according to some embodiments of the present disclosure.

[0007] [Figure 6] Figures 6A and 6B illustrate another exemplary process for forming a polymer TGV buffer layer on a glass substrate, according to some embodiments of the present disclosure.

[0008] [Figure 7] This is a diagram of an exemplary package substrate having a glass core with a polymer TGV buffer layer, according to embodiments of this specification.

[0009] [Figure 8] This is a diagram of an exemplary multi-die package having a glass core with a polymer TGV buffer layer, according to embodiments of this specification.

[0010] [Figure 9] This is a diagram of another exemplary multi-die package having a glass core with a polymer TGV buffer layer, according to embodiments of this specification.

[0011] [Figure 10]FIG. 10A and FIG. 10B are diagrams of an exemplary system that may incorporate the glass core architecture described herein.

[0012] [Figure 11] Top views of a wafer and die that may be included within a microelectronic assembly, according to any embodiment disclosed herein.

[0013] [Figure 12] Side cross-sectional views of an integrated circuit device that may be included within a microelectronic assembly, according to any embodiment disclosed herein.

[0014] [Figure 13] Block diagram of an exemplary electrical device that may include a microelectronic assembly, according to any embodiment disclosed herein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Integrated circuit devices have been continuously shrinking in size, and with this shrinkage, the improvement of device performance has been focused on two directions: (1) achieving chip stacking using thin chips and (2) improving the input / output (I / O) density in the substrate for multi-chip integration. Manufacturing these continuously increasing devices has been made possible by temporary bonding and peeling techniques using a hard carrier wafer, such as a glass-based core wafer. However, one of the problems associated with temporary bonding and peeling techniques is the control of warping or shrinkage after the removal of the hard carrier. When the hard glass carrier is peeled off after bump formation, the substrate may be expected to warp due to the inherent residual stress and the CTE (coefficient of thermal expansion) mismatch between various components, such as between silicon (2.6 ppm / °C), ABF (about 39 ppm / °C), and copper (17 ppm / °C). This can affect the backend process related to bump formation and the assembly process.

[0016] One way to address the above problem is to use glass or glass-based materials as the permanent substrate core since glass is harder than the organic core material. For example, glass can have a modulus of elasticity of about 60 - 90 GPa as compared to about 25 - 30 GPa for the organic core material. The permanent glass core can limit warping, thereby maintaining the TTV requirements for smaller pitch scaling. Glass Through Vias (TGVs) provide electrical connections through the glass core substrate, for example, providing electrical connections between metallization layers on both sides of the core. Current TGVs can be implemented as fully plated TGVs where the through-holes in the glass core are completely filled with a metal (e.g., copper) used for plating after a seed layer has been deposited (e.g., by sputtering). However, fully plated TGVs can be plagued by thermo-mechanical stress-related challenges due to a large amount of copper and a large CTE mismatch between copper and glass. More specifically, the large CTE mismatch between copper and glass used for plating results in radial stress when heated and tensile stress when cooled, which can cause stress cracks or other problems in the glass core.

[0017] Figure 1 illustrates an exemplary substrate 100 having a glass core layer 102 exhibiting stress cracks 110. In particular, Figure 1 illustrates a side section view showing glass through vias (TGVs) 108 within the substrate 100. The TGVs 108 may be formed from a metal (e.g., copper) and are formed within the glass core layer 102 of the substrate 100, which can form the core layer of an integrated circuit package substrate as further described below. The TGVs 108 extend from the top surface to the bottom surface of the glass core layer 102, as shown. The glass core layer 102 may comprise glass or a glass-based material. In certain embodiments, the glass core layer 102 may comprise silicon (e.g., at least 23% by weight) and oxygen (e.g., at least 26% by weight). The glass core layer 102 may be amorphous and, in some embodiments, may contain one or more additive elements (e.g., at least 5% by weight) such as aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. For example, the glass core layer 102 may be formed from one or more of the following exemplary materials: aluminosilicate, borosilicate, aluminoborosilicate, silica, or fused silica. In some embodiments, the glass core layer 102 may further contain one or more additives such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. In some embodiments, the glass core layer 102 may be made from spin-on glass (SOG) material.

[0018] As shown in the figure, the substrate 100 includes a TGV buffer layer 104 on the top and bottom surfaces of the glass core layer 102. The TGV buffer layer 104 is made of SiO x SiN x , or carbon-doped SiO xThe substrate may include one or more of the above and may be deposited by physical or chemical vapor deposition. As shown in the figure, the substrate 100 further includes a build-up dielectric layer 106 on the TGV buffer layer 104, which may be formed from an organic build-up dielectric material, such as Ajinomoto Build-Up Film (ABF).

[0019] In some cases, stress cracks (e.g., 110) may form near the area where the glass core material, TGV material, and buffer layer material come into contact. This area can be a particularly high-stress region, and cracks are likely to occur during heat treatment or high-temperature processes that the substrate may undergo during their manufacture, which may be due to a mismatch in the coefficients of thermal expansion between each of the three materials.

[0020] Embodiments herein may address these or other problems by including an organic flexible polymer buffer layer between the glass core layer and the TGV within the glass core layer. This may relieve stress on the glass core during high-temperature processes and enable higher yields of glass core substrates for integrated circuit packages or other applications. For example, some embodiments may include layers of polymers with low Young's modulus, such as polypyrrole, polythiophene, polyaniline, PEDOT (poly(3,4-ethylenedioxythiophene) polymer), PEDOT:PSS (a mixture or compound of PEDOT and polystyrene sulfonate (PSS)), polyamine, other thiophene polymers, pyrrole polymers, aniline polymers, or other low Young's modulus materials as described herein, which may avoid stress cracking / propagation.

[0021] Figures 2A and 2B illustrate exemplary substrates 200A and 200B according to embodiments of the present disclosure, which mount polymer TGV buffer layers 212 and 220 between a glass core 202 and glass through-vias (TGVs) 208. More specifically, substrate 200A in Figure 2A includes a glass core 202 with TGVs 208 passing through the glass core 202. Each exemplary substrate, as shown, includes a glass core 202 with buffer layers 204 on the top and bottom surfaces of the glass core 202, and further includes a build-up dielectric layer 206 on the buffer layers 204. In some embodiments, the buffer layer 204 is made of SiN x SiO x This may include dielectric materials such as, or other types of dielectric materials. In some embodiments, the buffer layer 204 may include a conductive material, such as a conductive seed material such as copper or another metal. The substrate may include additional layers, such as additional build-up layers and / or metallization layers, as described in the specific examples below.

[0022] The exemplary substrate 200A in Figure 2A includes an intermediate layer 210 and a polymer buffer layer 212 between the glass core 202 and the TGV 208, as shown, while the exemplary substrate 200B in Figure 2B includes a polymer buffer layer directly between the glass core 202 and the TGV 208. The polymer buffer layer may be formed as described in the following examples or in other preferred forms. As shown in each example, the metal of the TGV 208 is not in direct contact with the glass core 202 due to the presence of the polymer layer, which can be a relatively flexible material with a low Young's modulus, thereby avoiding stress on the glass core 202 and, consequently, avoiding stress cracks that may form if such a buffer layer is not present.

[0023] Figures 3A to 3H illustrate an exemplary process 300 for manufacturing a glass core substrate having a polymer buffer layer according to an embodiment of the present disclosure. The exemplary process illustrated may include operations additional to, fewer than, or different from those illustrated or described below. In some embodiments, one or more of the operations illustrated or described include multiple operations, sub-operations, and the like. Thus, the figures of FIGS. 3A to 3H may represent various stages in the manufacturing process of a device such as an integrated circuit package substrate. Although process 300 is illustrated with respect to two TGVs in the glass core substrate, it will be understood that process 300 may be used in a glass core substrate having any number of TGVs.

[0024] Referring to FIG. 3A, process 300 begins by forming holes 301 in glass core layer 302 as shown. Holes 301 may be formed by laser drilling, wet etching processes, or other suitable techniques. Next, as shown in FIGS. 3B to 3C, an adhesive layer 310 is formed on the surface of glass core layer 302, and then a polymer material layer 312 is formed on adhesive layer 310.

[0025] In some embodiments, adhesive layer 310 is a seed layer formed from a conductive material, such as a metal like copper or silver, which is deposited using atomic layer deposition (ALD). Polymer material layer 312 may include an organic conductive polymer material such as, for example, polypyrrole (containing carbon and nitrogen), polythiophene (containing carbon and sulfur), or polyaniline (containing carbon and nitrogen). When adhesive layer 310 includes a metal, conductive polymer material layer 312 may be deposited onto layer 310 by electroplating.

[0026] In other embodiments, adhesive layer 310 is an oxide or nitride dielectric material (e.g., AlO x 、ZnO x 、AlN x or TiO x) may include, for example, an organic polymer material such as PEDOT:PSS (containing carbon, sulfur, and oxygen), and the polymer material layer 312 may be deposited on the oxide / nitride adhesive layer 310 in liquid phase or by chemical vapor deposition (CVD).

[0027] After the polymer material layer 312 is formed, metal 308 may be formed inside the pores 301 and on the top / bottom surfaces of the layer, as shown in Figure 3D. In some cases, this may involve the initial formation of a seed layer followed by the growth of metal 308. Next, as shown in Figure 3E, the top and bottom surfaces may be ground or polished (e.g., by chemical mechanical polishing: CMP) to remove portions of metal 308, polymer material layer 312, and adhesive layer 310 from the top and bottom surfaces of the glass core layer 302. Next, as shown in Figure 3F, a buffer layer 304 may be formed on the top and bottom surfaces of the glass core layer 302. Next, as shown in Figure 3G, pores 305 may be formed in the buffer layer 304 above and below the TGV, and then the pores 305 may be filled with metal 315, as shown in Figure 3H, to form a connection to the TGV. Next, build-up and / or metallization layers may be formed on each side of the substrate as desired.

[0028] Figures 4A to 4G illustrate another exemplary process 400 for manufacturing a glass core substrate having a polymer buffer layer according to embodiments of the present disclosure. The illustrated exemplary process may include additional, fewer, or different operations than those illustrated or described below. In some embodiments, one or more of the operations illustrated or described include multiple operations, sub-operations, etc. Thus, the figures in Figures 4A to 4B may represent various stages in a manufacturing process for a device such as an integrated circuit package substrate. Although process 400 is illustrated with respect to two TGVs in a glass core substrate, it will be understood that process 400 may be used in glass core substrates having any number of TGVs.

[0029] Referring to Figure 4A, process 400 is initiated by forming pores 401 within the glass core layer 402 as shown. The pores 401 may be formed by laser drilling, wet etching, or other preferred techniques. Next, a polymer material layer 410 is formed on the surface of the glass core layer 402, as shown in Figure 4B. In some embodiments, the polymer material layer 410 includes an organic conductive polymer material such as PEDOT. In certain embodiments, the polymer material layer 410 may be deposited on the glass core layer 402 by molecular layer deposition (MLD) (e.g., oxidized MLD), which may, in certain cases, allow for direct deposition on the glass core layer 402 without a conductive seed layer, as in the example above. For example, a PEDOT layer may be formed on the glass core layer 402 by depositing 3,4-ethylenedioxythiophene (EDT) monomer in the presence of an oxidizing agent such as MoCl5, ReCl5, or SbCl5. In other embodiments, the polymer material layer 410 is formed by the process described below with respect to Figures 5A-5C and 6A-6B.

[0030] After the polymer material layer 410 is formed, metal 408 may be formed inside the pores 401 and on the top / bottom surfaces of the layer, as shown in Figure 4C. Next, as shown in Figure 4D, the top and bottom surfaces may be ground or polished (e.g., by chemical mechanical polishing (CMP)) to remove the metal 408 and portions of the polymer material layer 410 on the top and bottom surfaces of the glass core layer 402. Next, as shown in Figure 4E, a buffer layer 404 may be formed on the top and bottom surfaces of the glass core layer 402. Next, as shown in Figure 4F, pores 405 may be formed in the buffer layer 404 above and below the TGV, and then the pores 405 may be filled with metal 415, as shown in Figure 4G, to form connections to the TGV. Next, build-up and / or metallization layers may be formed on each side of the substrate as desired.

[0031] Figures 5A to 5C illustrate exemplary processes 500 for forming a polymer buffer layer on a glass substrate according to some embodiments of the present disclosure. The illustrated exemplary processes may include additional, fewer, or different operations than those illustrated or described below. In some embodiments, one or more of the operations illustrated or described include multiple operations, sub-operations, etc. Although process 500 is illustrated with respect to a single TGV in a glass core substrate, it will be understood that process 500 may be used in glass core substrates having any number of TGVs. In some cases, process 500 may be considered an operation performed within process 400 described above, for example, with respect to forming a polymer layer 410.

[0032] Referring to Figure 5A, the inner surfaces of the pores 501 within the glass core layer 502 are pre-treated by depositing a conductive cationic polymer 506 such as a polyamine. In some embodiments, the top and bottom surfaces of the glass core layer 502 may have a conductive seed layer 504 deposited thereon, as shown in the figure. Next, as shown in Figure 5B, permanganate (MnO -4) The treatment is applied to a conductive cationic polymer, which allows MnO2 to be absorbed on the inner wall of the pore 501. Next, as shown in Figure 5C, the EDT monomer is deposited onto the conductive cationic polymer (e.g., by spraying the monomer), and the polymer is oxidized in the presence of PSS, resulting in the formation of a thin conductive polymer layer 510, which in certain embodiments may be PEDOT:PSS. The PSS can donate H+ ions and make the layer 510 conductive.

[0033] Figures 6A and 6B illustrate another exemplary process 600 for forming a polymer buffer layer on a glass substrate according to some embodiments of the present disclosure. The illustrated exemplary processes may include additional, fewer, or different operations than those illustrated or described below. In some embodiments, one or more of the operations illustrated or described include multiple operations, sub-operations, etc. Although process 500 is illustrated with respect to a single TGV in a glass core substrate, it will be understood that process 500 may be used in glass core substrates having any number of TGVs. In some cases, process 600 may be considered an operation performed within process 300 described above, for example, with respect to forming layers 310, 312.

[0034] Referring to Figure 6A, as illustrated, a conductive seed layer 604 is deposited on the surface of the glass core layer 602. In certain embodiments, the conductive seed layer 604 may be a metal such as silver or copper, or another conductive material (e.g., a polymer material with high conductivity), deposited using ALD. In some embodiments, the conductive seed layer 604 may be deposited in a non-isolated manner. Next, as shown in Figure 6B, a layer of organic polymer material 610 is deposited on the seed layer 604 and electrolytic polymerization is performed. Electrolytic polymerization may be performed using a potentiostat, galvanostat, or cyclic voltammetry in certain embodiments. The polymer material 610 may fill the gap remaining from the seed layer 604, resulting in one or more of the advantages described above, such as preventing stress crack formation in the glass core layer 602. The seed layer 604 may be used as a working electrode for the electrolytic polymerization process and also enhance the conductivity of the resulting buffer layer. Various organic materials such as thiophene polymers, pyrrole polymers, aniline polymers, functionalized conjugated materials with adjustable work function, hydrophobic two-dimensional conjugated materials, or covalent organic frameworks (COFs) can be used as polymer materials 610. The thickness and properties of the resulting polymer buffer layer can be controlled by adjusting one or more of the following: the concentration of the solution, the thickness of the deposited organic layer, the time of the electropolymerization process, and the type of electropolymerization used. This process can be more cost-effective than techniques relying on vapor deposition (dry processes) and may also provide higher throughput compared to dry processes.

[0035] The polymer buffer layers described herein may result in low modulus values, and they can function as stress buffer layers to prevent damage to the glass core substrate from the TGV. The techniques described herein provide a simple and cost-effective method for forming such stress buffer layers within high aspect ratio structures such as TGVs, but also in blind vias or trenches.

[0036] Figure 7 illustrates an exemplary package substrate 700 having a glass core 702 having a polymer TGV buffer layer according to embodiments of this specification. The glass core 702 may contain silicon (e.g., at least 23% by weight) and oxygen (e.g., at least 26% by weight). The glass core 702 may be amorphous and, in some embodiments, may contain one or more additive elements (e.g., at least 5% by weight) such as aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. For example, the glass core 702 may be formed from one or more of the following exemplary materials: aluminosilicate, borosilicate, aluminoborosilicate, silica, or fused silica. In some embodiments, the glass core 702 may further contain one or more additives such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. In some embodiments, the glass core 702 may be made from spin-on-glass (SOG) material.

[0037] As shown, the substrate 700 includes a polymer layer 722 between the glass core 702 and the TGV 703 within the glass core 702. The polymer layer 722 may be formed according to embodiments of the present disclosure, such as those described above. In some embodiments, though not shown, the substrate 700 may include a seed layer between the glass core 702 and the polymer layer 722, similar to the intermediate layer 210 in Figure 2A and the layer 310 in Figures 3A to 3H.

[0038] Furthermore, the glass core 702 includes a dielectric layer 704 on its top and bottom surfaces, which is located between the glass core 702 and the build-up layers 706A and 706B. The build-up layers 706A and 706B are formed on the top and bottom sides of the glass core 702, with build-up layer 706A on the top side of the glass core 702 and build-up layer 706B on the bottom side of the glass core 702. The build-up layer 706 includes metallization layers (e.g., 707A-D) connected by vias (e.g., 709), which, together with TGV 703, electrically couple the solder bump 708 at the top of the package substrate 700 to the pad 710 at the bottom of the substrate. In certain cases, for example, an integrated circuit die may be coupled to the top side of the package substrate 700 and connected to a solder bump 708, and the package substrate 700 may be coupled to a circuit board (e.g., a motherboard, mainboard, etc.) by a pad 710 located at the bottom of the package substrate 700. For example, the package substrate 700 may be incorporated into the system 1000 of Figure 10A as package substrate 1004. The package substrate 700 also includes a land-side capacitor 712 coupled to the bottom side of the package substrate 700.

[0039] Figure 8 illustrates an exemplary multi-die package 800 having a glass core 802 with a polymer TGV buffer layer, according to an embodiment of this specification. The glass core 802 may be the same as the glass core 702. The package 800 also includes dielectric layers 804 on the top and bottom sides of the glass core 802, and a polymer layer 822 between the TGV 803 and the glass core 802. The polymer layer 822 may be formed similarly to the polymer layer 722, i.e., according to the embodiment of this specification. Furthermore, although not shown, in some embodiments the package 800 may include a seed layer between the glass core 802 and the polymer layer 822, similar to the intermediate layer 210 in Figure 2A and the layer 310 in Figures 3A to 3H.

[0040] Package 800 further includes build-up layers 806A and 806B formed on the top and bottom sides of the glass core 802, with build-up layer 806A formed on the top side of the glass core 802 and build-up layer 806B formed on the bottom side of the glass core 802. Build-up layers 806A and 806B include metallization layers (e.g., 807A-E) connected by vias (e.g., 809), similar to the example described above, which, together with TGV 803, electrically couple the integrated circuit (IC) dies 812A and 812B at the top of the multi-die package 800 to the pads 810 at the bottom of the package 800.

[0041] Furthermore, package 800 includes a bridge circuit configuration component 814 located within the build-up layer 806A, which electrically couples the first IC die 812A with the second IC die 812B. The bridge circuit configuration component 814 may include passive and / or active components for interconnecting the IC dies 812A and 812B. In certain embodiments, the bridge circuit configuration component 814 may be an Intel® embedded multi-die interconnect bridge (EMIB). In certain cases, the multi-die package 800 may be coupled to a circuit board (e.g., a motherboard, mainboard, etc.) by a pad 810 located at the bottom of package 800. For example, package 800 may be incorporated into system 1010 in Figure 10B as a multi-die package 1014.

[0042] Figure 9 illustrates another exemplary multi-die package 900 having a glass core 902 with a polymer TGV buffer layer, according to embodiments of this specification. The glass core 902 may be the same as the glass core 702 or the glass core 802. The package 900 also includes dielectric layers 904 on the top and bottom sides of the glass core 902, and a polymer layer 922 between the TGV 903 and the glass core 902. The polymer layer 922 may be formed similarly to the polymer layers 722 and 822, i.e., according to embodiments of this specification. Furthermore, although not shown, in some embodiments the package 900 may include a seed layer between the glass core 902 and the polymer layer 922, similar to the intermediate layer 210 in Figure 2A and the layer 310 in Figures 3A to 3H.

[0043] The multi-die package 900 further includes build-up layers 906A and 906B formed on the top and bottom sides of the glass core 902, with build-up layer 906A formed on the top side of the glass core 902 and build-up layer 906B formed on the bottom side of the glass core 902. Layers 906A and 906B include metallization layers (e.g., 907A-E) connected by vias (e.g., 909), which, together with TGV 903, electrically couple the integrated circuit (IC) dies 912A and 912B at the top of the multi-die package 900 to the pads 910 at the bottom of the package 900.

[0044] The multi-die package 900 also includes a bridge circuit component 914, similar to the bridge circuit component 814 of the multi-die package 800; however, the bridge circuit component 914 includes vias 916 from the top surface to the bottom surface of the bridge circuit component 914. The vias 916 can connect IC dies 912A, 912B to specific traces, pillars, etc., within the build-up layer 906A. In certain embodiments, the bridge circuit component 914 may be an embedded multi-die interconnect bridge with Intel® TSV (EMIB-T). In certain cases, the multi-die package 900 may be coupled to a circuit board (e.g., a motherboard, mainboard, etc.) by pads 910 located at the bottom of the package 900. For example, package 900 may be incorporated into system 1010 in Figure 10B as a multi-die package 1014.

[0045] Figures 10A and 10B illustrate exemplary systems 1000 and 1010 that may incorporate the glass core architecture described herein. The exemplary system 1000 in Figure 10A includes a circuit board 1002, which in some embodiments may be implemented as a motherboard or mainboard of a computer system. The exemplary system 1000 also includes a package substrate 1004 on which an integrated circuit die 1006 is mounted. The die 1006 may be a packaged or unpacked integrated circuit product comprising one or more integrated circuit dies (e.g., die 1102 in Figure 11, integrated circuit device 1200 in Figure 12) and / or one or more other suitable components. The die 1006 may comprise one or more computing system components, such as one or more processor units (e.g., a system-on-a-chip: SoC, a processor core, a graphics processor unit: GPU, an accelerator, a chipset processor), an I / O controller, memory, or a network interface controller. In some embodiments, the die 1006 may comprise one or more additional active or passive elements, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. In addition to comprising one or more processor units, the die 1006 may comprise additional components, such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, an input / output (I / O) controller, or a memory controller. Any of these additional components may reside on the same integrated circuit die as the processor units, or on one or more separate integrated circuit dies from the integrated circuit die comprising the processor units. These isolated integrated circuit dies may be referred to as "chiplets." The package substrate 1004 can provide an electrical connection between the die 1006 and the circuit board 1002.

[0046] Similar to system 1000, system 1010 also includes a circuit board 1012 which, in some embodiments, can be implemented as a motherboard or mainboard of a computer system. System 1010 also includes a multi-die package 1014 which includes multiple integrated circuits / dies (e.g., 1006) and interconnections between dies in one or more metallization layers. The multi-die package 1014 may include, for example, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (e.g., Intel® Embedded Multi-Die Interconnect Bridge (EMIB)), or a combination thereof.

[0047] The main circuit boards 1002 and 1012 may provide electrical connections to other components of the computer system, such as memory, storage, network interfaces, peripheral devices, power supplies, etc. The main circuit board may include one or more trace and circuit components to provide interconnections between such computer system components.

[0048] Figure 11 is a top view of a wafer 1100 and a die 1102 that may be implemented in or with any embodiment disclosed herein. The wafer 1100 may be composed of a semiconductor material and may include one or more dies 1102 having an integrated circuit structure formed on the surface of the wafer 1100. An individual die 1102 may be an iterative unit of an integrated circuit product containing any suitable integrated circuit. After the manufacturing of the semiconductor product is complete, the wafer 1100 may undergo a pulverization process in which the dies 1102 are separated from each other to provide discrete “chips” of the integrated circuit product. The die 1102 may include one or more transistors (e.g., some of the transistors 1240 in Figure 12 discussed below), support circuit configurations for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the wafer 1100 or die 1102 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, conductive-bridging RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1102. For example, a memory array formed by multiple memory devices may be formed on the same die 1102 as a processor unit (e.g., processor unit 1302 in Figure 13) or other logic configured to store information in the memory devices or execute instructions stored in the memory array.

[0049] Figure 12 is a lateral cross-sectional view of an integrated circuit device 1200 that may be included in any embodiment disclosed herein. One or more of the integrated circuit devices 1200 may be included in one or more dies 1102 (Figure 11). The integrated circuit device 1200 may be formed on a die substrate 1202 (e.g., wafer 1100 in Figure 11) and may be included in a die (e.g., die 1102 in Figure 11). The die substrate 1202 may be a semiconductor substrate composed of a semiconductor material system including, for example, a system of n-type or p-type material (or a combination of both). The die substrate 1202 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1202 may be formed using alternative materials, which may or may not be combined with silicon, including, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate 1202. Only a few examples of materials from which the die substrate 1202 may be formed are described here, but any material that can function as the basis for the integrated circuit device 1200 may be used. The die substrate 1202 may be part of a flaked die (e.g., die 1102 in Figure 11) or a wafer (e.g., wafer 1100 in Figure 11).

[0050] The integrated circuit device 1200 may include one or more device layers 1204 disposed on the die substrate 1202. The device layer 1204 may include features of one or more transistors 1240 (e.g., metal oxide semiconductor field-effect transistors: MOSFETs) formed on the die substrate 1202. The transistor 1240 may include, for example, one or more source and / or drain (S / D) regions 1220, a gate 1222 that controls the current between the S / D regions 1220, and one or more S / D contacts 1224 that route electrical signals to and from the S / D regions 1220. The transistor 1240 may include additional features not depicted for clarity, such as device isolation regions, gate contacts, and similar. The transistor 1240 is not limited to the type and configuration depicted in Figure 12 and may include a variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors such as double-gate or tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbons, nanosheets, or nanowire transistors.

[0051] Returning to Figure 12, the transistor 1240 may include a gate 1222 formed by at least two layers, a gate dielectric, and a gate electrode. The gate dielectric may include one layer or a stack of multiple layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric material.

[0052] High-k dielectric materials may contain elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used for gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when high-k materials are used, an annealing process may be performed on the gate dielectric layer to improve its quality.

[0053] The gate electrode may be formed on a gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1240 should be a p-type metal-oxide-semiconductor (PMOS) or an n-type metal-oxide-semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, one or more of which are work function metal layers and at least one of which is a filler metal layer. Furthermore, metal layers may be included for other purposes, such as barrier layers.

[0054] In the case of PMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, any of the metals discussed below with reference to NMOS transistors (e.g., for work function tuning), including ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and NMOS transistors (e.g., for work function tuning). In the case of NMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, any of the metals discussed above with reference to PMOS transistors (e.g., for work function tuning), including hafnium, zirconium, titanium carbide, tantalum carbide, and aluminum carbide, and hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0055] In some embodiments, when viewed as a cross-section of the transistor 1240 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 1202 and two sidewall portions substantially perpendicular to the top surface of the die substrate 1202. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 1202 and not including sidewall portions substantially perpendicular to the top surface of the die substrate 1202. In other embodiments, the gate electrode may consist of a combination of U-shaped and non-U-shaped planar structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed on the top surface of one or more planar non-U-shaped layers.

[0056] In some embodiments, pairs of sidewall spacers may be formed on opposing faces of the gate stack so as to surround the gate stack. These sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Multiple processes for forming sidewall spacers are well known in the art and generally include deposition and etching steps. In some embodiments, multiple spacer pairs may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposing faces of the gate stack.

[0057] The S / D region 1220 may be formed within the die substrate 1202 adjacent to the gate 1222 of an individual transistor 1240. The S / D region 1220 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1202 to form the S / D region 1220. An annealing process to activate the dopants and further diffuse them into the die substrate 1202 may follow the ion implantation process. In the latter process, the die substrate 1202 may first be etched to form a recess at the location of the S / D region 1220. Next, an epitaxial growth process may be performed to fill the recess with the material used to manufacture the S / D region 1220. In some packaging configurations, the S / D region 1220 may be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially grown silicon alloy may be in situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D region 1220 may be formed using one or more alternative semiconductor materials, such as germanium or Group III-V materials or alloys. In further embodiments, one or more layers of metals and / or metal alloys may be used to form the S / D region 1220.

[0058] Electrical signals, such as power and / or input / output (I / O) signals, can be routed to and from the device (e.g., transistor 1240) on the device layer 1204 through one or more interconnect layers (shown as interconnect layers 1206-1210 in Figure 12). For example, conductive features of the device layer 1204 (e.g., gate 1222 and S / D contact 1224) can be electrically coupled to the interconnect structure 1228 of the interconnect layers 1206-1210. One or more interconnect layers 1206-1210 can form a metallization stack (also referred to as the "ILD stack") 1219 of the integrated circuit device 1200.

[0059] The interconnect structure 1228 may be arranged within interconnect layers 1206-1210 to route electrical signals according to a variety of designs; in particular, the arrangement is not limited to the specific configuration of the interconnect structure 1228 depicted in Figure 12. Although a specific number of interconnect layers 1206-1210 are depicted in Figure 12, embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than those depicted.

[0060] In some embodiments, the interconnect structure 1228 may include lines 1228a and / or vias 1228b filled with a conductive material such as metal. Lines 1228a may be arranged to route electrical signals in a plane substantially parallel to the surface of the die substrate 1202 on which the device layer 1204 is formed. For example, lines 1228a may route electrical signals toward and from the page, and / or across the page from the viewpoint of Figure 12. Vias 1228b may be arranged to route electrical signals in a plane substantially perpendicular to the surface of the die substrate 1202 on which the device layer 1204 is formed. In some embodiments, vias 1228b may electrically couple lines 1228a of different interconnect layers 1206-1210 together.

[0061] As shown in Figure 12, interconnect layers 1206-1210 may include dielectric material 1226 disposed between interconnect structures 1228. In some embodiments, the dielectric material 1226 disposed between interconnect structures 1228 in different interconnect layers 1206-1210 may have different compositions; in other embodiments, the composition of the dielectric material 1226 between different interconnect layers 1206-1210 may be the same. Device layer 1204 may also include dielectric material 1226 disposed between transistor 1240 and the bottom layer of the metallization stack. The dielectric material 1226 included in device layer 1204 may have a different composition from the dielectric material 1226 included in interconnect layers 1206-1210. In other embodiments, the composition of the dielectric material 1226 in device layer 1204 may be the same as the dielectric material 1226 included in any one of interconnect layers 1206-1210.

[0062] The first interconnect layer 1206 (referred to as metal 1 or "M1") may be formed directly on the device layer 1204. As shown in the illustration, in some embodiments, the first interconnect layer 1206 may include lines 1228a and / or vias 1228b. Lines 1228a of the first interconnect layer 1206 may be coupled to contacts of the device layer 1204 (e.g., S / D contacts 1224). Vias 1228b of the first interconnect layer 1206 may be coupled to lines 1228a of the second interconnect layer 1208.

[0063] A second interconnect layer 1208 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1206. In some embodiments, the second interconnect layer 1208 may include vias 1228b that connect line 1228a of the second interconnect layer 1208 to line 1228a of the third interconnect layer 1210. Although line 1228a and via 1228b are structurally depicted using lines within separate interconnect layers for clarity, line 1228a and via 1228b may be structurally and / or materially adjacent in some embodiments (e.g., filled simultaneously during a dual damascene process).

[0064] A third interconnect layer 1210 (referred to as metal 3 or "M3") (and additional interconnect layers as desired) may be formed in succession on the second interconnect layer 1208 according to similar techniques and configurations described in relation to the second interconnect layer 1208 or the first interconnect layer 1206. In some embodiments, "higher" (i.e., further away from device layer 1204) interconnect layers in the metallization stack 1219 within the integrated circuit device 1200 may be thicker than lower interconnect layers in the metallization stack 1219, and lines 1228a and vias 1228b in the higher interconnect layers may be thicker than those in the lower interconnect layers.

[0065] The integrated circuit device 1200 may include a solder resist material 1234 (e.g., polyimide or a similar material) and one or more conductive contacts 1236 formed on interconnect layers 1206-1210. In Figure 12, the conductive contacts 1236 are shown to take the form of bonding pads. The conductive contacts 1236 may be electrically coupled to an interconnect structure 1228 and configured to route electrical signals from transistor 1240 to an external device. For example, solder joints may be formed on one or more conductive contacts 1236 to mechanically and / or electrically couple the integrated circuit die containing the integrated circuit device 1200 to another component (e.g., a printed circuit board or package substrate, e.g., 112). The integrated circuit device 1200 may include additional or alternative structures for routing electrical signals from interconnect layers 1206-1210; for example, the conductive contacts 1236 may include other similar features (e.g., posts) for routing electrical signals to an external component.

[0066] In some embodiments where the integrated circuit device 1200 is a double-sided die, the integrated circuit device 1200 may include another metallization stack (not shown) on the opposite side of the device layer 1204. This metallization stack may include a number of interconnect layers, as discussed above with reference to interconnect layers 1206-1210, to provide conductive paths (including conductive lines and vias) between the device layer 1204 and additional conductive contacts (not shown) on the opposite side of the conductive contact 1236 of the integrated circuit device 1200.

[0067] In other embodiments where the integrated circuit device 1200 is a double-sided die, the integrated circuit device 1200 may include one or more through-silicon vias (TSVs) through the die substrate 1202. These TSVs may contact the device layer 1204 and provide a conductive path between the device layer 1204 and additional conductive contacts (not shown) of the integrated circuit device 1200 on the opposite side of the conductive contact 1236. In some embodiments, TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts of the integrated circuit device 1200 on the opposite side of the conductive contact 1236 to the transistor 1240 and any other components integrated on the die, and the metallization stack 1219 may be used to route I / O signals from the conductive contact 1236 to the transistor 1240 and any other components integrated on the die.

[0068] In individual stacked devices, multiple integrated circuit devices 1200 may be stacked using one or more TSVs that provide connections between one of the devices and any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies may be stacked on a base integrated circuit die, and TSVs in the HBM die may provide connections between the individual HBM and base integrated circuit dies. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine-pitch solder bumps (microbumps).

[0069] Figure 13 is a block diagram of an exemplary electrical device 1300, which may include one or more embodiments disclosed herein. For example, any preferred components of the electrical device 1300 may include one or more integrated circuit devices 1200 or integrated circuit dies 1102 disclosed herein. Although numerous components are shown in Figure 13 as being included in the electrical device 1300, one or more of these components may be omitted or duplicated if appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1300 may be mounted on one or more motherboard mainboards or system boards. In some embodiments, one or more of these components are manufactured on a single system-on-chip (SoC) die.

[0070] Additionally, in various embodiments, the electrical device 1300 does not have to include one or more of the components shown in Figure 13, but it may include an interface circuit configuration for coupling one or more components. For example, the electrical device 1300 does not have to include the display device 1306, but it may include a display device interface circuit configuration (e.g., a connector and driver circuit configuration) to which the display device 1306 can be coupled. In another set of examples, the electrical device 1300 does not have to include the audio input device 1324 or the audio output device 1308, but it may include an audio input or output device interface circuit configuration (e.g., a connector and support circuit configuration) to which the audio input device 1324 or the audio output device 1308 can be coupled.

[0071] The electrical device 1300 may include one or more processor units 1302 (e.g., one or more processor units). As used herein, the terms “processor unit,” “processing device,” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1302 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. Therefore, the processor unit may be referred to as XPU (or xPU).

[0072] The electrical device 1300 may include a memory 1304 which itself may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memory), solid-state memory, and / or a hard drive. In some embodiments, the memory 1304 may include memory located on the same integrated circuit die as the processor unit 1302. This memory can be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0073] In some embodiments, the electrical device 1300 may comprise one or more processor units 1302 that are heterogeneous or asymmetrical with other processor units 1302 in the electrical device 1300. There may be various differences between the processing units 1302 in the system in terms of various value criteria, including architecture, microarchitecture, thermal performance, power consumption characteristics, and so on. These differences may effectively manifest themselves as asymmetrical and heterogeneous between the processor units 1302 in the electrical device 1300.

[0074] In some embodiments, the electrical device 1300 may include a communication component 1312 (e.g., one or more communication components). For example, the communication component 1312 may manage wireless communication for the transfer of data to and from the electrical device 1300. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data by the use of modulated electromagnetic radiation over a non-solid medium. The term “wireless” does not imply that the associated device does not include any wires, although in some embodiments it may not.

[0075] The communication component 1312 may implement any of several wireless standards or protocols, including, but are not limited to, Wi-Fi® (IEEE 802.11 family), IEEE standards including the IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), and Long-Term Evolution (LTE) projects including any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP®2")). Broadband radio access (BWA) networks compatible with IEEE 802.16 are commonly referred to as WiMAX® networks. This acronym stands for Worldwide Interoperability for Microwave Access, and is a certification mark for products that have passed compliance and interoperability tests for the IEEE 802.16 standard. The communication component 1312 may operate in accordance with the Global System for Mobile Communications (GSM®), General-Purpose Packet Radio Service (GPRS), Universal Mobile Communications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1312 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1312 may operate in accordance with Code Division Multiplexing (CDMA), Time Division Multiplexing (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and their derivatives, as well as any other radio protocols designated as 3G, 4G, 5G and beyond.In other embodiments, the communication component 1312 may operate according to several other radio protocols. The electrical device 1300 may include an antenna 1322 for facilitating and / or receiving other radio communications (such as AM or FM radio transmissions).

[0076] In some embodiments, the communication component 1312 may manage wired communications such as electrical, optical, or any other suitable communication protocol (e.g., the IEEE 802.3 Ethernet® standard). As mentioned above, the communication component 1312 may include multiple communication components. For example, a first communication component 1312 may be dedicated to shorter-range wireless communications such as Wi-Fi® or Bluetooth®, and a second communication component 1312 may be dedicated to longer-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication component 1312 may be dedicated to wireless communications, and the second communication component 1312 may be dedicated to wired communications.

[0077] The electrical device 1300 may include a battery / power circuit configuration 1314. The battery / power circuit configuration 1314 may include one or more energy storage devices (e.g., batteries or capacitors) and / or a circuit configuration for coupling components of the electrical device 1300 to an energy source separate from the electrical device 1300 (e.g., AC line power).

[0078] The electrical device 1300 may include a display device 1306 (or the corresponding interface circuit configuration discussed above). The display device 1306 may include one or more embedded or wired or wireless external visual indicators, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0079] The electrical device 1300 may include an audio output device 1308 (or the corresponding interface circuit configuration discussed above). The audio output device 1308 may include any embedded, wired, or wireless external device that generates an audible indicator, such as a speaker, headset, or earbud.

[0080] The electrical device 1300 may include an audio input device 1324 (or a corresponding interface circuit configuration as discussed above). The audio input device 1324 may include any embedded, wired, or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a MIDI (musical instrument digital interface) output). The electrical device 1300 may include a Global Navigation Satellite System (GNSS) device 1318 (or a corresponding interface circuit configuration as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 1318 may communicate with a satellite-based system and determine the geographic location of the electrical device 1300 based on information received from one or more GNSS satellites, as is known in the art.

[0081] The electrical device 1300 may include another output device 1310 (or the corresponding interface circuit configuration discussed above). Examples of other output devices 1310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0082] The electrical device 1300 may include another input device 1320 (or a corresponding interface circuit configuration as discussed above). Examples of other input devices 1320 may include an accelerometer, gyroscope, compass, image capture device (e.g., a planar or stereoscopic camera), trackball, trackpad, touchpad, keyboard, cursor control device such as a mouse, stylus, touchscreen, proximity sensor, microphone, barcode reader, Quick Response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoelectric fingertip plethysmography) sensor, galvanic skin reaction sensor, any other sensor, or radio frequency identification (RFID) reader.

[0083] The electrical device 1300 may have any desired form factor, such as handheld or mobile electrical devices (e.g., mobile phones, smartphones, mobile internet devices, music players, tablet computers, laptop computers, 2-in-1 convertible computers, portable all-in-one computers, netbooks, ultrabooks, personal digital assistants (PDAs®), ultramobile personal computers, portable gaming consoles, etc.), desktop electrical devices, servers, rack-level computing solutions (e.g., blade, tray, or thread computing systems), workstations or other networked computing components, printers, scanners, monitors, set-top boxes, entertainment control units, stationary gaming consoles, smart TVs, vehicle control units, digital cameras, digital video recorders, wearable electrical devices, or embedded computing systems (e.g., computing systems that are part of vehicles, smart appliances, consumer electronics or equipment, or manufacturing facilities). In some embodiments, the electrical device 1300 may be any other electronic device that processes data. In some embodiments, the electrical device 1300 may comprise a plurality of discrete physical components. Given the range of devices that the electrical device 1300 may present as in various embodiments, in some embodiments, the electrical device 1300 may be referred to as a computing device or computing system.

[0084] In the above description, various embodiments of the exemplary implementations are described using terminology commonly adopted by those skilled in the art to convey the essence of their operation to others skilled in the art. However, it will be apparent to those skilled in the art that the disclosure may be implemented in only some of the embodiments described. For explanatory purposes, specific numbers, materials, and configurations are described to allow for a full understanding of the exemplary implementations. However, it will be apparent to those skilled in the art that the disclosure may be implemented without all specific details. In other instances, well-known features have been omitted or simplified so as not to obscure the exemplary implementations.

[0085] Furthermore, the concepts described herein are illustrated in the accompanying figures as examples, not as limitations. In the examples shown and further described below, it will be understood that the figures may not be drawn to scale and may not include all possible layers and / or circuit components. In addition, while certain figures show transistor designs having source / drain regions, electrodes, etc., with orthogonal (e.g., vertical) boundaries, it will be understood that embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., within + / - 5 or 10 degrees of orthogonality) due to the manufacturing method used to create such devices or for other reasons. Where deemed appropriate, reference numerals may be repeated between certain figures to indicate corresponding or similar elements.

[0086] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). For the purposes of this disclosure, the phrase "at least one of A, B, and C" means (A and B), (A and C), or (A, B, and C).

[0087] As used herein, the terms “above,” “below,” “between,” “above,” and “adjacent to” may refer to the relative position of one material layer or component with respect to another layer or component. For example, a layer placed above or below another layer may be in direct contact with that other layer, or may have one or more intervening layers. Furthermore, a layer placed between two layers may be in direct contact with those two layers, or may have one or more intervening layers. In contrast, a first layer “adjacent to” a second layer is in direct contact with that second layer. Similarly, unless otherwise specified, a feature placed between two features may be in direct contact with an adjacent feature, or may have one or more intervening features.

[0088] As used herein, the term “located” in the context of a first layer or component located on a second layer or component means that the first layer or component is physically directly attached to the second layer or component (with no layers or components between the first and second layers or components), or that one or more layers or components interpose to the second layer or component. As used herein, the term “adjacent” means layers or components that are physically in contact with each other; that is, there are no layers or components between the indicated adjacent layers or components. For example, layer Y and adjacent layer X means a layer that is physically in contact with layer Y.

[0089] The above description may use the phrases "in an embodiment" or "in embodiments," which may refer to one or more of the same or different embodiments, respectively. Furthermore, the terms "equip," "include," "have," and similar terms used with respect to embodiments of this disclosure are synonyms.

[0090] The term “combined” may be used herein, along with its derivatives. “Combined” may mean one or more of the following: “Combined” may mean that two or more elements are in direct physical or electrical contact. However, “combined” may also mean that two or more elements are indirectly in contact with each other but still cooperate or interact with each other, and that one or more other elements are combined or connected between the elements said to be combined with each other. The term “directly combined” may mean that two or more elements are in direct contact.

[0091] In various embodiments, the phrase "first feature formed, deposited, or otherwise positioned on a second feature" may mean that the first feature is formed, deposited, or positioned above the second feature and that at least a portion of the first feature may be in direct contact (e.g., direct physical and / or electrical contact) or indirect contact (e.g., having one or more other features between the first and second features).

[0092] Whereever this disclosure refers to “one” or “first” element, or an equivalent expression, such disclosure includes one or more such elements, but does not require or exclude two or more such elements. Furthermore, ordinal markers for identified elements (e.g., first, second, or third) are used to distinguish between those elements and, unless otherwise specifically stated, do not indicate or suggest a required or limited number of such elements, nor do they indicate a particular position or order of such elements.

[0093] Examples for describing the techniques described throughout this disclosure are provided below. Embodiments of these techniques may include one or more of the examples described below, and any combination thereof. In some embodiments, at least one of the systems or components described in one or more of the preceding figures may be configured to perform one or more of the operations, techniques, processes, and / or methods described in the examples below.

[0094] Example 1 is a device comprising a glass layer having a pore between a first side of the glass layer and a second side of the glass layer opposite to the first side; conductive vias within the glass layer electrically coupling the first side of the glass layer and the second side of the glass layer; and a polymer layer between the glass layer and the conductive vias.

[0095] Example 2 includes the apparatus described in Example 1, further comprising an intermediate layer between the glass layer and the polymer layer.

[0096] Example 3 includes the apparatus described in Example 2, wherein the intermediate layer is in contact with the inner surface of the pores in the glass layer, and the polymer layer is in contact with the vias.

[0097] Example 4 includes the apparatus described in Example 2 or 3, wherein the intermediate layer is conductive and contains copper or silver.

[0098] Example 5 includes the apparatus described in Example 2 or 3, wherein the intermediate layer is a dielectric and contains oxygen and one or more of aluminum, zinc, and titanium.

[0099] Example 6 includes the apparatus described in Example 2 or 3, wherein the intermediate layer is a dielectric and contains nitrogen and aluminum.

[0100] Example 7 includes the apparatus described in any one of Examples 1 to 6, wherein the polymer layer has a thiophene-based polymer, a pyrrole-based polymer, or an aniline-based polymer.

[0101] Example 8 includes the apparatus described in any one of Examples 1 to 7, wherein the polymer layer comprises one of polypyrrole, polythiophene, polyaniline, PEDOT (poly(3,4-ethylenedioxythiophene)), polystyrene sulfonic acid (PSS), and polyamine.

[0102] Example 9 includes the apparatus according to any one of Examples 1 to 8, wherein the conductive via is not in direct contact with the glass layer.

[0103] Example 10 further comprises a first build-up layer above the glass layer and a second build-up layer below the glass layer, wherein a metal trace in the first build-up layer is connected to a metal trace in the second build-up layer by conductive vias, and includes the apparatus described in any one of Examples 1 to 9.

[0104] Example 11 includes the apparatus described in Example 10, further comprising an integrated circuit die, wherein conductive contacts of the integrated circuit die are connected to the metal traces in the first build-up layer.

[0105] Example 12 includes the apparatus according to any one of Examples 1 to 11, wherein the glass layer has at least 23% by weight of silicon and at least 26% by weight of oxygen.

[0106] Example 13 is a device comprising a package substrate having a glass core layer; glass through-vias (TGVs) within the glass core layer; a polymer layer between the TGVs and the glass core layer; and a build-up layer on the glass core layer, the build-up layer including metal traces connected to the TGVs.

[0107] Example 14 includes the apparatus described in Example 13, further comprising an intermediate layer between the glass core layer and the polymer layer.

[0108] Example 15 includes the apparatus described in Example 14, wherein the intermediate layer is in contact with the glass core layer and the polymer layer is in contact with the TGV.

[0109] Example 16 includes the apparatus described in Example 14 or 15, wherein the intermediate layer is conductive and contains copper or silver.

[0110] Example 17 includes the apparatus described in Example 14 or 15, wherein the intermediate layer is a dielectric and contains oxygen and one or more of aluminum, zinc, and titanium.

[0111] Example 18 includes the apparatus described in Example 14 or 15, wherein the intermediate layer is a dielectric and comprises nitrogen and aluminum.

[0112] Example 19 includes the apparatus according to any one of Examples 13 to 18, wherein the polymer layer comprises a thiophene-based polymer, a pyrrole-based polymer, or an aniline-based polymer.

[0113] Example 20 includes the apparatus described in any one of Examples 13 to 19, wherein the polymer layer comprises one of polypyrrole, polythiophene, polyaniline, PEDOT (poly(3,4-ethylenedioxythiophene)), polystyrene sulfonic acid (PSS), and polyamine.

[0114] Example 21 includes the apparatus according to any one of Examples 13 to 20, wherein the TGV is not in direct contact with the glass core layer.

[0115] Example 22 includes the apparatus according to any one of Examples 13 to 21, wherein the glass core layer contains at least 23% by weight of silicon and at least 26% by weight of oxygen.

[0116] Example 23 includes the apparatus according to any one of Examples 13 to 22, further comprising an integrated circuit die coupled to the package substrate.

[0117] Example 24 is a system comprising: an integrated circuit die; and a package substrate coupled to the integrated circuit die, the package substrate having: a glass core layer; a plurality of glass through-vias (TGVs) within the glass core layer; and a polymer layer between each TGV and the glass core layer.

[0118] Example 25 includes the system described in Example 24, further comprising an intermediate layer between the glass core layer and the polymer layer.

[0119] Example 26 includes the system described in Example 25, wherein the intermediate layer is in contact with the glass core layer and the polymer layer is in contact with the TGV.

[0120] Example 27 includes the system according to Example 25 or 26, wherein the intermediate layer is conductive and contains copper or silver.

[0121] Example 28 includes the system described in Example 25 or 26, wherein the intermediate layer is a dielectric and comprises oxygen and one or more of aluminum, zinc, and titanium.

[0122] Example 29 includes the system described in Example 25 or 26, wherein the intermediate layer is a dielectric and comprises nitrogen and aluminum.

[0123] Example 30 includes the system described in any one of Examples 24 to 29, wherein the polymer layer comprises a thiophene-based polymer, a pyrrole-based polymer, or an aniline-based polymer.

[0124] Example 31 includes the system described in any one of Examples 24 to 30, wherein the polymer layer comprises one of polypyrrole, polythiophene, polyaniline, PEDOT (poly(3,4-ethylenedioxythiophene)), polystyrene sulfonic acid (PSS), and polyamine.

[0125] Example 32 includes the system according to any one of Examples 24 to 31, wherein the TGV is not in direct contact with the glass core layer.

[0126] Example 33 includes the system according to any one of Examples 24 to 32, wherein the glass core layer contains at least 23% by weight of silicon and at least 26% by weight of oxygen.

[0127] Example 34 includes the system according to any one of Examples 24 to 33, wherein the integrated circuit die has a processor, and the system further comprises a circuit board coupled to the package substrate.

[0128] Example 35 is a method comprising the steps of: forming a pore within a glass layer; forming an adhesive layer on the inner surface of the pore; forming a polymer layer on the adhesive layer; filling the pore with metal; and forming a build-up layer on the glass layer, wherein the build-up layer has a plurality of traces and conductive vias, and at least one trace of the build-up layer is electrically coupled to the metal in the pore.

[0129] Example 36 includes the method of Example 35, wherein the adhesive layer has a metal and the polymer layer is formed using electroplating.

[0130] Example 37 includes the method of Example 36, wherein the polymer layer has a conductive polymer.

[0131] Example 38 includes the method of Example 37, wherein the polymer layer has one or more of polypyrrole, polythiophene, and polyaniline.

[0132] Example 39 includes the method of Example 35, wherein the adhesive layer has a metal and the polymer layer is formed using chemical vapor deposition (CVD).

[0133] Example 40 includes the method according to Example 39, wherein the polymer layer comprises poly(3,4-ethylenedioxythiophene) and polystyrene sulfonic acid (PEDOT:PSS).

[0134] Example 41 includes the method of Example 35, wherein the adhesive layer has a metal and the polymer layer is formed using electrolytic polymerization of a conjugated polymer.

[0135] Example 42 includes a method according to any one of Examples 35 to 41, wherein the adhesive layer is formed by atomic layer deposition (ALD).

[0136] Example 43 is a method comprising the steps of: forming a pore within a glass layer; forming a polymer layer on the inner surface of the pore; filling the pore with metal; and forming a build-up layer on the glass layer, wherein the build-up layer has a plurality of traces and conductive vias, and at least one trace of the build-up layer is electrically coupled to the metal in the pore.

[0137] Example 44 includes the method described in Example 43, wherein the polymer layer is formed using molecular layer deposition (MLD).

[0138] Example 45 includes the method of Example 43 or 44, wherein the step of forming the polymer layer includes a step of depositing monomers in the presence of an oxidizing agent.

[0139] Example 46 includes the method of Example 45, wherein the monomer comprises 3,4-ethylenedioxythiophene (EDT) and the oxidizing agent comprises chlorine and at least one of molybdenum, rhenium, and antimony.

[0140] Example 47 includes the method of Example 43, wherein the step of forming the polymer layer comprises the steps of depositing a conductive polymer on the inner surface of the pore; applying a permanganate treatment to the cationic polymer; and depositing monomers on the cationic polymer.

[0141] Example 48 includes the method according to Example 47, wherein the conductive polymer is a polyamine, the monomer is 3,4-ethylenedioxythiophene (EDT), and the EDT is deposited in the presence of polystyrene sulfonic acid (PSS).

[0142] Example 49 includes the method according to any one of Examples 43 to 48, wherein the polymer layer comprises poly(3,4-ethylenedioxythiophene) (PEDOT).

[0143] Example 50 includes the method according to Example 49, wherein the polymer layer further comprises polystyrene sulfonic acid (PSS).

[0144] Example 51 is a product formed by the method described in any one of Examples 35 to 50. [Other possible items] [Item 1] A glass layer having a pore between a first side of the glass layer and a second side of the glass layer opposite to the first side; Conductive vias within the glass layer that electrically connect the first side of the glass layer to the second side of the glass layer; and Polymer layer between the glass layer and the conductive via A device equipped with the following features. [Item 2] The apparatus according to item 1, further comprising an intermediate layer between the glass layer and the polymer layer. [Item 3] The apparatus according to item 2, wherein the intermediate layer is in contact with the inner surface of the pore in the glass layer, and the polymer layer is in contact with the via. [Item 4] The apparatus according to item 2, wherein the intermediate layer is conductive and contains copper or silver. [Item 5] The apparatus according to item 2, wherein the intermediate layer is a dielectric and comprises oxygen and one or more of aluminum, zinc, and titanium. [Item 6] The apparatus according to item 2, wherein the intermediate layer is a dielectric and contains nitrogen and aluminum. [Item 7] The apparatus according to item 1, wherein the polymer layer comprises a thiophene-based polymer, a pyrrole-based polymer, or an aniline-based polymer. [Item 8] The apparatus according to item 1, wherein the polymer layer comprises one of polypyrrole, polythiophene, polyaniline, PEDOT (poly(3,4-ethylenedioxythiophene)), polystyrene sulfonic acid (PSS), and polyamine. [Item 9] The apparatus according to item 1, wherein the conductive via is not in direct contact with the glass layer. [Item 10] The apparatus according to item 1, further comprising a first build-up layer above the glass layer and a second build-up layer below the glass layer, wherein a metal trace in the first build-up layer is connected to a metal trace in the second build-up layer by conductive vias. [Item 11] The apparatus according to item 10, further comprising an integrated circuit die, wherein conductive contacts of the integrated circuit die are connected to the metal trace in the first build-up layer. [Item 12] Package substrate, Glass core layer; Glass through vias (TGV) within the aforementioned glass core layer; The polymer layer between the TGV and the glass core layer; and A build-up layer on the glass core layer, the build-up layer includes a metal trace connected to the TGV, Package substrate A device equipped with the following features. [Item 13] The apparatus according to item 12, further comprising an intermediate layer between the glass core layer and the polymer layer. [Item 14] The apparatus according to item 12, wherein the polymer layer comprises a thiophene-based polymer, a pyrrole-based polymer, or an aniline-based polymer. [Item 15] The apparatus according to item 12, wherein the polymer layer comprises one of polypyrrole, polythiophene, polyaniline, PEDOT (poly(3,4-ethylenedioxythiophene)), polystyrene sulfonic acid (PSS), and polyamine. [Item 16] The apparatus according to item 12, wherein the TGV is not in direct contact with the glass core layer. [Item 17] The apparatus according to item 12, further comprising an integrated circuit die coupled to the package substrate. [Item 18] Integrated circuit dies; and The package substrate coupled to the integrated circuit die, the package substrate is: Glass core layer; Multiple glass through vias (TGV) within the glass core layer; and Each TGV and the polymer layer between the glass core layer Having, A system equipped with these features. [Item 19] The system according to item 18, further comprising an intermediate layer between the glass core layer and the polymer layer. [Item 20] The system according to item 18, wherein the integrated circuit die has a processor, and the system further comprises a circuit board coupled to the package substrate.

Claims

1. A glass layer having a pore between a first side of the glass layer and a second side of the glass layer opposite to the first side; Conductive vias within the glass layer that electrically connect the first side of the glass layer to the second side of the glass layer; and Polymer layer between the glass layer and the conductive via A device equipped with the following features.

2. The apparatus according to claim 1, further comprising an intermediate layer between the glass layer and the polymer layer.

3. The apparatus according to claim 2, wherein the intermediate layer is in contact with the inner surface of the pores in the glass layer, and the polymer layer is in contact with the conductive vias.

4. The apparatus according to claim 2, wherein the intermediate layer is conductive and contains copper or silver.

5. The apparatus according to claim 2, wherein the intermediate layer is a dielectric and comprises oxygen and one or more of aluminum, zinc, and titanium.

6. The apparatus according to claim 2, wherein the intermediate layer is a dielectric and comprises nitrogen and aluminum.

7. The apparatus according to claim 1, wherein the polymer layer comprises a thiophene-based polymer, a pyrrole-based polymer, or an aniline-based polymer.

8. The apparatus according to claim 1, wherein the polymer layer comprises one of polypyrrole, polythiophene, polyaniline, PEDOT (poly(3,4-ethylenedioxythiophene)), polystyrene sulfonic acid (PSS), and polyamine.

9. The apparatus according to claim 1, wherein the conductive via is not in direct contact with the glass layer.

10. The apparatus according to claim 1, wherein the glass layer is amorphous.

11. The apparatus according to claim 1, wherein the glass layer comprises at least 23% by weight of silicon and at least 26% by weight of oxygen.

12. The apparatus according to any one of claims 1 to 11, further comprising a first build-up layer above the glass layer and a second build-up layer below the glass layer, wherein a metal trace in the first build-up layer is connected to a metal trace in the second build-up layer by conductive vias.

13. The apparatus according to claim 12, further comprising an integrated circuit die, wherein a conductive contact of the integrated circuit die is connected to the metal trace in the first build-up layer.

14. Package substrate, Glass core layer; Glass through vias (TGVs) within the glass core layer; The polymer layer between the TGV and the glass core layer; and A build-up layer on the glass core layer, the build-up layer includes a metal trace connected to the TGV, Package substrate A device equipped with the following features.

15. The apparatus according to claim 14, further comprising an intermediate layer between the glass core layer and the polymer layer.

16. The apparatus according to claim 15, wherein the intermediate layer is in contact with the glass core layer and the polymer layer is in contact with the TGV.

17. The apparatus according to claim 14, wherein the polymer layer comprises a thiophene-based polymer, a pyrrole-based polymer, or an aniline-based polymer.

18. The apparatus according to claim 14, wherein the polymer layer comprises one of polypyrrole, polythiophene, polyaniline, PEDOT (poly(3,4-ethylenedioxythiophene)), polystyrene sulfonic acid (PSS), and polyamine.

19. The apparatus according to claim 14, wherein the TGV is not in direct contact with the glass core layer.

20. The apparatus according to any one of claims 14 to 19, further comprising an integrated circuit die bonded to the package substrate.

21. Integrated circuit dies; and The package substrate coupled to the integrated circuit die, the package substrate is: Glass core layer; Multiple glass through vias (TGVs) within the glass core layer; and Polymer layer between each TGV and the glass core layer Having, A system that includes these features.

22. The system according to claim 21, further comprising an intermediate layer between the glass core layer and the polymer layer.

23. The system according to claim 22, wherein the intermediate layer is in contact with the glass core layer and the polymer layer is in contact with the TGV.

24. The system according to claim 21, wherein the polymer layer comprises a thiophene-based polymer, a pyrrole-based polymer, or an aniline-based polymer.

25. The system according to any one of claims 21 to 24, wherein the integrated circuit die has a processor, and the system further comprises a circuit board coupled to the package substrate.

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