Plated magnetic vias for glass cores

Abstract

This invention provides a glass core for packaging that improves reliability by suppressing the effects of stress caused by vias formed through the glass core. [Solution] In a package substrate having a glass core 310, via openings 316 and 319 are provided that penetrate the thickness of the glass core 310, and a layer is provided on the side wall of the via opening. The glass core 310 has vias 320 in the via opening 316 which has a magnetic layer 335 A A via 320 is formed in the via opening 319 which does not have a magnetic layer 335. B Forms via 320 A and 320 B It is plated in the vertical direction.

Description

[Technical Field]

[0001] [Background technology] Glass cores for packaging substrates are an attractive option due to the improved rigidity and planarity they offer compared to existing organic cores. However, the brittle nature of glass presents several challenges in manufacturing. One problem that exists with glass cores is the high stress generated by vias formed through the glass core (i.e., through-glass vias: TGVs).

[0002] In conventional plating, a seed layer is provided along the sidewall of the via opening, and the via is plated from the sidewall. This provides a strong mechanical bond between the via and the glass core. During thermal cycling, the via expands more than the glass core, which generates high stress within the glass core. This high stress can cause crack formation or other defects that significantly affect the reliability of the glass core. [Brief explanation of the drawing]

[0003] [Figure 1] Figure 1A is a cross-sectional view of a plated magnetic via penetrating a glass core according to one embodiment, and Figure 1B is a cross-sectional view of a plated magnetic via penetrating a glass core according to one embodiment.

[0004] [Figure 2-1] Figure 2A is a cross-sectional view showing a process for forming plated magnetic vias using a bottom-up process according to one embodiment, and Figure 2B is a cross-sectional view showing a process for forming plated magnetic vias using a bottom-up process according to one embodiment.

[0005] [Figure 2-2] Figure 2C is a cross-sectional view showing a process for forming plated magnetic vias using a bottom-up process according to one embodiment, and Figure 2D is a cross-sectional view showing a process for forming plated magnetic vias using a bottom-up process according to one embodiment. [Figure 2-3] Figure 2E is a cross-sectional view showing a process for forming plated magnetic vias using a bottom-up process according to one embodiment, and Figure 2F is a cross-sectional view showing a process for forming plated magnetic vias using a bottom-up process according to one embodiment. [Figure 2-4] Figure 2G is a cross-sectional view showing a process for forming plated magnetic vias using a bottom-up process according to one embodiment.

[0006] [Figure 3-1] Figure 3A is a cross-sectional view showing a process for forming a package substrate having a glass core including plated magnetic vias formed using a bottom-up process, according to one embodiment. [Figure 3-2] Figure 3B is a cross-sectional view showing a process for forming a package substrate having a glass core including plated magnetic vias formed using a bottom-up process according to one embodiment, and Figure 3C is a cross-sectional view showing a process for forming a package substrate having a glass core including plated magnetic vias formed using a bottom-up process according to one embodiment. [Figure 3-3] Figure 3D is a cross-sectional view showing a process for forming a package substrate having a glass core including plated magnetic vias formed using a bottom-up process according to one embodiment, and Figure 3E is a cross-sectional view showing a process for forming a package substrate having a glass core including plated magnetic vias formed using a bottom-up process according to one embodiment. [Figure 3-4] Figure 3F is a cross-sectional view showing a process for forming a package substrate having a glass core including plated magnetic vias formed using a bottom-up process according to one embodiment, and Figure 3G is a cross-sectional view showing a process for forming a package substrate having a glass core including plated magnetic vias formed using a bottom-up process according to one embodiment. [Figure 3-5]FIG. 3H is a cross-sectional view showing a process of forming a package substrate having a glass core including electroplated magnetic vias formed using a bottom-up process according to one embodiment.

[0007] [Figure 4] It is a flowchart of a process of forming electroplated magnetic vias in a glass core using a bottom-up process according to one embodiment.

[0008] [Figure 5] FIG. 12 is a cross-sectional view of an electronic system including a package substrate having a glass core including electroplated magnetic vias formed using a bottom-up process according to one embodiment.

[0009] [Figure 6] FIG. 18 is a schematic diagram of a constructed computing device according to one embodiment.

DETAILED DESCRIPTION OF THE INVENTION

[0010] In accordance with various embodiments, a glass substrate having electroplated magnetic vias (PMVs) formed using a bottom-up process is described herein. In the following description, various aspects of the exemplary embodiments are described using terms commonly used by those skilled in the art to convey most of these studies to other skilled artisans. However, those skilled in the art will understand that the present disclosure may be implemented using only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are described to provide a deep understanding of the exemplary embodiments. However, those skilled in the art will understand that the present disclosure may be implemented without these specific details. In other instances, well-known features are omitted or simplified so as not to obscure the exemplary embodiments.

[0011] Various operations are described sequentially as multiple distinct operations in the manner most useful for understanding this disclosure. However, the order of these operations should not be interpreted as suggesting that they are necessarily order-dependent. In particular, these operations do not need to be performed in the order they are presented.

[0012] Various embodiments or aspects of the present disclosure are described herein. In some implementation examples, different embodiments are carried out individually. However, embodiments are not limited to those carried out individually. For example, two or more different embodiments can be combined together to be carried out as a single device, process, structure, or similar. In some examples, the entirety of various embodiments can be combined together. In other examples, a part of the first embodiment can be combined with a part of one or more different embodiments. For example, a part of the first embodiment can be combined with a part of the second embodiment, or a part of the first embodiment can be combined with a part of the second embodiment and a part of the third embodiment.

[0013] As mentioned above, existing glass cores offer rigidity and / or improved planarity compared to organic cores. However, the strong mechanical bonding between glass through vias (TGVs) and the glass core creates significant stress within the glass core during thermal cycling. This can lead to crack formation or other damage in the glass core, negatively impacting its reliability. Furthermore, the high aspect ratio of TGVs makes it difficult to form void-free TGVs in a cost-effective manner. For example, atomic layer deposition processes can be used. However, atomic layer deposition is a slow and expensive process, and such processes may not be suitable for mass production environments.

[0014] In some examples, inductive structures are integrated into the circuitry of the package substrate. For instance, an inductor may be used in a voltage regulator. Integrating the inductor within the core of the package substrate can achieve space savings. The inductor within the core can be oriented vertically, such as in a magnetic coaxial structure. A magnetic coaxial structure may include a magnetic shell surrounding conductive vias that penetrate the core. Such integrated solutions have been shown to handle significantly higher current densities compared to previous magnetic inductor arrays (MIAs) or air core inductors (ACIs). This results in improved reliability and performance in architectures with a high number of cores.

[0015] However, previous magnetic coaxial structures were fabricated within organic cores. As mentioned above, when such magnetic coaxial structures are formed within a glass core, reliability concerns may arise. Specifically, the plating of conductive vias from the side walls of the via openings can cause high stresses that could lead to crack formation and / or other damage to the glass core.

[0016] Accordingly, embodiments disclosed herein include a bottom-up plating process for forming magnetic coaxial structures such as plated magnetic vias (PMVs). In the bottom-up plating process, a magnetic layer is formed along the sidewall of the via opening, and then a conductive layer is provided across the entire bottom of the via opening. The plating proceeds vertically upward through the via opening into the shell of the magnetic layer. In such an embodiment, the interface between the via and the sidewall of the magnetic layer has a weaker mechanical bond than conventional plating from a seed layer along the sidewall of the magnetic layer. For example, the via may have a sidewall that is in contact with the sidewall of the magnetic layer at some locations and separated from the sidewall of the magnetic layer by a gap (e.g., an air gap) at other locations. The gap between the sidewall of the magnetic layer and the via may have a width on the submicron scale. Thus, conductivity is not significantly affected, and the mechanical reliability of the glass core can also be improved.

[0017] In some embodiments, the conductive layer beneath the via opening may be supported by a carrier. In some embodiments, the carrier may be bonded to the glass core by the conductive layer. For example, the conductive layer may be a conductive adhesive. In some examples, the conductive adhesive may also include an underlying conductive seed layer (e.g., containing titanium and / or copper) to improve the plating process by improving the conductivity of the conductive adhesive.

[0018] Referring here to Figure 1A, a cross-sectional view of a glass core 110 having a PMV structure penetrating an opening that passes from a first surface 111 to a second surface 112 is shown according to one embodiment. In one embodiment, the PMV structure may include vias 120 surrounded by a magnetic layer 135. The vias 120 and the magnetic layer can at least partially fill the opening penetrating the glass core 110 defined by the sidewall 113. In the illustrated embodiment, the sidewall 113 may be inclined. For example, in Figure 1A, the sidewall 113 defines an hourglass-shaped via opening. However, in other embodiments, the sidewall 113 may have any suitable profile depending on the process used to form the opening penetrating the glass core 110.

[0019] In one embodiment, the magnetic layer 135 may be plated from a seed layer 134 provided on the side wall 113. The seed layer 134 may contain any suitable conductive material. For example, the seed layer 134 may contain ruthenium or ruthenium oxide. In one embodiment, the magnetic layer 135 may contain any suitable magnetic material. For example, the magnetic layer 135 may contain one or more of iron, cobalt, nickel, or the like.

[0020] In one embodiment, the via 120 is formed using a bottom-up plating process. The bottom-up plating process is described in more detail below. The bottom-up plating process may cause the formation of a gap 125 between the sidewall 124 of the via 120 and the sidewall 133 of the magnetic layer 135. However, there may also be locations in the height direction of the via 120 where the sidewall 124 is in direct contact with the sidewall 133 of the magnetic layer 135. For example, the sidewall 124 of the via 120 may be in contact with the sidewall 133 of the magnetic layer 135 at a first position 121, and the sidewall 124 may be separated from the sidewall 133 of the magnetic layer 135 by a gap 125 at a second position 122. In one embodiment, the width of the gap 125 may be about 1 micron or less, about 500 nm or less, about 100 nm or less, or about 50 nm or less. In contrast, in the case of vias 120 plated from the sidewall 133 of the magnetic layer 135, there may be no discernible gap 125 between the via 120 and the magnetic layer 135.

[0021] Referring now to Figure 1B, a cross-sectional view of the glass core 110 is shown according to an additional embodiment. As shown, multiple PMVs are provided within the glass core 110. In some embodiments, via 120 A , 120 B , and 120 C Traces 136 are provided on the first surface 111 and the second surface 112, respectively. A and 136 B They can be electrically coupled to each other by via 120. A ~Beer 120 C By electrically coupling PMVs in series, it may be possible to provide a higher inductance value to the circuit. In Figure 1B, three PMVs are electrically coupled in series, but it should be understood that any number of PMVs can be electrically coupled in series to provide the desired level of inductance.

[0022] Referring to Figures 2A to 2G, a series of cross-sectional views are shown illustrating a process for forming PMVs in a glass core using a bottom-up plating process according to one embodiment.

[0023] Referring here to Figure 2A, a cross-sectional view of the glass core 210 is shown according to one embodiment. In one embodiment, a via opening 216 is provided that penetrates the thickness of the glass core 210. The via opening 216 can be formed by any suitable process. For example, in some embodiments, a laser-assisted etching process can be used to form the via opening 216. In one embodiment, the via opening 216 may be a high aspect ratio via opening 216. For example, the aspect ratio (height:width) of the via opening 216 may be 5:1 or greater, 10:1 or greater, or 20:1 or greater. However, the embodiment can also be used with via openings 216 having smaller aspect ratios.

[0024] In the illustrated embodiment, the sidewall 213 of the via opening 216 is inclined with respect to the upper surface 211 and lower surface 212 of the glass core 210. The via opening 216 may have sidewall 213 that form an hourglass shape. However, in other embodiments, the sidewall 213 may have a single inclination to form a via opening 216 with a single taper. In other embodiments, the sidewall 213 may be substantially vertical (i.e., perpendicular to the upper surface 211), the sidewall 213 may be curved (e.g., non-planar), or may have any other suitable profile.

[0025] In one embodiment, the glass core 210 may be substantially entirely glass. The glass core 210 may be a solid mass containing a glass material having an amorphous crystalline structure, in which case the solid glass core may also include various structures filled with one or more other materials (e.g., metals, metal alloys, dielectric materials, etc.), such as vias, cavities, channels, or other features. Thus, the glass core 210 can be distinguished from, for example, the “prepreg” or “FR4” core of a printed circuit board (PCB) substrate, which typically contains glass fibers embedded in a resinous organic material such as epoxy.

[0026] The glass core 210 may have any suitable dimensions. In certain embodiments, the glass core 210 may have a thickness of about 50 μm or more. For example, the glass core 210 may have a thickness between about 50 μm and about 1.4 mm. However, thinner or thicker thicknesses may also be used. The glass core 210 may have edge dimensions (e.g., length, width, etc.) of about 10 mm or more. For example, the edge dimensions may be between about 10 mm and about 250 mm. However, larger or smaller edge dimensions may also be used. More generally, the area dimensions of the glass core 210 (from the top view) may be between about 10 mm × 10 mm and about 250 mm × 250 mm. In one embodiment, the first side surface of the glass core 210 may be perpendicular or orthogonal to the second side surface. In a more general embodiment, the glass core 210 may consist of a rectangular volume from which portions (e.g., vias) have been removed and which is filled with other materials (e.g., metal).

[0027] The glass core 210 may include a single monolithic glass layer. In other embodiments, the glass core 210 may consist of two or more separate glass layers stacked on top of each other. The separate glass layers may be in direct contact with each other, or they may be mechanically bonded to each other by an adhesive or the like. Each separate glass layer in the glass core 210 may have a thickness of less than about 50 μm. For example, the separate glass layers in the glass core 210 may have a thickness between about 25 μm and about 50 μm. However, in some embodiments, the separate glass layers may have greater or lesser thicknesses. As used herein, "about" may refer to a range of values ​​within 10% of the stated value. For example, about 50 μm may refer to a range between 45 μm and 55 μm.

[0028] The glass core 210 can be any suitable glass compound having the required mechanical robustness and compatibility with the semiconductor package manufacturing and assembly processes. For example, the glass core 210 may include aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, quartz glass, or similar. In some embodiments, the glass core 210 may include, but is not limited to, one or more additives such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, or Zn. More generally, in addition to silicon and oxygen, the glass core 210 may include one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, or zinc. In one embodiment, the glass core 210 may contain at least 23% by weight of silicon and at least 26% by weight of oxygen. In some embodiments, the glass core 210 may further contain at least 5% by weight of aluminum.

[0029] In one embodiment, the seed layer 234 can be formed on the side wall 213 of the via opening 216, the upper surface 211, and the lower surface 212 of the glass core 210. In one embodiment, the seed layer 234 may contain a conductive material such as ruthenium or ruthenium oxide.

[0030] Referring here to Figure 2B, a cross-sectional view of the glass core 210 after a magnetic layer 235 has been formed on the seed layer 234 according to one embodiment. In one embodiment, the magnetic layer 235 can be plated from the seed layer using any suitable process. Since the magnetic layer 235 does not completely fill the via openings 216, the stress induced in the glass core 210 is smaller than if the vias were plated to completely fill the via openings 216. In one embodiment, the magnetic layer 235 may contain any suitable magnetic material, such as iron, cobalt, nickel, or one or more of the same.

[0031] Referring now to Figure 2C, a cross-sectional view of the glass core 210 is shown, according to one embodiment, after a portion of the seed layer 234 and magnetic layer 235 has been removed from the upper surface 211 and lower surface 212 of the glass core 210. In one embodiment, a portion of the seed layer 234 and magnetic layer 235 can be removed by an etching process, a polishing process, or any other suitable subtractive process.

[0032] Referring here to Figure 2D, a cross-sectional view of the glass core 210 is shown after a conductive layer 203 has been provided on the lower surface 212 of the glass core 210 according to one embodiment. The conductive layer 203 may include a metallic material (e.g., titanium and / or copper). As will be described in more detail herein, the conductive layer 203 may also be a conductive adhesive layer for bonding the glass core 210 to a carrier substrate (not shown in Figure 2A). The conductive layer 203 may extend beyond the via opening 216. Thus, a portion of the conductive layer 203 is exposed by the via opening 216 to enable a bottom-up plating process, which will be described in more detail herein.

[0033] Referring now to Figure 2E, a cross-sectional view of the glass core 210 after a portion of the vias 220 have been plated according to one embodiment. As indicated by arrow 230, the plating of the vias 220 extends vertically from the conductive layer 203 in a bottom-up manner. The plating may be any suitable electroplating process. A bottom-up plating process may allow the sidewall 224 of the vias 220 to have a textured surface that forms an interface with the sidewall 233 of the magnetic layer 235. For example, the sidewall 224 may have a nonlinear shape with peaks and valleys. In one embodiment, the sidewall 224 of the vias 220 may be in direct contact with the sidewall 233 of the magnetic layer 235 at a first position 221, and the sidewall 224 of the vias 220 may be separated from the sidewall 233 of the magnetic layer 235 by a gap 225 at a second position 222.

[0034] In one embodiment, direct contact between the via 220 and the sidewall 233 of the magnetic layer 235 can mean that there is no intermediate layer between the via 220 and the sidewall 233. For example, in existing plating processes, a seed layer or similar may be provided between the sidewall 233 of the magnetic layer 235 and the sidewall 224 of the via 220. In one embodiment, the gap 225 can have any suitable dimensions. For example, the width of the gap 225 between the sidewall 233 of the magnetic layer 235 and the sidewall 224 of the via 220 may be a maximum of approximately 5 μm, a maximum of approximately 1 μm, a maximum of approximately 0.5 μm, or a maximum of approximately 0.1 μm. As described above, the presence of the gap 225 makes it possible to weaken the mechanical bond between the via 220, the magnetic layer 235, and ultimately the glass core 210. Accordingly, stresses related to the coefficient of thermal expansion (CTE) mismatch between the glass core 210 and the via 220 can be reduced, and the mechanical robustness of the glass core 210 is improved.

[0035] Referring now to Figure 2F, a cross-sectional view of the glass core 210 after the plating of vias 220 is completed is shown according to one embodiment. As shown, vias 220 substantially fill the via openings in the magnetic layer 235, except that gaps 225 exist at several positions along the height of vias 220. In certain embodiments, the cross-sectional area of ​​vias 220 along a plane (for example, the plane shown in Figure 2F) may be smaller than the cross-sectional area of ​​some of the via openings surrounded by the magnetic layer 235 along the same plane. In one embodiment, the difference between the cross-sectional area of ​​some of the via openings surrounded by the magnetic layer 235 and the cross-sectional area of ​​vias 220 may be occupied by the cross-sectional area of ​​all of the gaps 225. In one embodiment, the cross-sectional area of ​​the via 220 along this plane may be about 95% or more of the cross-sectional area of ​​a portion of the via opening surrounded by the magnetic layer 235, about 99% or more of the cross-sectional area of ​​a portion of the via opening surrounded by the magnetic layer 235, about 99.5% or more of the cross-sectional area of ​​a portion of the via opening surrounded by the magnetic layer 235, or about 99.9% or more of the cross-sectional area of ​​a portion of the via opening surrounded by the magnetic layer 235.

[0036] In one embodiment, via 220 may have a substantially uniform composition along the entire line from a first edge of via 220 parallel to the upper or lower surface 211 or 212 of the glass core 210 to a second edge of via 220. For example, via 220 may have a substantially uniform composition containing copper. This differs from many existing via architectures that include a seed layer along the sidewalls of the magnetic layer 235. In such an embodiment, the seed layer may cause the via to have a different composition along its outer edge. For example, there may be concentrations of titanium or other seed layer material at the edge of the via. However, the embodiments disclosed herein may have a substantially uniform composition from edge to edge because a bottom-up plating process is used.

[0037] Referring now to Figure 2G, a cross-sectional view of the glass core 210 after the conductive layer 203 has been removed is shown according to one embodiment. In one embodiment, the conductive layer 203 can be removed by an etching process, a polishing process, or the like. Because of the presence of the conductive layer 203, the lower surface of the via 220 can be substantially flat and coplanar with the lower surface 212 of the glass core 210. In some embodiments, the upper surface of the via 220 may be polished or planarized so that the upper surface is substantially flat and coplanar with the upper surface 211 of the glass core 210.

[0038] In the embodiments described above with respect to Figures 2A to 2G, the bottom-up plating process will be described in a way that shows the resulting structure of the vias 220 and magnetic layer 235 for forming the PMV. Specifically, the composition, structure, and / or interface with the sidewall 233 of the magnetic layer 235 will be described in detail. More detailed examples of how such a process can be implemented in a manufacturing setting are shown with respect to Figures 3A to 3H. In particular, the profiles and details of the PMV in Figures 2A to 2G are omitted to focus directly on the treatments and structures used to enable the bottom-up plating process. However, it should be understood that the structure, composition, and / or similar of the PMV in Figures 2A to 2G may be similar to any of those described in more detail herein.

[0039] Referring here to Figure 3A, a cross-sectional view of a glass core 310 is shown according to one embodiment. In one embodiment, the glass core 310 may be similar to either a glass core or a glass substrate, which will be described in more detail herein. In the illustrated embodiment, a single glass core 310 unit is shown. However, it should be understood that a glass panel or glass substrate having multiple glass core 310 units may be used according to similar embodiments. In one embodiment, the glass core 310 may include an upper surface 311 and a lower surface 312. Multiple via openings 316 penetrating the thickness of the glass core 310 may be formed. In the illustrated embodiment, the side walls 313 of the via openings 316 are substantially vertical. However, it should be understood that in some embodiments, the side walls 313 may be inclined with respect to the upper surface 311 or the lower surface 312. The via openings 316 may be formed by any suitable patterning process, such as a laser-assisted etching process.

[0040] Referring now to Figure 3B, a cross-sectional view of the glass core 310 is shown after one or more via openings 316 have been lined with a magnetic layer 335 according to one embodiment. As shown, four via openings 316 are lined with the magnetic layer 335, and four via openings 316 are masked with a masking layer 314 to prevent the magnetic layer 335 from depositing on the via openings 319. In one embodiment, the magnetic layer 335 can be formed in a plating process (e.g., on a seed layer (not shown)) using a process similar to the process shown in Figures 2A to 2C, which will be described in more detail above.

[0041] Referring now to FIG. 3C, a cross-sectional view of the glass core 310 after the carrier 302 is attached to the glass core 310 is shown in accordance with one embodiment. In one embodiment, the glass core 310 may be coupled to the carrier 302 by an electrically conductive adhesive layer 308. In one embodiment, the electrically conductive adhesive layer 308 may include an electrically conductive adhesive (ECA), an anisotropic conductive film (ACF), or the like. In some embodiments, the conductivity of the electrically conductive adhesive layer 308 can be enhanced by providing a conductive layer 305 between the electrically conductive adhesive layer 308 and the carrier 302. For example, the conductive layer 305 may include titanium and / or copper, or any other suitable conductive material. However, in some embodiments, the conductive layer 305 may be omitted if the electrically conductive adhesive layer 308 provides sufficient conductivity to drive the plating process. In one embodiment, the carrier 302 may be composed of any suitable rigid material. In certain embodiments, the carrier 302 may also include a glass layer.

[0042] Referring now to FIG. 3D, a cross-sectional view of the glass core 310 after vias 320 are formed in via openings 316 having a magnetic layer 335 and vias 320 are formed in via openings 319 having no magnetic layer 335 using a bottom-up plating process is shown in accordance with one embodiment. Since the exposed conductive surfaces within the via openings 316 and 319 are only the electrically conductive adhesive layer 308 exposed at the bottoms of the via openings 316 and 319, the vias 320 A and 320 B are plated in the vertical direction. The bottom-up plating process can include an electroplating process or the like. In one embodiment, the vias 320 A and 320 B may have an over-plated layer extending above the top surface 311 of the glass core 310.

[0043] Similar to the other embodiments described herein, the vias 320 A ​​​​and 320 B In some positions, this is in direct contact with the side walls of via openings 316 and 319, and in other positions, via 320 A and 320 B and may have a textured outer surface that provides a gap between the magnetic layer 335 or the side walls of the via opening 319. In particular, via 320 A The via 320 can directly contact a portion of the side wall 333 of the magnetic layer 335. B The via 320 can directly contact a portion of the side wall 313 of the via opening 319 because there is no seed layer along the side wall 313 of the via opening 319 or along the side wall 333 of the magnetic layer 335. Furthermore, because there is no seed layer in the via opening 319 or along the magnetic layer 335, the via 320 A and 320 B The composition can be substantially uniform.

[0044] Via 320 A and 320 B The profile of the side wall may be similar to the profile of the side wall 224 of via 220, which is described in more detail herein. For example, via 320 along a plane A and 320 B The cross-sectional area of ​​the via opening 316 can be smaller than the cross-sectional area of ​​the via opening 316 that lies in the same plane. Accordingly, the stress induced in the glass core 310 during the thermal cycle is reduced, and the glass core 310 becomes more robust than in previous solutions.

[0045] Referring now to Figure 3E, according to one embodiment, via 320 A and 320 B A cross-sectional view of the glass core 310 after the excess plating layer has been removed is shown. In one embodiment, the excess plating layer can be removed by a polishing or planarization process. For example, a chemical mechanical polishing (CMP) process can be used to remove the excess plating layer.

[0046] Referring now to Figure 3F, a cross-sectional view of the glass core 310 after the carrier 302 has been removed is shown according to one embodiment. In one embodiment, the carrier 302 can be removed by any suitable process. For example, the carrier 302 can be removed by a thermal debonding process, a laser debonding process, a UV peeling process, or the like. Removal of the carrier 302 may expose the surface of the conductive layer 305.

[0047] Referring now to Figure 3G, a cross-sectional view of the glass core 310 after the conductive layer 305 and the conductive adhesive layer 308 have been removed according to one embodiment. In one embodiment, the conductive layer 305 can be removed by a chemical etching process (e.g., a wet etching process) or a laser stripping process. In one embodiment, the conductive adhesive layer 308 can be removed by a cleaning process or any other suitable process.

[0048] Referring now to Figure 3H, a cross-sectional view of a package substrate 350 including a glass core 310 is shown according to one embodiment. In one embodiment, the glass core 310 may be covered by a top build-up layer 351 covering the upper surface 311 of the glass core 310 and a bottom build-up layer 352 covering the lower surface 312. In one embodiment, the top build-up layer 351 and the bottom build-up layer 352 may each include a plurality of laminated organic layers (e.g., build-up film layers). In one embodiment, conductive routing (not shown) within the top build-up layer 351 and the bottom build-up layer 352 is via 320 A and / or 320 BHowever, they may be electrically coupled to a first-level interconnect (FLI) 354 and a second-level interconnect (SLI) 353. Conductive routing may include pads, traces, vias, and / or similar. In one embodiment, one or more dies 355 may be electrically coupled to the top build-up layer 351 by the FLI 354. In some embodiments, a bridge substrate (not shown) embedded in or provided on the top build-up layer 351 may electrically couple two or more dies 355 together.

[0049] Referring now to Figure 4, a flowchart is shown illustrating a process 460 for forming a PMV within a glass core using a bottom-up plating process according to one embodiment. In one embodiment, process 460 may be similar to any of the bottom-up plating processes described in more detail. For example, the PMV may have vias with textured surfaces that reduce stress generation within the glass core due to CTE mismatch issues.

[0050] In one embodiment, process 460 may begin with operation 461, which includes the step of forming an opening through a substrate having a glass layer. In one embodiment, the substrate may be similar to any of the glass cores described in more detail herein. In one embodiment, the opening may be considered a via opening. The opening may be formed by any suitable patterning process, such as a laser-assisted etching process or similar.

[0051] In one embodiment, process 460 may proceed to operation 462, which includes the step of forming a magnetic layer on the sidewall of the opening. In one embodiment, the magnetic layer may include one or more of iron, cobalt, or nickel. In some examples, a seed layer may be provided between the magnetic layer and the substrate.

[0052] In one embodiment, process 460 may proceed to operation 463, which includes the step of attaching the carrier to the substrate using a conductive adhesive. In one embodiment, the conductive adhesive may include ECA or ACF. In some embodiments, a conductive layer may be provided between the conductive adhesive and the carrier to improve the conductivity of the conductive adhesive. For example, a layer containing titanium and / or copper may be provided between the conductive adhesive and the carrier. The carrier may be a glass substrate or any other suitable rigid substrate material.

[0053] In one embodiment, process 460 may proceed to operation 464, which includes a step of plating vias into the opening using a bottom-up process from a conductive adhesive. For example, the conductive adhesive may span the opening, and the exposed portion of the conductive adhesive can be used as a seed layer for plating the vias. This allows the vias to be plated so that the opening is filled from bottom to top. As with other embodiments described herein, the plated vias may have a textured surface that allows for the formation of a submicron-sized gap between the via edge and the sidewall of the magnetic layer. Accordingly, mechanical coupling is reduced and stress induced by the coefficient of thermal expansion (CTE) mismatch between the via and the substrate is minimized. Thus, the reliability of the substrate is improved.

[0054] In one embodiment, the process may proceed to operation 465, which includes the step of removing excess plating on the vias above the opening. For example, a polishing process may be used to remove excess plating formed on the upper surface of the substrate opposite to the carrier. For example, in some embodiments, a CMP process may be used.

[0055] In one embodiment, process 460 may proceed to operation 466, which includes the step of removing carriers from the substrate. In one embodiment, the carriers can be removed using any suitable debonding process, such as a laser debonding process, a thermal debonding process, a UV peeling process, or the like. After the carriers have been removed, the conductive adhesive and any selective conductive layer can also be removed. For example, the conductive adhesive and / or conductive layer can be removed using an etching process, a polishing process, and / or a cleaning process.

[0056] In one embodiment, the resulting substrate can then be incorporated into a package substrate via a typical build-up layer manufacturing process. For example, multiple layers are patterned to form electrical routing. In some embodiments, the electrical routing in the build-up layer can electrically couple vias to a die bonded to the package substrate.

[0057] Referring now to Figure 5, a cross-sectional view of an electronic system 590 is shown according to one embodiment. In one embodiment, the electronic system 590 may comprise a board 591, such as a printed circuit board (PCB), motherboard, or the like. In one embodiment, the board 591 may be coupled to a package substrate 550 by an SLI 553. In one embodiment, the SLI 553 may comprise solder balls, sockets, or the like.

[0058] In one embodiment, the package substrate 550 may be similar to any of the package substrates described in more detail herein. In one embodiment, the package substrate 550 has vias 520 A and 520 B It may be equipped with a glass core 510 having a via 520. A and 520 B These can be formed using a bottom-up plating process such as one of those described in more detail herein. In one embodiment, via 520 A and 520 BThe via 520 may have a textured surface, which allows for a reduction in the amount of stress induced within the glass core 510, as the mechanical bonding is weaker compared to existing plating processes. A and 520 B This may be similar to any of the vias described in more detail herein. For example, via 520 A is Via 520 A It may be part of a PMV having a magnetic layer 535 surrounding it. In one embodiment, the package substrate 550 may also include build-up layers 551 and 552 provided above and below the glass core 510.

[0059] In one embodiment, one or more dies 555 may be coupled to the build-up layer 551 by an FLI 554. The FLI 554 can be any suitable FLI architecture, such as solder balls, copper bumps, a hybrid bonding interface, or the like. In one embodiment, one or more dies 555 may be any type of die (e.g., processor dies (e.g., central processing unit: CPU, graphics processing unit: GPU, XPU), memory dies, communication dies, power management dies, and / or the like). In one embodiment, two or more dies 555 may be electrically coupled together by bridges (not shown) embedded in or provided on the build-up layer 551.

[0060] Figure 6 shows a computing device 600 according to one embodiment of the present disclosure. The computing device 600 houses a board 602. The board 602 may include, but is not limited to, a processor 604 and at least one communication chip 606. The processor 604 is physically and electrically coupled to the board 602. In some implementations, at least one communication chip 606 is also physically and electrically coupled to the board 602. In further implementations, the communication chip 606 is part of the processor 604. In one embodiment, a device package is coupled to the board 602. Either or both of the processor 604 or the communication chip 606 may be coupled to the board 602 via a device package.

[0061] These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, compact discs (CDs), digital multipurpose discs (DVDs)).

[0062] The communication chip 606 enables wireless communication for data transfer to and from the computing device 600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through the use of modulated electromagnetic radiation over a non-solid medium. This term does not imply that the devices involved are entirely wireless, although this may not be the case in some embodiments. The communication chip 606 may implement any of several wireless standards or protocols, including but not limited to Wi-Fi® (IEEE 802.11 family), WiMAX® (IEEE 802.16 family), IEEE 802.20, Long-Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM®, GPRS, CDMA, TDMA, DECT, Bluetooth®, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and later. The computing device 600 may include multiple communication chips 606. For example, a first communication chip 606 may be dedicated to short-range wireless communication such as Wi-Fi® and Bluetooth®, and a second communication chip 606 may be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX®, LTE, Ev-DO, and others.

[0063] The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. In some implementations of this disclosure, the integrated circuit die of the processor may be part of a package substrate having a glass core with a PMV formed using a bottom-up plating process, according to embodiments described herein. The term “processor” may refer to any or part of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory.

[0064] The communication chip 606 also includes an integrated circuit die packaged within the communication chip 606. According to another implementation example of this disclosure, the integrated circuit die of the communication chip may be part of a package substrate having a glass core with a PMV formed using a bottom-up plating process, according to embodiments described herein.

[0065] In one embodiment, the computing device 600 may be part of any device. For example, the computing device may be part of a personal computer, server, mobile device, tablet, automobile, or similar. That is, the computing device 600 is not limited to being used in any particular type of system, and may be included in any device that may benefit from computing capabilities.

[0066] The above description of the implementation of the disclosed information, including matters described in the abstract, is not intended to be exhaustive or to limit the disclosure to the exact form provided. While specific implementations and examples of the disclosed information are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosed information, as will be apparent to those skilled in the art.

[0067] These modifications can be made to the present disclosure in light of the detailed description above. The terms used in the following claims should not be construed as limiting the present disclosure to any specific embodiment disclosed herein or in the claims. Rather, the scope of the present disclosure should be determined by the entirety of the following claims, and their interpretation should follow established principles of claim interpretation.

[0068] Examples

[0069] Example 1: A device comprising a substrate, wherein the substrate includes a glass layer; an opening penetrating the thickness of the substrate; a layer covering the sidewall of the opening, wherein the layer includes a magnetic material; and a via within the opening, wherein the via is in direct contact with the layer at a first position, a gap is provided between the via and the layer at a second position, and the via is conductive.

[0070] Example 2: The apparatus described in Example 1, wherein the via sidewall is nonlinear.

[0071] Example 3: The apparatus according to Example 1 or Example 2, wherein the layer is separated from the side wall of the opening by a conductive seed layer.

[0072] Example 4: The apparatus according to Example 3, wherein the conductive seed layer contains ruthenium.

[0073] Example 5: The apparatus according to Examples 1 to 4, wherein the magnetic material comprises one or more of iron, cobalt, or nickel.

[0074] Example 6: The apparatus according to Examples 1-5, wherein the composition of the via is substantially uniform along the entire line from the first edge of the via to the second edge of the via, parallel to the upper and / or lower surface of the substrate.

[0075] Example 7: The apparatus according to Example 6, wherein the composition substantially contains copper.

[0076] Example 8: The apparatus according to Examples 1-7, wherein the aspect ratio (height:width) of the opening is approximately 10:1 or greater.

[0077] Example 9: The apparatus according to Examples 1 to 8, wherein the gap has a maximum width of 1 micron.

[0078] Example 10: The apparatus according to Examples 1 to 9, wherein the substrate is the core of the package substrate.

[0079] Example 11: Apparatus comprising: a substrate, the substrate including a glass layer; a first opening penetrating the thickness of the substrate; a layer covering a first sidewall of the first opening, wherein the layer includes a magnetic material; a first via within the first opening, wherein the first via is in direct contact with the layer at a first position, and a first gap is provided between the first via and the layer at a second position, and the first via is conductive; a second opening penetrating the thickness of the substrate; and a second via within the second opening, wherein the second via is in direct contact with a second sidewall of the second opening at a third position, and a second gap is provided between the second via and the second sidewall at a fourth position, and the second via is conductive.

[0080] Example 12: The apparatus according to Example 11, wherein the third side wall of the first via is nonlinear.

[0081] Example 13: The apparatus according to Example 11 or Example 12, wherein the layer is separated from the first sidewall of the first opening by a conductive seed layer.

[0082] Example 14: The apparatus according to Examples 11-13, wherein the magnetic material comprises one or more of iron, cobalt, or nickel.

[0083] Example 15: The apparatus according to Examples 11-14, wherein the first via is part of a coaxial inductor incorporated into the substrate.

[0084] Example 16: The apparatus according to Examples 11-15, wherein the substrate is the core of the package substrate.

[0085] Example 17: The apparatus according to Example 16, further comprising a die coupled to the package substrate and a board coupled to the package substrate.

[0086] Example 18: A method comprising the steps of forming a magnetic layer on the side wall of an opening penetrating a glass substrate; attaching carriers to the glass substrate using a conductive adhesive, wherein the conductive adhesive extends beyond the opening penetrating the glass substrate; plating vias into the opening from the conductive adhesive using a bottom-up process, wherein the vias are separated from the glass substrate by the magnetic layer; and removing the carriers from the glass substrate.

[0087] Example 19: The method according to Example 18, wherein the via is in direct contact with the side wall of the magnetic layer at a first position of the magnetic layer, and the via is spaced a gap away from the magnetic layer at a second position of the magnetic layer.

[0088] Example 20: The method according to Example 18 or Example 19, further comprising a layer containing titanium and / or copper between the conductive adhesive and the carrier. (Other possible items) (Item 1) A substrate, wherein the substrate includes a glass layer; An opening that penetrates the thickness of the aforementioned substrate; A layer covering the side wall of the opening, wherein the layer includes a magnetic material; and A via within the opening, wherein the via is in direct contact with the layer at a first position, and a gap is provided between the via and the layer at a second position, and the via is conductive. A device equipped with the following features. (Item 2) The apparatus described in item 1, wherein the via sidewalls are nonlinear. (Item 3) The apparatus according to item 1, wherein the layer is separated from the side wall of the opening by a conductive seed layer. (Item 4) The apparatus according to item 3, wherein the conductive seed layer contains ruthenium. (Item 5) The apparatus according to item 1, wherein the magnetic material comprises one or more of iron, cobalt, or nickel. (Item 6) The apparatus according to item 1, wherein the composition of the via is substantially uniform along the entire line from the first edge of the via to the second edge of the via, parallel to the upper and / or lower surface of the substrate. (Item 7) The apparatus according to item 6, wherein the composition substantially comprises copper. (Item 8) The apparatus according to item 1, wherein the aspect ratio (height:width) of the opening is approximately 10:1 or greater. (Item 9) The apparatus according to item 1, wherein the gap has a maximum width of 1 micron. (Item 10) The apparatus as described in item 1, wherein the aforementioned substrate is the core of the package substrate. (Item 11) A substrate, wherein the substrate includes a glass layer; A first opening that penetrates the thickness of the substrate; A layer covering the first side wall of the first opening, wherein the layer includes a magnetic material; A first via within the first opening, wherein the first via is in direct contact with the layer at a first position, and a first gap is provided between the first via and the layer at a second position, and the first via is conductive; A second opening that penetrates the thickness of the substrate; and A second via within the second opening, wherein the second via is in direct contact with the second side wall of the second opening at a third position, and a second gap is provided between the second via and the second side wall at a fourth position, and the second via is conductive. A device equipped with the following features. (Item 12) The apparatus according to item 11, wherein the third side wall of the first via is nonlinear. (Item 13) The apparatus according to item 11, wherein the layer is separated from the first side wall of the first opening by a conductive seed layer. (Item 14) The apparatus according to item 11, wherein the magnetic material comprises one or more of iron, cobalt, or nickel. (Item 15) The apparatus according to item 11, wherein the first via is part of a coaxial inductor incorporated into the substrate. (Item 16) The apparatus according to item 11, wherein the substrate is the core of the package substrate. (Item 17) Die bonded to the aforementioned package substrate; and Board attached to the aforementioned package substrate The apparatus according to claim 16, further comprising the above. (Item 18) A step in which a magnetic layer is formed on the side wall of an opening that penetrates a glass substrate; In the step of attaching the carrier to the glass substrate using a conductive adhesive, the conductive adhesive extends beyond the opening that penetrates the glass substrate; The step involves plating vias into the opening using a bottom-up process from the conductive adhesive, where the vias are separated from the glass substrate by the magnetic layer; and Steps to remove the carrier from the glass substrate, A method for providing this. (Item 19) The method according to item 18, wherein the via is in direct contact with the side wall of the magnetic layer at a first position of the magnetic layer, and the via is spaced apart from the magnetic layer by a gap at a second position of the magnetic layer. (Item 20) The method described in item 18 further comprises a layer containing titanium and / or copper between the conductive adhesive and the carrier.

Claims

1. A substrate, wherein the substrate includes a glass layer; An opening that penetrates the thickness of the aforementioned substrate; A layer covering the side wall of the opening, wherein the layer includes a magnetic material; and A via within the opening, wherein the via is in direct contact with the layer at a first position, and a gap is provided between the via and the layer at a second position, and the via is conductive. A device equipped with the following features.

2. The apparatus according to claim 1, wherein the via sidewall is nonlinear.

3. The apparatus according to claim 1, wherein the layer is separated from the side wall of the opening by a conductive seed layer.

4. The apparatus according to claim 3, wherein the conductive seed layer contains ruthenium.

5. The apparatus according to claim 1, wherein the magnetic material comprises one or more of iron, cobalt, or nickel.

6. The apparatus according to claim 1, wherein the composition of the via is substantially uniform along the entire line from the first edge of the via to the second edge of the via, parallel to the upper and / or lower surface of the substrate.

7. The apparatus according to claim 6, wherein the composition substantially comprises copper.

8. The apparatus according to claim 1, wherein the aspect ratio (height:width) of the opening is approximately 10:1 or greater.

9. The apparatus according to claim 1, wherein the gap has a maximum width of 1 micron.

10. The apparatus according to any one of claims 1 to 9, wherein the substrate is the core of a package substrate.

11. A substrate, wherein the substrate includes a glass layer; A first opening that penetrates the thickness of the substrate; A layer covering the first side wall of the first opening, wherein the layer includes a magnetic material; A first via within the first opening, wherein the first via is in direct contact with the layer at a first position, and a first gap is provided between the first via and the layer at a second position, and the first via is conductive; A second opening that penetrates the thickness of the substrate; and A second via within the second opening, wherein the second via is in direct contact with the second side wall of the second opening at a third position, and a second gap is provided between the second via and the second side wall at a fourth position, and the second via is conductive. A device equipped with the following features.

12. The apparatus according to claim 11, wherein the third side wall of the first via is nonlinear.

13. The apparatus according to claim 11, wherein the layer is separated from the first side wall of the first opening by a conductive seed layer.

14. The apparatus according to claim 11, wherein the magnetic material comprises one or more of iron, cobalt, or nickel.

15. The apparatus according to claim 11, wherein the first via is part of a coaxial inductor incorporated into the substrate.

16. The apparatus according to any one of claims 11 to 15, wherein the substrate is the core of a package substrate.

17. A die bonded to the aforementioned package substrate; and Board attached to the aforementioned package substrate The apparatus according to claim 16, further comprising:

18. A step in which a magnetic layer is formed on the side wall of an opening that penetrates the glass substrate; In the step of attaching the carrier to the glass substrate using a conductive adhesive, the conductive adhesive extends beyond the opening that penetrates the glass substrate; The step involves plating vias into the opening using a bottom-up process from the conductive adhesive, where the vias are separated from the glass substrate by the magnetic layer; and Steps to remove the carrier from the glass substrate, A method for providing this.

19. The method according to claim 18, wherein the via is in direct contact with the side wall of the magnetic layer at a first position of the magnetic layer, and the via is spaced apart from the magnetic layer by a gap at a second position of the magnetic layer.

20. The method according to claim 18 or 19, further comprising a layer containing titanium and / or copper between the conductive adhesive and the carrier.

Images