Printed circuit board

Abstract

The present invention provides a printed circuit board that incorporates an interposer that facilitates the connection of fine circuits between semiconductor chips and allows for large-area construction, thereby simplifying the manufacturing process. [Solution] The interposer-integrated printed circuit board 500 includes a plurality of insulating layers 212, 213, a plurality of wiring layers 223, 224 respectively arranged on or within the plurality of insulating layers, a plurality of via layers 232, 233 respectively arranged within the plurality of insulating layers and connected to at least one of the plurality of wiring layers, and an interposer 100-1 including a glass layer 110 and a rewiring layer 120 arranged on the glass layer, which is embedded inside the plurality of insulating layers.

Description

Technical Field

[0001] The present disclosure relates to a printed circuit board.

Background Art

[0002] In recent years, due to the chipletization of high-performance semiconductors, the increase in the bandwidth of memories, and the increase in the number of memories employed, there has been a demand for larger-area, higher-multi-layer, and 2.nD package technologies for package substrates. For the fine circuit connection of such chipletized semiconductor chips, EMIB (Embedded Multi-die Interconnect Bridge) or similar technologies can be used, but it is difficult to increase the area, impossible to assemble with a fine pitch, and there are difficulties in application. There is a limit in that it is necessary to change the chip design to increase the pitch for application.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the various objects of the present disclosure is to provide a printed circuit board incorporating an interposer that enables easy fine circuit connection between semiconductor chips and allows for a larger area.

[0004] Another of the various objects of the present disclosure is to provide a printed circuit board incorporating such an interposer that enables process simplification.

Means for Solving the Problems

[0005] One of the various solutions proposed through the present disclosure is to manufacture an interposer in which a polymer material is applied onto a glass panel capable of a larger area to form a metal pattern and metal vias to constitute a redistribution layer, and incorporate this into a multilayer printed circuit board.

[0006] For example, a printed circuit board according to one example may include a plurality of insulating layers, a plurality of wiring layers each disposed on or within the plurality of insulating layers, a plurality of via layers each disposed within the plurality of insulating layers and each connected to at least one of the plurality of wiring layers, and an interposer embedded inside the plurality of insulating layers, including a glass layer and a rewiring layer disposed on the glass layer.

[0007] For example, a printed circuit board according to one example includes a first substrate portion including a plurality of insulating layers and a plurality of wiring layers disposed on or within the plurality of insulating layers, and a second substrate portion including a glass plate, a plurality of polymer layers laminated on the glass plate, and a plurality of metal pattern layers disposed on or within the plurality of polymer layers, wherein the second substrate portion is built into the first substrate portion, and at least one of the plurality of metal pattern layers can be electrically connected to at least one of the plurality of wiring layers. [Effects of the Invention]

[0008] One of the various effects of this disclosure is the ability to provide a printed circuit board with a built-in interposer that facilitates the connection of fine circuits between semiconductor chips and allows for large-area scaling.

[0009] One of the various effects of this disclosure is that by incorporating such an interposer, it is possible to provide a printed circuit board that simplifies the manufacturing process. [Brief explanation of the drawing]

[0010] [Figure 1] This is a block diagram illustrating an example of an electronic equipment system. [Figure 2] This is a schematic cross-sectional view showing an example of an interposer. [Figure 3] This is a schematic cross-sectional view showing an example of a printed circuit board with an integrated interposer. [Figure 4] This is a schematic cross-sectional view illustrating an example of the manufacturing process of a printed circuit board with an integrated interposer. [Figure 5] This is a schematic cross-sectional view illustrating an example of the manufacturing process of a printed circuit board with an integrated interposer. [Figure 6] This is a schematic cross-sectional view illustrating an example of the manufacturing process of a printed circuit board with an integrated interposer. [Figure 7] This is a schematic cross-sectional view illustrating an example of the manufacturing process of a printed circuit board with an integrated interposer. [Modes for carrying out the invention]

[0011] The disclosure will be described below with reference to the attached drawings. The shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for clearer explanation.

[0012] Figure 1 is a block diagram illustrating an example of an electronic equipment system.

[0013] Referring to the drawing, the electronic device 1000 houses a main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, among others. These are also coupled with other electronic components, as described later, to form various signal lines 1090.

[0014] Chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Furthermore, these chip-related components 1020 can be combined with each other. Chip-related components 1020 can also be in the form of a package containing the aforementioned chips and electronic components.

[0015] Network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (Long Term Evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and later. It may also include any other numerous wireless or wired standards or protocols. Furthermore, network-related component 1030 can be combined with chip-related component 1020.

[0016] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, and MLCCs (multi-layer ceramic condensers). However, they are not limited to these, and may also include passive elements in the form of chip components used for various other applications. Furthermore, other components 1040 can be combined with chip-related components 1020 and / or network-related components 1030.

[0017] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the main board 1010, or not connected. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. However, it is not limited to these, and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. In addition, depending on the type of electronic device 1000, it may also include other electronic components used for various purposes.

[0018] The electronic device 1000 can be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an Automotive, etc. However, it is not limited thereto, and it can also be any other electronic device that processes data.

[0019] FIG. 2 is a cross-sectional view schematically showing an example of an interposer.

[0020] Referring to the drawings, an interposer 100 according to an example can include a glass layer 110 and a rewiring layer 120 disposed on the glass layer 110. If necessary, it can further include a through-via layer 131 penetrating the glass layer 110, at least one component 132 built in the glass layer 110, and / or a waveguide pattern 133 formed in the rewiring layer 120. The rewiring layer 120 can include a plurality of polymer layers 121 laminated on the glass layer 110, a plurality of metal pattern layers 122 respectively disposed on or in the plurality of polymer layers 121, and a plurality of metal via layers 123 respectively disposed in the plurality of polymer layers 121 and respectively connected to at least one of the plurality of metal pattern layers 122.

[0021] Thus, the interposer 100 according to an example includes a glass layer 110 that can be made large in area, and thus can be easily applied to large-area products. Also, since the glass layer 110 is excellent in rigidity, it may be advantageous for process warpage control. Also, the glass layer 110 can provide a flat base surface, and thus a redistribution layer 120 including a fine circuit can be easily formed on the glass layer 110, which may be advantageous for interconnection between semiconductor chips. Also, a through-via layer 131 including TGV (Through Glass Via) can be formed in the glass layer 110, whereby electrical conduction can be achieved not only on the upper side but also on the lower side of the interposer 100. Also, at least one component 132 can be incorporated in the glass layer 110, and the at least one component 132 can include, for example, a silicon bridge or a silicon capacitor, so that finer interconnection can also be achieved and it can be useful for efficient power management. Also, a waveguide pattern 133 can be formed in the redistribution layer 120, so that optical communication can be achieved and it can be easily connected to a PIC (Photonic Integrated Circuit).

[0022] Hereinafter, components of the interposer 100 according to an example will be described in more detail with reference to the drawings.

[0023] The glass layer 110 may include glass, which is an amorphous solid. Examples of glass include pure silicon dioxide (approximately 100% SiO2), soda-lime glass, borosilicate glass, and aluminosilicate glass. However, it is not limited to these; alternative glass materials, such as fluoroglass, phosphate glass, and chalcogenide glass, can also be used. Furthermore, other additives may be included to form glass with specific physical properties. These additives may include not only calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), but also magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as carbonates and / or oxides of these elements and other elements. The glass layer 110 may be distinct from organic insulating materials containing glass fibers (Glass Fiber, Glass Cloth, Glass Fabric), such as CCL (Copper Clad Laminate) and PPG (Prepreg). For example, the glass layer 110 can include a glass panel that can be made to cover a large area, such as a glass plate.

[0024] Each of the multiple polymer layers 121 may contain an insulating material. The insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing inorganic and / or organic fillers together with these resins. For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film), but is not limited to this, and other polymer materials may be used. The insulating material may also be a photosensitive insulating material such as PID (Photo Imageable Dielectric). The multiple polymer layers 121 may contain substantially the same insulating material to each other.

[0025] Each of the multiple metal pattern layers 122 may contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it may contain copper (Cu), but is not limited to this. Each of the multiple metal pattern layers 122 can perform various functions depending on the design. For example, it may include signal patterns, power patterns, ground patterns, etc. These patterns may each have various forms such as lines, planes, and pads. Each of the multiple metal pattern layers 122 may include an electroless plating layer (e.g., chemical copper) and an electroplating layer (e.g., electrolytic copper). A sputtering layer may be included instead of the electroless plating layer, and both the electroless plating layer and the sputtering layer may be included if necessary. The sputtering layer may be a laminated structure of titanium (Ti) layers and copper (Cu) layers, but is not limited to this.

[0026] Each of the multiple metal via layers 123 may contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it may contain copper (Cu), but is not limited thereto. Each of the multiple metal via layers 123 may contain filled vias that fill via holes, but may also contain conformal vias that are arranged along the walls of via holes. The multiple metal via layers 123 may be in a stacked via configuration and may be arranged alternately with the multiple metal pattern layers 122. The multiple metal via layers 123 can perform various functions depending on the design. For example, they may include ground vias, power vias, signal vias, etc. The multiple metal via layers 123 may have a tapered shape in the same direction in cross-section, for example, a tapered shape in cross-section where the width of the upper end is wider than the width of the lower end. The multiple metal via layers 123 may each include an electroless plating layer (e.g., chemical copper) and an electroplating layer (e.g., electrolytic copper). A sputtering layer may be included instead of the electroless plating layer, and both the electroless plating layer and the sputtering layer may be included if necessary. The sputtering layer may, but is not limited to, a laminated structure of titanium (Ti) layers and copper (Cu) layers.

[0027] The through-via layer 131 may contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it may contain copper (Cu), but is not limited thereto. Each through-via layer 131 may contain a filled via (TVIA) that fills the through-hole, for example, a Through Glass Via (TGV). The through-via layer 131 can perform various functions depending on the design. For example, it may contain ground through-vias, power through-vias, signal through-vias, etc. The through-via layer 131 may have a substantially hourglass shape in cross-section, but is not limited thereto, and may also have a substantially vertical shape. The through-via layer 131 may contain an electroless plating layer (e.g., chemical copper) and an electroplating layer (e.g., electrolytic copper). A sputtering layer may be included instead of the electroless plating layer, and both the electroless plating layer and the sputtering layer may be included if necessary. The sputtering layer can, but is not limited to, a laminated structure of titanium (Ti) and copper (Cu) layers. The through-via layer 131 can be connected to at least one of a plurality of metal pattern layers 122, for example, the metal pattern layer 122 located at the bottom.

[0028] Component 132 can be various types of electronic components, such as silicon bridges and / or silicon capacitors, but is not limited to these. Component 132 can be embedded on the upper side of the glass layer 110. Component 132 can be embedded in the glass layer 110 without a cavity, but is not limited to this, and can also be embedded in the glass layer 110 in a form where it is positioned within a cavity of the glass layer 110. Component 132 can be connected to at least one of a plurality of metal pattern layers 122 and a plurality of metal via layers 123.

[0029] The waveguide pattern 133 may have a structure for transmitting optical signals. The waveguide pattern 133 may be formed on the uppermost polymer layer 121, but is not limited to this, and may be formed on at least one of the inner polymer layers 121 if necessary. The waveguide pattern 133 may be formed from a variety of known materials such as metallic materials, semiconductor materials, dielectric materials, and encapsulating materials.

[0030] Figure 3 is a schematic cross-sectional view showing an example of a printed circuit board with an integrated interposer.

[0031] Referring to the drawings, an example of an interposer-integrated printed circuit board 500 may include a plurality of insulating layers 211, 212, 213, a plurality of wiring layers 221, 222, 223, 224 arranged on or within the plurality of insulating layers 211, 212, 213, a plurality of via layers 231, 232, 233 arranged within the plurality of insulating layers 211, 212, 213 and each connected to at least one of the plurality of wiring layers 211, 222, 223, 224, and an interposer 100-1 embedded inside the plurality of insulating layers 211, 212, 213. If necessary, the configuration may further include a first passivation layer 241 positioned above the plurality of insulating layers 211, 212, 213 and having a plurality of first openings h1, a second passivation layer 242 positioned below the plurality of insulating layers 211, 212, 213 and having a plurality of second openings h2, a plurality of first electrical connecting metals 251 positioned on each of the plurality of first openings h1, a plurality of second electrical connecting metals 252 positioned on each of the plurality of second openings h2, and / or a plurality of semiconductor chips 261, 262, 263 surface-mounted on the first passivation layer 241 via the plurality of first electrical connecting metals 251. Here, the remaining components excluding the interposer 100-1 may be a first substrate, and the interposer 100-1 may be a second substrate embedded in the first substrate. On the other hand, the interposer 100-1 may include a structure substantially identical to that of the interposer 100 according to the example described above.

[0032] As described above, the interposer-integrated printed circuit board 500, as an example, has a structure in which an interposer 100-1 is manufactured by forming a redistribution layer 120 at the panel level using a glass layer 110 with excellent numerical stability and rigidity as the base layer, and such an interposer 100-1 can be widely integrated into a multilayer printed circuit board, for example, over a large area. Furthermore, by using this as a package substrate and mounting multiple semiconductor chips 261, 262, and 263, a package structure can be obtained. In this case, large area integration and chip-to-chip fine circuit linking are possible. In addition, since it is possible to prevent the decrease in numerical stability that can be a problem in 2.1D package substrates, etc., additional processes carried out during foundry and assembly can be omitted, and the chips can be mounted directly to the substrate, simplifying the process. Furthermore, by directly integrating or forming components such as silicon capacitors and silicon bridges 132 and waveguide patterns 133 in the interposer 100-1, various technologies necessary for next-generation semiconductors can be provided as one of the interposers 100-1. It can also be easily applied to large-area substrates for servers.

[0033] In the following section, the components of an interposer-integrated printed circuit board 500, as an example, will be described in more detail with reference to the drawings.

[0034] The interposer 100-1 may include a glass layer 110 and a redistribution layer 120 disposed on the glass layer 110. It may further include a through-via layer 131 penetrating the glass layer 110, at least one component 132 embedded in the glass layer 110, and / or a waveguide pattern 133 formed on the redistribution layer 120. The redistribution layer 120 may include a plurality of polymer layers 121 laminated on the glass layer 110, a plurality of metal pattern layers 122 disposed on or within the plurality of polymer layers 121, and a plurality of metal via layers 123 disposed within the plurality of polymer layers 121 and each connected to at least one of the plurality of metal pattern layers 122. The descriptions of the glass layer 110, the plurality of polymer layers 121, the plurality of metal pattern layers 122, the plurality of metal via layers 123, the through-via layer 131, the component 132, the waveguide pattern 133, etc., are substantially the same as those described above, so redundant descriptions are omitted.

[0035] The multiple insulating layers 211, 212, and 213 may include a core insulating layer 211, multiple first build-up insulating layers 212 laminated on the upper surface of the core insulating layer 211, and multiple second build-up insulating layers 213 laminated on the lower surface of the core insulating layer 211. The interposer 100-1 can be embedded within the multiple first build-up insulating layers 212. For example, at least one of the multiple first build-up insulating layers 212 may have a cavity C. The interposer 100-1 can be placed in the cavity C. At least one of the multiple first build-up insulating layers 212 may cover at least a portion of the interposer 100-1. At least one of the multiple first build-up insulating layers 212 may fill at least a portion of the cavity C.

[0036] The core insulating layer 211 may contain an organic insulating material. The organic insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may contain an inorganic filler, an organic filler, and / or glass fiber (glass cloth, glass fabric) together with the resin. For example, the organic insulating material may be, but is not limited to, CCL (copper clad laminate) or PPG (prepreg). The core insulating layer 211 may be thicker than each of the multiple first and second build-up insulating layers 212, 213. The core insulating layer 211 may be divided into multiple layers as needed.

[0037] Each of the multiple first and second build-up insulating layers 212, 213 may contain an organic insulating material. The organic insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may contain an inorganic filler, an organic filler, and / or glass fiber (glass cloth, glass fabric) together with the resin. For example, the organic insulating material may be, but is not limited to, PPG (Prepreg) or ABF (Ajinomoto Build-up Film). The multiple first and second build-up insulating layers 212, 213 may be substantially identical in material to each other, but are not limited to this. The multiple first and second build-up insulating layers 212, 213 may have the same number of layers to each other, but are not limited to this.

[0038] The multiple wiring layers 221, 222, 223, and 224 may include a first core wiring layer 221 located on the upper surface of the core insulating layer 211, a second core wiring layer 222 located on the lower surface of the core insulating layer 211, multiple first build-up wiring layers 223 located on or within multiple first build-up insulating layers 212, and multiple second build-up wiring layers 224 located on or within multiple second build-up insulating layers 213.

[0039] The first and second core wiring layers 221 and 222 may each contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it may contain, but is not limited to, copper (Cu). The first and second core wiring layers 221 and 222 may each perform various functions depending on the design. For example, they may include signal patterns, power patterns, ground patterns, etc. These patterns may each have various forms such as lines, planes, and pads. The first and second core wiring layers 221 and 222 may each contain a seed layer and a plating layer. The seed layer may be formed by electroless plating (or chemical copper) and, if necessary, by a sputtering process. Alternatively, both may be used. The plating layer may be formed by electrolytic plating (or electroplated copper). Copper foil may be further included if necessary.

[0040] The multiple first and second build-up wiring layers 223, 224 can each contain a metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it can contain, but is not limited to, copper (Cu). The multiple first and second build-up wiring layers 223, 224 can each perform various functions depending on the design. For example, they can include signal patterns, power patterns, ground patterns, etc. These patterns can each have various forms such as lines, planes, pads, etc. The multiple first and second build-up wiring layers 223, 224 can each contain a seed layer and a plating layer. The seed layer can be formed by electroless plating (or chemical copper), and optionally by a sputtering process. Alternatively, both can be used. The plating layer can be formed by electrolytic plating (or electroplated copper). Optionally, it can further contain copper foil.

[0041] The average pitch of at least one pattern among the multiple metal pattern layers 122 can be smaller than the average pitch of at least one wiring among the multiple wiring layers 221, 222, 223, 224. Preferably, the average pitch of each pattern in the multiple metal pattern layers 122 can be smaller than the average pitch of each wiring in the multiple wiring layers 221, 222, 223, 224. Here, the pitch may be the sum of half the line widths of adjacent patterns (or wiring) and the spacing between adjacent patterns (or wiring). Alternatively, the average pitch may be the average value of the pitch measured at any five points with respect to the cross-section of the printed circuit board. In a similar view, the average inter-layer insulation distance of at least two adjacent layers among the multiple metal pattern layers 122 can be smaller than the average inter-layer insulation distance of two adjacent layers among the multiple wiring layers 221, 222, 223, 224. Here, the insulation distance may be the separation distance between adjacent patterns (or wiring). Furthermore, the average insulation distance can be the average value of the insulation distances measured at any five points with respect to the cross-section of the printed circuit board. For example, the second board section can contain a higher density circuit than the first board section.

[0042] The multiple via layers 231, 232, and 233 may include core via layers 231 that connect the first and second core wiring layers 221 and 222 to each other within the core insulating layer 211, multiple first build-up via layers 232 that connect the multiple first build-up wiring layers 223, the interposer 100-1, and the first core wiring layer 221 to each other within the multiple first build-up insulating layers 212, and multiple second build-up via layers 233 that connect the multiple second build-up wiring layers 224 and the second core wiring layer 222 to each other within the multiple second build-up insulating layers 213.

[0043] The core via layer 231 may contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it may contain, but is not limited to, copper (Cu). The core via layer 231 may contain a plurality of through vias penetrating between the upper and lower surfaces of the core insulating layer 211, thereby providing an electrical connection path within the core insulating layer 211. Each of the multiple through vias can perform various functions depending on the design. For example, they may include signal vias, power vias, ground vias, etc. The core via layer 231 may contain a seed layer and a plating layer. The seed layer may be formed by electroless plating (or chemical copper) and, if necessary, by a sputtering process. Alternatively, both may be used. The plating layer may be formed by electroplating (or electrolytic copper).

[0044] Each of the multiple first and second build-up via layers 232, 233 may contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it may contain, but is not limited to, copper (Cu). Each of the multiple first and second build-up via layers 232, 233 may contain multiple connection vias that penetrate at least a portion of each of the multiple first and second build-up insulating layers 212, 213, thereby providing electrical connection paths within each of the multiple first and second build-up insulating layers 212, 213. Each of the multiple connection vias may perform a variety of functions depending on the design. For example, they may include signal vias, power vias, ground vias, etc. Each of the multiple connection vias may include filled vias, in which the via hole is filled with metal, or conformal vias, in which the metal is positioned along the wall of the via hole. Multiple connection vias can each have a tapered shape in cross-section. For example, multiple connection vias of multiple first build-up via layers 232 can have a tapered shape in cross-section where the width of the upper end is wider than the width of the lower end. Similarly, multiple connection vias of multiple second build-up via layers 233 can have a tapered shape in cross-section where the width of the lower end is wider than the width of the upper end. Multiple first and second build-up via layers 232 and 233 can similarly include seed layers and plating layers contained in multiple first and second wiring layers 224 and 225, but are not limited thereto.

[0045] Any one of the multiple first build-up wiring layers 223 positioned above the interposer 100-1 can be connected to any one of the multiple metal pattern layers 122 of the interposer 100-1, for example, the uppermost metal pattern layer 122, via any one of the multiple first build-up via layers 232 positioned above the interposer 100-1. Any one of the multiple second build-up wiring layers 224 positioned below the interposer 100-1 can be connected to the through-via layer 131 of the interposer 100-1 via a connecting member 234. The connecting member 234 can include, but is not limited to, various types of conductive materials, such as solder bumps and conductive films. On the other hand, the conductive film can be, but is not limited to, ACF (Anisotropic Conductive Film) or UCF (Unclad Conductive Film). There can be multiple connecting members 234, each of which can be connected to a TGV (Through Glass Via) in the through-via layer 131.

[0046] A first passivation layer 241 can be placed above the plurality of first build-up insulating layers 212, covering at least a portion of the uppermost of the plurality of first build-up wiring layers 223. The first passivation layer 241 may have a plurality of first openings h1, each exposing at least another portion of the uppermost first build-up wiring layer 223. A second passivation layer 242 can be placed below the plurality of second build-up insulating layers 213, covering at least a portion of the lowermost of the plurality of second build-up wiring layers 224. The second passivation layer 242 may have a plurality of second openings h2, each exposing at least another portion of the lowermost second build-up wiring layer 224. The first and second passivation layers 241 and 242 may each include an organic insulating material. The organic insulating material may include thermosetting resins such as epoxy resins, thermoplastic resins such as polyimides, or inorganic fillers, organic fillers, and / or glass fibers (glass fiber, glass cloth, glass fabric) together with the resin. For example, the organic insulating material may be, but is not limited to, ABF (Ajinomoto Build-up Film) or SR (Solder Resist). The pad patterns exposed through the multiple first and second openings h1, h2 may be in the form of SMD (Solder Mask Defined) and / or NSMD (Non Solder Mask Defined), but is not limited to these.

[0047] Multiple first and second electrical connecting metals 251, 252 can each be positioned on multiple first and second openings h1, h2 and can be connected to at least the other exposed portion of the uppermost first build-up wiring layer 223 and at least the other exposed portion of the lowermost second build-up wiring layer 224, respectively. If necessary, multiple first and second electrical connecting metals 251, 252 can also be positioned on multiple first and second openings h1, h2 via multiple first and second underbump metals (not shown). Multiple first and second electrical connecting metals 251, 252 can each be formed from a low-melting-point metal, such as a tin (Sn)-aluminum (Al)-copper (Cu) solder, but this is just an example and the material is not particularly limited thereto. Multiple first and second electrical connecting metals 251, 252 can each be balls, pins, etc. The multiple first and second electrical connecting metals 251, 252 can each be formed in multiple layers or a single layer. When formed in multiple layers, they may include copper columns and solder, and when formed in a single layer, they may include tin-silver solder, but are not limited to these. The multiple second electrical connecting metals 252 allow the interposer-integrated printed circuit board 500 to be mounted on the main board of an electronic device or other substrate.

[0048] Multiple semiconductor chips 261, 262, and 263 can each be surface-mounted on a first passivation layer 241 via multiple first electrically coupled metals 251, and can be electrically coupled to each other via multiple first build-up wiring layers 223 and an interposer 100-1. Each of the multiple semiconductor chips 261, 262, and 263 may include an integrated circuit (IC) die in which hundreds to millions or more elements are integrated within a single chip. Integrated circuits can be, but are not limited to, logic chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), field-programmable gate arrays (FPGAs), digital signal processors, cryptographic processors, microprocessors, microcontrollers, application processors (e.g., APs), analog-to-digital converters, and ASICs (application-specific ICs). They can also be of different types, such as memory chips like volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, HBM (High Bandwidth Memory), or PICs (Photonic Integrated Circuits). For example, the multiple semiconductor chips 261, 262, and 263 could be HBM, an ASIC, and a PIC, respectively, but are not limited to these.

[0049] Figures 4 to 7 are schematic cross-sectional views illustrating an example of the manufacturing process of a printed circuit board with an integrated interposer.

[0050] Referring to Figure 4, a core insulating layer 211 is prepared using CCL or the like, through holes are formed in the core insulating layer 211 using a CNC drill or the like, and first and second core wiring layers 221, 222 and a core via layer 231 are formed in the core insulating layer 211 during the plating process. Next, multiple first and second build-up insulating layers 212, 213 are formed on the upper and lower sides of the core insulating layer 211, respectively, using lamination of ABF or PPG, via holes are formed in the multiple first and second build-up insulating layers 212, 213 using a laser drill or the like, and multiple first and second build-up wiring layers 223, 224 and multiple first and second build-up via layers 232, 233 are formed in the multiple first and second build-up insulating layers 212, 213, respectively during the plating process. For example, a multilayer printed circuit board can be formed by carrying out the build-up process on both sides of the core layer. On the other hand, no pattern can be formed in the region R in which the interposer is built, and a connection pad P can be formed in the part connected to the interposer.

[0051] Referring to Figure 5, cavities C are formed that penetrate through a portion of the multiple first build-up insulating layers 212. Cavities C can be formed using various processes such as laser processing and blasting. The connecting pads P can also function as stopper layers for processing cavities C. Next, a separately manufactured interposer 100-1 is placed in the cavity C. For example, the interposer 100-1 can be connected to the connecting pads P using connecting members 234 such as solder bumps or conductive films. The interposer 100-1 can be manufactured by forming through-via layers 131 and components 132, etc., in the panel-level glass layer 110, and then forming redistribution layers 120 and waveguide patterns 133, etc., in build-up and plating processes.

[0052] Referring to Figure 6, the first and second build-up insulating layers 212 and 213 are further formed on the already formed first and second build-up insulating layers 212 and 213 by ABF or PPG lamination, respectively. At this time, the further formed first build-up insulating layer 212 can fill at least a part of the cavity C and embed the interposer 100-1. Next, via holes are formed in the further formed first and second build-up insulating layers 212 and 213 using a laser drill or the like, and a plating process is carried out to further form the first and second build-up wiring layers 223 and 224 and the first and second build-up via layers 232 and 233. At this time, the further formed first build-up wiring layer 223 can be connected to the metal pattern layer 122 located on the uppermost side of the interposer 100-1 via the further formed first build-up via layer 232.

[0053] Referring to Figure 7, first and second passivation layers 241 and 242 are formed on multiple first and second build-up insulating layers 212 and 213 by ABF lamination, SR coating, or lamination, respectively. Next, multiple first and second apertures h1 and h2 are formed on the first and second passivation layers 241 and 242, respectively, by laser processing or photolithography. Through this series of processes, an interposer-integrated printed circuit board in the form of a package substrate can be formed. After this, if necessary, multiple first and second electrically connecting metals can be formed on the multiple first and second apertures h1 and h2, respectively, and multiple semiconductor chips can be mounted via the multiple first electrically connecting metals. Furthermore, processes such as reflow can be performed. Through this series of processes, an interposer-integrated printed circuit board in the form of a semiconductor package can be formed. Other explanations can be substantially the same as those described above, and therefore redundant explanations are omitted.

[0054] In this disclosure, thickness, width, length, pitch, depth, etc., can be measured using a scanning microscope or optical microscope based on a polished or cut cross-section of the printed circuit board. The cut cross-section can be vertical or horizontal, and the respective values ​​can be measured based on the required cut cross-section. If the values ​​are not constant, the values ​​can be determined by the average of the values ​​measured at any five points. The width of the upper and / or lower ends of the via can be measured on a cross-section cut through the substrate in the thickness direction along the via's central axis. The depth of the via can be measured as the distance from the upper end to the lower end of the via on a cross-section cut through the substrate in the thickness direction along the via's central axis.

[0055] In this disclosure, the expression "cover" may include not only covering the entire surface but also covering at least a portion of it, and may include not only direct covering but also indirect covering. Similarly, the expression "satisfy" may include not only completely satisfying the surface but also satisfying it roughly, for example, if there are some gaps or voids.

[0056] In this disclosure, the determination can be made including process errors, positional deviations, and measurement errors that substantially occur during the manufacturing process. For example, substantially identical line width, spacing, thickness, and height may include not only cases where the numerical values ​​are exactly the same, but also cases where they are roughly similar. Furthermore, substantially any shape may include not only cases where the shape is exactly that, but also cases where the shape is roughly that of the object.

[0057] In this disclosure, the term "same insulating material" can mean not only that it is exactly the same insulating material, but also that it includes insulating materials of the same type. Therefore, the composition of the insulating materials may be substantially the same, but their specific composition ratios may differ slightly.

[0058] In this disclosure, "cross-sectional" can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. "Planar" can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed from the top or bottom.

[0059] In this disclosure, terms such as "lower side," "bottom," and "bottom surface" are used for convenience to mean the downward direction relative to the cross-section of the drawing, while terms such as "upper side," "upper part," and "top surface" are used to mean the opposite direction. Furthermore, terms such as "side" and "side" are used to mean the direction perpendicular to the top and bottom surfaces. However, these are merely definitions of directions for explanatory purposes, and the scope of the claims is not specifically limited by these directions; the concepts of "up" and "down" may change at any time.

[0060] In this disclosure, the term "connected" includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" includes both physically connected and unconnected connections. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0061] The expression "example" as used in this disclosure does not mean that each embodiment is identical to the others, but is provided to highlight and illustrate the unique and distinct features of each embodiment. However, the examples presented above do not preclude their implementation in combination with features of other examples. For example, even if a matter described in one example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that contradicts or inconsistes with that matter.

[0062] The terms used in this disclosure are for illustrative purposes only and are not intended to limit the disclosure. Where otherwise, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of symbols]

[0063] 1000 electronic equipment 1010 Mainboard 1020 Chip-related components 1030 Network-related components 1040 Other parts 1050 Camera 1060 Antenna 1070 Display 1080 Battery 1090 signal line 500 Interposer-integrated printed circuit boards 100, 100-1 Interposer 110 glass layer 120 Redistribution layer 121 Polymer layer 122 Metal Pattern Layer 123 Metal via layer 131 Through-Via Layer 132 parts 133 Waveguide Patterns 211 Core insulating layer 212, 213 Build-up insulating layer 221, 222 Core wiring layers 223, 224 Build-up wiring layers 231 Corevia layer 232, 233 Build-up via layer 234 Connecting Member 241, 242 Passivation Layer 251, 252 Electrically connected metals 261, 262, 263 Semiconductor chips h1, h2 opening C Cavity P Connection Pad R Interposer Built-in Area

Claims

1. Multiple insulating layers, A plurality of wiring layers, each disposed on or within the plurality of insulating layers, A plurality of via layers, each disposed within the plurality of insulating layers and each connected to at least one of the plurality of wiring layers, A printed circuit board comprising: an interposer embedded within the plurality of insulating layers, including a glass layer and a redistribution layer disposed on the glass layer.

2. The printed circuit board according to claim 1, wherein the redistribution layer includes a plurality of polymer layers, a plurality of metal pattern layers disposed on or within the plurality of polymer layers, and a plurality of metal via layers disposed within the plurality of polymer layers and each connected to at least one of the plurality of metal pattern layers.

3. The printed circuit board according to claim 2, wherein the interposer further includes through-via layers that penetrate the glass layer and are connected to at least one of the plurality of metal pattern layers.

4. Any one of the plurality of wiring layers located above the interposer is connected to the uppermost metal pattern layer among the plurality of metal pattern layers via any one of the plurality of via layers located above the interposer. The printed circuit board according to claim 3, wherein one of the plurality of wiring layers, which is located below the interposer, is connected to the through-via layer via a connecting member.

5. The printed circuit board according to claim 4, wherein the connecting member includes a solder bump or a conductive film.

6. The interposer further includes a component embedded in the glass layer and connected to at least one of the plurality of metal pattern layers, The printed circuit board according to claim 2, wherein the component includes one or more of a silicon bridge and a silicon capacitor.

7. The printed circuit board according to claim 2, wherein the interposer further includes waveguide patterns disposed on or within the plurality of polymer layers.

8. The average pitch of at least one of the plurality of metal pattern layers is smaller than the average pitch of at least one of the plurality of wiring layers. The printed circuit board according to claim 2, wherein the average inter-layer insulation distance of at least two adjacent layers among the plurality of metal pattern layers is smaller than the average inter-layer insulation distance of at least two adjacent layers among the plurality of wiring layers.

9. The plurality of insulating layers include a core insulating layer and a plurality of first and second build-up insulating layers laminated above and below the core insulating layer, respectively. The printed circuit board according to claim 1, wherein the interposer is embedded within the plurality of first build-up insulating layers.

10. At least one of the plurality of first build-up insulating layers has a cavity, The interposer is placed in the cavity, The printed circuit board according to claim 9, wherein at least one of the plurality of first build-up insulating layers covers at least a portion of the interposer and fills at least a portion of the cavity.

11. The plurality of wiring layers include first and second core wiring layers disposed on the upper and lower surfaces of the core insulating layer, respectively; a plurality of first build-up wiring layers disposed on or within the plurality of first build-up insulating layers, respectively; and a plurality of second build-up wiring layers disposed on or within the plurality of second build-up insulating layers, respectively. The printed circuit board according to claim 9, wherein the plurality of via layers include core via layers that connect the first and second core wiring layers to each other within the core insulating layer, a plurality of first build-up via layers that connect the plurality of first build-up wiring layers, the interposer, and the first core wiring layer to each other within the plurality of first build-up insulating layers, and a plurality of second build-up via layers that connect the plurality of second build-up wiring layers and the second core wiring layer to each other within the plurality of second build-up insulating layers.

12. A first passivation layer having a plurality of first openings, which are positioned above the plurality of first build-up wiring layers, cover at least a portion of the uppermost first build-up wiring layer among the plurality of first build-up wiring layers, and expose at least other portions of the uppermost first build-up wiring layer, The printed circuit board according to claim 11, further comprising: a second passivation layer disposed below the plurality of second build-up wiring layers, having a plurality of second openings that cover at least a portion of the lowest second build-up wiring layer among the plurality of second build-up wiring layers, and exposing at least other portions of the lowest second build-up wiring layer.

13. Multiple semiconductor chips are each arranged on the upper surface of the first passivation layer, A plurality of first electrically connecting metals are arranged on the plurality of first openings, each connected to at least another exposed portion of the uppermost first build-up wiring layer, and each connected to at least one of the plurality of semiconductor chips, The printed circuit board according to claim 12, further comprising a plurality of second electrical connecting metals, each positioned on the plurality of second openings and each connected to at least other exposed portions of the lowermost second build-up wiring layer.

14. The printed circuit board according to claim 1, wherein the glass layer includes a glass plate.

15. A first substrate portion including a plurality of insulating layers and a plurality of wiring layers disposed on or within the plurality of insulating layers, A second substrate portion comprising a glass plate, a plurality of polymer layers laminated on the glass plate, and a plurality of metal pattern layers disposed on or within the plurality of polymer layers, The second substrate portion is built into the first substrate portion, A printed circuit board in which at least one of the plurality of metal pattern layers is electrically connected to at least one of the plurality of wiring layers.

16. The printed circuit board according to claim 15, wherein the second substrate portion further includes one or more through vias that penetrate the glass plate and are connected to at least one of the plurality of metal pattern layers, components embedded in the glass plate and connected to at least one of the plurality of wiring layers, and waveguide patterns arranged on or within the plurality of polymer layers.

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