Vertical stacked microdisplay panel and method for manufacturing the same

Abstract

In a vertically stacked microdisplay panel, a plurality of light-emitting units stacked vertically through a bonding layer of a back wafer on which a plurality of CMOS electrode pads are aligned on the upper surface include a plurality of LED stacks aligned on the plurality of CMOS electrode pads and a common electrode formed on the plurality of LED stacks, the bonding layer includes a first bonding layer for bonding the light-emitting units and a second bonding layer for bonding the light-emitting units in a state where the light-emitting units are bonded through the first bonding layer, and in the plurality of LED stacks, a short passage is formed in at least one of the light-emitting units, so that current is passed through the light-emitting units where the short passage is not formed and only a specific color is emitted. [Effects] By joining transparent conductive material and transparent insulating material, high light transmittance, electrical conductivity, chemical and thermal stability can be ensured, and at the same time, the reliability of the joint between light-emitting parts can be improved.

Description

Technical Field

[0001] The present invention relates to a vertical stacked microdisplay panel and a manufacturing method thereof. More specifically, by applying an Engineering monolithic epitaxy wafer method using a ceramic material in the bonding process of a front wafer and a back wafer, the present invention relates to a LEDoS microdisplay panel that eliminates the alignment process of an LED stack and CMOS electrode pads and a manufacturing method thereof.

Background Art

[0002] The types of Metaverse that have recently attracted attention are classified into four forms: VR (virtual reality), AR (augmented reality), MR (mixed reality), and XR (extended reality). Among these, it is expected that the Metaverse ecosystem will develop in the future centering on XR, which is a reality linked with VR, AR, and MR. In order to effectively implement this, in addition to software for a next-generation computing platform that can provide an innovative user experience, a device (such as smart glasses, a head-mounted display, etc.) that includes a microdisplay having a diagonal length of less than 1 inch as a core component is required. In particular, in order to provide the most immersive experience, visibility, and convenience to XR users and minimize dizziness, the development of high-performance microdisplay panel technology is absolutely necessary.

[0003] As shown in Figure 1, the conventional microdisplay panel 10 is a technology that combines a Si CMOS semiconductor wafer process with a high-resolution, high-brightness ultra-small display process. The conventional microdisplay panel 10 can have a structure in which a Si CMOS wafer 11 having 4 or more (100) crystal planes equipped with multiple CMOS electrode pads 12, and a transparent wafer 13 having 4 or more microLED chips 15 equipped with microLED electrode pads 14 are bonded together through a conductive junction (16). On the other hand, types of microdisplay panels expected to be applied to XR devices include LCoS (LC on Si) based on liquid crystal (LC), OLEDoS (OLED on Si) based on organic light-emitting diode (OLED), and LEDoS (LED on Si) based on ultra-small microLEDs with a pixel size of less than 5 μm. However, in the case of VR where displays with low pixel density are applied, LCoS and OLEDoS are the main types that have been developed and mass-produced.

[0004] However, with the advancement of metaverse implementation technologies, the need for lightweight AR, MR, and XR devices utilizing high-pixel-density microdisplay panels is increasing. This need has led to an urgent need for LEDoS (which employs a microLED pixel light source composed of red, green, and blue subpixels smaller than 5 μm), which is considered a theoretically ideal solution based on the advantages of inorganic materials. However, a microdisplay panel platform for this purpose has not yet been established.

[0005] LEDoS, an ultra-small microLED substrate with a pixel size of less than 5 μm, offers advantages when applied to XR devices, including an excellent power-to-performance ratio and fast response time. Furthermore, being composed of inorganic materials, it boasts a long lifespan, efficient power utilization, heat dissipation, and extended battery life. In particular, because XR devices have a very short distance between the display and the eye, even a slight delay in image conversion can easily cause discomfort such as dizziness. Therefore, LEDoS, with its nanosecond response time, is considered the most suitable for XR devices compared to LCoS and OLEDoS, which have microsecond response times.

[0006] Furthermore, the biggest reason why LEDoS is attracting attention in AR, MR, and XR devices, unlike VR, is considered to be its brightness and luminous efficiency. Due to the nature of smart glasses that can be worn anywhere, high brightness is an essential condition so that they can operate normally even in outdoor environments such as sunlight. Theoretically, microLEDs can support a brightness of tens to millions of nits, and while OLEDs are organic materials, microLEDs are inorganic materials, so they have the advantage of high luminous efficiency.

[0007] However, despite the aforementioned advantages, the main reason why LEDoS, an ultra-small microLED substrate with a pixel size of less than 5 μm, has not been positioned as a major component of XR devices is that mass production is difficult. In other words, because LEDoS requires fixing millions of ultra-small microLEDs onto a Si CMOS wafer, the process is highly complex and the yield is very low, leading to increased manufacturing costs and resulting in a high component price. This is reflected in the final consumer price, resulting in an expensive XR device that is difficult to supply in line with market demand.

[0008] On the other hand, as shown in Figure 2, until recently, the development of LEDoS using group 3-5 compound (GaN, GaP, etc.) microLED light sources has been developed through traditional approaches such as (1) monolithic integration of wafers (or unit dies) composed of microLED arrays on CMOS wafers, or (2) hybridization between wafers (or unit dies) on blue, green, and red light source wafers (or unit dies) on which CMOS wafers or microLED arrays have been fabricated.

[0009] One of the biggest obstacles to LEDoS development using blue, green, and red microLED light sources composed of group 3-5 compounds to date is the difficulty in securing solutions for pixels smaller than 5 μm. However, recently, 5 μm level pixels have been successfully demonstrated using monolithic integration technology, and prototypes developed based on hybridization technology have achieved 10 μm level pixels by fabricating them through sapphire flip chips. Furthermore, it has been demonstrated that it is possible to reduce the size of 5 μm level pixels in the same way by using microtube wiring in addition to hybridization technology. However, both monolithic integration technology and hybridization technology are impractical solutions that are considerably difficult to mass-produce in terms of quality and yield, and mass production is not feasible.

[0010] The aforementioned monolithic integration and hybridization technologies share the common characteristic of assembling a front-plane wafer composed of group 3-5 compound microLED arrays and a Si CMOS back-plane wafer composed of numerous IC electrode pad arrays, after separate design and fabrication. However, regardless of the method, the microLED arrays fabricated on the Si CMOS wafer at the unit die-level or wafer-level must be ultra-fine aligned. At this time, alignment is limited by the precision of process-related equipment, which consequently has a significant impact on the pixel and pitch limitations, making mass production difficult. Therefore, in order to manufacture LEDoSs with high resolution, high brightness, and high-speed driving blue, green, and red microLED light sources with pixels smaller than 5 μm and pitches smaller than 3 μm, a new alternative solution that can circumvent the aforementioned ultra-fine alignment constraints is needed.

[0011] Consequently, several impressive prototypes with 6μm pixels have recently been released using engineering monolithic epitaxy wafers manufactured through a low-temperature metal bonding process between Si CMOS wafers and microLED array wafers. However, it is believed that mass production would be impossible due to low quality and yield issues resulting from low-temperature metal bonding, and the use of small-diameter wafers of 6 inches or less. Above all, when fabricating ultra-fine pixels of less than 3μm for microdisplays using conventional engineering monolithic epitaxy wafers utilizing metal bonding, even greater difficulties arise during the etching process of the patterning.

[0012] Another example is the recent proposal of a novel approach to engineered monolithic epitaxy wafers, which has made significant progress in solving the problems limiting the brightness and resolution of LEDoS using group 3-5 compound microLED light sources, and which can provide mass production and low-cost manufacturing solutions by using 12-inch large-diameter Si CMOS wafers.

[0013] Referring to Figure 3, the process using the engineering monolithic epitaxy wafer is carried out through the following four steps: (1) First, using the LED epitaxy wafer, LED epitaxies cut to a predetermined size (e.g., 4 mm x 6 mm) are aligned and bonded at the unit die level onto a 12-inch large-diameter Si blanket wafer. Subsequently, the LED epitaxy growth wafer and buffer layer are removed and then planarized to leave only the LED active layer of a predetermined thickness (e.g., approximately 1.5 μm) on the large-diameter Si blanket wafer, completing the LED fab process into a pixel chip form. (2) Next, the Si blanket wafer with the completed pixel chip is bonded to a 12-inch CMOS IC Si wafer at the wafer level through multilayer metal bonding. (3) Next, the Si blanket wafer is removed. (4) Finally, residual processes are performed on the CMOS IC Si wafer for the microLED array that will function as a pixel.

[0014] However, in stage (1), when bonding the LED epitaxy unit die onto the Si blanket wafer, there is a limitation that positional alignment must be performed using a CMOS IC Si wafer of the same size before bonding. In stage (2), when bonding with a multilayer metal containing low-melting-point metals (Sn, In), there is a problem that the ejection phenomenon of overflowing low-melting-point metal components occurs relatively easily, causing short-circuit defects that electrically connect between or adjacent CMOS IC electrode pad arrays within the microLED subpixel array in the panel. Consequently, in stage (2), the optically opaque nature of the Si blanket wafer and the multilayer metal bonding layer makes ultra-fine alignment wafer bonding (bonding) between the Si blanket wafer (i.e., the front plane wafer) and the CMOS IC Si wafer difficult, leading to defects. Here, ultra-fine alignment means matching and aligning the microLED array, which is a multi-layer (hundreds to tens of millions) of ultra-small pixel chips on the Si blanket wafer, with the CMOS IC electrode pad array on the CMOS IC Si wafer in a 1:1 ratio.

[0015] In other words, the engineering monolithic epitaxy wafer approach method presented in the aforementioned technology is considered to have provided a solution that brings us one step closer to realizing LEDoS for ultra-small microLED substrates with pixel sizes of less than 5 μm. However, there are quality and yield issues caused by the use of metal (low temperature, multilayer) in wafer bonding, making it quite difficult to manufacture high-resolution microdisplays with ultra-fine pixels of less than 3 μm. Furthermore, there are problems with some alignment processes, so a new alternative is needed.

[0016] Furthermore, in conventional microdisplays employing microLED pixel light sources, the vertically stacked tandem structure still requires the application of color filters to achieve full color, resulting in disadvantages in terms of color quality, process complexity, and productivity.

[0017] On the other hand, when using only transparent conductive oxide (TCO) such as ITO as the bonding layer in the manufacturing process of vertically stacked microdisplay panels, a problem arises where the bonding reliability between light-emitting parts decreases, which in turn reduces the overall quality and manufacturing yield of the microdisplay panel. [Prior art documents] [Patent Documents]

[0018] [Patent Document 1] Republic of Korea Patent Publication No. 10-2018-0009116 [Overview of the Initiative] [Problems that the invention aims to solve]

[0019] The object of the present invention is to solve the aforementioned conventional problems and to provide an LEDoS vertical stacked microdisplay panel and a method for manufacturing the same, which eliminates the need for an alignment process between the LED stack and the CMOS electrode pads by applying an engineering monolithic epitaxy wafer method that utilizes ceramic material in the bonding process between the front wafer and the back wafer.

[0020] Furthermore, an object of the present invention is to solve the aforementioned conventional problems and to provide an LEDoS vertical stacked microdisplay panel and a method for manufacturing the same that can ensure high light transmittance, excellent electrical conductivity, chemical and thermal stability through bonding between a transparent conductive material and a transparent insulating material, as well as improve the surface flatness of the bonding layer and improve the bonding reliability between light-emitting parts. [Means for solving the problem]

[0021] The above object is achieved by a vertical stacked microdisplay panel according to the present invention, which includes a back wafer having a plurality of CMOS electrode pads aligned on its upper surface; a plurality of LED stacked bodies each including a plurality of light emitting parts vertically stacked through a bonding layer and aligned on the plurality of CMOS electrode pads respectively; and a common electrode formed on the plurality of LED stacked bodies. The bonding layer includes a first bonding layer for bonding the light emitting parts on the back wafer and a second bonding layer for bonding another light emitting part on the light emitting parts in a state where the light emitting parts are bonded on the back wafer through the first bonding layer. Each of the plurality of LED stacked bodies has a short circuit formed in at least one of the plurality of light emitting parts, so that current is applied to the light emitting parts in which the short circuit is not formed to emit only a specific color of light.

[0022] Further, the first bonding layer may be formed of a metallic material.

[0023] Further, the first bonding layer may be formed of a transparent electrically conductive material.

[0024] Further, the second bonding layer may be formed of a transparent electrically insulating material.

[0025] Further, a functional layer that is ohmic contacted with the light emitting part is formed on one surface of the light emitting part, and the second bonding layer can bond another light emitting part on the light emitting part by being bonded to the functional layer.

[0026] Further, the short circuit may be formed through the first bonding layer.

[0027] The above object is achieved by the present invention through the following steps: a preparation step of preparing a front wafer including a support wafer and a light-emitting part, and a back wafer having a plurality of CMOS electrode pads aligned on its upper surface; a bonding step of bonding the front wafer onto the back wafer through a bonding layer and then repeatedly removing the support wafer, thereby bonding a plurality of the light-emitting parts onto the back wafer; an etching step of etching the stacked plurality of the light-emitting parts and the bonding layer to separate them into preset units, so that a plurality of LED stacked bodies are respectively aligned on the plurality of the CMOS electrode pads; and a forming step of forming a common electrode on the plurality of the LED stacked bodies. The bonding layer includes a first bonding layer for bonding the light-emitting part onto the back wafer and a second bonding layer for bonding another light-emitting part onto the light-emitting part in a state where the light-emitting part is bonded onto the back wafer through the first bonding layer. Each of the plurality of the LED stacked bodies has a short circuit formed in at least one of the plurality of the light-emitting parts, so that current is passed through the light-emitting part in which the short circuit is not formed to emit only a specific color, which is achieved by a manufacturing method of a vertical stacked type microdisplay panel.

[0028] Also, the first bonding layer may be formed of a metallic substance.

[0029] Also, the first bonding layer may be formed of a transparent electrically conductive substance.

[0030] Also, the second bonding layer may be formed of a transparent electrically insulating substance.

[0031] Also, a functional layer that is ohmic contacted with the light-emitting part is formed on one surface of the light-emitting part, and the second bonding layer can bond another light-emitting part onto the light-emitting part by being bonded to the functional layer.

[0032] Also, the short circuit may be formed by penetrating the first bonding layer.

Advantages of the Invention

[0033] According to the present invention, unlike existing monolithic integration or hybridization methods in which alignment issues exist, an engineered monolithic epitaxy wafer is first manufactured, and then the laminate on the engineered monolithic epitaxy wafer is etched and separated into predetermined units so that multiple LED laminates are aligned on multiple CMOS electrode pads. This makes it possible to use not only small-diameter wafers of 6 inches or less, but also large-diameter wafers of 8 inches or more, which has the effect of significantly increasing product yield.

[0034] Furthermore, according to the present invention, high light transmittance, excellent electrical conductivity, chemical and thermal stability can be ensured through bonding between a transparent conductive material and a transparent insulating material, and the surface flatness of the bonding layer can be improved, thereby improving the reliability of the bonding between light-emitting parts.

[0035] On the other hand, the effects of the present invention are not limited to those mentioned above, and a variety of effects may be included within the scope that is obvious to an ordinary person, as described below. [Brief explanation of the drawing]

[0036] [Figure 1] This diagram illustrates the structure of a conventional microdisplay panel. [Figure 2] This diagram illustrates the conventional approach to LEDoS development. [Figure 3] This diagram illustrates an approach method using conventional engineering monolithic epitaxy wafers. [Figure 4] This figure illustrates the process by which a p-side-up front wafer is prepared in a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention. [Figure 5] This figure illustrates the process by which an n-side-up front wafer is prepared in a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention. [Figure 6]This figure illustrates the process of preparing a back wafer in a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention. [Figure 7] This is a flowchart of a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention. [Figure 8] This figure illustrates the process by which a vertically stacked microdisplay panel is manufactured using a manufacturing method for a vertically stacked microdisplay panel according to one embodiment of the present invention. [Figure 9] This figure illustrates the process by which a vertically stacked microdisplay panel is manufactured using a manufacturing method for a vertically stacked microdisplay panel according to one embodiment of the present invention. [Figure 10] This figure illustrates the process by which a vertically stacked microdisplay panel is manufactured using a manufacturing method for a vertically stacked microdisplay panel according to one embodiment of the present invention. [Figure 11] This figure illustrates a vertically stacked microdisplay panel manufactured by a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention. [Figure 12] This figure illustrates a case where the first bonding layer is made of a different material during the manufacturing process of a vertically stacked microdisplay panel using a manufacturing method for a vertically stacked microdisplay panel according to one embodiment of the present invention. [Figure 13] This figure illustrates a case where the first bonding layer is made of a different material during the manufacturing process of a vertically stacked microdisplay panel using a manufacturing method for a vertically stacked microdisplay panel according to one embodiment of the present invention. [Figure 14] This figure illustrates a case where the first bonding layer is made of a different material during the manufacturing process of a vertically stacked microdisplay panel using a manufacturing method for a vertically stacked microdisplay panel according to one embodiment of the present invention. [Figure 15] This figure illustrates a case where the first bonding layer of a vertically stacked microdisplay panel manufactured by a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention is made of a different material. [Modes for carrying out the invention]

[0037] Some embodiments of the present invention will be described in detail below with reference to illustrative drawings. Note that when assigning reference numerals to the components in each drawing, efforts have been made to ensure that the same component has the same reference numeral whenever possible, even if it is shown in other drawings.

[0038] Furthermore, in describing embodiments of the present invention, if a specific description of a related known configuration or function is deemed to hinder understanding of the embodiments of the present invention, such detailed description will be omitted.

[0039] Furthermore, when describing the components of the embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc., may be used. Such terms are merely used to distinguish a component from other components, and do not limit the essence, order, or sequence of the component in question.

[0040] From here on, a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention (S100) will be described in detail with reference to the attached drawings.

[0041] Figure 7 is a flowchart of a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention.

[0042] Referring to Figure 7, a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention (S100) includes a preparation step (S110), a bonding step (S120), a cutting step (S130), and a forming step (S140).

[0043] The preparation stage (S110) is the stage in which multiple front wafers 110 and back wafers 140 are prepared.

[0044] Here, the front wafer 110 refers to a front plane wafer and may include a first front wafer containing a first light-emitting section 121 that emits a first color, a second front wafer containing a second light-emitting section 122 that emits a second color different from the first color, and a third front wafer containing a third light-emitting section 123 that emits a third color different from the first and second colors. On the other hand, the first, second, and third colors may be, for example, red, green, and blue, respectively, but are not limited to these, and may include a variety of other colors.

[0045] Such a front wafer 110 may include a support wafer S and a light-emitting section 120 positioned on top of the support wafer S.

[0046] The light-emitting part 120 generates light and can emit blue, green, or red light. In the present invention, when the light-emitting part 120 emits blue or green light, binary, ternary, or quaternary compounds such as InN, InGaN, GaN, AlGaN, AlN, and AlGaInN, which are group 3 (Al, Ga, In) nitride semiconductors among group 3-5 compound semiconductors, can be arranged in the appropriate positions and order on the initial growth wafer G and grown epitaxially.

[0047] In particular, a high-quality InGaN group 3 nitride semiconductor having a high In composition to emit blue or green light must be preferentially formed on top of a group 3 nitride semiconductor composed of GaN, AlGaN, AlN, or AlGaInN, but is not limited thereto.

[0048] Furthermore, in the present invention, when the light-emitting section 120 emits red light, binary, ternary, and quaternary compounds such as InP, InGaP, GaP, AlInP, AlGaP, AlP, and AlGaInP, which are group 3 (Al, Ga, In) phosphide semiconductors among group 3-5 compound semiconductors, can be epitaxy-grown by arranging them in appropriate positions and order on the initial growth wafer G. In addition, in recent years, in order to further improve equipment and process technology development and the value of display panel products, when emitting red light, in addition to group 3 phosphide semiconductors, high-quality InGaN group 3 nitride semiconductors having a high In composition of 30% or more may be preferentially formed on top of the group 3 nitride semiconductor composed of GaN, AlGaN, AlN, and AlGaInN.

[0049] In particular, to emit red light, a high-quality InGaP group 3 phosphide semiconductor having a high In composition must be preferentially formed on top of a group 3 phosphide semiconductor composed of GaP, AlInP, AlGaP, AlP, and AlGaInP, but is not limited to this, and the following explanation will be based on group 3 nitride semiconductors.

[0050] Each light-emitting portion 120 more specifically includes a first semiconductor region 1201 (e.g., a p-type semiconductor region), an active region 1203 (e.g., multi-quantum wells, MQWs), and a second semiconductor region 1202 (e.g., an n-type semiconductor region). The structure can be formed by sequentially epitaxy-growing the second semiconductor region 1202, the active region 1203, and the first semiconductor region 1201 on a growth wafer G. The final structure can contain various multilayer group 3 nitrides and have an overall thickness of typically 5.0 to 8.0 μm, but is not limited to this.

[0051] The first semiconductor region 1201, the active region 1203, and the second semiconductor region 1202 may each consist of a single layer or multiple layers. Although not shown, prior to epitaxy growth of the light-emitting portion 120 on the top of the growth wafer G, necessary layers such as buffer layers may be added to improve the quality of the epitaxy-grown light-emitting portion 120. For example, the buffer layer may consist of a nucleation layer (NL) and a compliance layer (CL) composed of an undoped semiconductor region to relieve stress and improve the quality of the thin film, and may have a thickness of approximately 4.0 μm. Also, when removing the growth wafer G using the laser lift-off (LLO) technique, a sacrificial layer (SL) may be provided between the nucleation layer and the undoped semiconductor region, and the seed layer may function as the sacrificial layer.

[0052] The second semiconductor region 1202 has a second conductivity (n-type) and is formed on the growth wafer G. Such a second semiconductor region 1202 can have a thickness of 2.0 to 3.5 μm.

[0053] The active region 1203 generates light by utilizing the recombination of electrons and holes, and is formed on the second semiconductor region 1202. Such an active region 1203 can have a multilayer structure with a thickness of several tens of nanometers.

[0054] The first semiconductor region 1201 has a first conductivity (p-type) and is formed on the active region 1203. Such a first semiconductor region 1201 can have a thickness of several tens of nanometers to several micrometers in multiple layers, and its surface can have gallium polarity (Ga-polarity).

[0055] In other words, the active region 1203 is interposed between the first semiconductor region 1201 and the second semiconductor region 1202, and when holes in the first semiconductor region 1201, which is a p-type semiconductor region, and electrons in the second semiconductor region 1202, which is an n-type semiconductor region, are recombined in the active region 1203, light can be generated.

[0056] Furthermore, a functional layer 124 may be formed on the upper surface of the light-emitting section 120.

[0057] Specifically, the functional layer 124 is formed to be in contact with the light-emitting portion 120 and to be in ohmic contact, and can be formed as a single layer or a multilayer.

[0058] In this case, if the functional layer 124 is formed as a single layer, it may include only an ohmic contact layer. On the other hand, if the functional layer 124 is formed as a multilayer, it may include both an ohmic contact layer and a highly permeable bonding layer.

[0059] Specifically, when the functional layer 124 is formed as a single layer, the ohmic contact layer must have excellent ohmic properties, permeability, and bonding properties. On the other hand, when the functional layer 124 is formed as a multilayer, it is important for the ohmic contact layer to ensure excellent ohmic properties and a certain level of permeability, while the highly permeable bonding layer can perform its bonding function by being formed from a transparent material (e.g., ITO, IZO, etc.) that is conductive, even if its ohmic properties are relatively low.

[0060] Such functional layer 124 materials may include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, ITO, IZO, IGZO, ZITO, IMoO, ITiO, ITON, IZON, NiO-Au and / or NiO-Ag, of which ITO, IZO, NiO-Au, or NiO-Ag may be preferentially selected, but are not limited thereto.

[0061] The support wafer S supports the light-emitting section 120 located on top. If the initial growth wafer G is not removed, the growth wafer G may be the support wafer S, or it may be a separate wafer bonded to remove the initial growth wafer G.

[0062] On the other hand, in the present invention, the front wafer 110 may be manufactured and prepared in a p-side-up or n-side-up configuration.

[0063] Figure 4 illustrates the process by which a p-side-up front wafer is prepared in a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention.

[0064] Referring to Figure 4, the process by which the front wafer 110 is manufactured and prepared in a p-side-up configuration is as follows:

[0065] In the case of blue or green light, a second semiconductor region 1202, an active region 1203, and a first semiconductor region 1201 are sequentially epitaxi-grown on a sapphire (α-phase Al2O3) growth wafer G (or a GaAs growth wafer G, etc., in the case of red light). Then, a p-side-up front wafer 110 is prepared by forming a p-type functional layer 124 with transparent conductivity on the upper surface of the first semiconductor region 1201. At this time, the growth wafer G acts as a support wafer S, and the structure can have a configuration in which the support wafer S, the second semiconductor region 1202, the active region 1203, the first semiconductor region 1201, and the functional layer 124 are sequentially stacked.

[0066] On the other hand, in the case of blue light and green light, the blue or green light emitting portion 120 may be formed on Si having a (111) crystal plane instead of the sapphire (α-phase Al2O3) growth wafer G, in which case the Si growth wafer G can be separated and removed by mechanical polishing or chemical lift-off (CLO) technique.

[0067] Figure 5 illustrates the process by which an n-side-up front wafer is prepared in a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention.

[0068] As illustrated in Figure 5, the process by which the n-side-up front wafer 110 is manufactured and prepared is as follows.

[0069] In the case of blue or green light, a second semiconductor region 1202, an active region 1203, and a first semiconductor region 1201 are sequentially epitaxi-grown on a sapphire (α-phase Al2O3) growth wafer G (or a GaAs growth wafer G in the case of red light), and then a support wafer S is bonded to the upper surface through a temporary bonding layer B. Subsequently, the growth wafer G is separated from the light-emitting region 120 using a laser lift-off (LLO) or chemical lift-off (CLO) technique, the second semiconductor region 1202 is etched to reduce its thickness, and then an n-type functional layer 124 with transparent conductivity is formed on the surface of the reduced-thickness second semiconductor region 1202 to prepare an n-side-up front wafer 110. In this case, the support wafer S may be formed of a Si material having (111), (110), or (100) crystal planes, but is not limited thereto, and can have a structure in which the support wafer S, temporary bonding layer B, first semiconductor region 1201, active region 1203, second semiconductor region 1202, and functional layer 124 are sequentially stacked.

[0070] Furthermore, in this invention, the growth wafer G and / or support wafer S materials can all be sapphire or silicon (Si), respectively, but the choice of material can be determined by the wafer bonding method.

[0071] For example, when bonding at room temperature via a surface activation process, wafers made of different materials such as sapphire or silicon (Si) may be selected regardless of their thermal expansion coefficients. However, when bonding between the growth wafer G, support wafer S, and back wafer 140 at a temperature of 50°C or higher, or when annealing is performed at a temperature of 50°C or higher without removing one of the wafers after bonding has been completed, wafers made of the same material must be selected.

[0072] On the other hand, if the surface of the first semiconductor region 1201 is exposed before the functional layer 124 is formed on the surface of the first semiconductor region 1201 or the surface of the second semiconductor region 1202 during the manufacturing process of the front wafer 110 described above, the surface can be polished and planarized smoothly through mechanical polishing (MP) or chemical-mechanical polishing (CMP), respectively, so that it can have a smooth surface.

[0073] Furthermore, the surface of the functional layer 124 formed on the front wafer 110 can also be polished and planarized smoothly through mechanical polishing (MP) or chemical-mechanical polishing (CMP).

[0074] Figure 6 illustrates the process by which a back wafer is prepared in a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention.

[0075] Referring to Figure 6, the back wafer 140 is an actively driven IC driven by an active matrix (AM) method, and represents a CMOS backplane wafer or CMOS panel on which a plurality of CMOS electrode pads 141 are arranged in an array on its upper surface. The plurality of CMOS electrode pads 141 include individual CMOS electrode pads 141 that function as individual electrodes and common CMOS electrode pads 141 that function as common electrodes, and a passivation layer P may be formed on the back wafer 140 so that the upper surfaces of the plurality of CMOS electrode pads 141 are not exposed.

[0076] At this time, the surface of the CMOS electrode pad 141 may be exposed to the outside by forming an opening hole in the passivation layer P above the CMOS electrode pad 141, or by etching the entire passivation layer P to the same height as the CMOS electrode pad 141.

[0077] Furthermore, the back wafer 140 may be made of a Si wafer having a (100) crystal plane, and may be made of an 8-inch or 12-inch Si wafer by a standard CMOS IC process, but the size of the back wafer 140 is not particularly limited, considering that the usual LED wafer for bonding (front wafer 110) is 4 inches or 6 inches.

[0078] Figures 8 to 10 illustrate the process by which a vertically stacked microdisplay panel is manufactured using a manufacturing method for a vertically stacked microdisplay panel according to one embodiment of the present invention.

[0079] The vertically stacked microdisplay panel 100 of the present invention can be manufactured using a front wafer 110 in a p-side-up or n-side-up configuration. Below, the manufacturing process using a front wafer 110 in a p-side-up configuration will be described with reference to Figures 8 to 10.

[0080] The bonding step (S120) is a step in which a plurality of light-emitting parts 120 are bonded to the back wafer 140 and stacked vertically by repeatedly bonding the front wafer 110 to the back wafer 140 through the bonding layer 130 and then removing the support wafer S.

[0081] When using only transparent conductive oxide (TCO) such as ITO as the inter-light-emitting bonding layer 130 in the manufacturing process of a vertically stacked microdisplay panel 100, a problem arises in which the bonding reliability between light-emitting parts decreases, leading to a reduction in the overall quality and manufacturing yield of the microdisplay panel.

[0082] Therefore, in this invention, an optically transparent electrically insulating material is additionally introduced during bonding between light-emitting parts. This ensures high light transmittance, excellent electrical conductivity, and chemical and thermal stability through bonding between the transparent conductive material and the transparent insulating material. At the same time, the surface flatness of the bonding layer can be improved, thereby enhancing the reliability of the bonding between light-emitting parts.

[0083] At this time, the bonding layer includes a first bonding layer 131 for bonding the light-emitting portion 120 onto the back wafer 140, and a second bonding layer 132 for bonding another light-emitting portion 120 onto the light-emitting portion 120, with the light-emitting portion 120 already bonded to the back wafer 140 through the first bonding layer 131.

[0084] The joining stage (S120) more specifically includes a first joining stage and a second joining stage.

[0085] The first bonding step is the step of bonding the light-emitting portion 120 onto the back wafer 140 by bonding the front wafer 110 onto the back wafer 140 through the first bonding layer 131 and then removing the support wafer S.

[0086] Specifically, in the first bonding stage, a first bonding layer 131 made of a metallic material is first formed on the front wafer 110, and then a first bonding layer 131 is also formed on the back wafer 140, where the CMOS electrode pads 141 are exposed to the outside, so as to be electrically connected to the CMOS electrode pads 141. After that, the first bonding layer 131 of the front wafer 110 and the first bonding layer 131 of the back wafer 140 are bonded to each other, thereby bonding the front wafer 110 to the back wafer 140.

[0087] Here, the metal bonding method may include, but is not limited to, eutectic bonding, diffusion bonding, or direct bonding.

[0088] Furthermore, the first bonding layer 131 for bonding the front wafer onto the back wafer may be formed as a single layer or a multilayer, and if the first bonding layer 131 is formed as a multilayer, it may include a highly reflective layer, a diffusion prevention layer, and a metal bonding reinforcement layer.

[0089] Such first bonding layer 131 material may include Ag, AgCu, AgPd, AgCuPd, Ag alloy, Au, Au alloy, Rh, Rh alloy, Al, or Al alloy, and when the first bonding layer 131 is formed in multiple layers, the highly reflective layer may include Ag, Al, Rh, Au, Pt, Ir, or Cu, the diffusion-preventing layer may include W, Pd, Cu, Mo, Ta, TiN, or CrN, and the metal bonding strengthening layer may include, but is not limited to, Cr, Ti, Ni, Zr, V, Co, Mn, or Nb.

[0090] After the front wafer 110 and the back wafer 140 are bonded, the support wafer S of the front wafer 110 is removed by laser lift-off (LLO) or chemical lift-off (CLO), etc., to expose the surface of the light-emitting portion 120 on which the functional layer 124 is not formed.

[0091] For example, when using a front wafer 110 having a p-side-up configuration, in the first bonding stage, the first bonding layer 131 formed on the uppermost part of the first front wafer 111 and the first bonding layer 131 formed on the back wafer 140 are bonded to each other, and then the support wafer S is removed to laminate the first light-emitting part 121 that emits a first color onto the back wafer 140. This results in an n-side-up structure in which the first bonding layer 131, a p-type functional layer 124, a first semiconductor region 1201, an active region 1203, and a second semiconductor region 1202 are sequentially laminated on the back wafer 140. At this time, it is of course possible to reduce the thickness of the exposed second semiconductor region 1202 by etching it.

[0092] Thereafter, in the first bonding stage, a second bonding layer 132 is formed on the surface of the second semiconductor region 1202 of the first light-emitting part 121. The second bonding layer 132 may be formed of a transparent electrical insulating material, such as SiO2, SiNx, AlN, or Al2O3, but is not limited to these.

[0093] Subsequently, in the first bonding stage, through holes are formed in the second bonding layer 132 and a portion of the first light-emitting section 121, and then these through holes are filled to form the short layer 170.

[0094] Specifically, in the first bonding stage, a through-hole is formed in the region where the second LED stack L2 and the third LED stack L3 are formed, from the second bonding layer 132 through the active region 1203 of the first light-emitting part 121. Then, in the first bonding stage, a through-hole is formed in the second bonding layer 132 in the region where the first LED stack L1 is formed, so that the surface of the second semiconductor region 1202 of the first light-emitting part 121 is exposed.

[0095] Subsequently, in the first bonding stage, the through-holes are filled to form a short layer 170 that covers the second bonding layer 132.

[0096] Here, the through-holes can be filled using a direct self-align method or through a liquid coating method such as a sol-gel, thereby forming the short layer 170, but is not limited to these methods.

[0097] On the other hand, the short layer 170 is preferably formed of an optically transparent and electrically conductive material, which may include, but is not limited to, In2O3, SnO2, ZnO, IZO, ITO, and IGZO.

[0098] Furthermore, the short layer 170 may be formed of a metallic material, which may include Ag, Al, Rh, Cu, Au, etc., and a laminated structure in which thin adhesion-improving materials such as Ti, Ni, Cr, and Pt are formed with a thickness of a few nanometers or less is also possible. It may also be provided with alloys such as AgCu and AgNi, but is not limited to these.

[0099] Subsequently, in the first bonding stage, the short layer 170 is etched by mechanical polishing (MP) or chemical-mechanical polishing (CMP) to expose the surface of the lower second bonding layer 132. As a result, a short passage 180 is formed in the region where the second LED stack L2 and the third LED stack L3 are formed, and an n-type ohmic contact electrode 1242 is formed in the region where the first LED stack L1 is formed.

[0100] The second bonding step involves bonding multiple other light-emitting units 120 onto the light-emitting unit 120 by repeatedly bonding the front wafer 110 onto the light-emitting unit 120 through the second bonding layer 132, and then removing the support wafer S, while the light-emitting unit 120 is bonded onto the back wafer 140 through the first bonding layer 131.

[0101] For example, in the second bonding stage, the p-type functional layer 124 formed on the uppermost part of the p-side-up second front wafer 112 and the second bonding layer 132 formed on the upper part of the first light-emitting part 121 after the first bonding stage are bonded to each other, and then the support wafer S is removed, thereby allowing the second light-emitting part 122 to be stacked on the back wafer 140 in an n-side-up structure that emits a second color. At this time, it is of course possible to reduce the thickness of the exposed second semiconductor region 1202 by etching the second semiconductor region 1202.

[0102] Subsequently, in the second bonding stage, a second bonding layer 132 is formed on the surface of the second semiconductor region 1202 of the second light-emitting part 122. Then, through holes are formed in the second bonding layer 132 and a part of the second light-emitting part 122, and the through holes are filled to form a short layer 170.

[0103] Specifically, in the second bonding stage, a through-hole is formed from the second bonding layer 132 through the active region 1203 of the second light-emitting section 122 in the region where the first LED stack L1 and the third LED stack L3 are formed, and a through-hole is formed in the second bonding layer 132 in the region where the second LED stack L2 is formed, so that the surface of the second semiconductor region 1202 of the second light-emitting section 122 is exposed.

[0104] Subsequently, in the second bonding stage, the through-holes are filled to form a short layer 170 that covers the second bonding layer 132, and the short layer 170 is etched by mechanical polishing (MP) or chemical-mechanical polishing (CMP) to expose the surface of the lower second bonding layer 132. Accordingly, a short passage 180 is formed in the region where the first LED stack L1 and the third LED stack L3 are formed, and an n-type ohmic contact electrode 1242 is formed in the region where the second LED stack L2 is formed.

[0105] Next, in the second bonding stage, the p-type functional layer 124 formed on the uppermost part of the p-side-up third front wafer 113 and the second bonding layer 132 formed on the upper part of the second light-emitting part 122 are bonded to each other. Then, by removing the support wafer S, the third light-emitting part 123 can be stacked on the back wafer 140 in an n-side-up structure that emits a third color. At this time, it is of course possible to reduce the thickness of the exposed second semiconductor region 1202 by etching it.

[0106] On the other hand, although the above example described a case in which the first light-emitting section 121, the second light-emitting section 122, and the third light-emitting section 123 are stacked sequentially, the light-emitting section 120 is not limited to this, and can be stacked in various orders and numbers.

[0107] The etching step (S130) is a step in which multiple stacked light-emitting parts 120, functional layers 124, first bonding layer 131, and second bonding layer 132 are etched and separated into predetermined units, thereby aligning multiple LED stacks L on individual CMOS electrode pads 141. This step eliminates the need for the conventional step of aligning the LED stacks L on the front wafer 110 and the CMOS electrode pads 141 on the back wafer 140 with each other.

[0108] For example, in the etching stage (S130), the light-emitting portion 120, functional layer 124, first bonding layer 131, and second bonding layer 132 are etched vertically until the passivation layer P of the back wafer 140 is exposed, so that the LED stack L is aligned on top of the individual CMOS electrode pads 141, and the top of the common CMOS electrode pad 141 is also exposed to the outside. At this time, the first bonding layer 131 remains on top of the common CMOS electrode pad 141 and can function as a connecting electrode.

[0109] On the other hand, the predefined unit here means a pixel or subpixel unit, and may mean the diameter (width) of the LED stack L. The LED stack L may include a first LED stack L1 for emitting only the first color, a second LED stack L2 for emitting only the second color, and a third LED stack L3 for emitting only the third color.

[0110] In this case, since both the second bonding layer 132 and the functional layer 124 of the present invention utilize ceramic materials rather than metals, there is an advantage in that the etching process is easy and the problem of etching byproducts being re-deposited does not occur.

[0111] Subsequently, in the etching stage (S130), molded portions 150 are formed to fill the spaces between multiple LED stacks L, and then through-holes are formed in the molded portions 150 and a part of the third light-emitting portion 123.

[0112] Specifically, in the etching stage (S130), through-holes are formed from the upper molded portion 150 of each first LED stack L1 and second LED stack L2, penetrating the active region 1203 of the third light-emitting portion 123, and through-holes are formed in the upper molded portion 150 of the third LED stack L3, so that the surface of the second semiconductor region 1202 of the third light-emitting portion 123 is exposed. Consequently, in the etching stage (S130), through-holes are formed in the molded portion 150 so that the first junction layer 131 on the upper part of the common CMOS electrode pad 141 is exposed to the outside.

[0113] The formation step (S140) is the step of forming a common electrode 160 on top of multiple LED stacks L.

[0114] Specifically, in the formation stage (S140), the through-holes formed in the etching stage (S130) are filled to form a common electrode 160, through which a short passage 180 is formed in the first LED stack L1 and the second LED stack L2, and an n-type ohmic contact electrode 1242 is formed in the third LED stack L3.

[0115] Such a common electrode 160 may be formed from a material having transparent conductivity, similar to the functional layer 124. When the common electrode is the negative electrode, the common electrode material may include, but is not limited to, In, InGa, Ga, InN, InGaN, GaN, TiN, TiNO, CrN, VN, In2O3, SnO2, ZnO, ITO, IZO, STO, and / or IGZO. When the common electrode is the positive electrode, the common electrode material may include, but is not limited to, NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, ITO, IZO, IGZO, ZITO, IMoO, ITiO, ITON, IZON, NiO-Au, and / or NiO-Ag.

[0116] Figure 11 illustrates a vertically stacked microdisplay panel manufactured by a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention.

[0117] Referring to Figure 11, the vertically stacked microdisplay panel 100 manufactured by the manufacturing method (S100) of a vertically stacked microdisplay panel according to one embodiment of the present invention described above includes a back wafer 140 on which a plurality of CMOS electrode pads 141 are aligned on the upper surface, and a plurality of light-emitting units 120 stacked vertically through a bonding layer. It also includes a plurality of LED stacks L aligned on the plurality of CMOS electrode pads 141 and a common electrode 160 formed on the plurality of LED stacks L. The bonding layer includes a first bonding layer 131 for bonding the light-emitting units 120 to the back wafer 140, and a second bonding layer 132 for bonding other light-emitting units 120 to the light-emitting units 120 while the light-emitting units 120 are bonded to the back wafer 140 through the first bonding layer 131. Here, the first bonding layer 131 may be formed of a metallic material.

[0118] At this time, a functional layer 124 is formed on one surface of the light-emitting part 120, which is in ohmic contact with the light-emitting part 120. However, a second bonding layer 132, which is made of a transparent electrical insulating material, is bonded to the functional layer 124, which is made of a transparent electrical conductive material, so that another light-emitting part 120 can be bonded onto the light-emitting part 120.

[0119] In particular, each of the multiple LED stacks L of the present invention has a short-circuit passage 180 formed in at least one of the multiple light-emitting sections 120, so that current is supplied to the light-emitting sections 120 in which the short-circuit passage 180 is not formed, allowing only a specific color to be emitted.

[0120] Specifically, the first LED laminate L1 of the present invention has short passages 180 formed so as to penetrate the third light-emitting section 123 and the second light-emitting section 122, respectively, so that current is not injected into the third light-emitting section 123 and the second light-emitting section 122, and current is supplied only to the first light-emitting section 121, causing only the first color to be emitted.

[0121] Furthermore, the second LED laminate L2 of the present invention has short passages 180 formed so as to penetrate the third light-emitting section 123 and the first light-emitting section 121, respectively, so that current is not injected into the third light-emitting section 123 and the first light-emitting section 121, and current is supplied only to the second light-emitting section 122, causing only the second color to be emitted.

[0122] Furthermore, the third LED laminate L3 of the present invention has short passages 180 formed so as to penetrate the second light-emitting section 122 and the first light-emitting section 121, respectively, so that current is not injected into the second light-emitting section 122 and the first light-emitting section 121, and current is supplied only to the third light-emitting section 123, allowing only the third color to be emitted.

[0123] In other words, in each stacked LED stack L, a short-circuit passage 180 is formed in at least one of the multiple light-emitting sections 120, so that current is supplied to the light-emitting sections 120 that do not have a short-circuit passage D180, causing them to emit only a specific color.

[0124] Figures 12 to 14 illustrate the case where the first bonding layer is made of a different material during the manufacturing process of a vertically stacked microdisplay panel using a manufacturing method for a vertically stacked microdisplay panel according to one embodiment of the present invention.

[0125] On the other hand, referring to Figures 12 to 14, the first bonding layer 131 of the present invention can be formed from a transparent electrically conductive material.

[0126] At this time, the first junction layer 131 may be formed of the same or similar transparent conductive oxide as the functional layer 124, and may be formed of TCO materials such as ITO, IZO, IMoO, or ITiO, TCN materials such as TiN, or TCON materials such as ITON, IZON, or TiNO, but is not limited to these.

[0127] Specifically, in the first bonding stage, a first bonding layer 131 made of a transparent electrically conductive material is formed on the back wafer 140, on which the CMOS electrode pads 141 are exposed to the outside, so as to be electrically connected to the CMOS electrode pads 141. Then, the first bonding layer 131 is etched by mechanical polishing (MP) or chemical-mechanical polishing (CMP) to expose the surface of the underlying passivation layer P.

[0128] Furthermore, although not shown in the diagram, after etching the first bonding layer 131 by mechanical polishing (MP) or chemical-mechanical polishing (CMP), the first bonding layer 131 can optionally be perpendicularly connected to the CMOS electrode pad 141 and can exist with a uniform thickness on top of the electrically insulating passivation layer P on the back wafer 140.

[0129] Subsequently, in the first bonding stage, the functional layer 124 of the front wafer 110 and the passivation layer P of the back wafer 140 are bonded to each other, thereby bonding the front wafer 110 onto the back wafer 140.

[0130] Although not shown in the diagram, the functional layer 124 of the front wafer 110 and the first bonding layer 131 of the back wafer 140 can be bonded to each other as needed, thereby bonding the front wafer 110 onto the back wafer 140.

[0131] After bonding the front wafer 110 and the back wafer 140, the support wafer S of the front wafer 110 is removed by laser lift-off (LLO) or chemical lift-off (CLO), etc., to expose the surface of the light-emitting portion 120 where the functional layer 124 is not formed, i.e., the surface of the second semiconductor region 1202. Then, the second bonding layer 132 is formed on the surface, and the subsequent steps are carried out in the same manner as described above.

[0132] According to this, the light-emitting part 120, the first bonding layer 131, the second bonding layer 132, and the functional layer 124 of the present invention are all transparent and therefore transmit visible light, which has the advantage of eliminating alignment error issues in the exposure process. Furthermore, since the first bonding layer 131, the second bonding layer 132, and the functional layer 124 of the present invention all utilize ceramic materials rather than metals, etching is easy in the plasma dry process, and there is no problem of etching byproducts being re-deposited.

[0133] Figure 15 illustrates a case where the first bonding layer of a vertically stacked microdisplay panel manufactured by a method for manufacturing a vertically stacked microdisplay panel according to one embodiment of the present invention is made of a different material.

[0134] Referring to Figure 15, the vertically stacked microdisplay panel 100 of the present invention includes a back wafer 140 on which a plurality of CMOS electrode pads 141 are aligned on the upper surface, and a plurality of light-emitting units 120 stacked vertically through a bonding layer. It also includes a plurality of LED stacks L aligned on the plurality of CMOS electrode pads 141 and a common electrode 160 formed on the plurality of LED stacks L. The bonding layer includes a first bonding layer 131 for bonding the light-emitting units 120 to the back wafer 140, and a second bonding layer 132 for bonding other light-emitting units 120 to the light-emitting units 120 while the light-emitting units 120 are bonded to the back wafer 140 through the first bonding layer 131. Here, the first bonding layer 131 may be formed of a metallic material.

[0135] At this time, a functional layer 124 is formed on one surface of the light-emitting part 120, which is in ohmic contact with the light-emitting part 120. However, a second bonding layer 132, which is made of a transparent electrical insulating material, is bonded to the functional layer 124, which is made of a transparent electrical conductive material, so that another light-emitting part 120 can be bonded onto the light-emitting part 120.

[0136] Although all components constituting the embodiments of the present invention have been described as being either combined into one or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the objectives of the present invention, all components may be selectively combined into one or more units and operate in combination.

[0137] Furthermore, unless otherwise stated, terms such as "includes," "constitutes," or "possesses" used above mean that the relevant component may be inherent, and should be interpreted as including other components rather than excluding them. All terms, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which this invention belongs, unless otherwise defined. Commonly used terms, such as dictionary definitions, should be interpreted as corresponding to their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this invention.

[0138] Furthermore, the above explanation is merely illustrative in describing the technical concept of the present invention, and a person with ordinary skill in the art to which the present invention belongs can make various modifications and variations without departing from the essential characteristics of the present invention.

[0139] Therefore, the embodiments disclosed herein are for illustrative purposes only and not to limit the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention should be interpreted in accordance with the following claims, and all technical concepts within an equivalent scope should be interpreted as being included within the scope of the rights of the present invention. [Explanation of Symbols]

[0140] 100: Vertical stacked microdisplay panel according to one embodiment of the present invention 110: Front wafer 111: First front wafer 112: Second front wafer 113: Third Front Wafer G: Growth wafer S: Support wafer B: Temporary bonding layer L:LED laminate L1: First LED stack L2: Second LED stack L3: Third LED stack 120: Light-emitting part 1201: First Semiconductor Area 1202: Second Semiconductor Area 1203:Active region 121: First light-emitting section 122: Second light-emitting section 123: Third light-emitting section 124: Functional Layer 1242: Ohmic contact electrode 131: 1st bonding layer 132:Second bonding layer 140: Back wafer 141: CMOS electrode pads P: Passivation layer 150: Mold part 160: Common electrode 170: Short Layer 180: Short aisle

Claims

1. A back wafer with multiple CMOS electrode pads aligned on its upper surface; A plurality of LED stacks each containing a plurality of light-emitting units stacked vertically through a bonding layer, and each being aligned on a plurality of CMOS electrode pads; and Including a common electrode formed on a plurality of the LED stacks, The aforementioned bonding layer is The bonding layer includes a first bonding layer for bonding the light-emitting portion to the back wafer, and a second bonding layer for bonding another light-emitting portion to the light-emitting portion while the light-emitting portion is bonded to the back wafer through the first bonding layer. Each of the multiple LED stacks is, A vertically stacked microdisplay panel in which a short passage is formed in at least one of the multiple light-emitting sections, thereby allowing current to be supplied to the light-emitting sections where the short passage is not formed, causing only a specific color to be emitted.

2. The first bonding layer is A vertically stacked microdisplay panel according to claim 1, formed of a metallic material.

3. The first bonding layer is A vertically stacked microdisplay panel according to claim 1, formed from a transparent electrically conductive material.

4. The aforementioned second junction layer is A vertically stacked microdisplay panel according to claim 1, formed of a transparent electrically insulating material.

5. On one surface of the light-emitting part, A functional layer is formed that is in ohmic contact with the light-emitting portion. The aforementioned second junction layer is The vertically stacked microdisplay panel according to claim 4, wherein other light-emitting parts are bonded to the light-emitting part by bonding with the functional layer.

6. The aforementioned short passage is A vertically stacked microdisplay panel according to claim 5, formed by penetrating the first bonding layer.

7. Preparation step involves preparing a front wafer containing a support wafer and light-emitting section, and a back wafer with multiple CMOS electrode pads aligned on its upper surface; A bonding step in which a plurality of light-emitting portions are bonded to the back wafer by repeatedly bonding the front wafer to the back wafer through a bonding layer and then removing the support wafer; A etching step in which multiple stacked LED stacks are aligned on multiple CMOS electrode pads by etching the multiple stacked light-emitting parts and the bonding layer to separate them into predetermined units; and The process includes a forming step of forming a common electrode on a plurality of the LED stacks, The aforementioned bonding layer is The bonding layer includes a first bonding layer for bonding the light-emitting portion to the back wafer, and a second bonding layer for bonding another light-emitting portion to the light-emitting portion while the light-emitting portion is bonded to the back wafer through the first bonding layer. Each of the multiple LED stacks is, A method for manufacturing a vertically stacked microdisplay panel, wherein a short passage is formed in at least one of the multiple light-emitting sections, so that current is supplied to the light-emitting sections where the short passage is not formed, causing only a specific color to be emitted.

8. The first bonding layer is A method for manufacturing a vertically stacked microdisplay panel according to claim 7, which is formed of a metallic material.

9. The first bonding layer is A method for manufacturing a vertically stacked microdisplay panel according to claim 7, which is formed of a transparent electrically conductive material.

10. The aforementioned second junction layer is A method for manufacturing a vertically stacked microdisplay panel according to claim 7, which is formed of a transparent electrically insulating material.

11. On one surface of the light-emitting part, A functional layer is formed that is in ohmic contact with the light-emitting portion. The aforementioned second junction layer is A method for manufacturing a vertically stacked microdisplay panel according to claim 10, wherein other light-emitting parts are bonded to the light-emitting part by bonding with the functional layer.

12. The aforementioned short passage is A method for manufacturing a vertically stacked microdisplay panel according to claim 11, wherein the panel is formed through the first bonding layer.

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