Insulated switches, electronic equipment

Abstract

A capacitor is used to transmit pulse signals. [Solution] The isolation switch 400 includes, for example, a switch circuit 422 connected between a first node T4 and a second node T5 and switched on / off by a switch drive signal Vg; a pulse generation circuit 411 that generates a first drive pulse Pa and a second drive pulse Pb in opposite phases to each other; a switch drive circuit 421 that receives a third drive pulse Ia and a fourth drive pulse Ib and generates a switch drive signal Vg; and a first isolation capacitor Cia and a second isolation capacitor Cib that transmit the first drive pulse Pa and the second drive pulse Pb as a third drive pulse Ia and a fourth drive pulse Ib, respectively, while insulating the pulse generation circuit 411 and the switch drive circuit 421.

Description

Technical Field

[0001] The present disclosure relates to an isolation switch and an electronic device.

Background Art

[0002] Conventionally, an isolation switch configured to drive a switch element in a secondary circuit system in accordance with a control signal of a primary circuit system while electrically isolating the primary circuit system and the secondary circuit system has been used in various applications (such as a power supply device or a motor drive device).

[0003] As an example of the related prior art, Patent Document 1 by the applicant of the present application can be cited.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] In the conventional isolation switch, there has been room for consideration regarding the signal transmission method.

[0006] The isolation switch according to the present disclosure includes, for example, a switch circuit connected between a first node and a second node and configured to be turned on / off by a switch drive signal, a pulse generation circuit configured to generate a first drive pulse and a second drive pulse in opposite phases to each other, a switch drive circuit configured to receive a third drive pulse and a fourth drive pulse and generate the switch drive signal, and a first isolation capacitor and a second isolation capacitor configured to transmit the first drive pulse and the second drive pulse as the third drive pulse and the fourth drive pulse, respectively, while insulating between the pulse generation circuit and the switch drive circuit.

Brief Description of the Drawings

[0007] [Figure 1] Figure 1 shows the basic configuration of a signal transmission device. [Figure 2] Figure 2 shows the basic structure of a transformer chip. [Figure 3] Figure 3 is a perspective view of a semiconductor device used as a 2-channel transformer chip. [Figure 4] Figure 4 is a plan view of the semiconductor device shown in Figure 3. [Figure 5] Figure 5 is a plan view showing the layer in the semiconductor device of Figure 3 where the low-potential coil is formed. [Figure 6] Figure 6 is a plan view showing the layer in the semiconductor device of Figure 3 where the high-potential coil is formed. [Figure 7] Figure 7 is a cross-sectional view along the line VIII-VIII shown in Figure 6. [Figure 8] Figure 8 shows an enlarged view (separated structure) of region XIII shown in Figure 7. [Figure 9] Figure 9 is a schematic diagram showing an example of a transformer chip layout. [Figure 10] Figure 10 shows a comparative example of an insulated switch. [Figure 11] Figure 11 shows a first embodiment of an insulated switch. [Figure 12] Figure 12 shows a second embodiment of the insulated switch. [Figure 13] Figure 13 shows a third embodiment of the insulated switch. [Figure 14] Figure 14 shows a first example of a discharge circuit. [Figure 15] Figure 15 shows a second example of a discharge circuit. [Figure 16] Figure 16 shows a fourth embodiment of the insulated switch. [Figure 17] Figure 17 shows an example of a voltage control circuit configuration.

[0008] [Detailed explanation] <Signal transmission device (basic configuration)> Figure 1 shows the basic configuration of a signal transmission device. The signal transmission device 200 in this example configuration is a semiconductor integrated circuit device (a so-called isolated gate driver IC) that transmits pulse signals from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) and the secondary circuit system 200s (VCC2-GND2 system), and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 consists of a controller chip 210, a driver chip 220, and a transformer chip 230, all packaged together.

[0009] The controller chip 210 is a semiconductor chip that operates on a power supply voltage VCC1 (for example, up to 7V relative to GND1). The controller chip 210 integrates, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0010] The pulse transmission circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmission circuit 211 indicates that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it indicates that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. In other words, the pulse transmission circuit 211 pulse-drives either the transmission pulse signal S11 or S21 depending on the logic level of the input pulse signal IN.

[0011] The buffer 212 receives the input of the transmitted pulse signal S11 from the pulse transmission circuit 211 and pulses the transformer chip 230 (specifically the transformer 231).

[0012] The buffer 213 receives the input of the transmitted pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically the transformer 232).

[0013] The driver chip 220 is a semiconductor chip that operates by receiving a supply of a power supply voltage VCC2 (for example, up to 30V with respect to the GND2 reference). Integrated in the driver chip 220 are, for example, buffers 221 and 222, a pulse receiving circuit 223, and a driver 224.

[0014] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transchip 230 (specifically, the transformer 231) and outputs it to the pulse receiving circuit 223.

[0015] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transchip 230 (specifically, the transformer 232) and outputs it to the pulse receiving circuit 223.

[0016] The pulse receiving circuit 223 generates an output pulse signal OUT by driving the driver 224 according to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level upon receiving a pulse drive of the received pulse signal S12, while the output pulse signal OUT falls to a low level upon receiving a pulse drive of the received pulse signal S22. That is, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT according to the logic level of the input pulse signal IN. As the pulse receiving circuit 223, for example, an RS flip-flop can be suitably used.

[0017] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223.

[0018] The transformer chip 230 uses transformers 231 and 232 to DC-isolate the controller chip 210 and the driver chip 220, and outputs the transmitted pulse signals S11 and S21 input from the pulse transmitting circuit 211 as received pulse signals S12 and S22, respectively, to the pulse receiving circuit 223. In this specification, "DC-isolated" means that the objects to be isolated are not connected by a conductor.

[0019] More specifically, transformer 231 outputs a received pulse signal S12 from its secondary coil 231s in response to a transmitted pulse signal S11 input to its primary coil 231p. On the other hand, transformer 232 outputs a received pulse signal S22 from its secondary coil 232s in response to a transmitted pulse signal S21 input to its primary coil 232p.

[0020] Thus, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0021] In this example, the signal transmission device 200 has a separate transformer chip 230 containing only transformers 231 and 232, in addition to the controller chip 210 and driver chip 220, and these three chips are sealed in a single package.

[0022] With this configuration, both the controller chip 210 and the driver chip 220 can be formed using a general low-to-medium voltage process (several volts to tens of volts), eliminating the need to use a dedicated high-voltage process (several kV voltage), and thus reducing manufacturing costs.

[0023] The signal transmission device 200 can be suitably used, for example, in a power supply unit or motor drive unit for in-vehicle equipment mounted on a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (xEVs such as BEV [battery electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV (plug-in hybrid electric vehicle / plug-in hybrid vehicle], or FCEV / FCV (fuel cell electric vehicle / fuel cell vehicle)).

[0024] <Trans-chip (basic structure)> Next, the basic structure of the transformer chip 230 will be described. Figure 2 shows the basic structure of the transformer chip 230. In the transformer chip 230 shown in this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that are opposed to each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that are opposed to each other in the vertical direction.

[0025] The primary coils 231p and 232p are both formed in the first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed in the second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is positioned directly above the primary coil 231p and faces it. Similarly, the secondary coil 232s is positioned directly above the primary coil 232p and faces it.

[0026] The primary coil 231p is laid in a spiral pattern, starting from its first end connected to internal terminal X21 and surrounding internal terminal X21 in a clockwise direction, with its second end, corresponding to its endpoint, connected to internal terminal X22. On the other hand, the primary coil 232p is laid in a spiral pattern, starting from its first end connected to internal terminal X23 and surrounding internal terminal X23 in a counterclockwise direction, with its second end, corresponding to its endpoint, connected to internal terminal X22. Internal terminals X21, X22, and X23 are arranged linearly in the order shown in the figure.

[0027] Internal terminal X21 is connected to external terminal T21 of the second layer 230b via conductive wiring Y21 and via Z21. Internal terminal X22 is connected to external terminal T22 of the second layer 230b via conductive wiring Y22 and via Z22. Internal terminal X23 is connected to external terminal T23 of the second layer 230b via conductive wiring Y23 and via Z23. External terminals T21 to T23 are arranged in a straight line and are used for wire bonding to the controller chip 210.

[0028] The secondary coil 231s is laid in a spiral pattern, starting from its first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with its second end, corresponding to its endpoint, connected to the external terminal T25. On the other hand, the secondary coil 232s is laid in a spiral pattern, starting from its first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with its second end, corresponding to its endpoint, connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure and are used for wire bonding with the driver tip 220.

[0029] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, respectively, and are DC-isolated from the primary coils 231p and 232p. In other words, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-isolated from the controller chip 210 by the transformer chip 230.

[0030] <Trans-chip (2-channel type)> Figure 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. Figure 4 is a plan view of the semiconductor device 5 shown in Figure 3. Figure 5 is a plan view showing the layer in the semiconductor device 5 shown in Figure 3 where the low-potential coil 22 (corresponding to the primary coil of the transformer) is formed. Figure 6 is a plan view showing the layer in the semiconductor device 5 shown in Figure 3 where the high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed. Figure 7 is a cross-sectional view along the line VIII-VIII shown in Figure 6. Figure 8 is an enlarged view of region XIII shown in Figure 7, showing the separation structure 130.

[0031] Referring to Figures 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide-bandgap semiconductor, and a compound semiconductor.

[0032] Wide-bandgap semiconductors consist of semiconductors with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of a wide-bandgap semiconductor is preferably 2.0 eV or greater. The wide-bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0033] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a laminated structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0034] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a rectangular shape (in this form, a rectangular shape) when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view").

[0035] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long side of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along a first direction X and face a second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short side of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in a second direction Y and face a first direction X. The chip sidewalls 44A to 44D consist of a ground surface.

[0036] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that aligns with the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0037] The insulating sidewalls 53A to 53D include the first insulating sidewall 53A, the second insulating sidewall 53B, the third insulating sidewall 53C, and the fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are connected to the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form a ground surface that is flush with the chip sidewalls 44A to 44D.

[0038] The insulating layer 51 consists of a multilayer insulating laminate structure including a bottom insulating layer 55, an upper insulating layer 56, and a plurality (11 layers in this embodiment) of interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The upper insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the upper insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the upper insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the thickness of the upper insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0039] Each of the multiple interlayer insulating layers 57 has a laminated structure including a first insulating layer 58 on the bottom insulating layer 55 side and a second insulating layer 59 on the top insulating layer 56 side. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, about 0.3 μm).

[0040] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, about 2 μm). Preferably, the thickness of the second insulating layer 59 exceeds the thickness of the first insulating layer 58.

[0041] The total thickness DT of the insulating layer 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layer 51 and the number of layers of the interlayer insulating layer 57 are arbitrary and are adjusted according to the dielectric strength (dielectric breakdown voltage) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layer 57 are arbitrary and are not limited to any specific insulating material.

[0042] The semiconductor device 5 includes a first functional device 45 formed on the insulating layer 51. The first functional device 45 includes one or more (in this embodiment, more) transformers 21 (corresponding to the transformers mentioned earlier). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed in the inner part of the insulating layer 51, spaced apart from the insulating side walls 53A to 53D. The multiple transformers 21 are formed spaced apart in the first direction X.

[0043] The multiple transformers 21 specifically include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating sidewall 53C to the insulating sidewall 53D in a plan view. The multiple transformers 21A to 21D each have a similar structure. The structure of the first transformer 21A will be used as an example below. The explanation of the structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D will be omitted, as the explanation of the structure of the first transformer 21A will be applied mutatis mutandis.

[0044] Referring to Figures 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed within the insulating layer 51. The high-potential coil 23 is formed within the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in the region sandwiched between the bottom insulating layer 55 and the top insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0045] The low-potential coil 22 is formed within the insulating layer 51 on the side of the bottom insulating layer 55 (semiconductor chip 41), and the high-potential coil 23 is formed within the insulating layer 51 on the side of the top insulating layer 56 (main insulating surface 52) relative to the low-potential coil 22. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 in between. The placement of the low-potential coil 22 and the high-potential coil 23 is arbitrary. Furthermore, the high-potential coil 23 only needs to face the low-potential coil 22 with one or more interlayer insulating layers 57 in between.

[0046] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of interlayer insulating layer 57) is appropriately adjusted according to the dielectric breakdown voltage and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this configuration, the low-potential coil 22 is formed in the third interlayer insulating layer 57 counting from the bottom insulating layer 55. In this configuration, the high-potential coil 23 is formed in the first interlayer insulating layer 57 counting from the top insulating layer 56.

[0047] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first helical portion 26 that is spirally routed between the first inner end 24 and the first outer end 25. The first helical portion 26 is spirally routed in an elliptical (long oval) shape in plan view. The portion forming the innermost periphery of the first helical portion 26 defines an elliptical first inner region 66 in plan view.

[0048] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the first helical portion 26 is 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in the direction perpendicular to the helical direction. The first turn pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the first turn pitch is 1 μm or more and 3 μm or less. The first turn pitch is defined by the distance between two adjacent portions in the first helical portion 26 in the direction perpendicular to the helical direction.

[0049] The winding shape of the first helical portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the forms shown in Figure 5, etc. The first helical portion 26 may be wound in a polygonal shape such as a triangle or a square, or in a circular shape in a plan view. The first inner region 66 may be divided into a polygonal shape such as a triangle or a square, or in a circular shape in a plan view, depending on the winding shape of the first helical portion 26.

[0050] The low-potential coil 22 may contain at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a laminated structure including a barrier layer and a main body layer. The barrier layer partitions a recess space within the interlayer insulating layer 57. The barrier layer may contain at least one of titanium and titanium nitride. The main body layer may contain at least one of copper, aluminum, and tungsten.

[0051] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second helical portion 29 that is spirally routed between the second inner end 27 and the second outer end 28. The second helical portion 29 is spirally routed in an elliptical (oval) shape in plan view. In this embodiment, the portion forming the innermost periphery of the second helical portion 29 defines an elliptical second inner region 67 in plan view. The second inner region 67 of the second helical portion 29 faces the first inner region 66 of the first helical portion 26 in the normal direction Z.

[0052] The number of turns of the second helical section 29 may be between 5 and 30. The number of turns of the second helical section 29 relative to the number of turns of the first helical section 26 is adjusted according to the voltage value to be boosted. It is preferable that the number of turns of the second helical section 29 exceeds the number of turns of the first helical section 26. Of course, the number of turns of the second helical section 29 may be less than the number of turns of the first helical section 26, or it may be equal to the number of turns of the first helical section 26.

[0053] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the second helical portion 29 is 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in the direction perpendicular to the helical direction. Preferably, the width of the second helical portion 29 is equal to the width of the first helical portion 26.

[0054] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the second winding pitch is 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions in the second helical portion 29 in a direction perpendicular to the helical direction. Preferably, the second winding pitch is equal to the first winding pitch of the first helical portion 26.

[0055] The winding shape of the second helical portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the forms shown in Figure 6, etc. The second helical portion 29 may be wound in a polygonal shape such as a triangle or a square, or in a circular shape in a plan view. The second inner region 67 may be divided into a polygonal shape such as a triangle or a square, or in a circular shape in a plan view, depending on the winding shape of the second helical portion 29.

[0056] It is preferable that the high-potential coil 23 is formed from the same conductive material as the low-potential coil 22. In other words, it is preferable that the high-potential coil 23 includes a barrier layer and a main body layer, similar to the low-potential coil 22.

[0057] Referring to Figure 4, the semiconductor device 5 includes a plurality (12 in this figure) of low-potential terminals 11 and a plurality (12 in this figure) of high-potential terminals 12. The plurality of low-potential terminals 11 are electrically connected to the low-potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high-potential terminals 12 are electrically connected to the high-potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0058] Multiple low-potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the multiple low-potential terminals 11 are formed in the region on the insulating side wall 53B side, spaced apart in the second direction Y from the multiple transformers 21A to 21D, and are arranged with spacing in the first direction X.

[0059] The multiple low-potential terminals 11 include a first low-potential terminal 11A, a second low-potential terminal 11B, a third low-potential terminal 11C, a fourth low-potential terminal 11D, a fifth low-potential terminal 11E, and a sixth low-potential terminal 11F. In this configuration, two of each of the multiple low-potential terminals 11A to 11F are formed. The number of multiple low-potential terminals 11A to 11F is arbitrary.

[0060] The first low-potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low-potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low-potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low-potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low-potential terminal 11E is formed in the region between the first low-potential terminal 11A and the second low-potential terminal 11B in a plan view. The sixth low-potential terminal 11F is formed in the region between the third low-potential terminal 11C and the fourth low-potential terminal 11D in a plan view.

[0061] The first low-potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low-potential coil 22). The second low-potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low-potential coil 22). The third low-potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low-potential coil 22). The fourth low-potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low-potential coil 22).

[0062] The fifth low-potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22). The sixth low-potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low-potential coil 22) and the first outer end 25 of the fourth transformer 21D (low-potential coil 22).

[0063] Multiple high-potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51, spaced apart from multiple low-potential terminals 11. Specifically, the multiple high-potential terminals 12 are formed in the region on the insulating side wall 53A side, spaced apart in the second direction Y from the multiple low-potential terminals 11, and are arranged with spacing in the first direction X.

[0064] Multiple high-potential terminals 12 are each formed in a region adjacent to the corresponding transformers 21A to 21D in a plan view. The proximity of the high-potential terminals 12 to the transformers 21A to 21D means that, in a plan view, the distance between the high-potential terminals 12 and the transformer 21 is less than the distance between the low-potential terminals 11 and the high-potential terminals 12.

[0065] Specifically, the multiple high-potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D in a plan view. More specifically, the multiple high-potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high-potential coil 23 and in the region between adjacent high-potential coils 23 in a plan view. As a result, the multiple high-potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0066] The multiple high-potential terminals 12 include a first high-potential terminal 12A, a second high-potential terminal 12B, a third high-potential terminal 12C, a fourth high-potential terminal 12D, a fifth high-potential terminal 12E, and a sixth high-potential terminal 12F. In this configuration, two of each of the multiple high-potential terminals 12A to 12F are formed. The number of multiple high-potential terminals 12A to 12F is arbitrary.

[0067] The first high-potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high-potential coil 23) in a plan view. The second high-potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high-potential coil 23) in a plan view. The third high-potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high-potential coil 23) in a plan view. The fourth high-potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high-potential coil 23) in a plan view. The fifth high-potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high-potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0068] The first high-potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high-potential coil 23). The second high-potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high-potential coil 23). The third high-potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high-potential coil 23). The fourth high-potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high-potential coil 23).

[0069] The fifth high-potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23). The sixth high-potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high-potential coil 23) and the second outer end 28 of the fourth transformer 21D (high-potential coil 23).

[0070] Referring to Figures 5 to 7, the semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34, each formed within the insulating layer 51. In this embodiment, a plurality of first low-potential wirings 31, a plurality of second low-potential wirings 32, a plurality of first high-potential wirings 33, and a plurality of second high-potential wirings 34 are formed.

[0071] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. Furthermore, the first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this configuration, the first low-potential wiring 31 and the second low-potential wiring 32 fix all the low-potential coils 22 of transformers 21A to 21D to the same potential.

[0072] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. Furthermore, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this configuration, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of transformers 21A to 21D to the same potential.

[0073] Multiple first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. Multiple first low-potential wirings 31 have similar structures. Below, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. For descriptions of the structures of other first low-potential wirings 31, the description of the structure of the first low-potential wiring 31 connected to the first transformer 21A will be applied mutatis mutandis, and the description will be omitted.

[0074] The first low-potential wiring 31 includes a through-wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (in this embodiment, multiple) pad plug electrodes 76, and one or more (in this embodiment, multiple) substrate plug electrodes 77.

[0075] It is preferable that the through-wiring 71, low-potential connection wiring 72, lead-out wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, it is preferable that the through-wiring 71, low-potential connection wiring 72, lead-out wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0076] The through-wiring 71 penetrates multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this configuration, the through-wiring 71 is formed in the region between the lowest insulating layer 55 and the uppermost insulating layer 56 in the insulating layer 51. The through-wiring 71 has an upper end on the side of the uppermost insulating layer 56 and a lower end on the side of the lowest insulating layer 55. The upper end of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0077] In this embodiment, the through-wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through-wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. That is, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The first electrode layer 78 forms the upper end of the through-wiring 71. The second electrode layer 79 forms the lower end of the through-wiring 71. The first electrode layer 78 is formed in an island shape and faces the low-potential terminal 11 (first low-potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0079] Multiple wiring plug electrodes 80 are embedded in multiple interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the bottom insulating layer 55 to the top insulating layer 56 so as to be electrically connected to each other, and also electrically connect the first electrode layer 78 and the second electrode layer 79. Each of the multiple wiring plug electrodes 80 has a planar area less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0080] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this configuration, six wiring plug electrodes 80 are embedded within each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded within each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating multiple interlayer insulating layers 57.

[0081] The low-potential connection wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) within the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connection wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. It is preferable that the low-potential connection wiring 72 has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connection wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0082] The lead wire 73 is formed in the region between the semiconductor chip 41 and the through-wiring 71 within the interlayer insulating layer 57. In this embodiment, the lead wire 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead wire 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first and second ends. The first end of the lead wire 73 is located in the region between the semiconductor chip 41 and the lower end of the through-wiring 71. The second end of the lead wire 73 is located in the region between the semiconductor chip 41 and the low-potential connection wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip-like manner in the region between the first and second ends.

[0083] The first connecting plug electrode 74 is formed in the region between the through-wiring 71 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the first ends of the through-wiring 71 and the lead-out wiring 73. The second connecting plug electrode 75 is formed in the region between the low-potential connecting wiring 72 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the second ends of the low-potential connecting wiring 72 and the lead-out wiring 73.

[0084] Multiple pad plug electrodes 76 are formed in the region between the low-potential terminal 11 (first low-potential terminal 11A) and the through-wiring 71 within the uppermost insulating layer 56, and are electrically connected to the upper ends of the low-potential terminal 11 and the through-wiring 71, respectively. Multiple substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the lead-out wiring 73 within the lowermost insulating layer 55. In this embodiment, the substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the first end of the lead-out wiring 73, and are electrically connected to the first end of the semiconductor chip 41 and the lead-out wiring 73, respectively.

[0085] Referring to Figures 6 and 7, the multiple first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A to 12D and the second inner ends 27 of the corresponding transformers 21A to 21D (high-potential coils 23), respectively. The multiple first high-potential wirings 33 each have a similar structure. Below, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. For descriptions of the structures of the other first high-potential wirings 33, the description of the structure of the first high-potential wiring 33 connected to the first transformer 21A will be applied mutatis mutandis, and the descriptions will be omitted.

[0086] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, more) pad plug electrodes 82. Preferably, the high-potential connection wiring 81 and the pad plug electrodes 82 are formed of the same conductive material as the low-potential coil 22, etc. That is, preferably, the high-potential connection wiring 81 and the pad plug electrodes 82 include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0087] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. In a plan view, the high-potential connection wiring 81 is formed at a distance from the low-potential connection wiring 72 and does not face the low-potential connection wiring 72 in the normal direction Z. As a result, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the dielectric strength of the insulating layer 51 is enhanced.

[0088] Multiple pad plug electrodes 82 are formed within the uppermost insulating layer 56 in the region between the high-potential terminal 12 (first high-potential terminal 12A) and the high-potential connection wiring 81, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively. Each of the multiple pad plug electrodes 82 has a planar area less than the planar area of ​​the high-potential connection wiring 81 in a plan view.

[0089] Referring to FIG. 7, it is preferable that the distance D1 between the low potential terminal 11 and the high potential terminal 12 exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2 < D1). It is preferable that the distance D1 exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the required breakdown voltage.

[0090] Referring to FIGS. 6 and 7, the semiconductor device 5 includes dummy patterns 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0091] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high potential coil 23 and the low potential coil 22 and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low potential coil 22 and the high potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high potential coil 23. In this form, the dummy pattern 85 is routed with a line density equal to the line density of the high potential coil 23 per unit area. That the line density of the dummy pattern 85 is equal to the line density of the high potential coil 23 means that the line density of the dummy pattern 85 falls within the range of ±20% of the line density of the high potential coil 23.

[0092] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the dummy pattern 85 is formed in a region adjacent to the high-potential coil 23 with respect to the low-potential coil 22 with respect to the normal direction Z. Note that when we say that the dummy pattern 85 is adjacent to the high-potential coil 23 with respect to the normal direction Z, it means that the distance between the dummy pattern 85 and the high-potential coil 23 is less than the distance between the dummy pattern 85 and the low-potential coil 22 with respect to the normal direction Z.

[0093] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 with respect to the normal direction Z, the more effectively electric field concentration on the high-potential coil 23 can be suppressed. It is preferable that the dummy pattern 85 is formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be suppressed even more effectively. The dummy pattern 85 includes a plurality of dummy patterns with different electrical states. The dummy pattern 85 may also include a high-potential dummy pattern.

[0094] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the high-potential dummy pattern 86 is formed in a region adjacent to the high-potential coil 23 with respect to the normal direction Z relative to the low-potential coil 22. The high-potential dummy pattern 86 being adjacent to the high-potential coil 23 with respect to the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22 with respect to the normal direction Z.

[0095] The dummy pattern 85 includes a floating dummy pattern formed electrically in a floating state within the insulating layer 51 so as to be located around the transformers 21A to 21D.

[0096] In this embodiment, the floating dummy pattern is routed in a dense linear fashion so as to partially cover and partially expose the area surrounding the high-potential coil 23 in a plan view. The floating dummy pattern may be formed with ends or without ends.

[0097] The depth position of the floating dummy pattern within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated.

[0098] The number of floating lines is arbitrary and is adjusted according to the electric field to be mitigated. A floating dummy pattern may consist of multiple floating lines.

[0099] Referring to Figure 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using the surface layer of the first main surface 42 of the semiconductor chip 41 and / or the region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (bottom insulating layer 55). In Figure 7, the second functional device 60 is simplified by dashed lines shown on the surface layer of the first main surface 42.

[0100] The second functional device 60 is electrically connected to the low-potential terminal 11 via low-potential wiring and to the high-potential terminal 12 via high-potential wiring. The low-potential wiring has the same structure as the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 to connect to the second functional device 60. The high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 to connect to the second functional device 60. A detailed explanation of the low-potential and high-potential wiring related to the second functional device 60 is omitted.

[0101] The second functional device 60 may include at least one of a passive device, a semiconductor rectifier device, and a semiconductor switching device. The second functional device 60 may include a circuit network in which any two or more devices from among the passive device, semiconductor rectifier device, and semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0102] Passive devices may include semiconductor passive devices. Passive devices may include either a resistor or a capacitor, or both. Semiconductor rectifier devices may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. Semiconductor switching devices may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0103] Referring to Figures 5 to 7, the semiconductor device 5 further includes a sealing conductor 61 embedded in the insulating layer 51. In a plan view, the sealing conductor 61 is embedded in the insulating layer 51 in a wall-like manner, spaced apart from the insulating side walls 53A to 53D, and divides the insulating layer 51 into a device region 62 and an outer region 63. The sealing conductor 61 suppresses the intrusion of moisture and cracks from the outer region 63 into the device region 62.

[0104] The device region 62 is the region that includes the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. The outer region 63 is the region outside the device region 62.

[0105] The sealing conductor 61 is electrically isolated from the device region 62. Specifically, the sealing conductor 61 is electrically isolated from the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. More specifically, the sealing conductor 61 is electrically suspended. The sealing conductor 61 does not form a current path that connects to the device region 62.

[0106] In a plan view, the sealing conductor 61 is formed in a strip shape along the insulating side walls 53-53D. In this configuration, the sealing conductor 61 is formed in a rectangular ring shape (specifically, a rectangular ring shape) in a plan view. As a result, the sealing conductor 61 demarcates a rectangular (specifically, rectangular) device region 62 in a plan view. Furthermore, the sealing conductor 61 demarcates the outer rectangular ring (specifically, a rectangular ring shape) region 63 surrounding the device region 62 in a plan view.

[0107] Specifically, the seal conductor 61 has an upper end on the insulating main surface 52 side, a lower end on the semiconductor chip 41 side, and a wall portion extending wall-like between the upper end and the lower end. In this embodiment, the upper end of the seal conductor 61 is formed with a gap from the insulating main surface 52 toward the semiconductor chip 41 side and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed with a gap from the semiconductor chip 41 toward the upper end side.

[0108] Thus, in this embodiment, the sealing conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side relative to the multiple low-potential terminals 11 and the multiple high-potential terminals 12. Furthermore, within the insulating layer 51, the sealing conductor 61 faces the first functional device 45 (multiple transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating main surface 52. Within the insulating layer 51, the sealing conductor 61 may also face a portion of the second functional device 60 in a direction parallel to the insulating main surface 52.

[0109] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, multiple) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 of the plurality of seal plug conductors 64 forms the upper end of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end of the seal conductor 61. It is preferable that the seal plug conductors 64 and seal via conductors 65 are made of the same conductive material as the low-potential coil 22. That is, it is preferable that the seal plug conductors 64 and seal via conductors 65 include a barrier layer and a body layer, similar to the low-potential coil 22, etc.

[0110] Multiple seal plug conductors 64 are embedded in multiple interlayer insulating layers 57, and in a plan view, they are each formed in a rectangular ring (specifically, a rectangular ring) surrounding the device region 62. Multiple seal plug conductors 64 are stacked from the bottom insulating layer 55 toward the top insulating layer 56 so as to be connected to each other. The number of stacked seal plug conductors 64 corresponds to the number of stacked interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0111] If a single annular seal conductor 61 is formed by an assembly of multiple seal plug conductors 64, it is not necessary for all of the multiple seal plug conductors 64 to be formed in an annular shape. For example, at least one of the multiple seal plug conductors 64 may be formed with ends. Alternatively, at least one of the multiple seal plug conductors 64 may be divided into multiple end-shaped strips. However, considering the risk of moisture and cracks entering the device region 62, it is preferable that the multiple seal plug conductors 64 be formed in an endless (annular) shape.

[0112] Multiple seal via conductors 65 are formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the bottom insulating layer 55. The multiple seal via conductors 65 are formed at intervals from the semiconductor chip 41 and connected to the seal plug conductor 64. The multiple seal via conductors 65 have a planar area less than the planar area of ​​the seal plug conductor 64. If a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area greater than or equal to the planar area of ​​the seal plug conductor 64.

[0113] The width of the seal conductor 61 may be 0.1 μm or more and 10 μm or less. Preferably, the width of the seal conductor 61 is 1 μm or more and 5 μm or less. The width of the seal conductor 61 is defined by the width in the direction perpendicular to the direction in which the seal conductor 61 extends.

[0114] Referring to Figures 7 and 8, the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the sealing conductor 61, which electrically isolates the sealing conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 consists of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0115] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). Preferably, the field insulating film 131 consists of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidation of the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0116] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a rectangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion to which the lower end (seal via conductor 65) of the seal conductor 61 bites toward the semiconductor chip 41 side. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0117] The separation structure 130 includes an inner end portion 130A on the device region 62 side, an outer end portion 130B on the outer region 63 side, and a main body portion 130C between the inner end portion 130A and the outer end portion 130B. The inner end portion 130A demarcates the region where the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end portion 130A may be integrally formed with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0118] The outer end portion 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is connected to the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end portion 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end portion 130B forms a flush grinding surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end portion 130B may be formed within the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0119] The main body portion 130C has a flat surface that extends substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body portion 130C has a connection portion 132 to which the lower end (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in the main body portion 130C at a distance from the inner end portion 130A and the outer end portion 130B. The separation structure 130 can take various forms other than the field insulating film 131.

[0120] Referring to Figure 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating main surface 52 of the insulating layer 51 to cover the seal conductor 61. The inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating main surface 52.

[0121] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. Preferably, the first inorganic insulating layer 141 contains USG (undopped silicate glass), which is silicon oxide without impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength on the high-potential coil 23 can be increased.

[0122] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the dielectric breakdown voltage (V / cm) of USG exceeds the dielectric breakdown voltage (V / cm) of silicon nitride. Therefore, when thickening the inorganic insulating layer 140, it is preferable to form the first inorganic insulating layer 141 which is thicker than the second inorganic insulating layer 142.

[0123] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass) as examples of silicon oxide. However, in this case, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable that the first inorganic insulating layer 141 be made of USG in order to increase the dielectric strength on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure consisting of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0124] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61 and has a plurality of low-potential pad openings 143 and a plurality of high-potential pad openings 144 formed in the area outside the seal conductor 61. The plurality of low-potential pad openings 143 expose a plurality of low-potential terminals 11, respectively. The plurality of high-potential pad openings 144 expose a plurality of high-potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that ride up over the periphery of the low-potential terminals 11. The inorganic insulating layer 140 may also have overlapping portions that ride up over the periphery of the high-potential terminals 12.

[0125] The semiconductor device 5 further includes an organic insulating layer 145 formed on an inorganic insulating layer 140. The organic insulating layer 145 may contain a photosensitive resin. The organic insulating layer 145 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 contains polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0126] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably greater than or equal to the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Also, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. With these structures, the thickness of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, and at the same time, the dielectric strength on the high-potential coil 23 can be appropriately increased by the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145.

[0127] The organic insulating layer 145 includes a first portion 146 that covers the low-potential region and a second portion 147 that covers the high-potential region. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 in between. The first portion 146 has a plurality of low-potential terminal openings 148 that expose a plurality of low-potential terminals 11 (low-potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have overlapping portions that ride up on the periphery (overlap portion) of the low-potential pad openings 143.

[0128] The second portion 147 is formed at a distance from the first portion 146, exposing the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose a plurality of high-potential terminals 12 (high-potential pad openings 144). The second portion 147 may have overlapping portions that ride up on the periphery (overlap portion) of the high-potential pad openings 144.

[0129] The second section 147 covers the transformers 21A to 21D and the dummy pattern 85 together. Specifically, the second section 147 covers the multiple high-potential coils 23, the multiple high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121 together.

[0130] Embodiments of the present disclosure can be implemented in other forms. In the embodiments described above, an example was given in which a first functional device 45 and a second functional device 60 are formed. However, a form may be adopted in which only the second functional device 60 is present, without the first functional device 45. In this case, the dummy pattern 85 may be removed. With this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0131] In other words, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, unwanted conduction between the high-potential terminal 12 and the sealing conductor 61 can be suppressed.

[0132] Furthermore, the above-described embodiment described an example in which a second functional device 60 is formed. However, the second functional device 60 is not necessarily required and may be removed.

[0133] Furthermore, the above-described embodiment described an example in which a dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0134] Furthermore, in the embodiments described above, an example was given in which the first functional device 45 consists of a multi-channel type including multiple transformers 21. However, a first functional device 45 consisting of a single-channel type including a single transformer 21 may also be employed.

[0135] <Trans arrangement> Figure 9 is a schematic plan view (top view) showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the semiconductor device 5 mentioned earlier). The transformer chip 300 in this figure includes a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0136] In the transformer chip 300, pads a1 and b1 are connected to one end of the secondary coil L1s that forms the first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of the secondary coil L2s that forms the second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0137] Furthermore, pads a3 and b3 are connected to one end of the secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of the secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0138] Note that the primary coils forming the first transformer 301, the second transformer 302, the third transformer 303, and the fourth transformer 304 are not explicitly shown in this figure. However, each primary coil basically has the same configuration as the secondary coils L1s to L4s, and is positioned directly below each of the secondary coils L1s to L4s, facing them respectively.

[0139] Specifically, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Similarly, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0140] Furthermore, pads a7 and b7 are connected to one end of the primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Similarly, pads a8 and b8 are connected to one end of the primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0141] However, pads a5-a8, b5-b8, c3 and c4, and d3 and d4 are led from the inside of the trans tip 300 to the surface via vias (not shown).

[0142] Of the above multiple pads, pads a1 to a8 correspond to the first current supply pads, pads b1 to b8 correspond to the first voltage measurement pads, pads c1 to c4 correspond to the second current supply pads, and pads d1 to d4 correspond to the second voltage measurement pads.

[0143] Therefore, with the transformer chip 300 in this configuration example, the series resistance component of each coil can be accurately measured during defective product inspection. Consequently, it becomes possible to appropriately reject not only defective products with open circuits in each coil, but also defective products with abnormal resistance values ​​in each coil (for example, short circuits between coils), and ultimately, to prevent defective products from reaching the market.

[0144] Furthermore, for the transformer chip 300 that has passed the above-mentioned defect inspection, the multiple pads can be used as means of connecting to the primary chip and the secondary chip (for example, the controller chip 210 and driver chip 220 mentioned above).

[0145] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 should be connected to the signal input terminal or signal output terminal of the secondary chip, respectively. Also, pads c1 and d1, and pads c2 and d2 should be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0146] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 should be connected to the signal input terminal or signal output terminal of the primary chip, respectively. Also, pads c3 and d3, and pads c4 and d4 should be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0147] Here, the first transformers 301 to the fourth transformers 304 are arranged in a coupled configuration according to their respective signal transmission directions, as shown in Figure 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary side chip to the secondary side chip, are connected as a first pair by the first guard ring 305. Similarly, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary side chip to the primary side chip, are connected as a second pair by the second guard ring 306.

[0148] The reason for this coupling is to ensure voltage resistance between the primary and secondary coils when the primary and secondary coils forming the first to fourth transformers 301 to 304 are stacked in the vertical direction on the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0149] The first guard ring 305 and the second guard ring 306 can be connected to low-impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0150] Furthermore, in the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between their respective primary coils. By adopting this configuration, it is possible to reduce the number of pads and miniaturize the transformer chip 300.

[0151] Furthermore, as shown in Figure 9, it is desirable that the primary and secondary coils forming the first to fourth transformers 301 to 304 be wound in a rectangular shape (or a track shape with rounded corners) when viewed from above the transformer tip 300. This configuration increases the area of ​​the overlapping portion between the primary and secondary coils, thereby improving the transmission efficiency of the transformer.

[0152] Of course, the transformer arrangement in this diagram is merely an example, and the number, shape, and placement of coils, as well as the placement of pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to semiconductor devices in general that integrate coils on a semiconductor chip.

[0153] <Insulated switch (comparative example)> Figure 10 shows a comparative example of the isolation switch 400 (an example of a circuit configuration to be compared with the embodiment described later). The isolation switch 400 in this comparative example transmits a pulse signal from the primary circuit system 400p to the secondary circuit system 400s while insulating the primary circuit system 400p (VCC-GND system) from the secondary circuit system 400s (PVDD-PGND system).

[0154] The isolation switch 400 may be mounted on electronic equipment A together with load ZL1 or ZL2. Electronic equipment A may be, for example, industrial machinery or automotive equipment. The isolation switch 400 may also be offered to the market as a semiconductor integrated circuit device (so-called isolation switch IC) formed by integrating it. The isolation switch 400 is also called an isolation relay.

[0155] The isolation switch 400 is provided with external terminals T1 to T5 as means for establishing an electrical connection with the outside of the device. External terminal T1 is connected to the application terminal of the power supply voltage VCC. External terminal T2 is connected to the application terminal of the input pulse signal DIN. External terminal T3 is connected to the application terminal of the ground voltage GND. External terminal T4 is connected to the application terminal of the power supply voltage PVDD directly or via the load ZL1. External terminal T5 is connected to the application terminal of the ground voltage PGND directly or via the load ZL2.

[0156] Furthermore, the isolation switch 400 includes a primary circuit 410, a secondary circuit 420, and an isolation circuit 430.

[0157] The primary circuit 410 is provided in the primary circuit system 400p. Referring to this figure, the primary circuit 410 includes a pulse generation circuit 411 and an oscillation circuit 412.

[0158] The pulse generation circuit 411 outputs a transmit pulse signal Vd to the first terminal of the isolation capacitor Ci in response to the input pulse signal DIN. The transmit pulse signal Vd may be pulse-driven, for example, between the power supply voltage VCC and the ground voltage GND.

[0159] The oscillator circuit 412 supplies a clock signal to the pulse generation circuit 411. The transmitted pulse signal Vd is pulse-driven in synchronization with the clock signal output from the oscillator circuit 412.

[0160] The secondary circuit 420 is provided in the secondary circuit system 400s. Referring to this figure, the secondary circuit 420 includes a switch drive circuit 421 and a switch circuit 422.

[0161] The switch drive circuit 421 generates a switch drive signal Vg in response to the received pulse signal V1. As shown in the figure, the switch drive circuit 421 includes diodes Dx and Dy, a capacitor Cg, and a discharge circuit 421X.

[0162] The anode of diode Dx and the cathode of diode Dy are connected to the application terminal of the received pulse signal V1. The cathode of diode Dx and the first terminals of capacitor Cg and discharge circuit 421X are all connected to the application terminal of the switch drive signal Vg. The anode of diode Dy and the second terminals of capacitor Cg and discharge circuit 421X are all connected to the reference node nd. Capacitor Cg may also be a parasitic capacitor associated between the gate and source of transistors M0a and M0b, which will be described later. Diodes Dx and Dy and capacitor Cg rectify and smooth the received pulse signal V1 to generate the switch drive signal Vg.

[0163] The switch circuit 422 is connected between external terminals T4 and T5 and is switched on / off by the switch drive signal Vg. External terminal T4 corresponds to the first node. External terminal T5 corresponds to the second node.

[0164] For example, the switch circuit 422 includes transistors M0a and M0b that conduct / block the connection between external terminals T4 and T5 in accordance with a switch drive signal Vg. Transistors M0a and M0b may be, for example, N-channel type MOS (metal oxide semiconductor) field-effect transistors.

[0165] The drain of transistor M0a is connected to external terminal T4. The drain of transistor M0b is connected to external terminal T5. The source and back gate of transistors M0a and M0b are both connected to the reference node nd. The gates of transistors M0a and M0b are both connected to the application terminal of the switch drive signal Vg. Transistors M0a and M0b can be understood as output transistors, each with its gate connected to the application terminal of the switch drive signal Vg.

[0166] In the first connection configuration, the external terminal T4 may be connected to the application terminal of the power supply voltage PVDD via the load ZL1, and the external terminal T5 may be directly connected to the application terminal of the ground voltage PGND. In this case, the switch circuit 422 functions as a lower switch (sink output type).

[0167] In the second connection configuration, the external terminal T5 may be connected to the application terminal of the ground voltage PGND via the load ZL2, and the external terminal T4 may be directly connected to the application terminal of the power supply voltage PVDD. In this case, the switch circuit 422 functions as an upper switch (source output type).

[0168] The isolation circuit 430 transmits the transmitted pulse signal Vd as the received pulse signal V1 while DC-isolating the pulse generation circuit 411 and the switch drive circuit 421. As shown in the figure, the isolation circuit 430 includes an isolation capacitor Ci.

[0169] The isolation capacitor Ci is connected between the pulse generation circuit 411 and the switch drive circuit 421. As shown in the figure, the first end of the isolation capacitor Ci is connected to the application terminal of the transmitted pulse signal Vd. The second end of the isolation capacitor Ci is connected to the application terminal of the received pulse signal V1.

[0170] Next, the basic operation of the isolation switch 400 will be explained. During the high-level period of the input pulse signal DIN, the transmit pulse signal Vd applied to the first terminal of the isolation capacitor Ci is pulse-driven. At this time, the received pulse signal V1 is transmitted to the second terminal of the isolation capacitor Ci. The received pulse signal V1 is rectified and smoothed, raising the switch drive signal Vg to a signal level higher than the on-threshold voltage Vth of transistors M0a and M0b. Consequently, transistors M0a and M0b are turned on, and a drive current can be supplied to the load ZL1 or ZL2.

[0171] On the other hand, during the low-level period of the input pulse signal DIN, the pulse drive of the transmitted pulse signal Vd is stopped. Consequently, the received pulse signal V1 becomes low level (≒PGND). At this time, the switch drive signal Vg is reduced to a signal level lower than the on-threshold voltage Vth of transistors M0a and M0b by the action of the discharge circuit 421X. As a result, transistors M0a and M0b are in the off state, and no drive current is supplied to the load ZL1 or ZL2.

[0172] The switch drive circuit 421 receives power through the isolation circuit 430. That is, the switch drive circuit 421 generates the switch drive signal Vg using the received pulse signal V1 transmitted through the isolation circuit 430 as its power source. Conversely, the switch drive circuit 421 can generate the switch drive signal Vg without receiving power from the secondary circuit system 400s.

[0173] Thus, the insulating switch 400 in this comparative example transmits a pulse signal from the primary circuit system 400p to the secondary circuit system 400s while insulating the primary circuit system 400p and the secondary circuit system 400s through capacitive coupling using an insulating capacitor Ci.

[0174] <Considerations on signal attenuation> Incidentally, a parasitic capacitor Cp may be present between the application terminal of the received pulse signal V1 (= input pad of the secondary circuit 420) and the external terminal T5. The capacitance value of the isolation capacitor Ci integrated in the isolation circuit 430 is generally smaller than the capacitance value of the parasitic capacitor Cp (for example, Ci = 0.1 pF, Cp = 1 pF). Therefore, the received pulse signal V1 may be transmitted attenuated significantly from the transmitted pulse signal Vd. For this reason, in the isolation switch 400 of this comparative example, it may be difficult to raise the switch drive signal Vg to a signal level higher than the on-threshold voltage Vth of transistors M0a and M0b, respectively.

[0175] Conventionally, DMOS (double-diffused MOS) devices or CMOS (complementary MOS) devices are widely used as transistors M0a and M0b. When the power supply voltage PVDD of the secondary circuit system 400s is around 10 to 40V, there are no particular problems with the above device selection.

[0176] However, in recent years, there has been a demand or application for applying high voltages of as high as 600V as the power supply voltage PVDD. The aforementioned DMOS or CMOS devices may not be able to withstand such high voltage applications. Therefore, in order to meet the above requirements, it is necessary to use devices with higher voltage resistance than DMOS or CMOS devices as transistors M0a and M0b, such as GaN devices such as GaN-HEMT [high electron mobility transistor] or SiC devices such as SiC-MOSFET.

[0177] However, the on-threshold voltage of GaN or SiC devices is higher than that of DMOS or CMOS devices. Therefore, a mechanism is needed to raise the high level of the switch drive signal Vg.

[0178] In light of the above considerations, the following embodiment is proposed in which transistors M0a and M0b can be reliably turned on even in a capacitively coupled configuration.

[0179] <Insulated switch (first embodiment)> Figure 11 shows a first embodiment of the insulated switch 400. In this embodiment of the insulated switch 400, modifications have been made to the pulse generation circuit 411, switch drive circuit 421, switch circuit 422, and insulation circuit 430, while being based on the comparative example (Figure 10). Therefore, in this figure, the differences from the comparative example (Figure 10) are depicted, and the depiction of common parts is omitted.

[0180] Referring to this figure, the pulse generation circuit 411 includes drivers 411a and 411b and a controller 411c.

[0181] The input terminal of the driver 411a is connected to the first output terminal of the controller 411c, i.e., the terminal to which the drive pulse Pa is applied. The output terminal of the driver 411a is connected to the first terminal of the isolation capacitor Cia. The driver 411a drives the isolation capacitor Cia in accordance with the drive pulse Pa. For example, when the drive pulse Pa is at a high level, the driver 411a sources current from the terminal to which the power supply voltage VCC is applied to the isolation capacitor Cia. Conversely, when the drive pulse Pa is at a low level, the driver 411a sinks current from the isolation capacitor Cia to the terminal to which the ground voltage GND is applied.

[0182] The input terminal of driver 411b is connected to the second output terminal of controller 411c, i.e., the terminal to which the drive pulse Pb is applied. The output terminal of driver 411b is connected to the first terminal of isolation capacitor Cib. Driver 411b drives isolation capacitor Cib in response to the drive pulse Pb. For example, when the drive pulse Pb is high level, driver 411b sources current from the terminal to which the power supply voltage VCC is applied to isolation capacitor Cib. Conversely, when the drive pulse Pb is low level, driver 411b sinks current from isolation capacitor Cib to the terminal to which the ground voltage GND is applied.

[0183] The controller 411c generates drive pulses Pa and Pb in opposite phases. That is, when drive pulse Pa is high level (e.g., power supply voltage VCC or lower), drive pulse Pb is low level (e.g., ground voltage GND). Conversely, when drive pulse Pa is low level, drive pulse Pb is high level.

[0184] The switch drive circuit 421 rectifies and smooths the drive pulses Ia and Ib transmitted through the insulating capacitors Cia and Cib to generate the switch drive signal Vg. As shown in the figure, the switch drive circuit 421 includes diodes D1 to D8, capacitors C1, C2 and Co, and a discharge circuit 421X.

[0185] The cathode of diode D1 and the anode of diode D2 are connected to the second terminal of the insulating capacitor Cia. The anode of diode D1 is connected to the reference node nd. The cathode of diode D2 is connected to the terminal to which the node voltage Va is applied. Diodes D1 and D2 form a rectifier circuit 421a that generates the node voltage Va from the drive pulse Ia transmitted through the insulating capacitor Cia. Diode D1 corresponds to a first rectifier element connected between the insulating capacitor Cia and the reference node nd. Diode D2 corresponds to a second rectifier element connected between the insulating capacitor Cia and the terminal to which the node voltage Va is applied.

[0186] The cathode of diode D3 and the anode of diode D4 are connected to the second terminal of the isolation capacitor Cib. The anode of diode D3 is connected to the reference node nd. The cathode of diode D4 is connected to the terminal to which the node voltage Va is applied. Diodes D3 and D4 form a rectifier circuit 421b that generates the node voltage Va from the drive pulse Ib transmitted through the isolation capacitor Cib. Diode D3 corresponds to a third rectifier element connected between the isolation capacitor Cib and the reference node nd. Diode D4 corresponds to a fourth rectifier element connected between the isolation capacitor Cib and the terminal to which the node voltage Va is applied.

[0187] The cathode of diode D5 and the anode of diode D6 are connected to the first terminal of capacitor C1. The second terminal of capacitor C1 is connected to the second terminal of insulating capacitor Cia. The anode of diode D5 is connected to the terminal to which the node voltage Va is applied. The cathode of diode D6 is connected to the terminal to which the switch drive signal Vg is applied. Diodes D5 and D6 and capacitor C1 form a rectifier circuit 421c that generates the switch drive signal Vg from the drive pulse Ia transmitted through insulating capacitor Cia. Diode D5 corresponds to a fifth rectifier element connected between insulating capacitor Cia and the terminal to which the node voltage Va is applied. Diode D6 corresponds to a sixth rectifier element connected between insulating capacitor Cia and the terminal to which the switch drive signal Vg is applied. Capacitor C1 functions as a first DC-blocking capacitor connected between insulating capacitor Cia and diodes D5 and D6.

[0188] The cathode of diode D7 and the anode of diode D8 are connected to the first terminal of capacitor C2. The second terminal of capacitor C2 is connected to the second terminal of insulating capacitor Cib. The anode of diode D7 is connected to the terminal to which the node voltage Va is applied. The cathode of diode D8 is connected to the terminal to which the switch drive signal Vg is applied. Diodes D7 and D8 and capacitor C2 form a rectifier circuit 421d that generates the switch drive signal Vg from the drive pulse Ib transmitted through insulating capacitor Cib. Diode D7 corresponds to a seventh rectifier element connected between insulating capacitor Cib and the terminal to which the node voltage Va is applied. Diode D8 corresponds to an eighth rectifier element connected between insulating capacitor Cib and the terminal to which the switch drive signal Vg is applied. Capacitor C2 functions as a second DC-blocking capacitor connected between insulating capacitor Cib and diodes D7 and D8.

[0189] Thus, in the isolation switch 400 of this embodiment, the rectifier circuits 421c and 421d are connected in tandem to the output terminals of the rectifier circuits 421a and 421b, respectively, i.e., to the terminals to which the node voltage Va is applied. Therefore, the switch drive circuit 421 can obtain a switch drive signal Vg that is higher than the node voltage Va. Consequently, it is possible to reliably turn on the transistor M0 even if it is a GaN device or a SiC device.

[0190] Capacitor Co is connected between the application terminal of the node voltage Va and the reference node nd. The reference node nd is connected to the external terminal T5. Capacitor Co functions as an output capacitor that smooths the node voltage Va.

[0191] The discharge circuit 421X is connected between the terminal to which the switch drive signal Vg is applied and the terminal to which the ground voltage PGND is applied, just as in the comparative example (Figure 10) described earlier.

[0192] The switch circuit 422 includes transistor M0 instead of the previously mentioned transistors M0a and M0b. Transistor M0 may be, for example, an N-channel type. The drain of transistor M0 is connected to external terminal T4. The source of transistor M0 is connected to external terminal T5. The gate of transistor M0 is connected to the application terminal of the switch drive signal Vg. Thus, the output transistor forming the switch circuit 422 may be a single element.

[0193] The insulating capacitor Cia provides insulation between the pulse generation circuit 411 and the switch drive circuit 421, while transmitting the drive pulse Pa generated by the pulse generation circuit 411 as a drive pulse Ia to the switch drive circuit 421.

[0194] The insulating capacitor Cib provides insulation between the pulse generation circuit 411 and the switch drive circuit 421, while transmitting the drive pulse Pb generated by the pulse generation circuit 411 as a drive pulse Ib to the switch drive circuit 421.

[0195] Incidentally, the drive pulses Ia and Ib, which are current signals, frequently switch between positive and negative current directions. The positive direction can be defined as the direction from the primary circuit system 400p through the insulating capacitors Cia and Cib to the secondary circuit system 400s. On the other hand, the negative direction can be defined as the direction from the secondary circuit system 400s through the insulating capacitors Cia and Cib to the primary circuit system 400p.

[0196] However, as mentioned above, the drive pulses Ia and Ib are driven in opposite phases. That is, when drive pulse Ia flows in the positive direction, drive pulse Ib flows in the negative direction. Conversely, when drive pulse Ia flows in the negative direction, drive pulse Ib flows in the positive direction. Therefore, the sum of the currents of drive pulses Ia and Ib is ideally always zero. Consequently, fluctuations in the current flowing through capacitor Co are suppressed, and thus radiated noise can be reduced.

[0197] <Insulated switch (second embodiment)> Figure 12 shows a second embodiment of the insulated switch 400. In the insulated switch 400 of this embodiment, the switch drive circuit 421 is based on the first embodiment (Figure 11) described above, but includes a clamp circuit 421Y.

[0198] In this diagram, the rectifier circuits 421c and 421d, which are not essential for the introduction of the clamp circuit 421Y, have been omitted in order to focus on the clamp circuit 421Y. That is, the cathodes of diodes D2 and D4 are connected to the application terminals of the switch drive signal Vg. Therefore, the node voltage Va mentioned earlier corresponds to the switch drive signal Vg.

[0199] The clamp circuit 421Y limits the voltage generated at the application terminals of the drive pulses Ia and Ib. The clamp circuit 421Y can be understood as one of the CMTI (common mode transient immunity) countermeasures circuits.

[0200] Referring to this figure, the clamp circuit 421Y includes transistors Y1 and Y2, capacitors Y3 and Y4, resistors Y5 and Y6, and diodes Y7 and Y8.

[0201] The drain of transistor Y1 is connected to the second terminal of the insulating capacitor Cia. The source of transistor Y1 is connected to the reference node nd. Capacitor Y3 is connected between the gate of transistor Y1 and the second terminal of the insulating capacitor Cib. Resistor Y5 and diode Y7 are connected in parallel between the gate of transistor Y1 and the reference node nd. Transistor Y1, connected in this manner, functions as a first discharge element that conducts / blocks between the application terminal of the drive pulse Ia and the reference node nd in response to the drive pulse Ib. Transistor Y1 functions similarly to the diode D1 mentioned earlier. However, when a surge is introduced into the ground voltage GND, the parasitic diode associated with transistor Y1 functions similarly to diode D1.

[0202] The drain of transistor Y2 is connected to the second terminal of the insulating capacitor Cib. The source of transistor Y2 is connected to the reference node nd. Capacitor Y4 is connected between the gate of transistor Y2 and the second terminal of the insulating capacitor Cia. Resistor Y6 and diode Y8 are connected in parallel between the gate of transistor Y2 and the reference node nd. Transistor Y2, connected in this manner, functions as a second discharge element that conducts / blocks between the application terminal of the drive pulse Ib and the reference node nd in response to the drive pulse Ia. Transistor Y2 functions similarly to the diode D3 mentioned earlier. However, when a surge is introduced into the ground voltage GND, the parasitic diode associated with transistor Y2 functions similarly to diode D3.

[0203] When a positive surge is superimposed on the ground voltage GND of the primary circuit system 400pF, the voltage applied to the first terminals of the insulating capacitors Cia and Cib jumps relative to the ground voltage PGND of the secondary circuit system 400sF. Consequently, due to the capacitive coupling of the insulating capacitors Cia and Cib, the voltage applied to the second terminals of the insulating capacitors Cia and Cib also jumps.

[0204] If the clamp circuit 421Y is not installed, an excessive current will flow from the second terminals of the isolation capacitors Cia and Cib towards the gate of transistor M0. As a result, transistor M0 may unintentionally turn on.

[0205] On the other hand, when the clamp circuit 421Y is introduced, the voltage applied to the gates of transistors Y1 and Y2 increases as the voltage applied to the second terminals of the insulating capacitors Cia and Cib increases. Consequently, both transistors Y1 and Y2 turn ON. At this time, current flows from the second terminals of the insulating capacitors Cia and Cib through transistors Y1 and Y2 to the reference node nd. As a result, the increase in the voltage applied to the second terminals of the insulating capacitors Cia and Cib can be suppressed.

[0206] Furthermore, if a negative surge is superimposed on the ground voltage GND of the primary circuit system 400pF, the voltage applied to the second terminals of the isolation capacitors Cia and Cib can be clamped by the forward-biased diodes D1 and D2.

[0207] <Insulated switch (third embodiment)> Figure 13 shows a third embodiment of the isolation switch 400. In the isolation switch 400 of this embodiment, the switch drive circuit 421 is based on the first embodiment (Figure 11) but includes the clamp circuit 421Y of the second embodiment (Figure 12). The switch circuit 422 also includes transistors M0a and M0b as output transistors, as in the comparative example (Figure 10). Furthermore, the switch drive circuit 421 has been modified in the configuration of the rectifier circuits 421a, 421b, 421c, and 421d.

[0208] Referring to this figure, the switch drive circuit 421 includes transistors M1 to M8, capacitors C11 to C14 and C21 to C28, resistors R1 to R8, and diodes D11 to D18, instead of the previously mentioned diodes D1 to D8 and capacitors C1 and C2. Transistors M1, M3, M5, and M7 may be, for example, N-channel type. Transistors M2, M4, M6, and M8 may be, for example, P-channel type.

[0209] The drains of transistors M1 and M2 are connected to the first terminal of capacitor C11. The second terminal of capacitor C11 is connected to the second terminal of insulating capacitor Cia. The source of transistor M1 is connected to the reference node nd. The source of transistor M2 is connected to the terminal where the node voltage Va is applied. Transistors M1 and M2 form a rectifier circuit 421a that generates the node voltage Va from the drive pulse Ia transmitted through the insulating capacitor Cia. Transistor M1 corresponds to a first rectifier element connected between the insulating capacitor Cia and the reference node nd. Transistor M2 corresponds to a second rectifier element connected between the insulating capacitor Cia and the terminal where the node voltage Va is applied. Capacitor C11 may be omitted.

[0210] The drains of transistors M3 and M4 are connected to the first terminal of capacitor C12. The second terminal of capacitor C12 is connected to the second terminal of insulating capacitor Cib. The source of transistor M3 is connected to the reference node nd. The source of transistor M4 is connected to the application terminal of the node voltage Va. Transistors M3 and M4 form a rectifier circuit 421b that generates the node voltage Va from the drive pulse Ib transmitted through the insulating capacitor Cib. Transistor M3 corresponds to a third rectifier element connected between the insulating capacitor Cib and the reference node nd. Transistor M4 corresponds to a fourth rectifier element connected between the insulating capacitor Cib and the application terminal of the node voltage Va. Capacitor C12 may be omitted.

[0211] The drains of transistors M5 and M6 are connected to the first terminal of capacitor C13. The second terminal of capacitor C13 is connected to the second terminal of insulating capacitor Cia. The source of transistor M5 is connected to the terminal where the node voltage Va is applied. The source of transistor M6 is connected to the terminal where the switch drive signal Vg is applied. Transistors M5 and M6 and capacitor C13 form a rectifier circuit 421c that generates the switch drive signal Vg from the drive pulse Ia transmitted through the insulating capacitor Cia. Transistor M5 corresponds to a fifth rectifier element connected between the insulating capacitor Cia and the terminal where the node voltage Va is applied. Transistor M6 corresponds to a sixth rectifier element connected between the insulating capacitor Cia and the terminal where the switch drive signal Vg is applied. Capacitor C13 functions as a first DC-blocking capacitor connected between the insulating capacitor Cia and transistors M5 and M6.

[0212] The drains of transistors M7 and M8 are connected to the first terminal of capacitor C14. The second terminal of capacitor C14 is connected to the second terminal of insulating capacitor Cib. The source of transistor M7 is connected to the terminal where the node voltage Va is applied. The source of transistor M8 is connected to the terminal where the switch drive signal Vg is applied. Transistors M7 and M8 and capacitor C14 form a rectifier circuit 421d that generates the switch drive signal Vg from the drive pulse Ib transmitted through insulating capacitor Cib. Transistor M7 corresponds to a seventh rectifier element connected between insulating capacitor Cib and the terminal where the node voltage Va is applied. Transistor M8 corresponds to an eighth rectifier element connected between insulating capacitor Cib and the terminal where the switch drive signal Vg is applied. Capacitor C14 functions as a second DC-blocking capacitor connected between insulating capacitor Cib and transistors M7 and M7.

[0213] Thus, in the isolation switch 400 of this embodiment, the rectifier circuits 421c and 421d are connected in tandem to the output terminals of the rectifier circuits 421a and 421b, respectively, i.e., to the terminals to which the node voltage Va is applied. Therefore, the switch drive circuit 421 can obtain a switch drive signal Vg that is higher than the node voltage Va. Consequently, it is possible to reliably turn on the transistor M0 even if it is a GaN device or a SiC device.

[0214] In particular, the drain-source voltages Vds(M1) to Vds(M8) of transistors M1 to M8 when they are ON are lower than the forward drop voltages Vf(D1) to Vf(D8) of diodes D1 to D8 in the first embodiment (Figure 11). Therefore, in this embodiment, the voltage loss in the switch drive circuit 421 can be reduced compared to the first embodiment (Figure 11).

[0215] Capacitor C21 is connected between the gate of transistor M1 and capacitor C12, and consequently between the gate of transistor M1 and insulating capacitor Cib. Capacitor C22 is connected between the gate of transistor M2 and capacitor C12, and consequently between the gate of transistor M2 and insulating capacitor Cib.

[0216] Capacitor C23 is connected between the gate of transistor M3 and capacitor C11, and consequently between the gate of transistor M3 and the insulating capacitor Cia. Capacitor C24 is connected between the gate of transistor M4 and capacitor C11, and consequently between the gate of transistor M4 and the insulating capacitor Cia.

[0217] Capacitor C25 is connected between the gate of transistor M5 and capacitor C14, and consequently between the gate of transistor M5 and insulating capacitor Cib. Capacitor C26 is connected between the gate of transistor M6 and capacitor C14, and consequently between the gate of transistor M6 and insulating capacitor Cib.

[0218] Capacitor C27 is connected between the gate of transistor M7 and capacitor C13, and consequently between the gate of transistor M7 and the insulating capacitor Cia. Capacitor C28 is connected between the gate of transistor M8 and capacitor C13, and consequently between the gate of transistor M8 and the insulating capacitor Cia.

[0219] Resistors R1 to R8 are connected to the gate-source of transistors M1 to M8, respectively. In other words, the voltage across resistors R1 to R8 corresponds to the gate-source voltages Vgs(M1) to Vgs(M8) of transistors M1 to M8.

[0220] The cathode of diode D11 is connected to the gate of transistor M1. The anode of diode D11 is connected to the source of transistor M1. The anode of diode D12 is connected to the gate of transistor M2. The cathode of diode D12 is connected to the source of transistor M2.

[0221] The cathode of diode D13 is connected to the gate of transistor M3. The anode of diode D13 is connected to the source of transistor M3. The anode of diode D14 is connected to the gate of transistor M4. The cathode of diode D14 is connected to the source of transistor M4.

[0222] The cathode of diode D15 is connected to the gate of transistor M5. The anode of diode D15 is connected to the source of transistor M5. The anode of diode D16 is connected to the gate of transistor M6. The cathode of diode D16 is connected to the source of transistor M6.

[0223] The cathode of diode D17 is connected to the gate of transistor M7. The anode of diode D17 is connected to the source of transistor M7. The anode of diode D18 is connected to the gate of transistor M8. The cathode of diode D18 is connected to the source of transistor M8.

[0224] Transistors M1, M2, M5, and M6 are driven according to the drive pulse Ib. When the drive pulse Ib is active, the gate voltages of transistors M1, M2, M5, and M6 rise. Consequently, transistors M1 and M5 turn ON, and transistors M2 and M6 turn OFF. On the other hand, when the drive pulse Ib is stopped, the gate voltages of transistors M1, M2, M5, and M6 fall. Consequently, transistors M1 and M5 turn OFF, and transistors M2 and M6 turn ON.

[0225] Transistors M3, M4, M7, and M8 are driven according to the drive pulse Ia. When the drive pulse Ia is active, the gate voltages of transistors M3, M4, M7, and M8 rise. Consequently, transistors M3 and M7 turn ON, and transistors M4 and M8 turn OFF. On the other hand, when the drive pulse Ia is stopped, the gate voltages of transistors M3, M4, M7, and M8 fall. Consequently, transistors M3 and M7 turn OFF, and transistors M4 and M8 turn ON.

[0226] With this configuration, it is not necessary to prepare separate control signals for each of the transistors M1 to M8. If it is necessary to lower the on-resistance of each of the transistors M1 to M8, diodes D11 to D18 should be connected in parallel to resistors R1 to R8, respectively, in order to raise the gate-source voltage Vgs of each of the transistors M1 to M8.

[0227] <Discharge circuit (1st example)> Figure 14 shows a first example of the discharge circuit 421X. The first example of the discharge circuit 421X includes a resistor X1.

[0228] Resistor X1 can be understood as a discharge resistor connected between the application terminal of the switch drive signal Vg and the reference node nd. With the discharge circuit 421X of the first example, the switch drive signal Vg can be discharged with an extremely simple circuit configuration.

[0229] <Discharge circuit (2nd example)> Figure 15 shows a second example of the discharge circuit 421X. The second example of the discharge circuit 421X is based on the first example (Figure 14) and further includes transistors X2 and X3, a capacitor X4, resistors X5 and X6, and a diode X7. Transistors X2 and X3 may be, for example, N-channel type.

[0230] The drain of transistor X2 is connected to the application terminal of the switch drive signal Vg. The source of transistor X2 is connected to the reference node nd. Transistor X2 functions as a low-impedance discharge switch connected between the application terminal of the switch drive signal Vg and the reference node nd.

[0231] The anode of diode X7 is connected to the application terminal of the switch drive signal Vg. The cathode of diode X7 is connected to the first terminal of resistor X6. The second terminal of resistor X6, the drain of transistor X3, and the first terminals of capacitor X4 and resistor X5 are connected to the gate of transistor X2. The source of transistor X3, and the second terminals of capacitor X4 and resistor X5 are connected to the reference node nd. The gate of transistor X3 is connected to the application terminal of the control signal SX.

[0232] The application terminal of the control signal SX may be connected to a node that is pulse-driven when the switch drive signal Vg is set to a high level, for example, the gate of transistor M1 or M3 in the third embodiment (Figure 13).

[0233] When the control signal SX is pulse-driven, transistor X2 is in the off state. Therefore, the discharge path through transistor X2 is blocked. On the other hand, when the control signal SX is not pulse-driven, transistor X2 is in the on state. Therefore, the discharge path through transistor X2 is open.

[0234] Thus, the transistor X3, capacitor X4, resistors X5 and X6, and diode X7 form a controller CTRL that drives transistor X2 in response to the control signal SX. As shown in this figure, the controller CTRL may also operate using the switch drive signal Vg as its power source.

[0235] In the second example discharge circuit 421X, the switch drive signal Vg can be discharged faster compared to the first example (Figure 14). Therefore, high-speed switching of transistor M0, or transistors M0a and M0b, becomes possible.

[0236] Note that the discharge circuit 421X in the second example does not necessarily have to be based on the first example (Figure 14). In other words, resistor X1 may be omitted.

[0237] <Insulated switch (fourth embodiment)> Figure 16 shows a fourth embodiment of the isolation switch 400. The isolation switch 400 of this embodiment is based on the first embodiment (Figure 11) described above, and further includes a voltage control circuit 421Z as a component of the switch drive circuit 421.

[0238] When a GaN device or similar is used as transistor M0, a switch drive signal Vg with a certain degree of accuracy is required. For example, the switch drive signal Vg may require an output accuracy of 5V ± 10%. However, the rectifier circuits 421a to 421d, consisting of diodes D1 to D8 and capacitors C1, C2, and Co, may not necessarily achieve the above output accuracy.

[0239] Therefore, the isolation switch 400 of this embodiment includes a voltage control circuit 421Z as a component of the switch drive circuit 421. The voltage control circuit 421Z may be provided, for example, between the rectifier circuits 421c and 421d and the application terminal of the switch drive signal Vg. The voltage control circuit 421Z stabilizes the switch drive signal Vg and outputs it to the gate of the transistor M0. With this configuration, the transistor M0 can be driven appropriately.

[0240] <Voltage control circuit> Figure 17 shows an example configuration of the voltage control circuit 421Z. The voltage control circuit 421Z in this example configuration includes a Zener diode Z1. The cathode of the Zener diode Z1 is connected to the application terminal of the switch drive signal Vg. The anode of the Zener diode Z1 is connected to a common node nd, and consequently to an external terminal T5. The common node nd and the external terminal T5 can be understood as an example of a reference potential terminal. With this configuration, the voltage control circuit 421Z can be easily implemented.

[0241] <Combination of Embodiments> The various embodiments described so far may be combined in any way that is not contradictory. For example, the discharge circuit 421X in the first example (Figure 14) and the second example (Figure 15) may be applied to any of the first embodiment (Figure 11), the second embodiment (Figure 12), and the third embodiment (Figure 13). Also, the voltage control circuit 421Z mentioned earlier can be introduced into either the second embodiment (Figure 12) or the third embodiment (Figure 13).

[0242] <Note> According to this disclosure, the high level of the switch drive signal is increased. The above disclosure is further noted below.

[0243] [Note 1] A switch circuit (422) is connected between the first node (T4) and the second node (T5) and configured to be turned on / off by a switch drive signal (Vg), A pulse generation circuit (411) configured to generate a first drive pulse (Pa) and a second drive pulse (Pb) in opposite phases to each other, A switch drive circuit (421) is configured to receive a third drive pulse (Ia) and a fourth drive pulse (Ib) and generate the switch drive signal (Vg), A first isolation capacitor (Cia) and a second isolation capacitor (Cib) are configured to transmit the first drive pulse (Pa) and the second drive pulse (Pb) as the third drive pulse (Ia) and the fourth drive pulse (Ib), respectively, while insulating the pulse generation circuit (411) and the switch drive circuit (421). An insulated switch (400) equipped with [a specific feature].

[0244] [Note 2] The switch circuit (422) is an isolated switch (400) as described in Appendix 1, which includes at least one output transistor (M0, M0a, M0b) whose gate is connected to the application terminal of the switch drive signal (Vg).

[0245] [Note 3] The output transistors (M0, M0a, M0b) are GaN devices or SiC devices, as described in Appendix 2, for the isolation switch (400).

[0246] [Note 4] The aforementioned switch drive circuit (421) is A first rectifier circuit (421a) and a second rectifier circuit (421b) are configured to generate a node voltage (Va) from the third drive pulse (Ia) and the fourth drive pulse (Ib), A third rectifier circuit (421c) and a fourth rectifier circuit (421d) are connected in tandem to the output terminals of the first rectifier circuit (421a) and the second rectifier circuit (421b), respectively, and are configured to generate the switch drive signal (Vg) from the third drive pulse (Ia) and the fourth drive pulse (Ib) that is higher than the node voltage (Va), An insulating switch (400) as described in any of the appendices 1 to 3, including the one mentioned above.

[0247] [Note 5] The first rectifier circuit (421a) includes a first rectifier element (D1, M1) configured to be connected between the first isolation capacitor (Cia) and a reference node (nd), and a second rectifier element (D2, M2) configured to be connected between the first isolation capacitor (Cia) and the terminal to which the node voltage (Va) is applied. The second rectifier circuit (421b) includes a third rectifier element (D3, M3) configured to be connected between the second isolation capacitor (Cib) and the reference node (nd), and a fourth rectifier element (D4, M4) configured to be connected between the second isolation capacitor (Cib) and the terminal to which the node voltage (Va) is applied. The third rectifier circuit (421c) includes a fifth rectifier element (D5, M5) configured to be connected between the first isolation capacitor (Cia) and the terminal to which the node voltage (Va) is applied, a sixth rectifier element (D6, M6) configured to be connected between the first isolation capacitor (Cia) and the terminal to which the switch drive signal (Vg) is applied, and a first capacitor (C1, C13) configured to be connected between the first isolation capacitor (Cia) and the fifth rectifier element (D5, M5) and the sixth rectifier element (D6, M6). The isolation switch (400) described in Appendix 4 includes, in the fourth rectifier circuit (421d), a seventh rectifier element (D7, M7) configured to be connected between the second isolation capacitor (Cib) and the application terminal of the node voltage (Va), an eighth rectifier element (D8, M8) configured to be connected between the second isolation capacitor (Cib) and the application terminal of the switch drive signal (Vg), and a second capacitor (C2, C14) configured to be connected between the second isolation capacitor (Cib) and the seventh rectifier element (D7, M7) and the eighth rectifier element (D8, M8).

[0248] [Note 6] The first rectifier element (D1), the second rectifier element (D2), the third rectifier element (D3), the fourth rectifier element (D4), the fifth rectifier element (D5), the sixth rectifier element (D6), the seventh rectifier element (D7), and the eighth rectifier element (D8) are all diodes, as described in Appendix 5, for the isolation switch (400).

[0249] [Note 7] The isolation switch (400) described in Appendix 5, wherein the first rectifier element (M1), the second rectifier element (M2), the third rectifier element (M3), the fourth rectifier element (M4), the fifth rectifier element (M5), the sixth rectifier element (M6), the seventh rectifier element (M7), and the eighth rectifier element (M8) are all transistors.

[0250] [Note 8] The isolation switch (400) described in Appendix 7, wherein the first rectifier element (M1), the second rectifier element (M2), the fifth rectifier element (M5), and the sixth rectifier element (M6) are driven in accordance with the fourth drive pulse (Ib), and the third rectifier element (M3), the fourth rectifier element (M4), the seventh rectifier element (M7), and the eighth rectifier element (M8) are driven in accordance with the third drive pulse (Ia).

[0251] [Note 9] The isolation switch (400) according to any one of the appendices 1 to 8, further comprising a clamp circuit (421Y) configured to limit the voltage generated at the application terminals of the third drive pulse (Ia) and the fourth drive pulse (Ib).

[0252] [Note 10] The clamp circuit (421Y) is an isolation switch (400) as described in Appendix 9, comprising: a first discharge element (Y1) configured to conduct / interrupt between the application terminal of the third drive pulse (Ia) and a reference node (nd) in response to the fourth drive pulse (Ib); and a second discharge element (Y2) configured to conduct / interrupt between the application terminal of the fourth drive pulse (Ib) and the reference node (nd) in response to the third drive pulse (Ia).

[0253] [Note 11] The isolation switch (400) according to any one of the appendices 1 to 10, further comprising a discharge circuit (421X) configured to discharge the switch drive signal (Vg).

[0254] [Note 12] The discharge circuit (421X) is an isolated switch (400) as described in Appendix 11, which includes a discharge resistor (X1) configured to be connected between the application terminal of the switch drive signal (Vg) and a reference node (nd).

[0255] [Note 13] The discharge circuit (421X) is an isolated switch (400) according to Appendix 11 or 12, comprising a discharge switch (X2) configured to be connected between the application terminal of the switch drive signal (Vg) and a reference node (nd), and a controller (CTRL) configured to drive the discharge switch (X2) in response to a control signal (SX).

[0256] [Note 14] The controller (CTRL) is an isolated switch (400) as described in Appendix 13, which operates using the switch drive signal (Vg) as its power source.

[0257] [Note 15] The switch drive circuit (421) is an isolated switch (400) as described in any of Appendix 1 to 14, which includes a voltage control circuit (421Z) configured to stabilize the switch drive signal (Vg).

[0258] [Note 16] The voltage control circuit (421Z) is an isolated switch (400) as described in Appendix 15, which includes a Zener diode (Z1) configured to be connected between the application terminal of the switch drive signal (Vg) and the reference potential terminal (T5, nd).

[0259] [Note 17] Electronic equipment (A) equipped with an insulating switch (400) as described in any of the appendices 1 to 16.

[0260] <Other> Furthermore, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive. Moreover, the technical scope of this disclosure is defined by the claims and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of Symbols]

[0261] 5 Semiconductor Device 11, 11A - 11F Low - potential Terminals 12, 12A - 12F High - potential Terminals 21, 21A - 21D Transformers 22 Low - potential Coil (Primary - side Coil 23 High - potential Coil (Secondary - side Coil 24 First Inner End 25 First Outer End 26 First Spiral Portion 27 Second Inner End 28 Second Outer End 29 Second Spiral Portion 31 First Low - potential Wiring 32 Second Low - potential Wiring 33 First High - potential Wiring 34 Second High - potential Wiring 41 Semiconductor Chip 42 First Main Surface 43 Second Main Surface 44A - 44D Chip Sidewalls 45 First Functional Device 51 Insulation Layer 52 Insulation Main Surface 53A - 53D Insulation Sidewalls 55 Lowest Insulation Layer 56 Uppermost Insulation Layer 57 Inter - layer Insulation Layer 58 First Insulation Layer 59 Second Insulation Layer 60 Second Functional Device 61 Seal Conductor 62 Device Region 63 Outer Region 64 Seal Plug Conductor 65 Seal Via Conductor 66 First Inner Region 67 Second Inner Region 71 Through - wiring 72 Low - potential Connection Wiring 73 Lead - out Wiring 74 First Connection Plug Electrode 75 Second Connection Plug Electrode 76 Pad Plug Electrode 77 Substrate Plug Electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrodes 81 High-potential connection wiring 82 Pad plug electrodes 85 Dummy Patterns 86 High-Potential Dummy Pattern 87. First High-Potential Dummy Pattern 88. Second High-Potential Dummy Pattern 89 First area 90 Second area 91 Third area 92 First connection section 93 Pattern 1 94 Pattern 2 95 Pattern 3 96 First outer line 97 Second outer perimeter line 98 First Intermediate Line 99 First connection line 100 slits 130 Separation structure 140 Inorganic insulating layer 141 First Inorganic Insulating Layer 142 Second Inorganic Insulating Layer 143 Low-potential pad opening 144 High-potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmission circuit (pulse generator) 212, 213 buffers 220 Driver chip (second chip) 221, 222 buffers 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transchip (third chip) 230a First wiring layer (lower layer) 230b Second wiring layer (upper layer) 231, 232 Transformers 231p, 232p Primary coils 231s, 232s Secondary coils 300 Transchip 301 First transformer 302 Second transformer 303 Third transformer 304 Fourth transformer 305 First guard ring 306 Second guard ring 400 Insulated switch 400p Primary circuit system 400s Secondary circuit system 410 Primary side circuit 411 Pulse generation circuit 411a, 411b Drivers 411c Controller 412 Oscillation circuit 420 Secondary side circuit 421 Switch drive circuit 421a, 421b, 421c, 421d Rectifier circuits 421X Discharge circuit 421Y Clamp circuit 421Z Voltage control circuit​​​​​​​​​​​​​​​​​​​​ Cp parasitic capacitor CTRL controller D1-D8, D11-D18, Dx, Dy diodes L1p, L2p primary coil L1s, L2s, L3s, L4s secondary coils M0, M0a, M0b, M1~M8 transistors nd reference node R1~R8 Resistors T1, T2, T3, T4, T5 External terminals T21, T22, T23, T24, T25, T26 External terminals X 1st direction X1 resistance X2, X3 transistors X4 Capacitor X5, X6 resistance X7 Diode X21, X22, X23 internal terminals Y Second direction Y1, Y2 transistors Y3, Y4 Capacitors Y5, Y6 resistance Y7, Y8 diodes Y21, Y22, Y23 wiring Z normal direction Z1 Zener diode Z21, Z22, Z23 Via

Claims

1. A switch circuit connected between the first node and the second node and configured to be turned on / off by a switch drive signal, A pulse generation circuit configured to generate a first drive pulse and a second drive pulse in opposite phases to each other, A switch drive circuit configured to generate the switch drive signal upon receiving a third drive pulse and a fourth drive pulse, A first insulating capacitor and a second insulating capacitor configured to transmit the first drive pulse and the second drive pulse as the third drive pulse and the fourth drive pulse, respectively, while insulating the pulse generation circuit and the switch drive circuit, An insulated switch equipped with this feature.

2. The isolation switch according to claim 1, wherein the switch circuit includes at least one output transistor whose gate is connected to the terminal to which the switch drive signal is applied.

3. The isolation switch according to claim 2, wherein the output transistor is a GaN device or a SiC device.

4. The aforementioned switch drive circuit is A first rectifier circuit and a second rectifier circuit configured to generate a node voltage from the third drive pulse and the fourth drive pulse, A third rectifier circuit and a fourth rectifier circuit are connected in tandem to the output terminals of the first rectifier circuit and the second rectifier circuit, respectively, and are configured to generate the switch drive signal higher than the node voltage from the third drive pulse and the fourth drive pulse, The insulating switch according to claim 1, including the feature described above.

5. The first rectifier circuit includes a first rectifier element configured to be connected between the first isolation capacitor and a reference node, and a second rectifier element configured to be connected between the first isolation capacitor and the node voltage application terminal. The second rectifier circuit includes a third rectifier element configured to be connected between the second isolation capacitor and the reference node, and a fourth rectifier element configured to be connected between the second isolation capacitor and the node voltage application terminal, The third rectifier circuit includes a fifth rectifier element configured to be connected between the first isolation capacitor and the terminal to which the node voltage is applied, a sixth rectifier element configured to be connected between the first isolation capacitor and the terminal to which the switch drive signal is applied, and a first capacitor configured to be connected between the first isolation capacitor and the fifth and sixth rectifier elements. The isolation switch according to claim 4, wherein the fourth rectifier circuit includes a seventh rectifier element configured to be connected between the second isolation capacitor and the terminal to which the node voltage is applied, an eighth rectifier element configured to be connected between the second isolation capacitor and the terminal to which the switch drive signal is applied, and a second capacitor configured to be connected between the second isolation capacitor and the seventh rectifier element and the eighth rectifier element.

6. The isolation switch according to claim 5, wherein the first rectifier element, the second rectifier element, the third rectifier element, the fourth rectifier element, the fifth rectifier element, the sixth rectifier element, the seventh rectifier element, and the eighth rectifier element are all diodes.

7. The isolation switch according to claim 5, wherein the first rectifier element, the second rectifier element, the third rectifier element, the fourth rectifier element, the fifth rectifier element, the sixth rectifier element, the seventh rectifier element, and the eighth rectifier element are all transistors.

8. The isolation switch according to claim 7, wherein the first rectifier element, the second rectifier element, the fifth rectifier element and the sixth rectifier element are driven in accordance with the fourth drive pulse, and the third rectifier element, the fourth rectifier element, the seventh rectifier element and the eighth rectifier element are driven in accordance with the third drive pulse.

9. The isolation switch according to claim 1, wherein the switch drive circuit further includes a clamp circuit configured to limit the voltage generated at the application terminals of the third drive pulse and the fourth drive pulse, respectively.

10. The isolation switch according to claim 9, wherein the clamp circuit includes a first discharge element configured to conduct / interrupt between the application end of the third drive pulse and a reference node in response to the fourth drive pulse, and a second discharge element configured to conduct / interrupt between the application end of the fourth drive pulse and the reference node in response to the third drive pulse.

11. The isolation switch according to claim 1, wherein the switch drive circuit further includes a discharge circuit configured to discharge the switch drive signal.

12. The isolation switch according to claim 11, wherein the discharge circuit includes a discharge resistor configured to be connected between the application terminal of the switch drive signal and a reference node.

13. The isolation switch according to claim 11, wherein the discharge circuit includes a discharge switch configured to be connected between the application terminal of the switch drive signal and a reference node, and a controller configured to drive the discharge switch in accordance with a control signal.

14. The isolation switch according to claim 13, wherein the controller operates using the switch drive signal as a power source.

15. The isolated switch according to claim 1, wherein the switch drive circuit includes a voltage control circuit configured to stabilize the switch drive signal.

16. The isolation switch according to claim 15, wherein the voltage control circuit includes a Zener diode configured to be connected between the application terminal of the switch drive signal and the reference potential terminal.

17. An electronic device comprising an insulating switch according to any one of claims 1 to 16.

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