Gate driver circuits, motor drive devices using them, and electronic devices.

Abstract

Turn on multiple power transistors simultaneously. [Solution] Multiple high-side driver units DRH1, DRH2 correspond to multiple high-side transistors MH1, MH2. The first output sensor 280 outputs voltage V OUT a predetermined first threshold voltage V TH1 When the signal crosses, the first output detection signal VOUTDET1 is asserted. The timer circuit 290 measures the timing of the assertion of the first output detection signal VOUTDET1. The drive capability of each of the multiple high-side driver units DRH1 and DRH2 is adjustable. The control circuit 210 adjusts the drive capability of each high-side driver unit DRH1 and DRH2 so that the timing of the assertion of the first output detection signal VOUTDET1 is synchronized when each of the multiple high-side driver units DRH1 and DRH2 is operated individually.

Description

[Technical Field]

[0001] This disclosure relates to a gate driver circuit. [Background technology]

[0002] Half-bridge circuits, H-bridge circuits, and three-phase bridge circuits (hereinafter collectively referred to as switching circuits) using power transistors are used in motor driver circuits, DC / DC converters, power conversion devices, and the like.

[0003] In high-power switching circuits, multiple power transistors are connected in parallel to form an arm. Here, the gate threshold voltage V of the multiple power transistors GS(th) When these vary, they affect the gate threshold voltage V GS(th) The engine will turn on / off in a specific order based on this, and it cannot be turned on / off simultaneously.

[0004] If the turn-on / turn-off timings of multiple power transistors are out of sync, it can cause current concentration, leading to the degradation of the power transistors receiving the concentrated current. Furthermore, timing misalignment can potentially cause oscillation. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] International Publication No. WO2022 / 259780

[0006] [overview] This disclosure is made in the present circumstances, and one exemplary objective of a certain aspect thereof is to provide a gate driver circuit capable of suppressing variations in the turn-on and turn-off timing of multiple power transistors constituting a single arm.

[0007] A gate driver circuit in one aspect of the present disclosure drives an inverter circuit including a plurality of high-side transistors with upper arms connected in parallel. The gate driver circuit comprises a plurality of high-side driver units, each corresponding to a plurality of high-side transistors, each generating a high-side drive voltage at the gate of the corresponding high-side transistor; a first output sensor that asserts a first output detection signal when the output voltage of the inverter circuit crosses a predetermined first threshold voltage; a control circuit that controls the plurality of high-side driver units in accordance with an output command; and a timer circuit that measures the timing of asserting the first output detection signal. The drive capability of each of the plurality of high-side driver units is adjustable. The control circuit adjusts the drive capability of each high-side driver unit so that the timing of asserting the first output detection signal is synchronized when each of the plurality of high-side driver units is operated independently.

[0008] Another aspect of the present disclosure is also a gate driver circuit. This gate driver circuit drives an inverter circuit which includes a plurality of low-side transistors connected in parallel by lower arms. The gate driver circuit comprises a plurality of low-side driver units corresponding to the plurality of low-side transistors, each generating a low-side drive voltage at the gate of the corresponding low-side transistor; a second output sensor which asserts a second output detection signal when the output voltage of the inverter circuit crosses a predetermined second threshold voltage; a control circuit which controls the plurality of low-side driver units in accordance with an output command; and a timer circuit which measures the timing of asserting the second output detection signal. The drive capability of each of the plurality of low-side driver units is adjustable. The control circuit adjusts the drive capability of each low-side driver unit so that the timing of asserting the second output detection signal is synchronized when each of the plurality of low-side driver units is operated independently.

[0009] Furthermore, any combination of the above components, and any substitution of the components or expressions of this disclosure between methods, apparatus, systems, etc., are also valid embodiments of the present invention. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a circuit diagram of a switching circuit according to an embodiment. [Figure 2] Figure 2 illustrates the operation of the switching circuit before calibration. [Figure 3] Figure 3 illustrates the calibration of a high-side driver in a switching circuit. [Figure 4] Figure 4 illustrates the operation of the switching circuit after calibration. [Figure 5] Figure 5 illustrates the operation of the switching circuit before calibration. [Figure 6] Figure 6 illustrates the calibration of the low-side driver in a switching circuit. [Figure 7] Figure 7 illustrates the operation of the switching circuit after calibration. [Figure 8] Figure 8 is a circuit diagram of a gate driver circuit according to one embodiment. [Figure 9] Figure 9 shows the operating waveform of the gate driver circuit in Figure 8. [Figure 10] Figure 10 is a circuit diagram of a motor drive device according to an embodiment.

[0011] [Detailed explanation] (Summary of the embodiment) This section outlines some exemplary embodiments of the present disclosure. This outline is intended to provide a basic understanding of the embodiments and to simplify some concepts of one or more embodiments, serving as a prelude to the more detailed descriptions that follow later, and is not intended to limit the scope of the invention or disclosure. For convenience, “one embodiment” may be used to refer to one embodiment (example or variation) or more embodiments (example or variation) disclosed herein.

[0012] This summary is not intended to be a comprehensive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to define the scope of some or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed descriptions that will follow.

[0013] A gate driver circuit according to one embodiment drives an inverter circuit that includes a plurality of high-side transistors with upper arms connected in parallel. The gate driver circuit comprises a plurality of high-side driver units, each corresponding to a plurality of high-side transistors and generating a high-side drive voltage at the gate of the corresponding high-side transistor; a first output sensor that asserts a first output detection signal when the output voltage of the inverter circuit crosses a predetermined first threshold voltage; a control circuit that controls the plurality of high-side driver units according to an output command; and a timer circuit that measures the timing of asserting the first output detection signal. The drive capability of each of the plurality of high-side driver units is adjustable. The control circuit adjusts the drive capability of each high-side driver unit so that the timing of asserting the first output detection signal is synchronized when each of the plurality of high-side driver units is operated independently.

[0014] This configuration allows the driving capability of multiple high-side transistors to be calibrated based on the time it takes for the output voltage to change. This enables the timing of the turn-on of multiple high-side transistors to be synchronized when the characteristics of the multiple high-side transistors, specifically the gate threshold voltage, vary, thereby suppressing current concentration between the multiple high-side transistors and oscillations in the current flowing through each high-side transistor.

[0015] The "driving capability" of a driver unit refers to its ability to change the gate voltage of the high-side transistor, and can be understood as parameters such as (i) the amount of current output by the driver unit, (ii) the output impedance of the driver unit, and (iii) the size of the transistors constituting the driver unit (gate width / gate length ratio, W / L).

[0016] In one embodiment, each of the multiple high-side driver units may be configured to supply turn-on current to the gate of the corresponding high-side transistor. The driving capability may be the amount of turn-on current.

[0017] In one embodiment, multiple high-side driver units may be configured to change the amount of turn-on current over time. The amplitude of the turn-on current waveform may be adjustable as a driving capability.

[0018] In one embodiment, the control circuit may increase the amount of turn-on current generated by the multiple high-side driver units in response to the assertion of the first output detection signal.

[0019] In this configuration, the first output detection signal is used to calibrate the driving capability of multiple high-side driver units and also as a trigger for switching the amount of turn-on current. Therefore, the amount of turn-on current generated by multiple high-side driver units can be increased at the same time.

[0020] In one embodiment, the gate driver circuit may further include a plurality of high-side gate sensors, each corresponding to a plurality of high-side transistors, each asserting a high-side gate detection signal when the gate-source voltage of the corresponding high-side transistor exceeds a first voltage. In response to the assertion of each high-side gate detection signal, the control circuit may reduce the amount of turn-on current generated by the corresponding high-side gate driver.

[0021] In one embodiment, the lower arm of the inverter circuit may include a plurality of low-side transistors connected in parallel. The gate driver circuit may further include a plurality of low-side driver units corresponding to the plurality of low-side transistors, each generating a low-side drive voltage at the gate of the corresponding low-side transistor, and a second output sensor that asserts a second output detection signal when the output voltage of the inverter circuit crosses a predetermined second threshold voltage. The control circuit may control the plurality of low-side driver units in accordance with output commands. The drive capability of each of the plurality of low-side driver units may be adjustable. The control circuit may adjust the drive capability of each low-side driver unit so that the timing of asserting the second output detection signal is synchronized when each of the plurality of low-side driver units is operated independently.

[0022] This configuration allows the driving capability of multiple low-side transistors to be calibrated based on the time it takes for the output voltage to change. This enables the timing of the turn-on of multiple low-side transistors to be synchronized when their characteristics, specifically the gate threshold voltage, vary, thereby suppressing current concentration among multiple low-side transistors and oscillations in the current flowing through each low-side transistor.

[0023] In one embodiment, each of the low-side driver units is configured to supply a turn-on current to the gate of the corresponding low-side transistor, and the driving capability may be the amount of the turn-on current.

[0024] In one embodiment, multiple low-side driver units are configured to change the amount of turn-on current over time, and the amplitude of the turn-on current waveform may be adjustable as a driving capability.

[0025] In one embodiment, the control circuit may increase the amount of turn-on current generated by the multiple low-side driver units in response to the assertion of the second output detection signal.

[0026] In this configuration, the second output detection signal is used to calibrate the driving capability of multiple low-side driver units and also as a trigger for switching the amount of turn-on current. Therefore, the amount of turn-on current generated by multiple low-side driver units can be increased at the same time.

[0027] In one embodiment, the gate driver circuit may further include a plurality of low-side gate sensors, each corresponding to a plurality of low-side transistors, each asserting a low-side gate detection signal when the gate-source voltage of the corresponding low-side transistor exceeds a predetermined voltage. The control circuit may reduce the amount of turn-on current generated by the corresponding low-side gate driver in response to the assertion of each low-side gate detection signal.

[0028] In one embodiment, the multiple high-side transistors may be SiC transistors.

[0029] In one embodiment, the multiple high-side transistors may be Si transistors.

[0030] A gate driver circuit according to one embodiment drives an inverter circuit that includes a plurality of low-side transistors with lower arms connected in parallel. The gate driver circuit comprises a plurality of low-side driver units, each corresponding to a plurality of low-side transistors, which generate a low-side drive voltage at the gate of the corresponding low-side transistor; a second output sensor that asserts a second output detection signal when the output voltage of the inverter circuit crosses a predetermined second threshold voltage; a control circuit that controls the plurality of low-side driver units according to an output command; and a timer circuit that measures the timing of asserting the second output detection signal. The drive capability of each of the plurality of low-side driver units is adjustable. The control circuit adjusts the drive capability of each low-side driver unit so that the timing of asserting the second output detection signal is synchronized when each of the plurality of low-side driver units is operated independently.

[0031] In one embodiment, the gate driver circuit may be integrated onto a single semiconductor substrate. "Integrated integration" includes cases where all the circuit components are formed on the semiconductor substrate, or where the main components of the circuit are integrated, and some resistors, capacitors, etc., may be provided outside the semiconductor substrate for adjusting circuit constants. Integrating the circuit onto a single chip can reduce the circuit area and maintain uniformity of the characteristics of the circuit elements.

[0032] A motor drive device according to one embodiment comprises a bridge circuit including an upper arm and a lower arm, and a gate driver circuit as described above for driving the bridge circuit.

[0033] An electronic device according to one embodiment comprises a motor and the motor drive device described above for driving the motor.

[0034] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing will be denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Furthermore, these embodiments are illustrative and not limiting to the invention, and not all features or combinations thereof described in the embodiments are necessarily essential to the invention.

[0035] In this specification, "member A connected to member B" includes not only cases where member A and member B are directly connected physically, but also cases where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection or impair the functions or effects produced by their combination.

[0036] Similarly, "the state in which member C is provided between member A and member B" includes not only cases where member A and member C, or member B and member C, are directly connected, but also cases where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions or effects produced by their combination.

[0037] Figure 1 is a circuit diagram of a switching circuit 100 according to an embodiment. The switching circuit 100 comprises a bridge circuit 110 and a gate driver circuit 200. Here, only the configuration of one phase of the switching circuit 100 is shown, but the switching circuit 100 may be a three-phase circuit or an H-bridge circuit.

[0038] The bridge circuit 110 includes an upper arm 112 provided between the power line (input line) 102 and the output terminal (output line) 104, and a lower arm 114 provided between the output line 104 and the ground line 106.

[0039] The upper arm 112 includes multiple N (N≧2) high-side transistors MH1, MH2 connected in parallel and independently controllable on / off. The lower arm 114 includes multiple low-side transistors ML1, ML2 connected in parallel. The high-side transistors MH1, MH2 and the low-side transistors ML1, ML2 are discrete components.

[0040] In this embodiment, the case where N=2 is described, but the number of parallel transistors may be 3 or more.

[0041] The gate driver circuit 200 drives the upper arm 112 and lower arm 114 of the bridge circuit 110 in response to the input signal IN. The input signal IN is the output voltage V of the bridge circuit 110. OUT This is a signal that instructs [something].

[0042] The gate driver circuit 200 turns on the upper arm 112 and off the lower arm 114 when the input signal IN is at a first level (e.g., high). At this time, the output voltage V of the bridge circuit 110 OUT High voltage V M Conversely, when the input signal IN is at the second level (for example, low), the gate driver circuit 200 turns off the upper arm 112 and on the lower arm 114. At this time, the output voltage V of the bridge circuit 110 OUT The low voltage is V SS This is the result.

[0043] The configuration of the gate driver circuit 200 will be explained.

[0044] Between the bootstrap pin BST and output line 104 is the bootstrap capacitor C. BST The connection is established.

[0045] The plurality of high-side gate pins HG1, HG2 correspond to the plurality of high-side transistors MH1, MH2, and each high-side gate pin HGi (i = 1, 2... N) is connected to the gate of the corresponding high-side transistor MHi. The switching pin SW is connected to the sources of the high-side transistors MH1, MH2, the drains of the low-side transistors ML1, ML2, and the output line 104.

[0046] The plurality of low-side gate pins LG1, LG2 correspond to the plurality of low-side transistors ML1, ML2, and each low-side gate pin LGi (i = 1, 2... N) is connected to the gate of the corresponding low-side transistor MLi.

[0047] The bootstrap line 202 is connected to the bootstrap pin BST. A constant voltage V is applied to the bootstrap line 202 via the rectifying element 203. REG The rectifying element 203 and the bootstrap capacitor C form a bootstrap circuit, which maintains the voltage V of the bootstrap line 202 at V + V - Vf. Vf is the forward voltage of the rectifying element 203. BST The rectifying element 203 and the bootstrap capacitor C form a bootstrap circuit, which maintains the voltage V of the bootstrap line 202 at V + V - Vf. Vf is the forward voltage of the rectifying element 203. BST The rectifying element 203 and the bootstrap capacitor C form a bootstrap circuit, which maintains the voltage V of the bootstrap line 202 at V + V - Vf. Vf is the forward voltage of the rectifying element 203. OUT +V REG -Vf. Vf is the forward voltage of the rectifying element 203.

[0048] The gate driver circuit 200 includes a control circuit 210, a high-side driver 220, a low-side driver 250, a first output sensor 280, a second output sensor 282, a high-side off sensor 284, a low-side off sensor 286, and a timer circuit 290, and is a functional IC integrated on one semiconductor substrate. The control circuit 210 controls the high-side driver 220 and the low-side driver 250 according to the input signal IN.

[0049] The high-side driver 220 includes a plurality of high-side driver units DRH1, DRH2 corresponding to the plurality of high-side transistors MH1, MH2. The high-side driver 220 is provided between the bootstrap line 202 and the switching line 204.

[0050] Each high-side driver unit DRHi generates a high-side drive voltage V at the gate, i.e., the high-side gate terminal HGi, of the corresponding high-side transistor MHi. HGi It controls and drives the high-side transistor MHi.

[0051] The low-side driver 250 includes multiple low-side driver units DRL1, DRL2 corresponding to multiple low-side transistors ML1, ML2. The low-side driver 250 is located between the power line 206 and the ground line 208.

[0052] Each low-side driver unit DRLi generates a low-side drive voltage V at the gate, i.e., the low-side gate terminal LSi, of the corresponding low-side transistor MLi. LGi This controls and drives the low-side transistor MLi.

[0053] The control circuit 210 controls multiple high-side driver units DRH1, DRH2 and multiple low-side driver units DRL1, DRL2 in response to the input signal IN, which is an output command.

[0054] Specifically, the control circuit 210 controls the high-side driver units DRH1 and DRH2 so that the high-side transistor MH turns on when the input signal IN is at a first level (for example, high), and controls the low-side driver units DRL1 and DRL2 so that the low-side transistor ML turns off.

[0055] Furthermore, the control circuit 210 controls the high-side driver units DRH1 and DRH2 so that the high-side transistor MH is turned off when the input signal IN is at the second level (for example, low), and controls the low-side driver units DRL1 and DRL2 so that the low-side transistor ML is turned on.

[0056] When the input signal IN changes from the first level to the second level, the control circuit 210 controls the high-side driver units DRH1 and DRH2 so that the high-side transistors MH1 and MH2 turn off first. Then, after the high-side transistors MH1 and MH2 have turned off, the control circuit 210 controls the low-side driver units DRL1 and DRL2 so that the low-side transistors ML1 and ML2 turn on. The turn-off of the high-side transistors MH1 and MH2 is detected by the high-side off sensor 284. The high-side off sensor 284 monitors the gate-source voltage of each of the high-side transistors MH1 and MH2, and asserts the high-side off signal HS_OFF when the voltage falls below a predetermined level.

[0057] When the input signal IN changes from the second level to the first level, the control circuit 210 controls the low-side driver units DRL1 and DRL2 so that the low-side transistors ML1 and ML2 turn off first. Then, after the low-side transistors ML1 and ML2 have turned off, the control circuit 210 controls the high-side driver units DRH1 and DRH2 so that the high-side transistors MH1 and ML2 turn on. The turn-off of the low-side transistors ML1 and ML2 is detected by the low-side off sensor 286. The low-side off sensor 286 monitors the gate-source voltage of each of the low-side transistors ML1 and ML2, and asserts the low-side off signal LS_OFF when the voltage falls below a predetermined level.

[0058] When the upper arm 112 is turned on, it is desirable that multiple high-side transistors MH1 and MH2 turn on simultaneously. However, due to variations in the electrical characteristics of the high-side transistors MH1 and MH2, they may turn on at different timings. In particular, variations in characteristics are significant in SiC transistors, and therefore this disclosure is especially effective when the high-side transistors MH1 and MH2 and the low-side transistors ML1 and ML2 are SiC, but it is also applicable to Si transistors.

[0059] The gate driver circuit 200 has a function to calibrate the high-side driver 220 so that multiple high-side transistors MH1 and MH2 turn on simultaneously.

[0060] For this calibration, the multiple high-side driver units DRH1 and DRH2 that make up the high-side driver 220 are each configured to have independently adjustable drive capabilities.

[0061] The first output sensor 280 controls the output voltage V of the bridge circuit 110. OUT It monitors the output voltage V. The first output sensor 280 monitors the output voltage V. OUT a predetermined first threshold voltage V TH1 When this crosses, the first output detection signal VOUTDET1 is asserted.

[0062] In calibration mode, the control circuit 210 does not operate multiple high-side driver units DRH1 and DRH2 simultaneously, but operates them one at a time.

[0063] The timer circuit 290 measures the timing of the assertion of the first output detection signal VOUTDET1. For example, the timer circuit 290 measures the time from when the input signal IN changes from the second level (low) to the first level (high) until the assertion of the first output detection signal VOUTDET1. In other words, the timer circuit 290 measures the timing of the assertion of the first output detection signal VOUTDET1 with respect to the point of change of the input signal IN. The assertion timing when the i-th high-side driver unit DRHi is operated is denoted as Toni.

[0064] The control circuit 210 adjusts the driving capability of each high-side driver unit DRH1 and DRH2 so that the assertion timings Ton1 and Ton2 of the first output detection signal VOUTDET1 are synchronized when each of the multiple high-side driver units DRH1 and DRH2 is operated independently.

[0065] The gate driver circuit 200 also has a function to calibrate the low-side driver 250 so that multiple low-side transistors ML1 and ML2 turn on simultaneously for the lower arm 114 as well.

[0066] For this calibration, the multiple low-side driver units DRL1 and DRL2 that make up the low-side driver 250 are each configured to have independently adjustable drive capabilities.

[0067] The second output sensor 282 controls the output voltage V of the bridge circuit 110. OUT The second output sensor 282 monitors the output voltage V. OUT The predetermined second threshold voltage V TH2 When it crosses, the second output detection signal VOUTDET2 is asserted.

[0068] In calibration mode, the control circuit 210 does not operate multiple low-side driver units DRL1 and DRL2 simultaneously, but operates them one by one.

[0069] The timer circuit 290 measures the timing of the assertion of the second output detection signal VOUTDET2. For example, the timer circuit 290 measures the time from when the input signal IN changes from the first level (high) to the second level (low) until the assertion of the second output detection signal VOUTDET2. In other words, the timer circuit 290 measures the timing of the assertion of the second output detection signal VOUTDET2 with respect to the point of change of the input signal IN. The assertion timing when the i-th low-side driver unit DRLi is operated is denoted as Toni.

[0070] The control circuit 210 adjusts the driving capability of each low-side driver unit DRL1 and DRL2 so that the assertion timings Ton1 and Ton2 of the second output detection signal VOUTDET2 are synchronized when each of the multiple low-side driver units DRL1 and DRL2 is operated independently.

[0071] The above describes the configuration of the switching circuit 100. Next, its operation will be explained.

[0072] Figure 2 illustrates the operation of the switching circuit 100 before calibration. Before time t0, the input signal IN is low, the upper arm 112 is off, the lower arm 114 is on, and the output voltage V OUT The low voltage (ground voltage) is 0V.

[0073] At time t0, the input signal IN transitions from low to high. The control circuit 210 controls the low-side driver 250, and the gate-source voltage V of the low-side transistors ML1 and ML2 LGS The voltage is reduced, and the lower arm 114 is turned off. When the lower arm 114 is turned off at time t1, the low-side off signal LS_OFF is asserted.

[0074] In response to the assertion of the low-side off signal LS_OFF, the control circuit 210 controls the high-side driver 220 to turn on the upper arm 112.

[0075] Before calibration, the drive capability of the high-side driver units DRH1 and DRH2 is in its initial state, and the gate-source voltages V of the high-side transistors MH1 and MH2 are respectively HGS1 ,V HGS2 It rises at the same slope.

[0076] Gate-source voltage V of high-side transistor MH1 GS(th)1 and the gate-source voltage V of the high-side transistor MH2 GS(th)2 Let's assume that there is variation. For example, V GS(th)2 <V GS(th)1 If this is the case, the high-side transistor MH2 will turn on first, followed by the high-side transistor MH1. Therefore, current will concentrate in the high-side transistor MH2, and the drain current I of the high-side transistor MH2 will be MH2 However, the drain current I of the high-side transistor MH1 MH1It will become larger than that.

[0077] Thus, a timing difference in the turn-on of multiple power transistors MH1 and MH2 can cause current concentration. Furthermore, this can lead to accelerated degradation of the power transistors experiencing current concentration. Additionally, timing differences can potentially cause oscillation.

[0078] Figure 3 illustrates the calibration of the high-side driver 220 in the switching circuit 100. As described above, calibration is performed by operating the high-side driver units DRH1 and DRH2 in sequence.

[0079] Figure 3 shows the waveform when the i-th (i=1,2) high-side driver unit DRHi is in operation.

[0080] Before time t0, the input signal IN is low, the upper arm 112 is off, the lower arm 114 is on, and the output voltage V OUT This represents a low voltage of 0V.

[0081] At time t0, the input signal IN transitions from low to high. The control circuit 210 controls the low-side driver 250 and turns off the lower arm 114. At time t1, when the lower arm 114 is turned off, the low-side off signal LS_OFF is asserted.

[0082] In response to the assertion of the low-side off signal LS_OFF, the control circuit 210 controls the high-side driver unit DRHi of the high-side driver 220. The output voltage V of the high-side driver unit DRHi HGi When V rises, the gate-source voltage V of the high-side transistor MHi increases. HGSi The gate-source voltage V rises. HGSi The rate of increase depends on the driving capability of the high-side driver unit DRHi.

[0083] At time t2, the gate-source voltage V HGSiis the gate threshold voltage V of the high-side transistor MHi GS(th)i exceeds, the high-side transistor MHi turns on, and the output voltage V OUT begins to rise.

[0084] And at time t3, when the output voltage V OUT exceeds the first threshold voltage V TH1 the first output detection signal VOUTDET1 is asserted.

[0085] The timer circuit 290 measures the time Toni from the change of the input signal IN to the assertion of the first output detection signal VOUTDET1 as the timing of the assertion of the first output detection signal VOUTDET1.

[0086] This timing Toni becomes slower as the gate threshold voltage V of the transistor MHi GS(th)i is higher, and becomes faster as the gate threshold voltage V GS(th)i is lower.

[0087] The control circuit 210 adjusts the driving ability of the high-side driver unit DRHi so that Toni measured for a certain high-side driver unit DRHi is equal to Tonj measured for another high-side driver unit DRHj.

[0088] That is, when Toni>Tonj, the driving ability of the high-side driver unit DRHi is increased. As a result, the rising speed of the voltage V between the gate and source of the high-side transistor MHi HGSi increases, so Toni can be shortened and brought closer to Tonj.

[0089] Conversely, when Toni<Tonj, the driving ability of the high-side driver unit DRHi is decreased. As a result, the rising speed of the voltage V between the gate and source of the high-side transistor MHi HGSi decreases, so Toni can be lengthened and brought closer to Tonj.

[0090] The procedure for adjusting the high-side driver units DRH1 and DRH2 is not particularly limited. For example, the time Ton1 measured for the first high-side driver unit DRH1 is used as a reference. The driving capability of the other high-side driver unit DRH2 may then be adjusted so that the time Ton2 measured for DRH2 approaches Ton1.

[0091] Figure 4 illustrates the operation of the switching circuit 100 after calibration. Before time t0, the input signal IN is low, the upper arm 112 is off, the lower arm 114 is on, and the output voltage V OUT This represents a low voltage of 0V.

[0092] At time t0, the input signal IN transitions from low to high. The control circuit 210 controls the low-side driver 250 and turns off the lower arm 114. At time t1, when the lower arm 114 is turned off, the low-side off signal LS_OFF is asserted.

[0093] In response to the assertion of the low-side off signal LS_OFF, the control circuit 210 controls the high-side driver 220 to turn on the upper arm 112.

[0094] After calibration, the drive capability of the high-side driver units DRH1 and DRH2 is optimized, and the gate-source voltage V of the high-side transistors MH1 and MH2 is optimized. HGS1 ,V HGS2 The currents rise at different rates. Due to calibration, high-side transistors MH1 and MH2 turn on virtually simultaneously. As a result, high-side transistors MH1 and MH2 receive the same amount of drain current I. MH1 ,I MH2 This allows current to flow, suppressing current concentration.

[0095] Next, I will explain the calibration of the Low Side Driver 250.

[0096] Figure 5 illustrates the operation of the switching circuit 100 before calibration. Before time t0, the input signal IN is high, the upper arm 112 is ON, the lower arm 114 is OFF, and the output voltage V OUT This is high voltage (input voltage) V M That is the case.

[0097] At time t0, the input signal IN transitions from high to low. The control circuit 210 controls the high-side driver 220, and the gate-source voltage V HGS The voltage is reduced, and the upper arm 112 is turned off. When the upper arm 112 is turned off at time t1, the high-side off signal HS_OFF is asserted.

[0098] In response to the assertion of the high-side off signal HS_OFF, the control circuit 210 controls the low-side driver 250 and turns on the lower arm 114.

[0099] Before calibration, the drive capability of the low-side driver units DRL1 and DRL2 is in its initial state, and the gate-source voltages V of the low-side transistors ML1 and ML2 are respectively LGS1 ,V LGS2 It rises at the same slope.

[0100] Gate-source voltage V of low-side transistor ML1 GS(th)1 and the gate-source voltage V of the low-side transistor ML2 GS(th)2 Let's assume that there is variation. For example, V GS(th)2 <V GS(th)1 If this is the case, then the low-side transistor ML2 will turn on first, followed by the low-side transistor ML1. Therefore, current will concentrate in the low-side transistor ML2, and the drain current I of the low-side transistor ML2 will be ML2 However, the drain current I of the low-side transistor ML1 ML1 It will become larger than that.

[0101] Thus, a timing difference in the turn-on of multiple power transistors ML1 and ML2 can cause current concentration. Furthermore, this can lead to accelerated degradation of the power transistors experiencing current concentration. Additionally, timing differences can potentially cause oscillation.

[0102] Figure 6 illustrates the calibration of the low-side driver 250 in the switching circuit 100. As described above, calibration is performed by operating the low-side driver units DRL1 and DRL2 in sequence.

[0103] Figure 6 shows the waveform when the i-th (i=1,2) low-side driver unit DRLi is in operation.

[0104] Before time t0, the input signal IN is high, the upper arm 112 is on, the lower arm 114 is off, and the output voltage V OUT High voltage V M That is the case.

[0105] At time t0, the input signal IN transitions from high to low. The control circuit 210 controls the high-side driver 220 and turns off the upper arm 112. At time t1, when the upper arm 112 is turned off, the high-side off signal HS_OFF is asserted.

[0106] In response to the assertion of the high-side off signal HS_OFF, the control circuit 210 controls the low-side driver unit DRLi of the low-side driver 250. The output voltage V of the low-side driver unit DRLi LGi When it rises, the gate-source voltage V of the low-side transistor MLi increases. LGSi The gate-source voltage V rises. LGSi The rate of increase depends on the driving capability of the low-side driver unit DRLi.

[0107] At time t2, the gate-source voltage V LGSi The gate threshold voltage V of the low-side transistor MLi GS(th)iWhen it exceeds, the low-side transistor MLi turns on and the output voltage V OUT begins to decrease.

[0108] And at time t3, when the output voltage V OUT becomes lower than the second threshold voltage V TH2 the second output detection signal VOUTDET2 is asserted.

[0109] The timer circuit 290 measures the time Toni from the change of the input signal IN to the assertion of the second output detection signal VOUTDET2 as the timing of the assertion of the second output detection signal VOUTDET2.

[0110] This timing Toni becomes slower as the gate threshold voltage V GS(th)i of the transistor MLi is higher, and becomes faster as the gate threshold voltage V GS(th)i is lower.

[0111] The control circuit 210 adjusts the driving ability of the low-side driver unit DRLi so that Toni measured for a certain low-side driver unit DRLi is equal to Tonj measured for another low-side driver unit DRLj.

[0112] That is, when Toni>Tonj, the driving ability of the low-side driver unit DRLi is increased. As a result, since the rising speed of the gate-source voltage V LGSi of the low-side transistor MLi increases, Toni can be shortened and brought closer to Tonj.

[0113] Conversely, when Toni<Tonj, the driving ability of the low-side driver unit DRLi is decreased. As a result, since the rising speed of the gate-source voltage V LGSi of the low-side transistor MLi becomes slower, Toni can be lengthened and brought closer to Tonj.

[0114] The procedure for adjusting the low-side driver units DRL1 and DRL2 is not particularly limited. For example, the time Ton1 measured for the first low-side driver unit DRL1 may be used as a reference. The driving capability of the other low-side driver unit DRL2 may then be adjusted so that the time Ton2 measured for that unit approaches Ton1.

[0115] Figure 7 illustrates the operation of the switching circuit 100 after calibration. Before time t0, the input signal IN is high, the lower arm 114 is off, the upper arm 112 is on, and the output voltage V OUT High voltage V M That is the case.

[0116] At time t0, the input signal IN transitions from high to low. The control circuit 210 controls the high-side driver 220 and turns off the upper arm 112. At time t1, when the upper arm 112 is turned off, the high-side off signal LS_OFF is asserted.

[0117] In response to the assertion of the high-side off signal HS_OFF, the control circuit 210 controls the low-side driver 220 to turn on the lower arm 114.

[0118] After calibration, the drive capability of the low-side driver units DRL1 and DRL2 is optimized, and the gate-source voltage V of the low-side transistors ML1 and ML2 is optimized. LGS1 ,V LGS2 The currents rise at different rates. Due to calibration, the low-side transistors ML1 and ML2 turn on virtually simultaneously. As a result, the same amount of drain current I is applied to both low-side transistors ML1 and ML2. ML1 ,I ML2 This allows current to flow, suppressing current concentration.

[0119] Next, we will explain a specific example of the gate driver circuit 200 configuration.

[0120] Figure 8 is a circuit diagram of a gate driver circuit 200A according to one embodiment. Here, the configuration of the high-side driver 220 will be described, but the low-side driver 250 is configured similarly. For the configuration of the low-side driver 250, simply replace "high-side" with "low-side".

[0121] Each high-side driver unit DRHi includes a turn-on circuit 230 and a turn-off circuit 232. The turn-on circuit 230 becomes active when the high-side transistor MHi is turned on, and a turn-on current I is supplied to the gate of the high-side transistor MHi. HONi Source it.

[0122] The turn-off circuit 232 becomes active when the high-side transistor MHi is turned off, and a turn-off current I is drawn from the gate of the high-side transistor MHi. HOFFi Sync it.

[0123] As described above, the high-side driver unit DRHi is configured to have adjustable drive capability. In the example in Figure 8, the turn-on current I generated by the turn-on circuit 230 HONi The amount of current can be adjusted.

[0124] Furthermore, multiple high-side gate sensors GS1 and GS2 are provided, corresponding to each of the multiple high-side driver units DRH1 and DRH2. The high-side gate sensor GSi controls the gate-source voltage V of the corresponding high-side transistor MHi. HGSi A predetermined voltage V ON Compared to the two voltages V HGSi and V ON When the crossover occurs, the high-side gate detection signal VGSDETi is asserted.

[0125] In this embodiment, the high-side driver unit DRHi generates a turn-on current I during the turn-on operation of the high-side transistor MHi. HONi It is configured to change the amount of current over time. In other words, the turn-on current IHONi It does not change in a fixed amount but changes according to a certain waveform.

[0126] In one embodiment, during the turn-on operation of the high-side transistor MHi, the high-side driver unit DRHi changes the amount of turn-on current I HONi in three steps.

[0127] In response to the assertion of the first output detection signal VDET1, the control circuit 210 increases the amount of turn-on current I HONi generated by the high-side driver unit DRHi.

[0128] Also, in response to the assertion of the high-side gate detection signal VGSDETi, the control circuit 210 decreases the amount of turn-on current I HONi generated by the high-side gate driver DRHi.

[0129] The above is the configuration of the gate driver circuit 200A. Next, its operation will be described.

[0130] FIG. 9 is an operation waveform diagram of the gate driver circuit 200A in FIG. 8. At time t1, the turn-on circuit 230 of the high-side driver unit DRHi becomes active. Immediately after becoming active, the turn-on circuit 230 generates a turn-on current I HONi with a first current amount I1.

[0131] At time t a when the voltage V HGSi between the gate and source of the high-side transistor MHi exceeds a predetermined voltage V ON , the high-side gate detection signal VGSDET1 is asserted. In response to this, the control circuit 210 decreases the turn-on current I HONi to a second current amount I2. ​​​​​​​​​​​TH1 When it exceeds this value, the first output detection signal VOUTDET1 is asserted. In response to this, the control circuit 210 controls the turn-on current I HONi Increase the current to the third current I3.

[0133] time t c Output voltage V OUT The second threshold voltage V TH2 When it exceeds this value, the high-side driver unit DRHi applies a high voltage V to the gate of the high-side transistor MHi. BST Apply the solution.

[0134] In the calibration described above, the timing of asserting the first output detection signal VOUTDET1 is adjusted. In other words, in the control shown in Figure 9, time t b The timing of the turn-on current I is set so that it is consistent for all high-side driver units DRH1 and DRH2. HON1 ,I HON2 The amount of current is adjusted.

[0135] Turn-on current I HONi One example of how to adjust the current is to scale the current while maintaining the ratio of currents I1, I2, and I3. In other words, the control circuit 210 controls the calibration turn-on current I HONi The amplitude of the waveform may be adjusted as the driving capability described above.

[0136] Next, we will explain a modified version of the gate driver circuit 200.

[0137] Note that the gate sensors GS1 and GS2 in Figure 8 may also be used in conjunction with the high-side off sensor 284.

[0138] In this embodiment, during the calibration of the high-side driver unit DRHi, the timing of the assertion of the output detection signal VOUTDET1 is measured by the timer circuit 290 with reference to the change in the input signal IN, but this disclosure is not limited thereto. For example, the timing of the assertion of the output detection signal VOUTDET1 may be measured with reference to the assertion of the low-side off signal LS_OFF. In other words, in the waveform diagram of Figure 3, the period from time t1 to t3 may be measured by the timer circuit 290.

[0139] (Application) Next, the applications of the switching circuit 100 will be explained. The switching circuit 100 can be suitably used in a motor drive circuit.

[0140] Figure 10 is a circuit diagram of a motor drive device 300 according to an embodiment. The motor drive device 300 drives a three-phase motor 302, which is the load, and controls its rotational state.

[0141] The motor drive unit 300 comprises a bridge circuit 310 and a gate driver circuit 400. The bridge circuit 310 is a three-phase inverter having U-phase, V-phase, and W-phase legs, and each phase leg has a high-side transistor MH and a low-side transistor ML.

[0142] The gate driver circuit 400 includes a control circuit 410 and high-side drivers 420U~420W and low-side drivers 450U~450W. The control circuit 410 generates control signals that indicate the state of the six arms constituting the bridge circuit 310 based on the state of the load, which is a three-phase motor 302.

[0143] The high-side drivers 420U to 420W are constructed using the same architecture as the high-side driver 220 described above. The low-side drivers 450U to 450W are constructed using the same architecture as the low-side driver 250 described above.

[0144] Here, a three-phase motor is used as an example, but a single-phase motor can also be used. In this case, the bridge circuit 310 becomes an H-bridge circuit.

[0145] Next, the applications of the motor drive unit 300 will be explained. The motor drive unit 300 can be used to control the spindle motor of a hard disk, or to control the lens drive motor of an imaging device. Alternatively, it can be used to drive the drive motor of a printer head, or the paper feed motor. Alternatively, the motor drive unit 300 can be used to drive motors in electric vehicles, hybrid vehicles, and the like.

[0146] The embodiments are illustrative, and it will be understood by those skilled in the art that various modifications are possible in combinations of their components and processing steps, and that such modifications also fall within the scope of this disclosure or the present invention. Such modifications will be described below.

[0147] (Variation 1) The power transistor may be constructed using an IGBT (Insulated Gate Bipolar Transistor).

[0148] (Modification 2) The applications of the switching circuit 100 are not limited to the motor drive device 300. For example, the switching circuit 100 can be suitably used in switching regulators (DC / DC converters), various power conversion devices (inverters and converters), inverters for lighting discharge lamps, digital audio amplifiers, and so on. Therefore, the switching circuit 100 can be used in consumer electronics including electronic devices and home appliances, automobiles and in-vehicle components, industrial vehicles and industrial machinery.

[0149] The embodiments described using specific terminology merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted in the embodiments, without departing from the spirit of the present invention as defined in the claims.

[0150] (Note) This specification discloses the following technologies:

[0151] (Item 1) A gate driver circuit that drives an inverter circuit including multiple high-side transistors connected in parallel, wherein the upper arm is a gate driver circuit, Multiple high-side driver units, each corresponding to the multiple high-side transistors, generate a high-side drive voltage at the gate of the corresponding high-side transistor, A first output sensor asserts a first output detection signal when the output voltage of the inverter circuit crosses a predetermined first threshold voltage, A control circuit that controls the plurality of high-side driver units in accordance with the output command, A timer circuit for measuring the timing of asserting the first output detection signal, Equipped with, Each of the aforementioned high-side driver units has an adjustable drive capability. The control circuit is a gate driver circuit that adjusts the driving capability of each high-side driver unit so that the timing of asserting the first output detection signal is synchronized when each of the plurality of high-side driver units is operated independently.

[0152] (Item 2) Each of the aforementioned high-side driver units is configured to supply turn-on current to the gate of the corresponding high-side transistor. The gate driver circuit described in item 1, wherein the driving capability is the amount of the turn-on current.

[0153] (Item 3) The aforementioned multiple high-side driver units are configured to change the amount of the turn-on current over time. The gate driver circuit described in item 2, wherein the amplitude of the waveform of the turn-on current is adjustable as the driving capability.

[0154] (Item 4) The gate driver circuit according to item 3, wherein the control circuit increases the amount of the turn-on current generated by the plurality of high-side driver units in response to the assertion of the first output detection signal.

[0155] (Item 5) The system further comprises multiple high-side gate sensors, each corresponding to a plurality of high-side transistors, each asserting a high-side gate detection signal when the gate-source voltage of the corresponding high-side transistor exceeds a predetermined voltage. The control circuit reduces the amount of the turn-on current generated by the corresponding high-side gate driver in response to the assertion of each high-side gate detection signal, as described in item 3 or 4 of the gate driver circuit.

[0156] (Item 6) The lower arm of the inverter circuit includes a plurality of low-side transistors connected in parallel. The aforementioned gate driver circuit is The above-mentioned multiple low-side transistors are each provided with multiple low-side driver units that generate a low-side drive voltage at the gate of the corresponding low-side transistor, A second output sensor asserts a second output detection signal when the output voltage of the inverter circuit crosses a predetermined third threshold voltage, Furthermore, The control circuit controls the plurality of low-side driver units in accordance with the output command. Each of the aforementioned low-side driver units has an adjustable driving capacity. The timer circuit measures the timing of asserting the second output detection signal, The control circuit is a gate driver circuit according to any one of items 1 to 5, which adjusts the drive capability of each low-side driver unit so that the timing of asserting the second output detection signal is synchronized when each of the plurality of low-side driver units is operated independently.

[0157] (Item 7) Each of the aforementioned low-side driver units is configured to supply turn-on current to the gate of the corresponding low-side transistor. The gate driver circuit described in item 6, wherein the driving capability is the amount of the turn-on current.

[0158] (Item 8) The aforementioned multiple low-side driver units are configured to change the amount of the turn-on current over time. The gate driver circuit according to item 7, wherein the amplitude of the waveform of the turn-on current is adjustable as the driving capability.

[0159] (Item 9) The gate driver circuit according to item 8, wherein the control circuit increases the amount of the turn-on current generated by the plurality of low-side driver units in response to the assertion of the second output detection signal.

[0160] (Item 10) The system further comprises multiple low-side gate sensors, each corresponding to the multiple low-side transistors, which assert a low-side gate detection signal when the gate-source voltage of the corresponding low-side transistor exceeds a predetermined voltage. The gate driver circuit according to item 8 or 9, wherein the control circuit reduces the amount of the turn-on current generated by the corresponding low-side gate driver in response to the assertion of each low-side gate detection signal.

[0161] (Item 11) The gate driver circuit described in any of items 1 to 10, wherein the plurality of high-side transistors are SiC transistors.

[0162] (Item 12) The gate driver circuit described in any of items 1 to 10, wherein the plurality of high-side transistors are Si transistors.

[0163] (Item 13) A gate driver circuit that drives an inverter circuit including multiple low-side transistors connected in parallel, wherein the lower arm is a gate driver circuit, The above-mentioned multiple low-side transistors are each provided with multiple low-side driver units that generate a low-side drive voltage at the gate of the corresponding low-side transistor, A second output sensor asserts a second output detection signal when the output voltage of the inverter circuit crosses a predetermined third threshold voltage, A control circuit that controls the plurality of low-side driver units in accordance with the output command, A timer circuit for measuring the timing of asserting the second output detection signal, Equipped with, Each of the aforementioned low-side driver units has an adjustable driving capacity. The control circuit is a gate driver circuit that adjusts the driving capability of each low-side driver unit so that the timing of asserting the second output detection signal is synchronized when each of the plurality of low-side driver units is operated independently.

[0164] (Item 14) A gate driver circuit described in any of items 1 to 13, integrated onto a single semiconductor substrate.

[0165] (Item 15) A bridge circuit including an upper arm and a lower arm, A gate driver circuit according to any one of items 1 to 14 that drives the bridge circuit, A motor drive device equipped with the following features.

[0166] (Item 16) Motor and, The motor drive device described in item 15 for driving the motor, An electronic device equipped with the following features. [Explanation of symbols]

[0167] 100 Switching Circuits 102 Power Line 104 output lines 106 Grounding line 110 Bridge Circuit 112 Upper Arm 114 Lower Arm MH High-Side Transistor ML Low-Side Transistor 200 Gate Driver Circuit 202 Bootstrap Line 203 Rectifier 204 Switching Line 206 Power Line 208 Grounding line 210 Control circuits 220 High-Side Driver DRH1, DRH2 High-Side Driver Unit DRL1, DRL2 Low-Side Driver Unit 250 Low-Side Driver 280 First Output Sensor 282 Second Output Sensor 284 High-side off-sensor 286 Low-side off-sensor 290 Timer Circuit VOUTDET1 First output detection signal VOUTDET2 Second output detection signal 300 Motor drive unit 302 Three-phase motor 310 Bridge Circuit 400 Gate Driver Circuit

Claims

1. A gate driver circuit that drives an inverter circuit including multiple high-side transistors connected in parallel, wherein the upper arm is a gate driver circuit, Multiple high-side driver units, each corresponding to the multiple high-side transistors, generate a high-side drive voltage at the gate of the corresponding high-side transistor, A first output sensor asserts a first output detection signal when the output voltage of the inverter circuit crosses a predetermined first threshold voltage, A control circuit that controls the plurality of high-side driver units in accordance with the output command, A timer circuit for measuring the timing of asserting the first output detection signal, Equipped with, Each of the aforementioned high-side driver units has an adjustable drive capability. The control circuit is a gate driver circuit that adjusts the driving capability of each high-side driver unit so that the timing of asserting the first output detection signal is synchronized when each of the plurality of high-side driver units is operated independently.

2. Each of the aforementioned high-side driver units is configured to supply turn-on current to the gate of the corresponding high-side transistor. The gate driver circuit according to claim 1, wherein the driving capability is the amount of the turn-on current.

3. The aforementioned multiple high-side driver units are configured to change the amount of the turn-on current over time. The gate driver circuit according to claim 2, wherein the amplitude of the waveform of the turn-on current is adjustable as the driving capability.

4. The gate driver circuit according to claim 3, wherein the control circuit increases the amount of the turn-on current generated by the plurality of high-side driver units in response to the assertion of the first output detection signal.

5. The system further comprises multiple high-side gate sensors, each corresponding to a plurality of high-side transistors, each asserting a high-side gate detection signal when the gate-source voltage of the corresponding high-side transistor exceeds a predetermined voltage. The gate driver circuit according to claim 3 or 4, wherein the control circuit reduces the amount of the turn-on current generated by the corresponding high-side gate driver in response to the assertion of each high-side gate detection signal.

6. The lower arm of the inverter circuit includes a plurality of low-side transistors connected in parallel. The aforementioned gate driver circuit is The above-mentioned multiple low-side transistors are each provided with multiple low-side driver units that generate a low-side drive voltage at the gate of the corresponding low-side transistor, A second output sensor asserts a second output detection signal when the output voltage of the inverter circuit crosses a predetermined third threshold voltage, Furthermore, The control circuit controls the plurality of low-side driver units in accordance with the output command. Each of the aforementioned low-side driver units has an adjustable driving capacity. The timer circuit measures the timing of asserting the second output detection signal, The gate driver circuit according to any one of claims 1 to 3, wherein the control circuit adjusts the driving capability of each low-side driver unit so that the timing of asserting the second output detection signal is synchronized when each of the plurality of low-side driver units is operated independently.

7. Each of the aforementioned low-side driver units is configured to supply turn-on current to the gate of the corresponding low-side transistor. The gate driver circuit according to claim 6, wherein the driving capability is the amount of the turn-on current.

8. The aforementioned multiple low-side driver units are configured to change the amount of the turn-on current over time. The gate driver circuit according to claim 7, wherein the amplitude of the waveform of the turn-on current is adjustable as the driving capability.

9. The gate driver circuit according to claim 8, wherein the control circuit increases the amount of the turn-on current generated by the plurality of low-side driver units in response to the assertion of the second output detection signal.

10. The system further comprises multiple low-side gate sensors, each corresponding to the multiple low-side transistors, which assert a low-side gate detection signal when the gate-source voltage of the corresponding low-side transistor exceeds a predetermined voltage. The gate driver circuit according to claim 8, wherein the control circuit reduces the amount of the turn-on current generated by the corresponding low-side gate driver in response to the assertion of each low-side gate detection signal.

11. The gate driver circuit according to any one of claims 1 to 3, wherein the plurality of high-side transistors are SiC transistors.

12. The gate driver circuit according to any one of claims 1 to 3, wherein the plurality of high-side transistors are Si transistors.

13. A gate driver circuit that drives an inverter circuit including multiple low-side transistors connected in parallel, wherein the lower arm is a gate driver circuit, The above-mentioned multiple low-side transistors are each provided with multiple low-side driver units that generate a low-side drive voltage at the gate of the corresponding low-side transistor, A second output sensor asserts a second output detection signal when the output voltage of the inverter circuit crosses a predetermined third threshold voltage, A control circuit that controls the plurality of low-side driver units in accordance with the output command, A timer circuit for measuring the timing of asserting the second output detection signal, Equipped with, Each of the aforementioned low-side driver units has an adjustable driving capacity. The control circuit is a gate driver circuit that adjusts the driving capability of each low-side driver unit so that the timing of asserting the second output detection signal is synchronized when each of the plurality of low-side driver units is operated independently.

14. A gate driver circuit according to any one of claims 1 to 3, which is integrated on a single semiconductor substrate.

15. A bridge circuit including an upper arm and a lower arm, A gate driver circuit according to any one of claims 1 to 3 for driving the bridge circuit, A motor drive device equipped with the following features.

16. Motor and, A motor drive device according to claim 15 for driving the motor, An electronic device equipped with the following features.

Images