Semiconductor equipment

Abstract

The objective is to provide a semiconductor device. [Solution] According to the embodiment, the laminate comprises a substrate, a plurality of wiring layers and an insulating layer on the substrate, a plurality of laminates formed by alternately stacking the plurality of wiring layers and a plurality of insulating layers along a first direction, and a columnar body extending in the first direction within each laminate and having a block insulating film, a charge storage film, a tunnel insulating film and a semiconductor film provided on the plurality of wiring layers and a plurality of insulating layers in a second direction, a hole formed in each laminate that extends in the first direction and accommodates the columnar body, and a portion of the hole having an inner diameter that changes continuously along the first direction, and the thickness of at least one of the block insulating film, charge storage film and tunnel insulating film being larger in the position where the inner diameter of the hole is small compared to the position where the inner diameter of the hole is large, and smaller in the position where the inner diameter of the hole is large.

Description

Technical Field

[0001] An embodiment relates to a semiconductor device.

Background Art

[0002] In recent years, semiconductor devices in which memory cells are three-dimensionally integrated have been proposed. In such a semiconductor device, a through hole is formed in a stacked body in which insulating layers and conductive layers are alternately stacked, and a memory layer and a silicon layer capable of storing charges are formed on the inner surface of the through hole, whereby a memory cell is formed between the silicon layer and the conductive layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor device with improved uniformity of write voltage.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment comprises a substrate, a plurality of laminates, and a columnar body. The laminates are provided on the substrate and have a plurality of wiring layers and a plurality of insulating layers, with the plurality of wiring layers and the plurality of insulating layers alternately stacked along a first direction. The columnar body extends through each of the laminates in the first direction. In a second direction intersecting the first direction, the columnar body has a block insulating film provided on the plurality of wiring layers and the plurality of insulating layers. In the second direction, the columnar body has a charge storage film provided on the block insulating film. In the second direction, the columnar body has a tunnel insulating film provided on the charge storage film. In the second direction, the columnar body has a semiconductor film provided on the tunnel insulating film. Each of the laminates has a hole formed therein that extends in the first direction and accommodates the columnar body. The hole has a portion in which the inner diameter changes continuously along the first direction. Of the block insulating film, the charge storage film, and the tunnel insulating film, the thickness of at least one of them has an inverse correlation, such that the thickness is larger at the location with a smaller inner diameter of the hole and smaller at the location with a larger inner diameter of the hole, when compared to the location with a smaller inner diameter of the hole and the location with a larger inner diameter of the hole. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a block diagram showing an example of the configuration of a memory system according to the first embodiment. [Figure 2] Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 3] Figure 3 is a perspective view showing an example of the appearance of a semiconductor memory device according to the first embodiment. [Figure 4] Figure 4 is a perspective view showing an overview of the bonding structure of the semiconductor memory device according to the first embodiment. [Figure 5] Figure 5 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to the first embodiment. [Figure 6]Figure 6 is a plan view showing an example of a planar layout in the memory cell region of a memory cell array provided in a semiconductor memory device according to the first embodiment. [Figure 7] Figure 7 is a cross-sectional view along line VII-VII in Figure 6, showing an example of the cross-sectional structure in the memory region of a memory cell array in a semiconductor memory device according to the first embodiment. [Figure 8] Figure 8 shows an example of the vertical cross-sectional structure of a columnar body provided in the memory area. [Figure 9] Figure 9 shows an example of a cross-sectional structure of a columnar body provided in the memory area. [Figure 10A] Figure 10A is a cross-sectional view showing an example of a memory hole formed in the memory cell region. [Figure 10B] Figure 10B is a cross-sectional view showing the state in which a block oxide film has been formed on the memory hole. [Figure 10C] Figure 10C is a cross-sectional view showing the same block oxide film after its thickness has been adjusted by slimming. [Figure 11] Figure 11 is a partially enlarged cross-sectional view showing an example of the cross-sectional structure of memory holes and block oxide film in the memory region of the memory system according to the second embodiment. [Figure 12] Figure 12 is a partially enlarged cross-sectional view showing an example of the cross-sectional structure of memory holes and block oxide film in the memory region of a memory system according to the third embodiment. [Modes for carrying out the invention]

[0007] The semiconductor devices according to each embodiment will be described in detail below with reference to the attached drawings. The following drawings are schematic, and the dimensions and proportions shown in the drawings are not necessarily the same as those of actual devices. Furthermore, the present invention is not limited to these embodiments. In the following description, components having substantially the same function and configuration will be denoted by the same reference numeral. In the following description, "connected" to another second element means that the first element is connected to the second element indirectly, either through an intermediate element that is always or selectively conductive, or directly without an intermediate element.

[0008] "First Embodiment" A semiconductor device according to the first embodiment will now be described. The semiconductor device is, for example, a non-volatile semiconductor memory device (semiconductor memory) in which a plurality of memory cells are arranged in a three-dimensional direction. 1.1 Configuration 1.1.1 Memory System A semiconductor memory device according to the first embodiment will now be described. Figure 1 is a block diagram showing an example of the configuration of a memory system according to the first embodiment. Memory system 1 is a memory device configured to be connected to an external host device (not shown). Memory system 1 is, for example, an SD TM The memory is a card-like memory card, UFS (Universal Flash Storage), or SSD (Solid State Drive). The memory system 1 includes a memory controller 2 and a semiconductor storage device 3.

[0009] The memory controller 2 is composed of an integrated circuit, such as a System on a Chip (SoC). The memory controller 2 controls the semiconductor memory device 3 based on requests from an external host device. Specifically, the memory controller 2 writes data requested to be written by the external host device to the semiconductor memory device 3. The memory controller 2 also reads data requested to be read from the semiconductor memory device 3 and outputs it to the external host device.

[0010] The semiconductor memory device 3 is, for example, a NAND flash memory capable of storing data non-volatilely. Communication between the memory controller 2 and the semiconductor memory device 3 complies with, for example, an SDR (Single Data Rate) interface, a toggle DDR (Double Data Rate) interface, or an ONFI (Open NAND Flash Interface).

[0011] 1.1.2 Semiconductor Memory Device Continuing, referring to the block diagram shown in FIG. 1, the internal configuration of the semiconductor memory device 3 according to the first embodiment will be described. The semiconductor memory device 3 includes, for example, a memory cell array 10, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0012] The memory cell array 10 is a set of memory cell transistors and a set of components connected to the memory cell transistors. The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). A block BLK is an aggregate of a plurality of memory cell transistors capable of storing data non-volatily. A block BLK is used, for example, as an erasure unit when erasing the data stored in the memory cell transistors. Also, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell transistor is associated with, for example, a combination of one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0013] The input / output circuit 11 is an interface circuit that controls the transmission and reception of input / output signals between the memory controller 2. The input / output signals include, for example, data DAT, command CMD, address information ADD, and status information STA. The input / output circuit 11 inputs and outputs data DAT between the sense amplifier module 17 and the memory controller 2 respectively. The input / output circuit 11 outputs each of the command CMD and address information ADD transferred from the memory controller 2 to the register 13. The input / output circuit 11 outputs the status information STA transferred from the register 13 to the memory controller 2.

[0014] The logic control circuit 12 receives control signals input from the memory controller 2. Based on the control signals, the logic control circuit 12 controls each of the input / output circuit 11 and the sequencer 14. For example, the logic control circuit 12 notifies the input / output circuit 11 that the input / output signals received by the input / output circuit 11 are a command CMD, address information ADD, etc. The logic control circuit 12 commands the input / output circuit 11 to input or output the input / output signals. The logic control circuit 12 controls the sequencer 14 to enable the semiconductor memory device 3. Also, the logic control circuit 12 outputs a signal indicating whether the semiconductor memory device 3 is in a ready state or a busy state to the memory controller 2.

[0015] The register 13 temporarily stores the command CMD, address information ADD, and status information STA. The command CMD includes, for example, commands to cause the sequencer 14 to execute read operations, write operations, erase operations, etc. The address information ADD includes, for example, block address BA, page address PA, and column address CA. For example, the block address BA, page address PA, and column address CA are each used for the selection of the block BLK, word line, and bit line respectively. The status information STA is updated based on the control of the sequencer 14 and transferred to the input / output circuit 11.

[0016] The sequencer 14 controls the overall operation of the semiconductor memory device 3. For example, based on the command CMD stored in register 13, the sequencer 14 controls the driver module 15, the row decoder module 16, the sense amplifier module 17, etc., and performs read operations, write operations, erase operations, etc.

[0017] The driver module 15 generates multiple voltages of different magnitudes used in read, write, and erase operations. The driver module 15 supplies the generated voltages to the row decoder module 16 and the sense amplifier module 17, etc. The driver module 15 also applies the generated voltages to the signal lines corresponding to the word lines selected based on the page address PA stored in register 13, for example.

[0018] The row decoder module 16 selects a corresponding block BLK in the memory cell array 10 based, for example, on the block address BA stored in register 13. The row decoder module 16 then transfers, for example, the voltage of the signal line applied by the driver module 15 to the selected word line in the selected block BLK.

[0019] The sense amplifier module 17 includes a sense amplifier capable of determining data based on the voltage of the associated bit line, and a latch circuit for temporarily storing data. In a write operation, the sense amplifier module 17 applies a desired voltage to each bit line according to the write data DAT received from the input / output circuit 11. In a read operation, the sense amplifier module 17 determines the data stored in the memory cell transistor based on the magnitude of the bit line voltage. Subsequently, the sense amplifier module 17 transfers the determination result as read data DAT to the input / output circuit 11.

[0020] 1.1.3 Circuit configuration of memory cell array Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array provided in the semiconductor memory device 3 according to the first embodiment. Figure 2 shows a block BLK. The block BLK includes, for example, a plurality of string units STR (e.g., four STR0 to STR3).

[0021] Each string unit STR contains multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS contains memory cell transistors MT0 to MTn and selection transistors ST1 and ST2. Each memory cell transistor MT contains a control gate and a charge storage unit. The control gate of the memory cell transistor MT is connected to one of the word lines WL0 to WLn. Each memory cell transistor MT stores charge in the charge storage unit in accordance with the voltage applied to the control gate via the word line WL, thereby non-volatilely retaining data.

[0022] The drain of the drain-side selection transistor ST1 is connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side selection transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MTn. The control gate of the drain-side selection transistor ST1 is connected to one of the drain-side selection gate lines SGD0 to SGD3. The drain-side selection transistor ST1 is electrically connected to the row decoder module 16 via the drain-side selection gate line SGD. The drain-side selection transistor ST1 connects the NAND string NS and the bit line BL when a predetermined voltage is applied to the corresponding drain-side selection gate line SGD.

[0023] The drain of the source-side selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MTn. The source of the source-side selection transistor ST2 is connected to the source line SL. The control gate of the source-side selection transistor ST2 is connected to one of the source-side selection gate lines SGS0 to SGS3. The source-side selection transistor ST2 connects the NAND string NS to the source line SL when a predetermined voltage is applied to the source-side selection gate line SGS. Alternatively, the source-side selection gate line SGS0 may be divided by component SSE as shown in Figure 7. In this case, the left source-side selection gate line SGS0 and the right source-side selection gate line SGS0 in Figure 7 may be connected to separate power supplies and controlled individually.

[0024] In the same block BLK, the control gates of memory cell transistors MT0 to MTn are commonly connected to their respective word lines WL0 to WLn. In the same string unit STR, the control gate of drain-side selection transistor ST1 is commonly connected to its corresponding drain-side selection gate line SGD. The control gate of source-side selection transistor ST2 is commonly connected to its corresponding source-side selection gate line SGS. In the memory cell array 10, the bit line BL is shared by multiple string units STR, each assigned the same column address as a NAND string NS.

[0025] Each of the word lines WL0 to WLn is provided for each block BLK. The source line SL is shared, for example, between multiple block BLKs. A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit STR is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0026] The circuit configuration of the memory cell array 10 in the semiconductor memory device 3 according to the first embodiment is not limited to the above description. For example, the number of string units STR included in each block BLK can be designed to be any number. However, it is desirable that the number of string units STR included in each block BLK be an even number. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to be any number.

[0027] 1.1.4 Appearance of semiconductor memory devices The semiconductor memory device 3 according to the first embodiment is formed by bonding together two semiconductor circuit boards, each having a semiconductor circuit formed on it, and then separating the bonded semiconductor circuit boards chip by chip. That is, the semiconductor memory device 3 according to the first embodiment includes a structure formed by bonding semiconductor substrates W1 and W2 together. Each of the semiconductor substrates W1 and W2 is, for example, a silicon substrate. The following explanation describes the case where the semiconductor substrate W2 is removed during the manufacturing process of the semiconductor memory device 3. However, depending on the structure of the memory cell array 10, a portion of the semiconductor substrate W2 may remain after bonding.

[0028] Figure 3 is a perspective view showing an example of the appearance of a semiconductor memory device according to the first embodiment. Hatching has been added to Figure 3 to improve the visibility of the drawing, but this does not necessarily relate to the material or characteristics of the components to which the hatching has been added. As shown in Figure 3, the semiconductor memory device 3 has a structure in which, for example, a semiconductor substrate W1, a control circuit layer 100, a junction layer B1, a junction layer B2, a memory layer 200, and a wiring layer 300 are stacked in order.

[0029] In the following explanation, the plane on which the semiconductor substrate W1 is stretched is defined as the XY plane. Of the directions in which the stacked structure is stacked, the direction from the semiconductor substrate W1 toward the wiring layer 300 is defined as the Z1 direction, and the direction from the wiring layer 300 toward the semiconductor substrate W1 is defined as the Z2 direction. The Z1 and Z2 directions are approximately perpendicular to the semiconductor substrate W1. When the Z1 and Z2 directions are not distinguished, each of them is simply referred to as the Z direction. The Z direction is also called the first direction.

[0030] The control circuit layer 100 includes a control circuit formed using a semiconductor substrate W1. The semiconductor substrate W1 has impurity diffusion regions, etc., according to the design of the control circuit. The control circuit layer 100 includes, for example, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a driver module 15, a low decoder module 16, and a sense amplifier module 17.

[0031] The bonding layer B1 is formed using the semiconductor substrate W1. The bonding layer B1 includes a plurality of bonding pads that are electrically connected to the control circuit provided in the control circuit layer 100 and form a part of the semiconductor circuit.

[0032] The junction layer B2 is formed using a semiconductor substrate W2 (not shown). The junction layer B2 includes a plurality of junction pads that are electrically connected to the memory cell array 10 provided on the memory layer 200 and form a part of the semiconductor circuit.

[0033] The memory layer 200 includes a memory cell array 10 formed using a semiconductor substrate W2 (not shown).

[0034] The wiring layer 300 is formed after the semiconductor substrates W1 and W2 are bonded together. The wiring layer 300 includes wiring connected to semiconductor circuits provided on the memory layer 200, as well as a plurality of pads PD. The plurality of pads PD are exposed on the surface of the semiconductor memory device 3. The plurality of pads PD are used to connect the semiconductor memory device 3 to the memory controller 2, etc.

[0035] Figure 4 is a perspective view showing an overview of the bonding structure of the semiconductor memory device according to the first embodiment. The bonding of semiconductor substrates W1 and W2 will be explained using Figure 4.

[0036] As shown in Figure 4, the multiple bonding pads BP1 included in bonding layer B1 and the multiple bonding pads BP2 included in bonding layer B2 are connected to each other. As a result, the control circuit provided in the control circuit layer 100 and the memory cell array 10 provided in the memory layer 200 are electrically connected to each other via the bonding pads BP1 and BP2. The space between bonding layers B1 and B2 corresponds to the boundary between the layer formed using semiconductor substrate W1 and the layer formed using semiconductor substrate W2 (not shown).

[0037] 1.1.5 Structure of a memory cell array An example of the structure of the memory cell array 10 provided in the semiconductor memory device 3 according to the first embodiment is described below. In the following description, the X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction (first direction) is the direction orthogonal to the X and Y directions. The Z direction is equal to the thickness direction of the semiconductor substrate W1. The plane extending in the X and Z directions is called the XZ plane. The plane extending in the Y and Z directions is called the YZ plane. In the plan view, hatching is added as appropriate to improve the visibility of the drawing. The hatching added to the plan view is not necessarily related to the material or characteristics of the component to which the hatching is added. In the cross-sectional view, the illustration of the components is omitted as appropriate to improve the visibility of the drawing.

[0038] 1.1.5.1 Overview Figure 5 is a plan view showing an example of a planar layout of a memory cell array in a semiconductor memory device according to the first embodiment. In Figure 5, regions corresponding to six blocks BLK0 to BLK5 are shown. The sequential numbers at the end to distinguish the blocks BLK are assigned in ascending order from the top of the page. In the memory cell array 10, for example, the layout shown in Figure 5 is repeatedly arranged in the Y direction. As shown in Figure 5, the memory cell array 10 includes a plurality of members SLT and a plurality of members SHE. The planar layout of the memory cell array 10 is divided, for example, in the X direction into a memory area MA and an extraction area HA. ​​The extraction area HA is provided adjacent to the memory area MA.

[0039] The lead-out region HA is a region used for connecting the stacked wiring, which is composed of multiple wiring layers (e.g., word lines WL0 to WLn, and selection gate lines SGS0, SGS1, and SGD) stacked apart from each other in the Z direction, to the low decoder module 16.

[0040] Multiple SLT members each extend along the X direction and are aligned in the Y direction. Each SLT member crosses the memory area MA in the X direction in the boundary region between adjacent blocks BLK. In other words, each region demarcated by an SLT member corresponds to one block BLK in the memory cell array 10. Each SLT member has a structure in which, for example, an insulator and plate-shaped contacts are embedded. Each SLT member separates adjacent stacked wiring through it.

[0041] Multiple members SHE are arranged in the memory area MA. Each of the multiple members SHE corresponding to the memory area MA is provided across the memory area MA in the X direction and aligned in the Y direction. The ends of each member SHE corresponding to the memory area MA are included in the draw-out area HA. ​​For example, in the memory area MA, three members SHE are each arranged between adjacent members SLT in the Y direction. Each combination of the regions demarcated by members SLT and SHE in the memory area MA corresponds to one string unit STR in the memory cell array 10. Each member SHE has, for example, a structure with an embedded insulator. Each member SHE separates adjacent selection gate lines SGD through the member SHE.

[0042] The planar layout of the memory cell array 10 in the semiconductor memory device 3 according to the first embodiment is not limited to the layout described above. For example, the number of members SHE arranged between adjacent members SLT can be designed to be any number. The number of string units STR formed between adjacent members SLT can be changed based on the number of members SHE arranged between adjacent members SLT. It is desirable that the number of string units STR formed between adjacent members SLT be an even number. That is, it is desirable that the number of members SHE in a single block BLK be an odd number.

[0043] The lead-out region HA includes multiple lead-out sections HP. Each lead-out section HP is provided with a connection point to a contact in each wiring layer of the multilayer wiring. Each lead-out section HP is arranged in the Y direction and is provided for each block BLK.

[0044] 1.1.5.2 Memory Area (Flat layout) Figure 6 is a plan view showing an example of a planar layout in the memory area of ​​a memory cell array in a semiconductor memory device according to the first embodiment. In Figure 6, the structure of one block BLK within the memory area MA is shown as representative. As shown in Figure 6, in the memory area MA, the memory cell array 10 includes a plurality of columnar bodies (memory pillars) MP, a plurality of contacts CV, and a plurality of bit lines BL. In addition, each member SLT includes a contact LI and a spacer SP.

[0045] Each of the columnar members MP functions, for example, as a single NAND string NS. Multiple columnar members MP are arranged in a staggered pattern, for example, 19 rows in the Y direction, in the region between two adjacent members SLT. In the example shown in Figure 6, one member SHE overlaps each of the columnar members MP in the 5th, 10th, and 15th rows, counting from the top of the paper.

[0046] Multiple bit lines BL each extend in the Y direction and are aligned in the X direction. Each bit line BL is positioned to overlap with at least one columnar body MP for each string unit STR. In the example shown in Figure 6, two bit lines BL are positioned to overlap with one columnar body MP. If multiple bit lines BL overlap with a columnar body MP, one bit line BL and the corresponding columnar body MP are electrically connected via a contact CV. If only one bit line BL overlaps with a columnar body MP, that bit line BL and the corresponding columnar body MP are electrically connected via a contact CV.

[0047] For example, the contact CV between a columnar body MP in contact with member SHE and the corresponding bit line BL is omitted. In other words, the contact CV between a columnar body MP and a bit line BL in contact with two different selected gate lines SGD is omitted. The number and arrangement of columnar bodies MP and member SHE between adjacent member SLTs are not limited to the configuration shown in Figure 6 and can be changed as appropriate. For example, the number of bit lines BL overlapping each columnar body MP can be designed to be any number.

[0048] Contact LI is a conductor extending in the XZ plane. The lower surface of contact LI is in contact with a source wire SL (not shown). Spacer SP is an insulator provided on the side of contact LI. In other words, spacer SP is provided in contact with contact LI so as to sandwich it in the Y direction.

[0049] (Cross-sectional structure) Figure 7 is a cross-sectional view along line VII-VII in Figure 6, showing an example of the cross-sectional structure in the memory region of a memory cell array in a semiconductor memory device according to the first embodiment. As shown in Figure 7, the memory cell array 10 further includes wiring layers 21-25, insulating layers 40-46, and a component SSE. In the following description, the Z2 direction may be described as upward and the Z1 direction as downward.

[0050] The stacked wiring included in the memory cell array 10 includes a wiring layer 22 corresponding to the selected gate line SGS, a plurality of wiring layers 23 corresponding to word lines WL0 to WLn, and a wiring layer 24 corresponding to the selected gate line SGD.

[0051] In the example shown in Figure 7, two wiring layers 22 corresponding to the selected gate line SGS are provided. In the following description, the selection gate line SGS corresponding to the upper wiring layer 22 will be referred to as selection gate line SGSa, and the selection gate line SGS corresponding to the lower wiring layer 22 will be referred to as selection gate line SGSb. Hereafter, when selection gate lines SGSa and SGSb are not distinguished, they will simply be referred to as selection gate line SGS. Each of the selection gate lines SGSa and SGSb is connected to the gates of the selection transistors ST2a and ST2b, respectively. The selection transistors ST2a and ST2b function as a single selection transistor ST2. The wiring layer 22 corresponding to the selection gate line SGS may be one layer or may consist of three or more layers. Furthermore, if the wiring layer 22 corresponding to the selection gate line SGS is formed from multiple layers, the respective selection transistors ST2a and ST2b may be configured to function independently.

[0052] An insulating layer 41 is stacked on top of a semiconductor substrate (not shown), and further above, a plurality of wiring layers 22 and a plurality of insulating layers 42 are stacked alternately in sequence. In the example shown in Figure 7, two layers of wiring layers 22 and two layers of insulating layers 42 are stacked alternately. The plurality of wiring layers 22 are formed, for example, in a plate shape stretched along the X direction on the XY plane. Each wiring layer 22 is used as a selection gate line SGSa and SGSb. Each wiring layer 22 contains, for example, tungsten (W) or molybdenum (Mo). Each of the insulating layer 41 and the plurality of insulating layers 42 contains, for example, silicon oxide (SiO).

[0053] Multiple wiring layers 23 and multiple insulating layers 43 are alternately stacked above the uppermost insulating layer 42. In the example shown in Figure 7, n layers of wiring layers 23 and (n-1) layers of insulating layers 43 are alternately stacked. Each wiring layer 23 is formed, for example, as a plate stretched along the X direction on the XY plane. Each wiring layer 23 is used as a word line WL0 to WLn, in order from the wiring layer 22 side. Each wiring layer 23 contains, for example, tungsten. Each insulating layer 43 contains, for example, silicon oxide.

[0054] An insulating layer 44, another insulating layer 24, and another insulating layer 45 are stacked in this order above the uppermost wiring layer 23. The wiring layer 24 is formed, for example, as a plate stretched along the X direction on the XY plane. The wiring layer 24 is used as a selectable gate wire SGD. The wiring layer 24 contains, for example, tungsten. The insulating layers 44 and 45 contain, for example, silicon oxide.

[0055] A wiring layer 25 is laminated above the insulating layer 45. The wiring layer 25 is formed, for example, in a line extending along the Y direction. The wiring layer 25 is used as a bit line BL. In a region not shown, multiple wiring layers 25 are arranged along the X direction. The wiring layer 25 contains, for example, copper. An insulating layer 46 is laminated above the wiring layer 25. The insulating layer 46 is a layer connected to the bonding layer B2 and includes multiple wirings (not shown).

[0056] In Figures 3 and 4, after the semiconductor substrate W2 (not shown) is removed, a wiring layer 21 and an insulating layer 40 are provided below the insulating layer 41 in the Z1 direction in that order. The wiring layer 21 is formed, for example, in a plate shape stretched along the X direction on the XY plane. The wiring layer 21 is used as a source wire SL. The wiring layer 21 contains, for example, phosphorus-doped silicon. Furthermore, a wiring layer 300 shown in Figure 3 may be provided below the insulating layer 40. This wiring layer 300 includes a plurality of wirings (not shown).

[0057] Each of the columnar members MP is provided extending along the Z direction (first direction). The columnar members MP penetrate the wiring layers 22-24 and the insulating layers 41-44. In the example shown in Figure 7, the laminated structure of the wiring layer 23 and the insulating layer 43 on the side closer to the insulating layer 40 is referred to as the first laminate 51. The structure has a three-layer configuration in which the second laminate 52 and the third laminate 53 are laminated above the first laminate 51. In the example shown in Figure 7, a three-layer structure having first to third laminates 51 to 53 is illustrated and explained as an example of a laminated structure having multiple laminates. However, the number of laminates can be any number of layers, such as two or four or more.

[0058] The first laminate 51 includes insulating layers 41 and 42 and wiring layers 22 laminated thereon, and further includes wiring layers 22 and insulating layers 43 that are repeatedly laminated above them. The second laminate 52 is stacked on top of the first laminate 51 and has a structure in which wiring layers 23 and insulating layers 43 are repeatedly stacked. The third laminate 53 is laminated on top of the second laminate 52 and includes a structure in which wiring layers 23 and insulating layers 43 are repeatedly laminated, and further includes insulating layers 44 and wiring layers 24.

[0059] In the example shown in Figure 7, the repeating laminated structure of the wiring layer 23 and the insulating layer 43 has a three-layer structure consisting of a first laminate 51, a second laminate 52, and a third laminate 53 of predetermined thickness from the insulating layer 42 side. The first laminate 51 has a first columnar body MP1 that penetrates the first laminate 51 in the Z direction. The second laminate 52 has a second columnar body MP2 that penetrates the second laminate 52 in the Z direction. The third laminate 53 has a third columnar body MP3 that penetrates the third laminate 53 in the Z direction. The first columnar body MP1, the second columnar body MP2, and the third columnar body MP3 are connected in series in the Z direction in this order, functioning as a single columnar body (memory pillar) MP.

[0060] Each of the first to third columnar bodies MP1, MP2, and MP3 includes a core film 30, a semiconductor film 31, and a multilayer film 32, as shown in Figure 9, for example. In each columnar body MP, the core film 30 is provided stretched along the Z direction. For example, the upper end of the core film 30 of the third columnar body MP3 is located within the insulating layer 45, and the lower end of the core film 30 of the first columnar body MP1 is located within the wiring layer 21. The core film 30 includes an insulator, such as silicon oxide. The semiconductor film 31 covers the periphery of the core film 30, for example. At the lower end of the first columnar body MP1, a portion of the semiconductor film 31 is in contact with the wiring layer 21. The semiconductor film 31 includes, for example, silicon. The multilayer film 32 covers the sides of the semiconductor film 31, except for the portion where the semiconductor film 31 and the wiring layer 21 are in contact.

[0061] Figure 9 shows an example of a cross-section of a columnar body MP provided in a semiconductor memory device according to the first embodiment. More specifically, Figure 9 shows the cross-sectional structure of the columnar body MP in a layer parallel to the surface of a semiconductor substrate (not shown) and including a wiring layer 23. As shown in Figure 9, the laminated film 32 includes, for example, a tunnel insulating film 33, a charge storage film 34, and a block insulating film 35.

[0062] In a cross-section including the wiring layer 23, the core film 30 is provided, for example, in the central part of the columnar body MP. The semiconductor film 31 surrounds the sides of the core film 30. The tunnel insulating film 33 surrounds the sides of the semiconductor film 31. The charge storage film 34 surrounds the sides of the tunnel insulating film 33. The block insulating film 35 surrounds the sides of the charge storage film 34. The wiring layer 23 surrounds the sides of the block insulating film 35. In the columnar body MP, the core film 30, semiconductor film 31, tunnel insulating film 33, charge storage film 34, and block insulating film 35 are each continuous from one end to the other in the Z direction of the columnar body MP.

[0063] The semiconductor film 31, tunnel insulating film 33, charge storage film 34, and block insulating film 35 are formed to have a predetermined thickness in the XY direction (second direction), which is a direction intersecting the Z direction (first direction). Therefore, in the second direction, the block insulating film 35 is provided on a plurality of wiring layers 23 and a plurality of insulating layers 43. Similarly, in the second direction, the charge storage film 34 is provided on the block insulating film 35. In the second direction, the tunnel insulating film 33 is provided on the charge storage film 34. In the second direction, the semiconductor film 31 is provided on the tunnel insulating film 33.

[0064] The semiconductor film 31 is used as the channel (current path) for the memory cell transistors MT0 to MTn and the selection transistors ST1 and ST2. The tunnel insulating film 33 and the block insulating film 35 each contain, for example, silicon oxide. The charge storage film 34 has the function of storing charge and contains, for example, silicon nitride (SiN). With this configuration, each columnar body MP can function as a single NAND string NS.

[0065] The first to third columnar structures MP1, MP2, and MP3 contain memory cells as non-volatile semiconductor memory devices. These memory cells are, for example, charge-trap type memory cells. The core film 30 functions as a region where channels are formed. The wiring layer 23 functions as the control gate for the memory cell. The charge storage film 34 functions as a data storage layer that stores the charge injected from the core film 30. In other words, at the intersection of the core film 30 and each wiring layer 23, a memory cell is formed with a structure in which a control gate surrounds the channel.

[0066] The block insulating film 35 is an insulating layer that prevents the charge accumulated in the charge storage film 34 from diffusing to the wiring layer 23. The block insulating film 35 is, for example, a silicon oxide layer. The block insulating film 35 may have a multilayer structure having a layer containing a material having a higher dielectric constant than silicon oxide. For example, silicon nitride can be used as the high dielectric constant material.

[0067] In this embodiment, the cross-sectional area (XY cross-sectional area) of the first columnar body MP1, the second columnar body MP2, and the third columnar body MP3 all gradually increases along the XY plane from bottom to top. In other words, the inner diameter of the memory hole MH1 forming the first columnar body MP1 gradually increases along the XY plane from bottom to top. That is, the memory hole MH1 has a portion in which its inner diameter changes continuously from bottom to top. The first columnar body MP1, the second columnar body MP2, and the third columnar body MP3, which are arranged to extend in the Z direction, are connected and function as a single columnar body MP.

[0068] The first columnar body MP1 is formed in the first memory hole MH1 formed in the first laminate 51. The second columnar body MP2 is formed in the second memory hole MH2 formed in the second laminate 52. The third columnar body MP3 is formed in the third memory hole MH3 formed in the third laminate 53. Therefore, the upper end of the first memory hole MH1 and the lower end of the second memory hole MH2 are connected, and the two holes are continuous. The upper end of the second memory hole MH2 and the lower end of the third memory hole MH3 are connected, and the two holes are connected.

[0069] A first memory hole MH1 is formed in the first laminate 51, and a first columnar body MP1 is housed in the first memory hole MH1. A second memory hole MH2 is formed in the second laminate 52, and a second columnar body MP2 is housed in the second memory hole MH2. A third memory hole MH3 is formed in the third laminate 53, and a third columnar body MP3 is housed in the third memory hole MH3.

[0070] Figure 8 shows a simplified relative relationship between the laminates 51, 52, and 53 shown in Figure 7 and the memory holes MH1, MH2, and MH3 that penetrate them in the Z direction. Figure 8 also shows only the block insulating film 35 formed inside each memory hole MH1, MH2, and MH3. In Figure 8, the Z-direction scale is different from that of Figure 7, reducing the Z-direction lengths of the memory holes MH1, MH2, and MH3. Therefore, in Figure 8, the Z-direction thickness variation of the block insulating film 35 is exaggerated to the extent that it can be displayed.

[0071] As shown in Figure 8, the block insulating film 35 of the first columnar body MP1 is thinnest at the upper end 35a located at the upper end (Z2 direction end) of the first columnar body MP1, gradually increasing in thickness from the Z2 direction to the Z1 direction, with the lower end 35b located at the lower end (Z1 direction end) of the first columnar body MP1 being the thickest. In other words, the thickness of the block insulating film 35 in the first columnar body MP1 is inversely correlated with the diameter of the first columnar body MP1. To put it another way, the thickness of the block insulating film 35 in the first columnar body MP1 is inversely correlated with the inner diameter of the first memory hole MH1.

[0072] For example, in this embodiment, the thickness of the block insulating film 35 at the lower end of the first columnar body MP1 is about 1 nm or more thicker than the thickness of the block insulating film 35 at the upper end of the first columnar body MP1. For example, in this embodiment, the inner diameter of the first memory hole MH1 has a difference of 10 nm or more when comparing the inner diameter at the lower end (minimum inner diameter position) of the first memory hole MH1 with the inner diameter at the upper end (maximum inner diameter position). That is, the maximum inner diameter and minimum inner diameter of the first memory hole MH1 have a difference of 10 nm or more.

[0073] Since the upper end of the first memory hole MH1 has a larger diameter than the lower end of the second memory hole MH2, a circumferential step portion 54 is formed in the XY plane direction at the upper end of the first memory hole MH1. The thickness of the protruding portion 35c of the block insulating film 35, which is formed along the inner surface of this circumferential step portion 54, is uniform. The protruding portion 35c connects the upper end of the block insulating film 35 of the first columnar body MP1 and the lower end of the block insulating film 35 of the second columnar body MP2. In the block insulating film 35, the thickness of the protruding portion 35c is smaller than the thickness of the upper end portion 35a of the block insulating film 35 on the first memory hole MH1 side. For example, in this embodiment, the inner diameter of the upper end of the first memory hole MH1 is 10 nm or more larger than the inner diameter of the lower end of the second memory hole MH2. For example, the film thickness of the block insulating film 35 located at the upper end of the first memory hole MH1 and the film thickness of the block insulating film 35 located at the lower end of the second memory hole MH2 have a film thickness difference of 1 nm or more. For example, the film thickness of the block insulating film 35 located at the lower end of the second memory hole MH2 is greater than the film thickness of the block insulating film 35 located at the upper end of the first memory hole MH1.

[0074] The block insulating film 35 of the second columnar body MP2 is thinnest at the upper end 35d located at the upper end (Z2 direction end) of the second columnar body MP2, and gradually thickens along the Z1 direction from the Z2 direction, with the lower end 35e located at the lower end (Z1 direction end) of the second columnar body MP2 being the thickest. In other words, the thickness of the block insulating film 35 in the second columnar body MP2 is inversely correlated with the diameter of the second columnar body MP2. To put it another way, the thickness of the block insulating film 35 in the second columnar body MP2 is inversely correlated with the inner diameter of the second memory hole MH2.

[0075] For example, in this embodiment, the thickness of the block insulating film 35 at the lower end of the second columnar body MP2 is about 1 nm or more thicker than the thickness of the block insulating film 35 at the upper end of the second columnar body MP2. For example, in this embodiment, the inner diameter of the second memory hole MH2 has a difference of 10 nm or more when comparing the inner diameter of the lower end of the second memory hole MH2 with the inner diameter of the upper end. That is, the maximum inner diameter and the smallest inner diameter of the second memory hole MH2 have a difference of 10 nm or more.

[0076] Since the upper end of the second memory hole MH2 has a larger diameter than the lower end of the third memory hole MH3, a circumferential step portion 54 is formed in the XY plane direction at the upper end of the second memory hole MH2. The thickness of the protruding portion 35f of the block insulating film 35 formed along the inner surface of the circumferential step portion 54 is uniform. The protruding portion 35f connects the upper end of the block insulating film 35 of the second columnar body MP2 and the lower end of the block insulating film 35 of the third columnar body MP3. In the block insulating film 35, the thickness of the protruding portion 35f is smaller than the thickness of the upper end portion 35d of the block insulating film 35 on the second memory hole MH2 side.

[0077] The block insulating film 35 of the third columnar body MP3 is thinnest at the upper end 35g located at the upper end (Z2 direction end) of the third columnar body MP3, and gradually thickens along the Z1 direction from the Z2 direction, with the lower end 35h located at the lower end (Z1 direction end) of the third columnar body MP3 being the thickest. In other words, the thickness of the block insulating film 35 in the third columnar body MP3 is inversely correlated with the diameter of the third columnar body MP3. To put it another way, the thickness of the block insulating film 35 in the third columnar body MP3 is inversely correlated with the inner diameter of the third memory hole MH3.

[0078] For example, in this embodiment, the thickness of the block insulating film 35 at the lower end of the third columnar body MP3 is about 1 nm or more thicker than the thickness of the block insulating film 35 at the upper end of the second columnar body MP2. For example, in this embodiment, the inner diameter of the third memory hole MH3 has a difference of 10 nm or more when comparing the inner diameter of the lower end of the third memory hole MH3 with the inner diameter of the upper end. That is, the maximum inner diameter and the smallest inner diameter of the third memory hole MH3 have a difference of 10 nm or more. For example, in this embodiment, the inner diameter of the upper end of the second memory hole MH2 is 10 nm or more larger than the inner diameter of the lower end of the third memory hole MH3. For example, the film thickness of the block insulating film 35 located at the upper end of the second memory hole MH2 and the film thickness of the block insulating film located at the lower end of the third memory hole MH3 have a film thickness difference of 1 nm or more. For example, the film thickness of the block insulating film 35 located at the lower end of the third memory hole MH3 is greater than the film thickness of the block insulating film 35 located at the upper end of the second memory hole MH2.

[0079] The film thickness of the block insulating film 35 formed on the first columnar body MP1, the second columnar body MP2, and the third columnar body MP3 has been described above. In contrast, the tunnel insulating film 33 and the charge storage film 34 may have similar film thickness relationships in each columnar body MP. Alternatively, the combined film thickness of the block insulating film 35 and the tunnel insulating film 33 may be similar to the film thickness relationship described in the comparison of the block insulating films 35. The combined film thickness of the block insulating film 35 and the charge storage film 34 may be similar to the film thickness relationship described in the comparison of the block insulating films 35. The combined film thickness of the tunnel insulating film 33 and the charge storage film 34 may be similar to the film thickness relationship described in the comparison of the block insulating films 35. The combined film thickness of the block insulating film 35, the tunnel insulating film 33, and the charge storage film 34 may be similar to the film thickness relationship described in the comparison of the block insulating films 35.

[0080] For example, the tunnel insulating film 33 of the first columnar body MP1 is thinnest at the upper end (Z2 direction end) of the first columnar body MP1, gradually increasing in thickness from the Z2 direction to the Z1 direction, and is thickest at the lower end (Z1 direction end) of the first columnar body MP1. The tunnel insulating films 33 formed on the second columnar body MP2 and the third columnar body MP3 have a similar film thickness relationship. For example, the charge storage film 34 of the first columnar body MP1 is thinnest at the upper end (Z2 direction end) of the first columnar body MP1, gradually increasing in thickness from the Z2 direction to the Z1 direction, with the lower end (Z1 direction end) of the first columnar body MP1 being the thickest. The charge storage films 34 formed on the second columnar body MP2 and the third columnar body MP3 have a similar film thickness relationship.

[0081] Incidentally, the relationship between the first memory hole MH1, the second memory hole MH2, and the film thickness of the block insulating film 35 shown in Figures 7 and 8 can be described as follows. The first memory hole (one memory hole) MH1 and the second memory hole (the other memory hole) MH2 are adjacent to each other in the Z direction (first direction). The first memory hole MH1 is located close to the semiconductor substrate W1, while the second memory hole MH2 is located far from the semiconductor substrate W1. At the connection point between the first memory hole MH1 and the second memory hole MH2, there is a portion where the inner diameters of the first memory hole MH1 and the second memory hole MH2 change discontinuously.

[0082] A block insulating film 35 with the aforementioned film thickness relationship is formed in the first memory hole MH1 and the second memory hole MH2, which have this relationship. In comparison to the position where the inner diameter of the memory holes MH1 and MH2 is small, the thickness of the block insulating film 35 is larger at the position where the inner diameter of the memory holes MH1 and MH2 is small, and smaller at the position where the inner diameter of the memory holes MH1 and MH2 is large.

[0083] For example, at the connection point between the first memory hole MH1 and the second memory hole MH2, the difference between the maximum inner diameter of the first memory hole MH1 and the minimum inner diameter of the second memory hole MH2 can be set to 10 nm or more. For example, the difference between the thickness of the block insulating film 35 formed at the maximum inner diameter position of the first memory hole MH1 and the thickness of the block insulating film 35 formed at the minimum inner diameter position of the second memory hole MH2 can be set to 1 nm or more. For example, this relationship can be similarly established in relation to the second memory hole MH2, the third memory hole MH3, and the film thickness of the block insulating film 35. For example, this relationship does not apply only to the block insulating film 35, but may also apply to at least one or more of the block insulating film 35, the charge storage film 34, and the tunnel insulating film 33, as described above.

[0084] In the columnar body MP shown in Figure 7, the portion where the wiring layer 22 intersects with columnar body MP1 functions as a selection transistor ST2. The portions where columnar bodies MP1 to MP3 intersect with each wiring layer 23 function as memory cell transistors MT0 to MTn, respectively. The portion where the wiring layer 24 intersects with columnar body MP3 functions as a selection transistor ST1.

[0085] A columnar contact CV is provided on the upper surface of the semiconductor film 31 within the columnar body MP. In the region shown in Figure 7, two of the six columnar bodies MPs are shown with two corresponding contact CVs. For columnar bodies MP in this region that do not overlap with member SHE and to which no contact CV is connected, another contact CV is connected in a region not shown.

[0086] Each contact CV has a wiring layer 25, i.e., one bit wire BL, in contact with its upper surface. One contact CV is connected to each wiring layer 25 in each of the spaces separated by members SLT and SHE. In other words, each wiring layer 25 is electrically connected, for example, to one columnar body MP in each region between adjacent members SLT and SHE, and to one columnar body MP in each region between two adjacent members SHE.

[0087] The SLT members are formed, for example, to extend along the XZ plane. Each SLT member penetrates the wiring layers 22-24 and the insulating layers 41-44. For example, each SLT member has a width in the Y direction that increases from bottom to top.

[0088] Within the component SLT, the contact LI is provided so as to extend along the XZ plane, and the spacer SP is provided between the contact LI and the wiring layers 22-24 and the insulating layers 41-45. The upper end of the contact LI is located, for example, within the insulating layer 45. The lower end of the contact LI is in contact with, for example, the wiring layer 21. Note that the contact LI may be omitted depending on the structure of the memory cell array 10.

[0089] Component SHE is formed, for example, as a plate extending along the XZ plane, and divides the wiring layer 24. The upper end of component SHE is located within the insulating layer 45. The lower end of component SHE is located, for example, within the uppermost insulating layer 43. Component SHE includes an insulator such as silicon oxide. The upper end of component SHE and the upper end of component SLT may or may not be aligned. Similarly, the upper end of component SHE and the upper end of columnar body MP may or may not be aligned.

[0090] The component SSE is formed in memory areas MA1 and MA2 as a plate extending along the XZ plane, for example, and divides a plurality of wiring layers 22. For example, the upper end of the component SSE may be located at the boundary between the uppermost insulating layer 42 and the lowermost wiring layer 23, or it may be located inside the uppermost insulating layer 42. For example, the lower end of the component SSE may be located at the boundary between the wiring layer 21 and the insulating layer 41, or it may be located inside the insulating layer 41. Preferably, the component SSE is provided in memory areas MA1 and MA2 at a position overlapping with one component SHE in the Z direction. The component SSE includes an insulator such as silicon oxide. The lower end of the component SSE and the lower end of the component SLT may or may not be aligned.

[0091] 1.2 Effects according to the first embodiment According to the first embodiment, the thickness of the block insulating film 35 in the first columnar body MP1 is inversely correlated with the diameter of the first columnar body MP1. The degree of electric field concentration acting on the block insulating film 35 differs between the larger and smaller diameter portions of the first columnar body MP1. The degree of electric field concentration is lower in the larger diameter portions of the first columnar body MP1, but higher in the smaller diameter portions. As a result, the degree of electric field concentration acting on the block insulating film 35 differs between the larger and smaller diameter portions of the first columnar body MP1. For example, writing becomes easier in areas with high electric field concentration and more difficult in areas with low electric field concentration.

[0092] In the structure of the first embodiment, as clearly shown in Figure 8, the block insulating film 35 is made thicker in the region where the diameter of the first columnar body MP1 is small and the electric field concentration is high, and thinner in the region where the diameter of the first columnar body MP1 is large and the electric field concentration is low. Making the block insulating film 35 thicker allows the electric field to be mitigated by the presence of the thick block insulating film 35. Therefore, writing can be slowed down in the region where the diameter of the first columnar body MP1 is small and the electric field concentration is high. This makes it possible to match the writing conditions in the region where the diameter of the first columnar body MP1 is large and the electric field concentration is low. Thus, the problem of inconsistent data writing to the memory depending on the size of the first columnar body MP1 can be solved. In other words, it is possible to promote the uniformity of the writing voltage in the memory cell array 10.

[0093] This effect can be obtained not only with the first columnar body MP1, but also with the second columnar body MP2 and the third columnar body MP3, which have a similar structure to the first columnar body MP1. Therefore, a similar effect can be obtained throughout the entire memory cell array 10 equipped with columnar MPs.

[0094] Furthermore, when reading data from memory, current semiconductor memory devices use a predetermined voltage lower than the write voltage to read the data. In this case, even if the read voltage is lower than the write voltage, a small amount of writing may occur. Depending on the diameter of the aforementioned columnar body MP, if the electric field concentration is high in the smaller diameter portion, the risk of a small amount of writing increases. In contrast, in the structure provided with the aforementioned first columnar body MP1, second columnar body MP2, and third columnar body MP3, the electric field strength can be adjusted according to the thickness of the block insulating film 35. Therefore, the problem of invalid writing, which may occur slightly during reading, can be reduced.

[0095] In current semiconductor memory devices, it has been achieved to create stacks of 100 or more wiring layers 23 and insulating layers 43. When forming memory holes MH in such a laminate, there is a limit to the number of layers that can be used. For this reason, currently, as shown in Figure 7, a structure in which a first laminate 51, a second laminate 52, a third laminate 53, etc. are stacked, or a structure with even more layers is used. Then, after forming the first laminate 51, the first memory hole MH1 is formed, after forming the second laminate 52, the second memory hole MH2 is formed, and after forming the third laminate 53, the third memory hole MH3 is formed, thereby creating a multilayer structure.

[0096] When etching is performed on such a thick laminated structure to form memory holes MH, the difference in processing time and the characteristics of the etching solution inevitably results in holes with smaller inner diameters at the bottom and larger inner diameters at the top of the laminate. Consequently, the first to third columnar bodies MP1, MP2, and MP3 formed in the first to third laminates 51, 52, and 53 also have the cross-sectional shapes illustrated in Figure 8. Therefore, by adopting the structure of this embodiment, it is possible to promote the uniformity of the writing voltage even in a multilayered stacked structure.

[0097] Up to this point, the explanation has focused on the effect of setting the film thickness of the block insulating film 35 in an inverse correlation as described above. However, the same inverse correlation may be applied not only to the block insulating film 35, but also to the tunnel insulating film 33 and the charge storage film 34. By setting the film thickness of the tunnel insulating film 33 and the film thickness of the charge storage film 34 in an inverse correlation as described above, the same effect as described above can be obtained. Furthermore, although the embodiments described so far have described an example in which this embodiment is applied to a laminated structure in which three laminates are stacked, the number of stacked laminates may be two or four or more, and there is no limit to the number of stacks.

[0098] 1.3 About Block Insulating Film Figure 10A shows one example of the shape of a memory hole MH0 formed in a part of the laminate. The memory hole MH0 shown in Figure 10A corresponds to the memory hole MH shown in Figure 9 and is shown as a cross-section of the portion that penetrates the wiring layer 23. The cross-sectional contour of this memory hole MH0 is not a circular shape, but rather a shape with varying radii of curvature. Memory holes MH0 with such varied radii of curvature can occur in memory cells with a microstructure of several tens of nanometers in inner diameter.

[0099] When forming a block insulating film on the inner surface of the memory hole MH0, a thick film 55 of the material constituting the block insulating film is formed in advance, as shown in Figure 10B. Then, this thick film 55 is subjected to a slimming process to form a block insulating film 56 of the desired thickness shown in Figure 10C. In this case, the block insulating film 56 is formed such that the variation in the radius of curvature on the inner side of the cross-sectional contour of the block insulating film 56 is smaller than the variation in the radius of curvature shown in the cross-sectional contour of the memory hole MH0 formed in the wiring layer 23 of the laminate. If the block insulating film 56 has a small variation in the radius of curvature on the inner circumference, it will result in a desirable structure as follows. For example, the film thickness will remain thicker in areas where the radius of curvature of the outer contour of the block insulating film 56 is small (indicated by the symbol a in Figure 10C) due to the slimming process. Also, the film thickness will become thinner (the variation in curvature will decrease) in areas where the radius of curvature of the outer contour of the block insulating film 56 is large (indicated by the symbol b in Figure 10C). As a result, the way in which the electric field is applied to the channel (in the XY direction and the circumferential direction) can be made uniform, resulting in a desirable structure.

[0100] Furthermore, the slimming process after forming the thick film is not limited to the block insulating film 56, but can also be applied to either the tunnel insulating film 33 or the charge storage film 34 used in the structure of the first embodiment. Therefore, by applying the slimming process, the curvature variation can be reduced in both the tunnel insulating film 33 and the charge storage film 34, as described above. As a result, the way the electric field is applied to the channel can be made uniform. Therefore, by performing a slimming process after thick film formation, variations in the radius of curvature on the inner side can be suppressed in at least one of the tunnel insulating film 33, charge storage film 34, and block insulating film 56. Consequently, the way the electric field is applied to the channel can be made uniform.

[0101] 2. Second Embodiment Next, the semiconductor memory device of the second embodiment will be described with reference to Figure 11. The semiconductor memory device of the second embodiment differs from that of the first embodiment in the shape of the memory holes formed in the first stack 51, second stack 52, and third stack 53, and also differs in the shape of the columnar bodies formed in the memory holes. Since the other structures are the same as those of the first embodiment, the structures of the memory holes and columnar bodies will be described below.

[0102] In the second embodiment, as shown in Figure 11, a first memory hole MH4 is formed in a first laminate 51 having the same structure as in the first embodiment, a second memory hole MH5 is formed in a second laminate 52, and a third memory hole MH6 is formed in a third laminate 53. The structure in which a first columnar body is formed inside the first memory hole MH4, a second columnar body is formed inside the second memory hole MH5, and a third columnar body is formed inside the third memory hole MH6 is the same as in the first embodiment.

[0103] Figure 11 shows the block insulating film formed inside each memory hole, scaled down and highlighted, corresponding to Figure 8. In the columnar body of the second embodiment, the structure in which the block insulating film, charge storage film, tunnel insulating film, semiconductor film, and core film are stacked to form the columnar body is the same as in the first embodiment. In the second embodiment, the shape of the first memory hole MH4 formed in the first laminate 51 is equivalent to the shape of the first memory hole MH1 formed in the first laminate 51 in the first embodiment. Therefore, the shape of the block insulating film 35 formed along the inner surface of the first memory hole MH4 is equivalent to the block insulating film 35 of the first embodiment.

[0104] In the second embodiment, the cross-sectional area (XY cross-sectional area) of the second memory hole MH5 gradually increases from the top to the bottom and from the bottom to the top along the XY plane. However, a connection portion 60 is formed at the bottom of the second memory hole MH5, and the cross-sectional area (XY cross-sectional area) of the connection portion 60 gradually increases from the top to the bottom along the XY plane.

[0105] Due to the shape of the second memory hole MH5, the second block insulating film 62A, which is formed from the top to the bottom of the second memory hole MH5, gradually increases in thickness as it approaches the bottom of the second memory hole MH5. In addition, the bottom block insulating film 62B, which is formed in the connection portion 60, gradually decreases in thickness as it approaches the first memory hole MH1. The thickness is thickest at the junction of the second block insulating film 62A and the bottom block insulating film 62B, and the second block insulating film 62A is formed to gradually decrease in thickness as it approaches the top, while the bottom block insulating film 62B is formed to gradually decrease in thickness as it approaches the bottom.

[0106] In the second embodiment, the structure of the third memory hole MH6 is the same as that of the second memory hole MH5. That is, the third block insulating film 63A, formed from the top to the bottom of the third memory hole MH6, gradually increases in thickness as it approaches the bottom of the third memory hole MH6. Also, the bottom block insulating film 62B, formed in the connection portion 63, gradually decreases in thickness as it approaches the second memory hole MH5. The thickness is thickest at the junction of the third block insulating film 63A and the bottom block insulating film 63B, and the third block insulating film 63A is formed to gradually decrease in thickness as it approaches the top, while the bottom block insulating film 63B is formed to gradually decrease in thickness as it approaches the bottom.

[0107] In the structure of the second embodiment, the thickness of the block insulating film 35 is generally inversely correlated with the diameter of the first columnar body MP1. As clearly shown in Figure 11, the block insulating film 35 is made thicker in the areas where the diameter of the first columnar body MP1 is small and the electric field concentration is high, and thinner in the areas where the diameter of the first columnar body MP1 is large and the electric field concentration is low. Therefore, writing can be slowed down in regions where the diameter of the first columnar body MP1 is small and the electric field concentration is high. This makes it possible to match the writing conditions in regions where the diameter of the first columnar body MP1 is large and the electric field concentration is low. Thus, the problem of inconsistent data writing to memory depending on the size of the first columnar body MP1 can be solved.

[0108] This effect can be obtained similarly in the second columnar body MP5, which has a structure similar to the first columnar body MP4, and also in the third columnar body MP6, which has a structure similar to the first columnar body MP4. Therefore, in the second embodiment as well, the same effects and advantages as in the first embodiment can be obtained for the entire memory cell array 10 provided with the columnar bodies MP.

[0109] 3. Third Embodiment Next, the semiconductor memory device of the third embodiment will be described with reference to Figure 12. The semiconductor memory device of the third embodiment differs from that of the first embodiment in the shape of the memory holes formed in the first stack 51, second stack 52, and third stack 53, and also differs in the shape of the columnar bodies formed in the memory holes. Since the other structures are the same as those of the first embodiment, the structures of the memory holes and columnar bodies will be described below.

[0110] In the third embodiment, as shown in Figure 12, a first memory hole MH7 is formed in a first laminate 51 having the same structure as in the first embodiment, a second memory hole MH8 is formed in a second laminate 52, and a third memory hole MH9 is formed in a third laminate 53. The structure in which a first columnar body is formed inside the first memory hole MH7, a second columnar body is formed inside the second memory hole MH8, and a third columnar body is formed inside the third memory hole MH9 is the same as in the first embodiment.

[0111] In Figure 12, only the block insulating film formed inside each memory hole is shown, corresponding to Figure 8. In the columnar body of the third embodiment, the structure in which the block insulating film, charge storage film, tunnel insulating film, semiconductor film, and core film are stacked to form the columnar body is the same as in the first embodiment. In the third embodiment, the shape of the first memory hole MH7 formed in the first laminate 51 is equivalent to the shape of the first memory hole MH1 formed in the first laminate 51 in the first embodiment. Therefore, the shape of the block insulating film 35 formed along the inner surface of the first memory hole MH7 is equivalent to the block insulating film 35 of the first embodiment.

[0112] In the third embodiment, the second memory hole MH8 has a cross-sectional area (XY cross-sectional area) that gradually increases from bottom to near top along the XY plane. However, a connection portion 67 is formed at the top of the second memory hole MH8. The connection portion 67 has a shape in which its cross-sectional area (XY cross-sectional area) that gradually decreases from bottom to top along the XY plane.

[0113] The second memory hole MH8 has the shape described above. Due to this relationship, the second block insulating film 64A, which is formed from the bottom to near the top of the second memory hole MH8, gradually decreases in thickness as it approaches the top of the second memory hole MH8. Also, the top block insulating film 64B, which is formed at the connection portion 67, gradually increases in thickness as it approaches the third memory hole MH9. The thickness is thinnest at the junction of the second block insulating film 64A and the top block insulating film 64B, and the top block insulating film 64B is formed to gradually increase in thickness as it goes upwards.

[0114] In the third embodiment, the third memory hole MH9 has a cross-sectional area (XY cross-sectional area) that gradually increases from bottom to top, from the bottom to near the top. However, a connection portion 67 is formed at the top of the third memory hole MH9, and the connection portion 67 has a shape in which the cross-sectional area (XY cross-sectional area) that gradually decreases from the bottom to the top, along the XY plane.

[0115] The third memory hole MH9 has the shape described above. Due to this relationship, the third block insulating film 65A, which is formed from the bottom to near the top of the third memory hole MH9, gradually decreases in thickness as it moves from the bottom to the top of the third memory hole MH9. Also, the top block insulating film 65B, which is formed at the connection portion 67, gradually increases in thickness as it approaches the top end. The thickness is thinnest at the junction of the third block insulating film 65A and the top block insulating film 65B, and the top block insulating film 65B is formed to gradually increase in thickness as it moves upward.

[0116] In the structure of the third embodiment, the thickness of the block insulating film 35 is inversely correlated with the size of the inner diameter of the memory hole MH7, similar to the first and second embodiments. As can be inferred from Figure 12, the block insulating film 35 is made thicker in the areas where the diameter of the first columnar body MP7 is small and the electric field concentration is high, and thinner in the areas where the diameter of the first columnar body MP is large and the electric field concentration is low. Therefore, writing can be slowed down in regions where the inner diameter of the first memory hole MH7 is small and the electric field concentration is high. This makes it possible to match the writing conditions in regions where the diameter of the first memory hole MH7 is large and the electric field concentration is low. Thus, the problem of inconsistent data writing to memory depending on the size of the first columnar body can be solved.

[0117] This effect can also be obtained in the second columnar body MP8, which shows an inverse correlation with the size of the inner diameter of the second memory hole MH8. Furthermore, the aforementioned effect can also be obtained in the third columnar body MP9, which shows an inverse correlation with the size of the inner diameter of the third memory hole MH9. Therefore, the same effects and advantages as in the first embodiment can be obtained in the entire memory cell array 10 equipped with columnar MPs employing the structure shown in Figure 12.

[0118] While embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0119] 1...Memory system, 3...Semiconductor memory device, 10...Memory cell array 23...Wiring layer, 31...Semiconductor film, 33...Tunnel insulating film, 34...Charge storage film 35... Block insulating film, 43, 44, 45, 46... Insulating layer, 51...First layer, 52...Second layer, 53...Third layer 62A, ...block insulating film, 62B, ...bottom block insulating film, 63...connection part, 63A...block insulating film, 63B...bottom block insulating film, 64A...Second block insulating film, 64B...Top block insulating film, 67...Connection part, 65A...Third block insulating film, 65B...Top block insulating film, BL...bit line, BLK...block, MH...Memory Hole, MH1, MH4, MH7...First Memory Hole, MH2, MH5, MH8...Second Memory Hole, MH3, MH6, MH9...Third Memory Hole MP...Columnar body, MP1...First columnar body, MP2...Second columnar body, MP3...Third columnar body, MP4...first columnar body, MP5...second columnar body, MP6...third columnar body, MP7...first columnar body, MP8...second columnar body, MP9...third columnar body, MT, MT0~MTn...memory cell transistors, W1…Semiconductor substrate, WL, WL0~WLn…Word lines

Claims

1. circuit board and A plurality of laminates are provided on the substrate, each having a plurality of wiring layers and a plurality of insulating layers, and the plurality of wiring layers and the plurality of insulating layers are alternately stacked along a first direction, Each of the aforementioned laminates extends in the first direction, In a second direction intersecting the first direction, a block insulating film is provided on a plurality of the wiring layers and a plurality of the insulating layers, In the second direction, a charge storage film provided on the block insulating film, In the second direction, a tunnel insulating film provided on the charge storage film, In the second direction, the semiconductor film provided on the tunnel insulating film, A columnar body having, Equipped with, Each of the laminates has a hole that extends in the first direction and accommodates the columnar body. The hole has a portion in which the inner diameter changes continuously along the first direction, Of the block insulating film, the charge storage film, and the tunnel insulating film, the thickness of at least one of them is such that, in comparison to the position of the hole with a small inner diameter and the position of the hole with a large inner diameter, the thickness is greater at the position of the hole with a small inner diameter and smaller at the position of the hole with a large inner diameter. Semiconductor equipment.

2. The difference between the maximum and minimum inner diameters of the aforementioned hole is 10 nm or more. Formed at the maximum inner diameter position of the hole, at least one of the block insulating film, the charge storage film, and the tunnel insulating film has a thickness, The difference in film thickness between at least one of the block insulating film, the charge storage film, and the tunnel insulating film, which is formed at the minimum inner diameter position of the hole, is 1 nm or more. The semiconductor device according to claim 1.

3. circuit board and A plurality of laminates are provided on the substrate, each having a plurality of wiring layers and a plurality of insulating layers, and the plurality of wiring layers and the plurality of insulating layers are alternately stacked along a first direction, Each of the aforementioned laminates extends in the first direction, In a second direction intersecting the first direction, a block insulating film is provided on a plurality of the wiring layers and a plurality of the insulating layers, In the second direction, a charge storage film provided on the block insulating film, In the second direction, a tunnel insulating film provided on the charge storage film, In the second direction, the semiconductor film provided on the tunnel insulating film, A columnar body having, Equipped with, Each of the laminates has a hole that extends in the first direction and accommodates the columnar body. In the first adjacent hole and the other hole, there is a portion where the inner diameter changes discontinuously at the connection point between the hole closer to the substrate and the other hole further from the substrate. Of the block insulating film, the charge storage film, and the tunnel insulating film, the thickness of at least one of them is such that, in comparison to the position of the hole with a small inner diameter and the position of the hole with a large inner diameter, the thickness is greater at the position of the hole with a small inner diameter and smaller at the position of the hole with a large inner diameter. Semiconductor equipment.

4. At the connection point between the one hole and the other hole, The difference between the maximum inner diameter of one of the holes and the minimum inner diameter of the other hole is 10 nm or more. Formed at the maximum inner diameter position of one of the holes, at least one of the block insulating film, the charge storage film, and the tunnel insulating film has a thickness, The difference in film thickness between at least one of the block insulating film, the charge storage film, and the tunnel insulating film, which is formed at the minimum inner diameter position of the other hole, is 1 nm or more. The semiconductor device according to claim 3.

5. The block insulating film, the charge storage film, the tunnel insulating film, and the semiconductor film are each continuous in each laminate from one end in the first direction to the other end in the first direction. The semiconductor device according to claim 1 or claim 3.

6. With respect to the variation in the radius of curvature of the cross-sectional contour of the aforementioned hole, The variation in the radius of curvature on the inner circumference side of the cross-sectional contour of the block insulating film, The variation in the radius of curvature on the inner side of the cross-sectional contour of the charge storage film, Of the variations in the radius of curvature on the inner circumference side of the cross-sectional contour of the tunnel insulating film, at least one variation is small. The semiconductor device according to claim 1 or claim 3.

7. In each of the aforementioned laminates, the inner diameter of the hole is gradually increased from one end in the first direction, which is closer to the substrate, to the other end in the first direction. The thickness of the block insulating film is gradually reduced in each of the laminates from one end to the other end. The semiconductor device according to claim 1 or claim 3.

8. Each of the laminates has a region in which the inner diameter of the hole gradually increases from one end in the first direction that is closer to the substrate to the other end in the first direction. In the aforementioned region, the thickness of the block insulating film is gradually reduced in each laminate from one end to the other end. Each of the aforementioned laminates has a connecting portion on one end or the other end that connects to the hole of another adjacent laminate along the first direction, In the connection portion, the thickness of at least one of the block insulating film, the charge storage film, and the tunnel insulating film decreases as the inner diameter of the connection portion increases. The semiconductor device according to claim 1 or claim 3.

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