Semiconductor equipment

Abstract

This suppresses the occurrence of bond wire breakage due to shrinkage during the curing of the sealing material. [Solution] The semiconductor device has an outer peripheral wall whose lower end contacts the upper surface of a heat dissipation base, surrounding the semiconductor unit, and housing the semiconductor unit 10b in a storage area R2 enclosed by the storage area R2 and the upper surface of the heat dissipation base; connection terminals 25a1 to 25a5 provided spaced apart from the semiconductor unit 10b in the storage area R2; bonding wires 15a1 to 15a5 that electrically connect the connection terminals 25a1 to 25a5 to the first control electrodes of the semiconductor chip 12; a sealing member that seals the storage area R2; and a partition member 28a provided in the upper area of ​​the semiconductor chip 12 within the storage area R2, which, in a plan view, divides the storage area R2 into a region R2a including the connection terminals 25a1 to 25a5 and the bonding wires 15a1 to 15a5, and a region R2b on the opposite side of region R2a from the connection terminals 25a1 to 25a5.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] In a semiconductor device, an electrode provided on a semiconductor chip is electrically connected to a connection terminal or a wiring board on an insulating substrate via a bonding wire or a lead frame.

[0003] Also, as related art, a power semiconductor module including a case in which a partition plate is formed has been proposed (see, for example, Patent Document 1). Also, a semiconductor device including a case including a beam portion has been proposed (see, for example, Patent Document 2). Also, a semiconductor device in which a relaxation plate is provided on a side portion of a wire has been proposed (see, for example, Patent Document 3). Also, a hybrid integrated circuit including a lid provided with a protrusion has been proposed (see, for example, Patent Document 4).

[0004] Also, a semiconductor device including a resin cover provided with a rib wall has been proposed (see, for example, Patent Document 5). Also, a semiconductor device including a plate-like member embedded in a sealing resin body has been proposed (see, for example, Patent Document 6). Also, a semiconductor device in which linear grooves are formed in a heat sink has been proposed (see, for example, Patent Document 7). Also, a semiconductor module including a partition portion that partitions an internal space of an outer frame has been proposed (see, for example, Patent Document 8).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

[0006] The present invention aims to provide a semiconductor device that can suppress the occurrence of bond wire breakage due to shrinkage during the curing of the sealing member. [Means for solving the problem]

[0007] According to one aspect of the invention, a semiconductor device is provided comprising: a heat dissipation base including an upper surface; a semiconductor unit disposed on the upper surface of the heat dissipation base and having a first semiconductor chip including a first control electrode on its upper surface; an outer peripheral wall whose lower end contacts the upper surface of the heat dissipation base, surrounds the semiconductor unit, and houses the semiconductor unit in a housing area enclosed by the upper surface of the heat dissipation base; a first connection terminal provided in the housing area spaced apart from the semiconductor unit; a first bonding wire electrically connecting the first connection terminal and the first control electrode of the first semiconductor chip; a sealing member for sealing the housing area; and a first partition member provided in the upper area of ​​the housing area above the first semiconductor chip, which, in a plan view, divides the housing area into a first area including the first connection terminal and the first bonding wire, and a second area on the opposite side of the first connection terminal from the first area.

[0008] It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Effects of the Invention]

[0009] According to the disclosed technology, it is possible to suppress the occurrence of breakage of bonding wires due to shrinkage when the sealing member hardens.

Brief Description of the Drawings

[0010] [Figure 1] It is a plan view (Part 1) of a semiconductor device according to the first embodiment. [Figure 2] It is a plan view (Part 2) of a semiconductor device according to the first embodiment. [Figure 3] It is a side view of a semiconductor device according to the first embodiment. [Figure 4] It is a plan view of a semiconductor unit according to the first embodiment. [Figure 5] It is a cross-sectional view (Part 1) of a semiconductor device according to the first embodiment. [Figure 6] It is a diagram for explaining the connection between the semiconductor unit and various terminals. [Figure 7] It is a diagram showing an equivalent circuit of the functions of a semiconductor module according to the first embodiment. [Figure 8] It is a cross-sectional view (Part 2) of a semiconductor device according to the first embodiment. [Figure 9] It is a plan view of a comparative example of a semiconductor device. [Figure 10] It is a cross-sectional view of a comparative example of a semiconductor device. [Figure 11] It is an enlarged view of the main part of the cross-sectional view shown in FIG. 10. [Figure 12] It is a plan view of a semiconductor device according to the second embodiment. [Figure 13] It is a plan view of a semiconductor device according to the third embodiment. [Figure 14] It is a cross-sectional view of a semiconductor device according to the third embodiment.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the "front surface" and the "upper surface" represent the X-Y plane facing upward (+Z direction) in the semiconductor device in the figure. Similarly, "up" represents the upward (+Z direction) in the semiconductor device in the figure. The "back surface" and the "lower surface" represent the X-Y plane facing downward (-Z direction) in the semiconductor device in the figure. Similarly, "down" represents the downward (-Z direction) in the semiconductor device in the figure. The same directionality is meant in other drawings as necessary. The "front surface", "upper surface", "up", "back surface", "lower surface", "down", and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical idea of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction with respect to the ground. That is, the directions of "up" and "down" are not limited to the gravitational direction.

[0012] [First Embodiment] First, an example of the overall configuration of the semiconductor device according to the first embodiment will be described using FIGS. 1 to 3. FIG. 1 is a plan view (part 1) of the semiconductor device according to the first embodiment. FIG. 2 is a plan view (part 2) of the semiconductor device according to the first embodiment. FIG. 3 is a side view of the semiconductor device according to the first embodiment. Note that FIG. 2 is a plan view of the state where the sealing member 4 is removed from the semiconductor device 1 in FIG. 1. Also, FIG. 3 is a side view of the semiconductor device 1 in FIG. 1 viewed in the +Y direction.

[0013] The semiconductor device 1 includes a semiconductor module 2 and a cooling device 3. The semiconductor module 2 includes semiconductor units 10a, 10b, 10c and a case 20 that houses the semiconductor units 10a, 10b, 10c. The case 20 is disposed above the cooling device 3, and the semiconductor units 10a, 10b, 10c are arranged in a row in the +X direction inside the case 20. Further, the semiconductor units 10a, 10b, 10c housed in the case 20 are sealed by a sealing member 4.

[0014] The semiconductor units 10a, 10b, and 10c all have the same configuration. Therefore, unless otherwise specified, the semiconductor units 10a, 10b, and 10c will be described simply as "semiconductor unit 10." Details of semiconductor unit 10 will be described later.

[0015] Case 20 includes an outer frame 21, first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, U-phase output terminal 24a, V-phase output terminal 24b, W-phase output terminal 24c, and control terminal sections 25, 26. The inner ends (connection terminals 25a, 26a) of the first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, U-phase output terminal 24a, V-phase output terminal 24b, W-phase output terminal 24c, and control terminal sections 25, 26 are made of solid plate-shaped metal material.

[0016] The outer frame 21 is rectangular in plan view and is surrounded on all four sides by side walls 21a, 21b, 21c, and 21d in order. Side walls 21a and 21c are the longer sides of the outer frame 21, and side walls 21b and 21d are the shorter sides. Also, in plan view, the corners where the side walls 21a, 21b, 21c, and 21d connect do not necessarily have to be right angles; for example, they may be chamfered with a radius as shown in Figure 1. The back surfaces of the outer frame 21 (side walls 21a, 21b, 21c, and 21d) may form a single plane and be parallel to the XY plane.

[0017] The outer frame 21 includes storage areas R1, R2, and R3 along the side walls 21a and 21c (±X direction) at the center of the ±Y direction of the front surface. In storage areas R1, R2, and R3, the front surface of the outer frame 21 is defined in a rectangular shape in plan view and has an opening. That is, the upper side (+Z direction side) of each of the storage areas R1, R2, and R3 forms an opening. However, as shown in Figure 1, the openings of storage areas R1, R2, and R3 are divided in the ±Y direction by partition members 28a, 28b, and 28c, respectively.

[0018] Semiconductor units 10a, 10b, and 10c are housed in storage areas R1, R2, and R3, respectively. Therefore, the size of storage areas R1, R2, and R3 only needs to be large enough to accommodate the semiconductor units 10a, 10b, and 10c. The bottoms of storage areas R1, R2, and R3 are closed by the upper surface of the cooling device 3 (the upper surface of the heat dissipation base 31, which will be described later). In addition, a partition wall 27a is provided between storage areas R1 and R2, and a partition wall 27b is provided between storage areas R2 and R3. The entire lower ends of partition walls 27a and 27b are in contact with the upper surface of the cooling device 3. Therefore, each of storage areas R1, R2, and R3 is a space enclosed by the inner wall formed by the outer frame 21 of the case 20 and partition walls 27a and 27b, and the upper surface of the cooling device 3. For example, the storage area R2 is surrounded by inner walls R2_1 and R2_2 (first and second inner walls) formed by the outer frame 21, inner walls R2_3 and R2_4 (third and fourth inner walls) formed by partition walls 27a and 27b respectively, and the upper surface of the cooling device 3.

[0019] These storage areas R1, R2, and R3 are filled with sealing material 4 up to the height of the upper ends of partition walls 27a and 27b. The sealing material 4 is a thermosetting resin. Examples of thermosetting resins include epoxy resin and silicone gel. In Figure 1, the areas filled with sealing material 4 are hatched.

[0020] In storage areas R1, R2, and R3, semiconductor units 10a, 10b, and 10c are installed on their bottom surfaces, i.e., on the top surfaces of the cooling device 3, respectively. In addition, steps 29a and 29b (see Figures 5 and 6) are formed on the inner walls of storage areas R1, R2, and R3 on the +Y side, protruding in the -Y direction. Steps 29a and 29b have upper surfaces, and the height of the upper surfaces of steps 29a and 29b is lower than the height of the partition walls 27a and 27b. Connection terminals 25a and 26a, which are the inner ends of the control terminal sections 25 and 26, are provided on the upper surfaces of steps 29a and 29b. Therefore, inside storage areas R1, R2, and R3, the semiconductor units 10a, 10b, and 10c and the connection terminals 25a and 26a are sealed by the sealing member 4.

[0021] In a plan view, the outer frame 21 is provided with first connection terminals 22a, 22b, 22c and second connection terminals 23a, 23b, 23c along the side wall 21a (±X direction) on the front side wall 21a. The first connection terminals 22a, 22b, 22c are positive side input terminals (P terminals), and the second connection terminals 23a, 23b, 23c are negative side input terminals (N terminals).

[0022] Furthermore, the outer frame 21 is provided with a U-phase output terminal 24a, a V-phase output terminal 24b, and a W-phase output terminal 24c on the front side wall 21c side along the side wall 21c (±X direction). In this case, the first connection terminal 22a and the second connection terminal 23a and the U-phase output terminal 24a are provided with a storage area R1 in between. The first connection terminal 22b and the second connection terminal 23b and the V-phase output terminal 24b are provided with a storage area R2 in between. The first connection terminal 22c and the second connection terminal 23c and the W-phase output terminal 24c are provided with a storage area R3 in between.

[0023] Furthermore, in a plan view, control terminal sections 25 and 26 are provided between the storage areas R1, R2, R3 and the U-phase output terminal 24a, V-phase output terminal 24b, and W-phase output terminal 24c. Control terminal sections 25 and 26 are provided for each storage area R1, R2, R3. The intermediate portions of the control terminal sections 25 and 26 are embedded in the outer frame 21. The inner ends of the control terminal sections 25 and 26 are exposed into the interior of the storage areas R1, R2, R3 from the inner wall on the +Y direction side of the storage areas R1, R2, R3 (for example, inner wall R2_1). These inner ends of the control terminal sections 25 and 26 form flat plate-shaped connection terminals 25a and 26a parallel to the XY plane and are located on the upper surfaces of the steps 29a and 29b. On the other hand, the outer ends of the control terminals 25 and 26 are exposed upward (+Z direction) from the upper surface of the outer frame 21, forming columnar external connection terminals 25b and 26b.

[0024] Such an outer frame 21 includes first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, U-phase output terminal 24a, V-phase output terminal 24b, W-phase output terminal 24c, and control terminal sections 25, 26, and is integrally molded by injection molding using a thermoplastic resin. This constitutes the case 20. The thermoplastic resin is, for example, polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0025] Furthermore, the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25, 26 are made of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy mainly composed of at least one of these. The surfaces of the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25, 26 may be plated. In this case, the plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy. The first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25, 26, which are plated, have improved corrosion resistance.

[0026] In the following explanation, the first connection terminals 22a, 22b, and 22c will be referred to as "first connection terminal 22" unless otherwise specified. Similarly, the second connection terminals 23a, 23b, and 23c will be referred to as "second connection terminal 23," and the U-phase output terminal 24a, V-phase output terminal 24b, and W-phase output terminal 24c will be referred to as "output terminal 24."

[0027] The cooling device 3 includes a heat dissipation base 31, side walls 32, and a cooling bottom plate 33. The heat dissipation base 31 is a flat metal member that forms a rectangle in plan view. The corners of the heat dissipation base 31 may be rounded in plan view. Semiconductor units 10a, 10b, and 10c are bonded to the front surface of the heat dissipation base 31 along the X direction. Multiple heat dissipation fins (not shown) are formed on the back surface of the heat dissipation base 31. Each heat dissipation fin, for example, has a flat plate shape parallel to the XZ plane and is arranged in parallel in the Y direction. The side walls 32 are formed continuously in an annular shape on the back surface of the heat dissipation base 31. The cooling bottom plate 33 is flat and has the same shape as the heat dissipation base 31 in plan view. The corners of the cooling bottom plate 33 may also be rounded in view. The cooling bottom plate 33 has an inlet 33a for the refrigerant to flow into the inside of the cooling device 3, and an outlet 33b for the refrigerant that has circulated inside to flow out to the outside.

[0028] The cooling device 3 cools the semiconductor unit 10 by releasing heat from the semiconductor unit 10 via a refrigerant. The refrigerant used here may be, for example, water, antifreeze (ethylene glycol aqueous solution), or long-life coolant. The cooling device 3 may also include a pump and a heat dissipation device (radiator). The pump introduces the refrigerant into the inlet 33a and circulates the refrigerant that has flowed out from the outlet 33b back into the inlet 33a. The heat dissipation device receives the refrigerant flowing out from the cooling device 3 and dissipates the heat from the refrigerant, which has been conducted with heat from the semiconductor unit 10, to the outside. Dispensing heads are attached to the inlet 33a and outlet 33b via annular rubber packings attached to the sealing area surrounding the inlet 33a and outlet 33b. Dispensing pipes connected to the pump are attached to the dispensing heads.

[0029] Next, the semiconductor unit 10 will be described using Figures 4 to 6. Figure 4 is a plan view of the semiconductor unit according to the first embodiment. Figure 5 is a cross-sectional view (part 1) of the semiconductor device according to the first embodiment. Figure 6 is a diagram for explaining the connection between the semiconductor unit and various terminals. Figure 5 is an enlarged view of the vicinity of the semiconductor unit 10b in the cross-sectional view obtained when the semiconductor device 1 is cut along the line I1-I1 in Figure 2. Figure 6 also illustrates the semiconductor unit 10b housed in the housing area R2. Note that the sealing member 4 is not shown in Figures 5 and 6.

[0030] The semiconductor unit 10 includes an insulating substrate 11, semiconductor chips 12 and 13, and wiring members 14a and 14b. The semiconductor chips 12 and 13 are bonded to the insulating substrate 11 via a bonding material. The wiring members 14a and 14b are bonded to the semiconductor chips 12 and 13, respectively, via a bonding material. Solder or sintered material can be used as the bonding material. The wiring members 14a and 14b are solid plate-shaped metal materials.

[0031] The insulating substrate 11 includes an insulating board 11a, wiring boards 11b1, 11b2, 11b3, and a metal plate 11c. The insulating board 11a and the metal plate 11c are rectangular in shape when viewed from above. The corners of the insulating board 11a and the metal plate 11c may be rounded (R-chamfered) or chamfered (C-chamfered). The size of the metal plate 11c is smaller than the size of the insulating board 11a when viewed from above, and it is formed inside the insulating board 11a.

[0032] The insulating plate 11a is made of a material that has insulating properties and excellent thermal conductivity. Such an insulating plate 11a may be made of ceramics or insulating resin. Examples of ceramics include aluminum oxide, aluminum nitride, silicon nitride, and silicon nitride. Examples of insulating resins include paper phenolic substrates, paper epoxy substrates, glass composite substrates, and glass epoxy substrates.

[0033] The wiring boards 11b1, 11b2, and 11b3 are formed on the front surface of the insulating board 11a. The wiring boards 11b1, 11b2, and 11b3 are made of a highly conductive metal containing copper. Such a metal may be, for example, an alloy containing aluminum in addition to copper.

[0034] The wiring board 11b2 occupies approximately half of the area on the +X side of the front surface of the insulating board 11a, and covers the entire area from the -Y side to the +Y side. The wiring board 11b1 (first wiring pattern) occupies approximately half of the area on the -X side of the front surface of the insulating board 11a. The wiring board 11b3 (second wiring pattern) occupies the area on the front surface of the insulating board 11a enclosed by the wiring boards 11b1 and 11b2.

[0035] Such wiring boards 11b1, 11b2, and 11b3 are formed on the front surface of the insulating board 11a as follows. A metal plate is formed on the front surface of the insulating board 11a, and etching or other processing is performed on this metal plate to obtain wiring boards 11b1, 11b2, and 11b3 of a predetermined shape. Alternatively, wiring boards 11b1, 11b2, and 11b3 cut out from a metal plate in advance may be pressed onto the front surface of the insulating board 11a. Note that wiring boards 11b1, 11b2, and 11b3 are just examples. The number, shape, size, and position of the wiring boards may be appropriately selected as needed.

[0036] The metal plate 11c is formed on the back surface of the insulating plate 11a. The metal plate 11c is rectangular in shape. The area of ​​the metal plate 11c in plan view is smaller than the area of ​​the insulating plate 11a, but larger than the area of ​​the region where the wiring boards 11b1, 11b2, and 11b3 are formed. The corners of the metal plate 11c may be rounded (R-chamfered) or chamfered (C-chamfered). For example, the metal plate 11c is formed over the entire surface of the insulating plate 11a, excluding the edges. The metal plate 11c is mainly composed of a metal with excellent thermal conductivity. The metal is, for example, copper, aluminum, or an alloy containing at least one of these.

[0037] As an insulating substrate 11 having such a configuration, if the insulating plate 11a is ceramic, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate may be used. If the insulating plate 11a is an insulating resin, a resin insulating substrate may be used. The insulating substrate 11 may be attached to the front surface of the heat dissipation base 31 of the cooling device 3 via a bonding member. Heat generated by the semiconductor chips 12 and 13 can be conducted to the cooling device 3 via the wiring boards 11b1 and 11b2, the insulating plate 11a, and the metal plate 11c to dissipate the heat.

[0038] Semiconductor chips 12 and 13 contain power device elements made of silicon. The power device elements are RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor). The RC-IGBT combines the functions of an IGBT, which is a switching element, and an FWD (Free Wheeling Diode), which is a diode element.

[0039] The front surface of the semiconductor chip 12 is rectangular in plan view, and a control electrode 12a and a main electrode, the emitter electrode 12b (output electrode), are formed on this front surface. In this embodiment, the control electrode 12a is provided on one of the shorter sides of the front surface of the semiconductor chip 12. The control electrode 12a is connected to the connection terminal 25a via a bonding wire 15a.

[0040] More specifically, on the front surface of the semiconductor chip 12, five control electrodes 12a1, 12a2, 12a3, 12a4, and 12a5 are arranged in parallel in the +X direction as control electrodes 12a. Also, on the upper surface of the step 29a formed on the inner wall of the housing regions R1, R2, and R3, five connection terminals 25a1, 25a2, 25a3, 25a4, and 25a5 are arranged in parallel in the +X direction as connection terminals 25a. The control electrodes 12a1, 12a2, 12a3, 12a4, and 12a5 and the connection terminals 25a1, 25a2, 25a3, 25a4, and 25a5 are connected via bonding wires 15a1, 15a2, 15a3, 15a4, and 15a5, respectively. As will be described later, among the control electrodes 12a1, 12a2, 12a3, 12a4, and 12a5 mentioned above, control electrode 12a3 is the gate electrode of the semiconductor chip 12.

[0041] The emitter electrode 12b is located on the short side in the -Y direction on the front surface of the semiconductor chip 12. A collector electrode (input electrode, not shown), which is the main electrode, is formed on the back surface of the semiconductor chip 12. The collector electrode is bonded to the wiring board 11b1 via a bonding material.

[0042] The semiconductor chip 13 has a similar configuration to the semiconductor chip 12, with a control electrode 13a and an emitter electrode 13b (output electrode) formed on the front surface of the semiconductor chip 13, and a collector electrode (input electrode, not shown) formed on the back surface of the semiconductor chip 13. The collector electrode is bonded to the wiring board 11b2 via a bonding material. The control electrode 13a is connected to the connection terminal 26a via a bonding wire 15b.

[0043] More specifically, on the front surface of the semiconductor chip 13, five control electrodes 13a1, 13a2, 13a3, 13a4, and 13a5 are arranged in parallel in the +X direction as control electrodes 13a. Also, on the upper surface of the step 29b formed on the inner wall of the housing regions R1, R2, and R3, five connection terminals 26a1, 26a2, 26a3, 26a4, and 26a5 are arranged in parallel in the +X direction as connection terminals 26a. The control electrodes 13a1, 13a2, 13a3, 13a4, and 13a5 and the connection terminals 26a1, 26a2, 26a3, 26a4, and 26a5 are connected via bonding wires 15b1, 15b2, 15b3, 15b4, and 15b5, respectively. As will be described later, among the control electrodes 13a1, 13a2, 13a3, 13a4, and 13a5 mentioned above, control electrode 13a3 serves as the gate electrode of the semiconductor chip 13.

[0044] The bonding wires 15a and 15b are mainly composed of a material with excellent conductivity. Such a material is, for example, gold, copper, aluminum, or an alloy containing at least one of these. Preferably, the bonding wires 15a and 15b may be an aluminum alloy containing a small amount of silicon. The diameter of the bonding wires 15a and 15b may be, for example, 20 μm or more and 500 μm or less.

[0045] The semiconductor chips 12 and 13 may also be equipped with a pair of switching elements and diode elements instead of RC-IGBTs. The switching elements are, for example, IGBTs and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Such semiconductor chips 12 and 13 have, for example, an input electrode (drain electrode or collector electrode) as the main electrode on the back surface, and a control electrode (gate electrode) and an output electrode (source electrode or emitter electrode) as the main electrode on the front surface. The diode elements are, for example, SBDs (Schottky Barrier Diodes) and PiN (P-intrinsic-N) diodes, which are used as FWDs. Such semiconductor chips 12 and 13 have an output electrode (cathode electrode) as the main electrode on the back surface and an input electrode (anode electrode) as the main electrode on the front surface.

[0046] Furthermore, the semiconductor chips 12 and 13 may include a switching element consisting of a power MOSFET mainly composed of silicon carbide. In this case, the semiconductor chips 12 and 13 are equipped with a forward drive (FWD) along with the power MOSFET. Such semiconductor chips 12 and 13 have a control electrode (gate electrode) and a main electrode, which is an output electrode (source electrode), on their front surface, respectively. The semiconductor chips 12 and 13 also have a main electrode, which is an input electrode (drain electrode), on their back surface.

[0047] The wiring member 14a connects the emitter electrode 12b on the front surface of the semiconductor chip 12 to the wiring board 11b3. The front surface of the wiring board 11b3 includes a bonding region 11d3 to which a connecting member for electrically connecting to the second connecting terminal 23 is bonded. The inner end of the second connecting terminal 23 is exposed inward from the inner wall on the -Y direction side of the housing regions R1, R2, R3. The inner end is flat, and a copper block is bonded to the lower surface of the inner end as the connecting member. The lower surface of the copper block is then bonded to the bonding region 11d3 of the wiring board 11b3 via a bonding material. For example, the inner end 23b1 of the second connecting terminal 23b is exposed inward from the inner wall R2_2 of the housing region R2, and a copper block 23b2 is bonded to the lower surface of the inner end 23b1 via a bonding material or by laser welding. Then, the lower surface of the copper block 23b2 is joined to the joining area 11d3 of the wiring board 11b3 via a bonding material. With this configuration, the wiring board 11b3 and the second connection terminals 23a, 23b, and 23c are electrically connected.

[0048] The wiring member 14b connects the emitter electrode 13b on the front surface of the semiconductor chip 13 to the wiring board 11b1. The front surface of the wiring board 11b1 includes a bonding region 11d1 to which a connecting member for electrically connecting to the output terminal 24 is bonded. The inner end of the output terminal 24 is exposed inward from the inner wall on the +Y direction side of the housing regions R1, R2, R3. The inner end is flat, and a copper block is bonded to the lower surface of the inner end as the connecting member. The lower surface of the copper block is then bonded to the bonding region 11d1 of the wiring board 11b1 via a bonding material. For example, the inner end 24b1 of the V-phase output terminal 24b is exposed inward from the inner wall R2_1 of the housing region R2, and a copper block 24b2 is bonded to the lower surface of the inner end 24b1 via a bonding material or by laser welding. The lower surface of the copper block 24b2 is then bonded to the bonding region 11d1 of the wiring board 11b1. With this configuration, the wiring board 11b1 and the output terminal 24 are electrically connected.

[0049] Furthermore, the front surface of the wiring board 11b2 includes a joining area 11d2 to which a connecting member for electrically connecting with the first connection terminal 22 is joined. The inner end of the first connection terminal 22 is exposed inward from the inner wall on the -Y direction side of the storage areas R1, R2, and R3. The inner end is flat, and a copper block is joined to the lower surface of the inner end as the connecting member. The lower surface of the copper block is then joined to the joining area 11d2 of the wiring board 11b2 via a joining material. For example, the inner end 22b1 of the first connection terminal 22b is exposed inward from the inner wall R2_2 of the storage area R2, and a copper block 22b2 is joined to the lower surface of the inner end 22b1 via a joining material or by laser welding. The lower surface of the copper block 22b2 is then joined to the joining area 11d2 of the wiring board 11b2 via a joining material. With this configuration, the wiring board 11b2 and the first connection terminal 22 are electrically connected.

[0050] With the above configuration, the semiconductor unit 10 constitutes a single-phase inverter circuit. The upper arm of the half-bridge circuit is formed by the wiring board 11b2, semiconductor chip 13, wiring member 14b, and wiring board 11b1. The lower arm of the half-bridge circuit is formed by the wiring board 11b1, semiconductor chip 12, wiring member 14a, and wiring board 11b3. The output terminal 24 connected to wiring board 11b1 becomes the M terminal, which constitutes an output terminal in the half-bridge circuit. The first connection terminal 22 connected to wiring board 11b2 becomes the P terminal, which constitutes the positive side input terminal in the half-bridge circuit, and the second connection terminal 23 connected to wiring board 11b3 becomes the N terminal, which constitutes the negative side output terminal in the half-bridge circuit. The switching operation of the semiconductor chips 12 and 13 is controlled according to the control signals input to the gate electrodes (control electrodes 12a3, 13a3) from the control signal input terminals included in the control terminal sections 25 and 26, respectively.

[0051] The wiring member 14a integrally includes a joint portion 14a1, a rising portion 14a2, a bridging portion 14a3, a rising portion 14a4, and a joint portion 14a5. The lower surface of the joint portion 14a1 is joined to the emitter electrode 12b of the semiconductor chip 12 via a bonding material, and the lower surface of the joint portion 14a5 is joined to the wiring board 11b3 via a bonding material. The wiring member 14b integrally includes a joint portion 14b1, a rising portion 14b2, a bridging portion 14b3, a rising portion 14b4, and a joint portion 14b5. The lower surface of the joint portion 14b1 is joined to the emitter electrode 13b of the semiconductor chip 13 via a bonding material, and the lower surface of the joint portion 14b5 is joined to the wiring board 11b1 via a bonding material. In this embodiment, both the wiring members 14a and 14b are lead frames that are substantially flat in shape. Furthermore, the wiring members 14a and 14b may be constructed by bending each of the above-mentioned parts.

[0052] The wiring members 14a and 14b are made of a highly conductive metal containing copper. Such a metal may be, for example, an alloy containing aluminum in addition to copper. Furthermore, to improve corrosion resistance, the surfaces of the wiring members 14a and 14b may be plated. In this case, the plating material used may be, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0053] For example, solder is used as a bonding material to join the joints 14a1, 14b1 to the semiconductor chips 12, 13, the joints 14a5, 14b5 to the wiring boards 11b3, 11b1, and the semiconductor chips 12, 13 to the wiring boards 11b1, 11b2. The solder components include lead-free solder mainly composed of a predetermined alloy. The predetermined alloy contains tin. Such alloys are, for example, at least one of the following: a tin-silver alloy, a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, a tin-silver-indium-bismuth alloy, or a tin-antimony alloy. Furthermore, such solder components may contain additives. Examples of additives include nickel, germanium, cobalt, or silicon. Therefore, the solder components may include, for example, tin along with at least one of silver, zinc, copper, bismuth, indium, and antimony.

[0054] Furthermore, a sintered body may be used as a joining material for joining the above-mentioned parts. When joining with a sintered body, the sintered material is, for example, a powder containing at least one of silver, iron, copper, aluminum, titanium, nickel, tungsten, and molybdenum.

[0055] Figure 7 shows an equivalent circuit of the functions of a semiconductor module according to the first embodiment. The semiconductor chip 13 includes a switching element (IGBT) M1 and a diode element (FWD) D1a that constitute an RC-IGBT, and diode elements D1b and D1c for temperature sensing. The semiconductor chip 12 includes a switching element (IGBT) M2 and a diode element D2a (FWD) that constitute an RC-IGBT, and diode elements D2b and D2c for temperature sensing.

[0056] The semiconductor module 2 includes an inverter circuit containing switching elements M1 and M2. Switching element M1 constitutes the upper arm of the half-bridge circuit, and switching element M2 constitutes the lower arm of the half-bridge circuit.

[0057] The collector of the switching element M1 is connected to the P terminal, which constitutes the positive input terminal in the half-bridge circuit. The P terminal corresponds to the first connection terminal 22. As described above, the collector electrode on the lower surface of the semiconductor chip 13 is electrically connected to the first connection terminal 22, which is the P terminal, via the wiring board 11b2.

[0058] The emitter of the switching element M2 is connected to the N terminal, which constitutes the negative input terminal in the half-bridge circuit. The N terminal corresponds to the second connection terminal 23. As described above, the emitter electrode 12b on the upper surface of the semiconductor chip 12 is electrically connected to the second connection terminal 23, which is the N terminal, via the wiring member 14a and the wiring board 11b3.

[0059] Furthermore, the emitter of the switching element M2 is also connected to the emitter electrode E2. The emitter electrode E2 corresponds to the control electrode 12a1 of the semiconductor chip 12. The control electrode 12a1 is electrically connected to the connection terminal 25a1 via the bonding wire 15a1. In addition, the sense emitter of the switching element M2 is connected to the sense emitter electrode S2. The sense emitter electrode S2 corresponds to the control electrode 12a2 of the semiconductor chip 12. The control electrode 12a2 is electrically connected to the connection terminal 25a2 via the bonding wire 15a2.

[0060] The emitter of switching element M1 and the collector of switching element M2 are connected, and this connection point is connected to the M terminal which constitutes the output terminal in the half-bridge circuit. The M terminal corresponds to the output terminal 24. As described above, the emitter electrode 13b on the upper surface of the semiconductor chip 13 is electrically connected to the collector electrode on the lower surface of the semiconductor chip 12 and the output terminal 24 via the wiring member 14b and the wiring board 11b1.

[0061] Furthermore, the emitter of the switching element M1 is also connected to the emitter electrode E1. The emitter electrode E1 corresponds to the control electrode 13a1 of the semiconductor chip 13. The control electrode 13a1 is electrically connected to the connection terminal 26a1 via the bonding wire 15b1. In addition, the sense emitter of the switching element M1 is connected to the sense emitter electrode S1. The sense emitter electrode S1 corresponds to the control electrode 13a2 of the semiconductor chip 13. The control electrode 13a2 is electrically connected to the connection terminal 26a2 via the bonding wire 15b2.

[0062] The gate of the switching element M1 is connected to the gate electrode G1, which is the input electrode for the control signal of the switching operation. The gate electrode G1 corresponds to the control electrode 13a3 of the semiconductor chip 13. As described above, the control electrode 13a3 is electrically connected to the connection terminal 26a3 via the bonding wire 15b3, and the external connection terminal 26b on the other end of the connection terminal 26a3 forms the gate terminal corresponding to the switching element M1.

[0063] The gate of the switching element M2 is connected to the gate electrode G2, which is the input electrode for the control signal of the switching operation. The gate electrode G2 corresponds to the control electrode 12a3 of the semiconductor chip 12. As described above, the control electrode 12a3 is electrically connected to the connection terminal 25a3 via the bonding wire 15a3, and the external connection terminal 25b on the other end of the connection terminal 25a3 forms the gate terminal corresponding to the switching element M2.

[0064] With the above configuration, the semiconductor unit 10, including semiconductor chips 12 and 13, constitutes a single-phase inverter circuit. The semiconductor device 1 of this embodiment is equipped with three semiconductor units 10a, 10b, and 10c, each constituting a single-phase inverter circuit. The inverter circuits corresponding to semiconductor units 10a, 10b, and 10c are connected in parallel. In this case, for example, semiconductor unit 10a generates a U-phase output voltage, semiconductor unit 10b generates a V-phase output voltage, and semiconductor unit 10c generates a W-phase output voltage. That is, a U-phase output voltage is output from the U-phase output terminal 24a connected to semiconductor unit 10a, a V-phase output voltage is output from the V-phase output terminal 24b connected to semiconductor unit 10b, and a W-phase output voltage is output from the W-phase output terminal 24c connected to semiconductor unit 10c.

[0065] Next, the circuit configuration for temperature sensing will be described. The anode electrode A1 is connected to the anode of diode element D1b and the cathode of diode element D1c. The cathode electrode K1 is connected to the cathode of diode element D1b and the anode of diode element D1c. The anode electrode A1 and the cathode electrode K1 are electrodes for temperature sensing of the semiconductor chip 13. The anode electrode A1 and the cathode electrode K1 also correspond to control electrodes 13a4 and 13a5 formed on the semiconductor chip 13, respectively. The control electrodes 13a4 and 13a5 are connected to connection terminals 26a4 and 26a5, respectively, via bonding wires 15b4 and 15b5.

[0066] Similarly, anode electrode A2 is connected to the anode of diode element D2b and the cathode of diode element D2c. Cathode electrode K2 is connected to the cathode of diode element D2b and the anode of diode element D2c. Anode electrode A2 and cathode electrode K2 serve as temperature sensing electrodes for the semiconductor chip 12. Anode electrode A2 and cathode electrode K2 also correspond to control electrodes 12a4 and 12a5 formed on the semiconductor chip 12, respectively. Control electrodes 12a4 and 12a5 are connected to connection terminals 25a4 and 25a5, respectively, via bonding wires 15a4 and 15a5.

[0067] As mentioned above, the interiors of the storage regions R1, R2, and R3 are filled with sealing material 4. The sealing material 4 seals the semiconductor units 10, connection terminals 25a, 26a, bonding wires 15a, 15b, etc., which are located in the storage regions R1, R2, and R3.

[0068] The thermosetting resin used as the sealing member 4 shrinks during curing. In particular, the amount of shrinkage during curing of epoxy resin is greater than that of silicone gel. When the sealing member 4 shrinks, stress is applied to the component sealed by the sealing member 4 in the direction of shrinkage. If a large stress is applied to the sealed component, that component may break.

[0069] Here, we consider the contraction of the sealing member 4 in the ±Y direction within the storage regions R1, R2, and R3. Since the bonding wires 15a and 15b generally stretch along the ±Y direction, if the sealing member 4 contracts in the ±Y direction, one or both ends of the bonding wires 15a and 15b may break.

[0070] Furthermore, considering the contraction of the sealing member 4 in the ±Y direction, the sealing member 4 contracts toward the center of the storage areas R1, R2, and R3. Therefore, the amount of contraction of the sealing member 4 (the amount of movement of the sealing member 4 due to contraction) is greater near the inner walls on the +Y and -Y sides than near the center of the storage areas R1, R2, and R3, and the stress generated by the contraction is greater. Near the inner walls on the +Y side of the storage areas R1, R2, and R3, the bonding wires 15a and 15b and the connecting terminals 25a and 26a are joined via a bonding material. As described above, a large stress is generated in this region toward the center of the storage areas R1, R2, and R3 (i.e., the -Y direction), making the bonding wires 15a and 15b and the connecting terminals 25a and 26a prone to fracture.

[0071] In this embodiment, partition members 28a, 28b, and 28c (first partition members) are provided in the upper regions of storage areas R1, R2, and R3, respectively, in order to prevent the bonding wires 15a and 15b from breaking.

[0072] The partition member 28a extends in the ±X direction in the upper region of the storage area R1, and in plan view, divides the upper region (opening) of the storage area R1 into region R1a (first region) and region R1b (second region) (see Figure 1). In plan view, region R1a includes the bonding wires 15a, 15b (first bonding wires) and connection terminals 25a, 26a (first connection terminals) within the storage area R1.

[0073] Similarly, the partition member 28b extends in the ±X direction in the upper region of the storage area R2, dividing the upper region (opening) of the storage area R2 into region R2a (first region) and region R2b (second region) in a plan view (see Figure 1). Region R2a, in a plan view, includes the bonding wires 15a, 15b (first bonding wires) and connection terminals 25a, 26a (first connection terminals) within the storage area R2.

[0074] Furthermore, the partition member 28c extends in the ±X direction in the upper region of the storage area R3, dividing the upper region (opening) of the storage area R3 into region R3a (first region) and region R3b (second region) in a plan view (see Figure 1). Region R3a, in a plan view, includes the bonding wires 15a, 15b (first bonding wires) and connection terminals 25a, 26a (first connection terminals) within the storage area R2.

[0075] Figure 8 is a cross-sectional view (part 2) of the semiconductor device according to the first embodiment. Figure 8 shows a cross-sectional view when the semiconductor device 1 is cut along the line I2-I2 in Figure 2. Note that the sealing member 4 is not shown in Figure 8. Using Figures 8 and 5, we will explain in more detail, as an example, the partition member 28b provided in the storage area R2, among the partition members 28a, 28b, and 28c.

[0076] The partition member 28b (first partition member) is provided in the storage area R2, specifically in the area above the semiconductor chip 12 (first semiconductor chip) within the storage area R2. The partition member 28b divides the storage area R2 into two regions in a plan view: region R2a (first region) which includes the bonding wire 15a (first bonding wire) and the connection terminal 25a (first connection terminal), and region R2b (second region) which is on the opposite side of region R2a from the connection terminal 25a.

[0077] In the examples shown in Figures 5 and 8, the partition member 28b is formed as a beam bridging between the inner wall R2_3 (third inner wall, see Figure 1) and inner wall R2_4 (fourth inner wall, see Figure 1) of the storage area R2. The height of the partition member 28b is equal to that of the inner walls R2_3 and R2_4 (i.e., the partition walls 27a and 27b). Therefore, the sealing member 4 fills up to the upper end of the partition walls 27a and 27b and the partition member 28b.

[0078] Here, a comparative example of the semiconductor device 1 will be described using Figures 9 and 10. The following comparative example shows a semiconductor device 1 according to the first embodiment in which the partition members 28a, 28b, and 28c are not provided.

[0079] Figure 9 is a plan view of a comparative example of a semiconductor device. Figure 10 is a cross-sectional view of the comparative example of a semiconductor device. Figure 11 is an enlarged view of the main part of the cross-sectional view shown in Figure 10.

[0080] Figure 10 shows a cross-sectional view of the semiconductor device 1a (comparative example) shown in Figure 9, when it is cut along the line I2a-I2a in Figure 9. The position of the line I2a-I2a relative to the semiconductor device 1a is the same as the position of the line I2-I2 relative to the semiconductor device 1 shown in Figure 2. Also, the sealing member 4 is not shown in Figure 10. Furthermore, the width of the housing region R2 in the ±Y direction is denoted as W1. Figure 11 is an enlarged view of the cross-sectional view of Figure 10, showing the area near the inner wall R2_1 of the housing region R2.

[0081] In the semiconductor device 1a shown in Figures 9 and 10, no partition member 28b is provided in the storage area R2. Therefore, in the storage area R2, the sealing member 4 contracts over the entire ±Y direction within the storage area R2. The sealing member 4 contracts toward the center in the ±Y direction within the storage area R2.

[0082] As shown in Figure 11, near the inner wall R2_1 on the +Y side of the storage area R2, the sealing member 4 contracts in the direction of arrow AR (-Y direction), generating stress in the direction of arrow AR. This can cause the end 4a of the sealing member 4 on the +Y side to separate from the inner wall R2_1, and consequently, the joint end 15a_e of the bonding wire 15a and the connecting terminal 25a may break. In particular, when using a relatively thin bonding wire 15a with a diameter of 20 μm or more and 500 μm or less, the joint end 15a_e of the bonding wire 15a is prone to breaking from the connecting terminal 25a.

[0083] On the other hand, in the semiconductor device 1 according to the first embodiment shown in Figures 5 and 8, the upper region of the storage region R2 is divided into regions R2a and R2b by a partition member 28b. Here, the widths of regions R2a and R2b in the ±Y directions are denoted as W2 and W3, respectively. In the upper region of region R2a, the sealing member 4 contracts in the ±Y directions in a region with a width W2 that is smaller than the overall width W1 of the storage region R2. Therefore, the amount of contraction of the sealing member 4 in the upper region of region R2a is smaller than the amount of contraction of the sealing member 4 in the same region when the partition member 28b is not provided.

[0084] Therefore, the ±Y direction stress generated in the vicinity of the bonding wire 15a, particularly near the connection between the bonding wire 15a and the connecting terminal 25a, due to the contraction of the sealing member 4, is smaller when the partition member 28b is provided. As a result, the possibility of the bonding wire 15a and the connecting terminal 25a breaking can be reduced.

[0085] To reduce the possibility of breakage between the bonding wire 15a and the connection terminal 25a, it is desirable that the partition member 28b extends as low as possible in the downward direction (-Z direction). On the other hand, from the viewpoint of ease of joining the bonding wire 15a to the control electrode 12a of the semiconductor chip 12, it is desirable that there be a distance between the lower end of the partition member 28b and the bonding wire 15a and control electrode 12a that does not hinder the joining work.

[0086] Furthermore, it is desirable that the lower end of the partition member 28b extends to the height of the upper surface of the step 29a. If the lower end of the partition member 28b does not reach the height of the upper surface of the step 29a, the sealing member 4 near the joint between the bonding wire 15a and the connection terminal 25a will not be separated by the partition member 28b. By having the lower end of the partition member 28b reach the height of the upper surface of the step 29a, the sealing member 4 near the joint between the bonding wire 15a and the connection terminal 25a is separated by the partition member 28b. Therefore, the influence of stress caused by the sealing member 4 near the joint can be reduced. For example, by positioning the partition member 28b in the ±Y direction on the -Y direction side of the control electrode 12a, it is possible to extend the lower end of the partition member 28b to the height of the step 29a while ensuring workability for joining the bonding wire 15a and the control electrode 12a.

[0087] In plan view, region R2b includes the emitter electrode 12b (first main electrode) and the wiring board 11b3 (second wiring pattern) of the semiconductor chip 12 (first semiconductor chip), and the wiring member (lead frame) 14a (first wiring member) that is bonded to it. Also, the width W3 in the ±Y direction of region R2b is greater than the width W2 in the ±Y direction of region R2a. Therefore, the amount of shrinkage of the sealing member 4 in the ±Y direction in the upper region of region R2a is greater than the amount of shrinkage in the upper region of region R1a. However, the bonding strength between the wiring member 14a and the emitter electrode 12b and the wiring board 11b3 is much greater than the bonding strength between the bonding wire 15a and the connection terminal 25a. Therefore, the possibility of the wiring member 14a and the emitter electrode 12b and the wiring board 11b3 breaking due to the shrinkage of the sealing member 4 in the ±Y direction in region R2b is low.

[0088] Furthermore, in a plan view, region R2a includes multiple connection terminals 25a (connection terminals 25a1, 25a2, 25a3, 25a4, 25a5) and multiple bonding wires 15a (bonding wires 15a1, 15a2, 15a3, 15a4, 15a5). In addition, in a plan view, region R2a includes multiple connection terminals 26a (connection terminals 26a1, 26a2, 26a3, 26a4, 26a5) and multiple bonding wires 15b (bonding wires 15b1, 15b2, 15b3, 15b4, 15b5). Furthermore, region R2a may include multiple control electrodes 12a (control electrodes 12a1, 12a2, 12a3, 12a4, 12a5) of the semiconductor chip 12 and multiple control electrodes 13a (control electrodes 13a1, 13a2, 13a3, 13a4, 13a5) of the semiconductor chip 13.

[0089] On the other hand, in a plan view, region R2b does not contain any connection terminals 25a, 26a or bonding wires 15a, 15b, nor does it contain any control electrodes 12a, 13a. In this way, by excluding the connection terminals 25a, 26a and bonding wires 15a, 15b from region R2b in a plan view and concentrating them in region R2a, it is possible to effectively prevent the breakage of the connection terminals 25a, 26a and bonding wires 15a, 15b due to the shrinkage of the sealing member 4. Furthermore, by excluding the control electrodes 12a, 13a and bonding wires 15a, 15b from region R2b in a plan view and concentrating them in region R2a, it is possible to effectively prevent the breakage of the control electrodes 12a, 13a and bonding wires 15a, 15b due to the shrinkage of the sealing member 4.

[0090] In a plan view, wiring members 14a and 14b, which are solid plate-like metal materials, are arranged in region R2b, and the lower surfaces of joining portions 14a5 and 14b5 of the wiring members 14a and 14b are joined to the upper surfaces of wiring boards 11b3 and 11b1, respectively. Also, in a plan view, copper blocks 22b2, 23b2, and 24b2 connected to the inner end portions 22b1 of the first connection terminal 22, the inner end portions 23b1 of the second connection terminal 23, and the inner end portions 24b1 of the output terminal 24 are arranged in region R2b, respectively. And the lower surfaces of the copper blocks 22b2, 23b2, and 24b2 are joined to the upper surfaces of wiring boards 11b2, 11b3, and 11b1, respectively. Since these joints are made between surfaces, the joint area is larger compared to the joints of bonding wires 15a and 15b. Therefore, the bonding force is strong and it is not easily detached. Thus, breakage due to the shrinkage of the sealing member 4 hardly occurs at these joint portions, and there is no particular problem even if these joint portions are arranged in region R2b, which is a wider region compared to region R2a.

[0091] Also, since W2 < W3 as described above, the area of region R2a is smaller than that of region R2b in a plan view. Thereby, the shrinkage amount of the sealing member 4 in region R2a including the bonding wire 15a can be made smaller than the shrinkage amount of the sealing member 4 in region R2b including the wiring member (lead frame) 14a. For this reason, the possibility that the bonding wire 15a and the connection terminal 25a break can be reduced.

[0092] Also, in the examples of FIGS. 5 and 8, the partition member 28b extends in the ±X direction in the upper region of the storage region R2. That is, the partition member 28b is disposed opposite to the inner wall R2_1 (first inner wall, see FIG. 1) of the storage region R2. Thereby, the bonding wire 15a and the connection terminal 25a can be included in region R1a in a plan view, and the possibility that the bonding wire 15a and the connection terminal 25a break can be reduced.

[0093] Furthermore, in the examples shown in Figures 5 and 8, the partition member 28b is positioned between the control electrode 12a (first control electrode) and the wiring member 14a (first wiring member) in a plan view. This ensures workability for joining the bonding wire 15a and the control electrode 12a while including the bonding wire 15a and the connection terminal 25a in region R1a in a plan view, and reduces the width W2 in the ±Y direction of region R2a, thereby enhancing the effect of preventing breakage between the bonding wire 15a and the connection terminal 25a.

[0094] Furthermore, in the examples of Figures 5 and 8, the height of the lower end of the partition member 28b is the same throughout, but the height of some parts may be lowered. For example, as shown in Figure 5, the height of the partition member 28b may be lowered in the range where it does not interfere with the bonding wires 15a, 15b or the inner end 24b1 of the output terminal 24 when viewed in the Y-axis direction. Specifically, in the range from a position a certain distance away from the bonding wire 15a in the -X direction to the partition wall 27a, and in the range from a position a certain distance away from the bonding wire 15b in the +X direction to the partition wall 27b, the lower end of the partition member 28b may extend to the vicinity of the wiring boards 11b1, 11b2, or to a position where it contacts the wiring boards 11b1, 11b2.

[0095] Next, a modified example in which a part of the semiconductor device 1 according to the first embodiment is modified will be described.

[0096] [Second Embodiment] Figure 12 is a plan view of a semiconductor device according to a second embodiment.

[0097] In the semiconductor device 1b according to the second embodiment, the combined area of ​​storage areas R1, R2, and R3 in the first embodiment is referred to as the overall area R0. In this semiconductor device 1b, the members between area R1b and area R2b, and between area R2b and area R3b, of the partition walls 27a and 27b in the first embodiment have been removed. As a result, an integrated area R0b is formed in which areas R1b, R2b, and R3b are combined.

[0098] On the other hand, of the partition walls 27a and 27b, the members between region R1a and region R2a, and the members between region R2a and region R3a, are left as partition walls 27a1 and 27b1 (third partition members), respectively. A partition member 28a extending in the ±X direction is provided between the inner wall on the -X side of the overall region R0 and partition wall 27a1. A partition member 28b extending in the ±X direction is provided between partition wall 27a1 and partition wall 27b1. A partition member 28c extending in the ±X direction is provided between partition wall 27b1 and the inner wall on the +X side of the overall region R0.

[0099] As a result, regions R1a, R2a, and R3a similar to those in the first embodiment are formed. Since the widths of regions R1a, R2a, and R3a in the ±Y directions are smaller than the widths of the overall region R0 in the ±Y directions, the possibility of the bonding wires 15a and connection terminals 25a included in regions R1a, R2a, and R3a being fractured in a plan view due to the contraction of the sealing member 4 can be reduced.

[0100] On the other hand, region R0b does not contain bonding wires, but it does contain wiring components (lead frames) that have a higher bonding strength to the electrodes than bonding wires. In region R0b, the possibility of the wiring components breaking due to the shrinkage of the sealing component 4 is low.

[0101] In the second embodiment, connection terminals 25a and 26a (first and second connection terminals) are provided in order along the +X direction (first direction) parallel to the inner wall R2_1 (first inner wall). In the semiconductor unit 10, a semiconductor chip 13 (second semiconductor chip) is positioned on the +X side relative to a semiconductor chip 12 (first semiconductor chip), and a wiring member 14b (second wiring member) is connected to the emitter electrode 13b (second main electrode) on the upper surface of the semiconductor chip 13. On the upper surface of the semiconductor chip 13, on the side of the inner wall R2_1 from the wiring member 14b, a control electrode 13a (second control electrode) is formed via the wiring member 14b and a bonding wire 15b (second bonding wire). Furthermore, multiple semiconductor units 10 (semiconductor units 10a, 10b, 10c) including the semiconductor chips 12 and 13 described above are arranged in a direction parallel to the inner wall R2_1. Furthermore, in a plan view, partition members 27a1 and 27b1 (second partition members) are provided to divide the storage area containing semiconductor units 10a, 10b, and 10c into regions R1a, R2a, and R3a, respectively, on the +Y direction side of partition members 28a, 28b, and 28c, which contain semiconductor units 10a, 10b, and 10c.

[0102] [Third Embodiment] Figure 13 is a plan view of a semiconductor device according to the third embodiment. Figure 14 is a cross-sectional view of the semiconductor device according to the third embodiment. Figure 14 is an enlarged view of the vicinity of the semiconductor unit 10b in a cross-sectional view obtained when the semiconductor device 1c according to the third embodiment is cut along the line I1a-I1a in Figure 13. Note that the position of the line I1a-I1a relative to the semiconductor device 1c is the same as the position of the line I1-I1 relative to the semiconductor device 1 shown in Figure 2.

[0103] In semiconductor device 1c, the upper region of region R1a shown in Figure 12 is divided in the ±X direction by a partition member 27c1 to form regions R1a1 and R1a2. In a plan view, region R1a1 includes bonding wire 15a and connection terminal 25a, and region R1a2 includes bonding wire 15b and connection terminal 26a.

[0104] Furthermore, the upper region of region R2a shown in Figure 12 is divided in the ±X direction by the partition member 27c2 to form regions R2a1 and R2a2. In a plan view, region R2a1 includes the bonding wire 15a and the connecting terminal 25a, and region R2a2 includes the bonding wire 15b and the connecting terminal 26a.

[0105] Furthermore, the upper region of region R3a shown in Figure 12 is divided in the ±X direction by the partition member 27c3 to form regions R3a1 and R3a2. In plan view, region R3a1 includes the bonding wire 15a and the connecting terminal 25a, and region R3a2 includes the bonding wire 15b and the connecting terminal 26a.

[0106] The height of the lower end of partition member 27c1 is the same as the height of the lower end of partition member 28a (28a1, 28a2). The height of the lower end of partition member 27c2 is the same as the height of the lower end of partition member 28b (28b1, 28b2). The height of the lower end of partition member 27c3 is the same as the height of the lower end of partition member 28c (28c1, 28c2). For example, as shown in Figure 14, the inner end 24b1 of the V-phase output terminal 24b is located on the lower side (-Z side) of partition member 27c2. The height of the lower end of partition member 27c2 is set so as not to come into contact with the upper surface of the V-phase output terminal 24b.

[0107] In the semiconductor device 1c according to the third embodiment, regions R1a1, R1a2, R2a1, R2a2, R3a1, and R3a2 are formed in which the width in the ±X direction is smaller than the regions R1a, R2a, and R3a in Figure 2. In these regions R1a1, R1a2, R2a1, R2a2, R3a1, and R3a2, the amount of shrinkage in ±X during the hardening of the sealing member 4 is also suppressed. Therefore, the possibility of the bonding wire 15a and the connecting terminal 25a breaking in regions R1a1, R2a1, and R3a1 can be reduced. In addition, the possibility of the bonding wire 15b and the connecting terminal 26a breaking in regions R1a2, R2a2, and R3a2 can be reduced.

[0108] In the third embodiment, connection terminals 25a and 26a (first and second connection terminals) are provided in order along the +X direction (first direction) along the inner wall R2_1 (first inner wall). In the semiconductor unit 10, a semiconductor chip 13 (second semiconductor chip) is positioned on the +X side relative to a semiconductor chip 12 (first semiconductor chip), and a wiring member 14b (second wiring member) is connected to the emitter electrode 13b (second main electrode) on the upper surface of the semiconductor chip 13. On the upper surface of the semiconductor chip 13, on the side of the inner wall R2_1 from the wiring member 14b, a control electrode 13a (second control electrode) is formed via the wiring member 14b and a bonding wire 15b (second bonding wire). Furthermore, in a plan view, partition members 27c1, 27c2, 27c3 (third partition members) are provided to divide the storage areas R1, R2, R3 containing the semiconductor chips 12, 13 as described above into areas R1a, R2a, R3a (first area) on the +Y direction side of partition members 28a, 28b, 28c, into areas R1a1, R2a1, R3a1 (third area) containing the bonding wire 15a (first bonding wire) and connection terminal 25a (first connection terminal), and areas R1a2, R2a2, R3a2 (fourth area) containing the bonding wire 15b (second bonding wire) and connection terminal 26a (first connection terminal). [Explanation of Symbols]

[0109] 1,1a,1b,1c Semiconductor device 2 Semiconductor Modules 3 Cooling device 4 Sealing member 4a end 10, 10a, 10b, 10c Semiconductor Unit 11 Insulating substrate 11a Insulating board 11b1,11b2,11b3 Wiring board 11c metal plate 11d1,11d2,11d3 Junction area 12,13 Semiconductor chips 12a, 12a1, 12a2, 12a3, 12a4, 12a5, 13a, 13a1, 13a2, 13a3, 13a4, 13a5 control electrodes 12b, 13b Emitter electrodes 14a, 14b Wiring components 14a1,14a5,14b1,14b5 joint 14a2, 14a4, 14b2, 14b4 rising section 14a3,14b3 Bridge 15a, 15a1, 15a2, 15a3, 15a4, 15a5, 15b, 15b1, 15b2, 15b3, 15b4, 15b5 Bonding wires 15a_e Joint end 20 cases 21 Outer frame 21a,21b,21c,21d Side wall 22, 22a, 22b, 22c First connection terminal 22b1,23b1,24b1 Inner end 22b2, 23b2, 24b2 copper blocks 23, 23a, 23b, 23c Second connection terminal 24 output terminals 24a U phase output terminal 24b V phase output terminal 24c W phase output terminal 25,26 Control terminal section 25a, 25a1, 25a2, 25a3, 25a4, 25a5, 26a, 26a1, 26a2, 26a3, 26a4, 26a5 Connection terminals 25b, 26b External connection terminals 27a,27a1,27b,27b1 Bulkhead 27c1, 27c2, 27c3, 28a, 28a1, 28a2, 28b, 28b1, 28b2, 28c, 28c1, 28c2 Partition members 29a, 29b Step 31 Heat dissipation base 32 Side wall 33 Cooling bottom plate 33a Inlet 33b Outlet A1, A2 Anode electrodes AR arrow D1a, D1b, D1c, D2a, D2b, D2c Diode elements E1, E2 Emitter electrodes G1, G2 gate electrodes K1, K2 cathode electrodes M1, M2 switching elements R0 whole area R0b,R1a,R1a1,R1a2,R1b,R2a,R2a1,R2a2,R2b,R3a,R3a1,R3a2,R3b area R1, R2, R3 storage area R2_1,R2_2,R2_3,R2_4 Inner wall S1, S2 Sense emitter electrodes W1, W2, W3 width

Claims

1. The heat dissipation base, including the top surface, A semiconductor unit is provided on the upper surface of the heat dissipation base, and a first semiconductor chip including a first control electrode is provided on the upper surface of the semiconductor unit, The lower end contacts the upper surface of the heat dissipation base, surrounds the semiconductor unit, and houses the semiconductor unit in a storage area enclosed by the upper surface of the heat dissipation base, A first connection terminal is provided in the aforementioned storage area, spaced apart from the semiconductor unit, A first bonding wire electrically connects the first connection terminal and the first control electrode of the first semiconductor chip, A sealing member that seals the aforementioned storage area, A first partition member is provided in the upper region of the first semiconductor chip within the storage region, and in a plan view, divides the storage region into a first region including the first connection terminal and the first bonding wire, and a second region on the opposite side of the first connection terminal from the first region. Semiconductor device.

2. The first connection terminal is provided on the first inner wall of the outer peripheral wall, The first partition member is positioned opposite the first inner wall, The semiconductor device according to claim 1.

3. The first semiconductor chip includes the first control electrode on the first inner wall side, and further includes a first main electrode on its upper surface, which is provided on the side opposite to the first inner wall relative to the first control electrode. The semiconductor unit further includes a first wiring member bonded to the first main electrode via a bonding material, The first partition member is positioned between the first control electrode and the first wiring member in a plan view. The semiconductor device according to claim 2.

4. The semiconductor unit further includes an insulating substrate disposed on the upper surface of the heat dissipation base, a first wiring pattern formed on the upper surface of the insulating substrate on the side of the first inner wall, and a second wiring pattern formed on the side opposite to the first inner wall. The first semiconductor chip is placed on the upper surface of the first wiring pattern, The first wiring member electrically connects the first main electrode of the first semiconductor chip and the upper surface of the second wiring pattern. The semiconductor device according to claim 3.

5. The outer peripheral wall includes a second inner wall facing the first inner wall, a third inner wall connecting one end of the first inner wall and the second inner wall, and a fourth inner wall connecting the other ends of the first inner wall and the second inner wall. The first partition member is bridged between the third inner wall and the fourth inner wall. The semiconductor device according to claim 2.

6. The first inner wall has a step that protrudes inward, and the first connection terminal is provided on the step. The semiconductor device according to claim 2.

7. The first inner wall is provided with a second connection terminal on the first direction side in a plan view along the first inner wall, relative to the first connection terminal. The aforementioned semiconductor unit is A second semiconductor chip is positioned on the first direction side relative to the first semiconductor chip, A second wiring member is electrically connected to the second main electrode on the upper surface of the second semiconductor chip via a bonding material, A second control electrode is formed on the upper surface of the second semiconductor chip, on the side of the second wiring member that is closer to the first inner wall, and is electrically connected to the second connection terminal via a second bonding wire. Includes, Multiple semiconductor units are arranged in the storage area in the first direction, Multiple sets of the first connection terminals and the second connection terminals are provided on the first inner wall, corresponding to each of the multiple semiconductor units, and are electrically connected to the first control electrode and the second control electrode included in the corresponding semiconductor unit via the first bonding wire and the second bonding wire. The semiconductor device further includes a second partition member that, in a plan view, divides the first region into regions containing each of the plurality of semiconductor units. The semiconductor device according to claim 3.

8. The first inner wall is provided with a second connection terminal on the first direction side in a plan view along the first inner wall, relative to the first connection terminal. The aforementioned semiconductor unit is A second semiconductor chip is positioned on the first direction side relative to the first semiconductor chip, A second wiring member is electrically connected to the second main electrode on the upper surface of the second semiconductor chip via a bonding material, A second control electrode is formed on the upper surface of the second semiconductor chip, on the side of the second wiring member that is closer to the first inner wall, and is electrically connected to the second connection terminal via a second bonding wire. Includes, The semiconductor device further includes a third partition member that, in a plan view, divides the first region into a third region including the first connection terminal and the first bonding wire, and a fourth region including the second connection terminal and the second bonding wire. The semiconductor device according to claim 3.

9. The third partition member is bridged between the first partition member and the first inner wall. The semiconductor device according to claim 8.

10. The first wiring member is a plate-shaped metal material. The semiconductor device according to claim 3.

11. In a plan view, the area of ​​the first region is smaller than the area of ​​the second region. The semiconductor device according to claim 1.

12. In plan view, the second region does not include the bonding wire. The semiconductor device according to claim 1.

13. The first connection terminals are provided in multiple locations on the first inner wall of the outer peripheral wall, in a direction along the first inner wall when viewed from above. Multiple first control electrodes are provided on the upper surface of the first semiconductor chip in a direction along the first inner wall in a plan view, and each of the multiple first control electrodes corresponds one-to-one with one of the multiple first connection terminals. The semiconductor device has a plurality of first bonding wires, and each of the plurality of first bonding wires electrically connects one of the plurality of first connection terminals to one of the plurality of first control electrodes that corresponds to the one first connection terminal. The first partition member is positioned opposite the first inner wall, The first region includes, in plan view, a plurality of first connection terminals and a plurality of bonding wires. The semiconductor device according to claim 12.

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