Semiconductor equipment

Abstract

To provide a semiconductor device with improved operating speed and reliability. [Solution] The semiconductor device includes a source, an insulator disposed above the source, a first conductive layer in contact with the insulator in a first region, a second conductive layer disposed between the source and the first conductive layer and in contact with the insulator in a second region at a lower height from the source than the first region, a first insulating layer disposed between the first conductive layer and the second conductive layer and in contact with the insulator in a third region connecting the first region and the second region in a first direction, and a first columnar conductive portion disposed at the boundary between the first region and the third region, extending in a second direction perpendicular to the first direction and connected to the first conductive layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor devices.

Background Art

[0002] Semiconductor packages using NAND-type flash memories as semiconductor devices are known. In order to increase the capacity of such NAND-type flash memories, three-dimensional NAND-type flash memories having a configuration in which many memory cells are stacked have been put into practical use. In such a stacked three-dimensional NAND-type flash memory, it is an issue to improve the operation speed and reliability.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments according to the present disclosure provide a semiconductor device with improved operation speed and reliability.

Means for Solving the Problems

[0005] A semiconductor device according to one embodiment includes a source, an insulator disposed above the source, a first conductive layer in contact with the insulator in a first region, a second conductive layer disposed between the source and the first conductive layer and in contact with the insulator in a second region at a lower height from the source than the first region, a first insulating layer disposed between the first conductive layer and the second conductive layer and in contact with the insulator in a third region connecting the first region and the second region in a first direction, and a first columnar conductive portion disposed at the boundary between the first region and the third region, extending in a second direction perpendicular to the first direction and connected to the first conductive layer. [Brief explanation of the drawing]

[0006] [Figure 1] This is a top view showing the overall configuration of a semiconductor device according to one embodiment. [Figure 2] This is a perspective view showing the configuration near the contact area HUR of the semiconductor device according to this embodiment. [Figure 3] A perspective view showing the configuration of the memory cell region (MCR) and the contact region (HUR) of a semiconductor device according to one embodiment. [Figure 4] This is a top view showing the configuration of the contact area HUR of a semiconductor device according to one embodiment. [Figure 5] This is a cross-sectional view showing the configuration of a contact plug in a semiconductor device according to one embodiment. [Figure 6] This is a cross-sectional view showing the configuration of a contact plug in a semiconductor device according to one embodiment. [Figure 7] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. [Figure 8] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. [Figure 9] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. [Figure 10] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. [Figure 11]This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. [Figure 12] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. [Figure 13] This is a cross-sectional view showing the configuration of a contact plug in a semiconductor device according to one embodiment. [Figure 14] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. [Figure 15] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. [Figure 16] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. [Figure 17] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. [Modes for carrying out the invention]

[0007] The semiconductor device according to this embodiment will be described in detail below with reference to the drawings. In the following description, elements having substantially the same function and configuration are denoted by the same reference numeral or by a reference numeral followed by an alphabet letter, and will be described redundantly only when necessary. The embodiments shown below illustrate devices and methods for realizing the technical idea of ​​this embodiment. Various modifications can be made to the embodiments without departing from the spirit of the invention. These embodiments and their variations are included within the scope of the invention and its equivalents as described in the claims.

[0008] While drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation, these are merely examples and do not limit the interpretation of the present invention. In this specification and in each drawing, elements having the same function as those described in previously shown drawings are denoted by the same reference numerals, and redundant explanations may be omitted.

[0009] In this specification, expressions such as "α is A, B, or C" do not exclude the case where α includes a plurality of combinations of A to C, unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.

[0010] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0011] In each embodiment of the present invention, the direction from the source to the memory cell is referred to as upward. Conversely, the direction from the memory cell to the source is referred to as downward. Thus, for the sake of convenience of explanation, the terms upward or downward are used for explanation. However, for example, the vertical relationship between the source and the memory cell may be arranged in the reverse of the illustration. Also, in the following explanation, an expression such as a memory cell on the source, for example, merely explains the vertical relationship between the source and the memory cell as described above, and other members may be arranged between the source and the memory cell.

[0012] [First Embodiment] [Overall Configuration of Semiconductor Device] The overall configuration of the semiconductor device according to this embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a top view showing the overall configuration of the semiconductor device 10 according to this embodiment. FIG. 2 is a perspective view showing the configuration near the contact region HUR of a certain block BLK according to this embodiment. In FIGS. 1 and 2, two directions parallel to the main surface of the source 11 and perpendicular to each other are referred to as the X direction and the Y direction, and a plane parallel to the main surface of the source 11 is referred to as the XY plane. A direction perpendicular to both the X direction and the Y direction is referred to as the Z direction (stacking direction).

[0013] The semiconductor device 10 is, for example, a NAND flash memory device. The semiconductor device 10 includes a source 11. Two memory cell regions MCR and a contact region HUR are partitioned on the source 11. A memory cell array 16 is formed in the memory cell region MCR, which includes a plurality of memory cells stacked in three dimensions. Specifically, a memory string is formed by connecting a source-side select gate transistor, a plurality of memory cell transistors (e.g., 64), and a drain-side select gate transistor in series in the direction perpendicular to the main surface (XY plane) of the source 11 (Z direction). Dummy cell transistors may be included at both ends of the plurality of memory cell transistors connected in series, or in some of the spaces between the plurality of memory cell transistors. The memory cell array 16 includes a laminate in which a plurality of conductive layers, which serve as source-side select gate lines, word lines, and drain-side select gate lines connected to each transistor, are stacked with an insulating layer in between. The plurality of conductive layers of the memory cell array 16 extend into the contact region HUR, forming a stacked wiring structure 17 and a bridge portion 18.

[0014] The contact region HUR is located between two memory cell regions MCR. The contact region HUR is positioned approximately in the center of the semiconductor device 10 in the X direction (the direction in which the slit ST extends). The memory cell arrays 16, which are spaced apart in the X direction, are electrically connected in the contact region HUR by a multilayer wiring structure 17 and a bridge portion 18 adjacent in the Y direction. The bridge portion 18 includes a laminate in which multiple conductive layers corresponding to wiring drawn from source-side select gate lines, word lines, and drain-side select gate lines connected to each transistor of the memory cell array 16 are stacked with an insulating layer in between. The bridge portion 18 extends in the X direction (the direction in which the slit ST extends) and electrically connects the memory cell arrays 16, which are spaced apart in the X direction, layer by layer.

[0015] A slit ST is formed in the semiconductor device 10. The slit ST extends in the stacking direction (Z direction) of the memory cell array 16, penetrating the memory cell array 16 and reaching the source 11. The slit ST extends in the X direction, separating the memory cell array 16 into multiple blocks BLK in the Y direction. An insulating layer is formed in the slit ST.

[0016] [Configuration of memory cell area (MCR) and contact area (HUR)] Figure 3 is a perspective view showing the configuration of the memory cell region (MCR) and contact region (HUR) of the semiconductor device according to this embodiment. To prevent confusion in the figure, conductive components are shown, while insulating components are omitted. The parts of Figure 3 where components are not shown are insulated using an insulating material such as silicon dioxide.

[0017] In the memory cell region (MCR), a memory cell array 16 is formed on a source 11. The source 11 can be a semiconductor substrate made of, for example, a silicon single crystal, a semiconductor layer made of polysilicon, or a conductive layer made of a metal such as tungsten. The memory cell array 16 has conductive layers 71, 72, 73, and 74 (when conductive layers 71 to 74 are not distinguished, they are referred to as conductive layer 70) that extend substantially parallel to the surface of the source 11. The memory cell array 16 has a laminate in which these multiple conductive layers 70 are stacked with insulating layers in between. Here, the material of the conductive layer 70 may be, for example, tungsten or molybdenum. The material of the insulating layer may be, for example, a silicon dioxide film (SiO2), or oxygen-containing silicon such as TEOS (Tetra Ethyl Ortho Silicate). In the figure, only four conductive layers 70 are shown, but many more layers, such as 33 layers or 65 layers, are stacked. These conductive layers 70 correspond to the source-side select gate line, word line, or drain-side select gate line connected to the transistor.

[0018] In the memory cell region (MCR), a memory pillar 60 is formed that penetrates multiple conductive layers 70 and multiple insulating layers. The memory pillar 60 is cylindrical in shape, and from the outer periphery toward the center, a block insulating film containing a silicon dioxide film, a charge storage film containing a silicon nitride film, a tunnel insulating film containing a silicon dioxide film, a semiconductor channel containing an amorphous or polycrystalline silicon film, and a silicon dioxide film are stacked. A portion of the charge storage film located between the conductive layers 71, 72, 73, and 74 corresponding to the select gate line or word line and the semiconductor channel functions as part of a non-volatile memory cell that traps carriers.

[0019] The upper end of the semiconductor channel of the memory pillar 60 is connected to a bit line BL (not shown). Multiple memory pillars 60, one selected from each block BLK separated in the Y direction by a slit ST, are connected to a common bit line BL that extends in the Y direction.

[0020] A multilayer wiring structure 17 is formed on the source 11 in the contact region HUR. The contact region HUR also has multiple insulating layers and multiple conductive layers 70 that extend from the memory cell region MCR. The multilayer wiring structure 17 has conductive layers 71, 72, 73, and 74 that extend substantially parallel to the surface of the source 11. The multilayer wiring structure 17 has a laminate in which these multiple conductive layers 70 are stacked with insulating layers in between. Although only four conductive layers are shown in the figure, as mentioned above, many more layers, such as 33 layers and 65 layers, are stacked. These multiple conductive layers 70 in the contact region HUR correspond to wiring drawn from the source-side select gate line, word line, or drain-side select gate line.

[0021] In the contact area HUR, the conductive layers 71, 72, 73, and 74 corresponding to the wiring drawn from the select gate line or word line are formed in a stepped structure in the X direction so as to expose a portion of the underlying conductive layer.

[0022] The contact region HUR has a contact plug 50 that penetrates multiple conductive layers 70 and multiple insulating layers. The contact plug 50 is roughly cylindrical in shape, but its details will be described later. The material of the contact plug 50 may be, for example, tungsten.

[0023] The conductive layers 71, 72, 73, and 74 are connected to their respective contact plugs 51, 52, 53, and 54 (referred to as contact plug 50 when contact plugs 51 through 54 are not distinguished) in the step regions exposed by the staircase structure. Here, conductive layer 71 is connected to contact plug 51, conductive layer 72 is connected to contact plug 52, conductive layer 73 is connected to contact plug 53, and conductive layer 74 is connected to contact plug 54. Although only four contact plugs 50 are shown in the figure, for example, the same number as the number of conductive layers may be arranged. Each contact plug 50 is insulated from the underlying conductive layer 70 other than the conductive layer 70 to which it is connected via an insulating layer (not shown). Each contact plug 50 is drawn out onto the laminated wiring structure 17 through a contact hole that penetrates an insulator (not shown).

[0024] [Configuration of stacked wiring structures and contact plugs] The configuration of the stacked wiring structure and contact plug according to this embodiment will be explained with reference to Figures 4 to 6. Figure 4 is a schematic top view showing the contact region HUR of a certain block BLK according to this embodiment. Figures 5 and 6 are cross-sectional views showing the configuration of the contact plug of the semiconductor device according to this embodiment. Figure 5 is a cross-sectional view obtained by cutting the contact region HUR shown in Figure 4 along A-A', and Figure 6 corresponds to a cross-sectional view obtained by cutting the contact region HUR shown in Figure 4 along B-B'.

[0025] As shown in Figure 4, the contact region HUR is provided with a multilayer wiring structure 17 for connecting contact plugs 50 to each of the multiple conductive layers 70. The multiple contact plugs 50 are arranged in a square grid along the X and Y directions within the multilayer wiring structure 17. In the multilayer wiring structure 17, the multiple conductive layers 70 are formed in a stepped structure so that each is exposed from the upper conductive layer 70 (opposite the source 11). An insulator 30 is placed on top of the multilayer wiring structure 17 (in the opening region). However, for the sake of explanation, this is omitted in Figure 4.

[0026] The multiple contact plugs 50 include multiple contact plugs 51a, 52a, 53a, 54a, 55a (referred to as contact plug 50a when contact plugs 51a to 55a are not distinguished) and multiple contact plugs 51b, 52b, 53b, 54b, 55b (referred to as contact plug 50b when contact plugs 51b to 55b are not distinguished). The multiple contact plugs 50a are positioned in the Y direction opposite to the bridge portion 18 and are connected to multiple conductive layers 70a. The multiple contact plugs 50b are positioned in the Y direction between the bridge portion 18 and the contact plugs 50a and are connected to multiple conductive layers 70b (referred to as conductive layer 70 when conductive layers 70a and conductive layers 70b are not distinguished).

[0027] As shown in Figure 5, adjacent contact plugs 50a in the X direction are arranged with one conductive layer 70a between each. Here, the conductive layer 71a placed on the insulating layer 41a is connected to the contact plug 51a, the conductive layer 72a placed above the insulating layer 42a is connected to the contact plug 52a, the conductive layer 73a placed above the insulating layer 43a is connected to the contact plug 53a, the conductive layer 74a placed above the insulating layer 44a is connected to the contact plug 54a, and the conductive layer 75a placed above the insulating layer 45a is connected to the contact plug 55a (here, when insulating layer 41a and insulating layer 45a are not distinguished, they are referred to as insulating layer 40a, and when conductive layer 71a and conductive layer 75a are not distinguished, they are referred to as conductive layer 70a).

[0028] As shown in Figure 6, contact plugs 50a and adjacent contact plugs 50b in the Y direction are arranged for every multiple conductive layers 70b. Figure 6 shows an example in which contact plug 54a and adjacent contact plug 54b in the Y direction are connected to multiple conductive layers 77b, but is not limited to this. Multiple contact plugs 50b may be arranged in the Y direction between the bridge portion 18 and the contact plug 50a. Here, the conductive layer 77b arranged on the insulating layer 47b is connected to the contact plug 54b.

[0029] As shown in Figure 6, the laminated wiring structure 17 includes a first region 1, a second region 2, and a third region 3 in the Y direction. The bridge portion 18 includes a fourth region 4 and a fifth region 5 in the Y direction. The first region 1, the second region 2, and the fourth region 4 are step regions of a staircase structure, where the conductive layer 70 corresponding to the upper surface of the laminate is exposed and is approximately parallel to the source 11. The conductive layer 70 exposed on the upper surface of the laminate is in contact with the insulator 30. The height of the first region 1 is lower from the source 11 than that of the fourth region 4, and the height of the second region 2 is lower from the source 11 than that of the first region 1. For example, the conductive layer 77b is exposed in the first region 1, the conductive layer 74a below the conductive layer 77b (on the source 11 side) is exposed in the second region 2, and the conductive layer 79b above the conductive layer 77b (on the opposite side from the source 11) is exposed in the fourth region 4. The step height of the staircase structure is not particularly limited (when conductive layers 77b...79b are not distinguished, it will be referred to as conductive layer 70b).

[0030] The third region 3 and the fifth region 5 are tapered regions that connect the step regions of the staircase structure in the Y direction, and the insulating layer 40 (referred to as insulating layer 40 when insulating layers 44a...47b...49b are not distinguished) is exposed. The third region 3 connects the first region 1 and the second region 2, and the fifth region 5 connects the first region 1 and the fourth region 4. For example, the insulating layer 47b below the conductive layer 77b (source 11 side) is exposed in the third region 3, and the insulating layer 49b below the conductive layer 79b (source 11 side) is exposed in the fifth region 5 (referred to as insulating layer 40b when insulating layers 47b...49b are not distinguished).

[0031] The conductive layer 77b exposed in the first region 1, the conductive layer 74a exposed in the second region 2, and the conductive layer 79b exposed in the fourth region 4 have a thickness in the Z direction (lamination direction) that is greater than that of the underlying conductive layer 70. Furthermore, the thickness of the conductive layer 77b exposed in the first region 1 is greater than the thickness of the conductive layer 77b in the fourth region 4, and the thickness of the conductive layer 74a exposed in the second region 2 is greater than the thickness of the conductive layer 74a in the first region 1. An insulator 30 that embeds the stepped structure is placed on top of the laminate of the insulating layer 40 and the conductive layer 70.

[0032] The contact plugs 50a and 50b (referred to as contact plug 50 when not distinguished) extend in the lamination direction (Z direction) of the laminate, penetrating the insulator 30 and the laminate of the insulating layer 40 and the conductive layer 70 to reach the source 11. Contact plug 50a is positioned in the second region 2. Contact plug 50b is positioned in the first region 1 and the third region 3. The width of the second region 2 in the Y direction is approximately the same as the sum of the width of the first region 1 in the Y direction and the width of the third region 3 in the Y direction. Therefore, contact plug 50b is positioned at the boundary (dotted arrow) between the first region 1 and the third region 3.

[0033] The contact plug 50a has a widened portion A that protrudes in the direction of connection with the conductive layer 70a. For example, the contact plug 54a has a disc-shaped widened portion A in the portion facing the conductive layer 74a in the step region of the staircase structure, which has a larger diameter (width in the XY direction) than the portion facing the insulating layer 44a one layer below. The widened portion A of the contact plug 54a connects with the conductive layer 74a in the XY direction in the second region 2.

[0034] The contact plug 50b has a widened portion B that protrudes in the direction of connection with the conductive layer 70b. For example, the contact plug 54b has a fan-shaped widened portion B in the part facing the conductive layer 77b in the step region of the staircase structure, which has a larger diameter (width in the Y direction) than the part facing the insulating layer 47b one layer below. The widened portion B of the contact plug 54b connects with the conductive layer 77b in the Y direction in the first region 1.

[0035] An insulating film 31 is placed between the contact plug 50 and the underlying conductive layer 70 other than the conductive layer 70 connected via the widened portion A or widened portion B. The contact plug 50 and the underlying conductive layer 70 other than the conductive layer 70 connected via the widened portion A or widened portion B can be insulated by the placement of the insulating film 31.

[0036] As described above, in the stacked wiring structure according to this embodiment, even if the contact plug 54b is placed in the tapered region of the stepped structure, the insulating film 31 is placed between the conductive layer 70b below the conductive layer 77b and the side surface of the contact plug 54b, so that the contact plug 54b and the conductive layer 77b can be reliably connected, thereby providing a semiconductor device 10 with improved reliability.

[0037] The Y-direction width of the second region 2 forming the contact plug 54a can be designed to be approximately the same as the sum of the Y-direction width of the first region 1 forming the contact plug 54b and the Y-direction width of the third region 3, thereby reducing the Y-direction width of the multilayer wiring structure 17. As a result, the Y-direction width of the bridge portion 18 can be increased, and the increase in resistance of the bridge portion 18 can be suppressed, making it possible to provide a semiconductor device with improved operating speed (read and program operation speed).

[0038] [Manufacturing method for stacked wiring structures] The manufacturing method of the stacked wiring structure 17 according to this embodiment will be described with reference to Figures 7 to 12.

[0039] First, an insulating layer 40 and a sacrificial layer 20 (referred to as sacrificial layer 20 when sacrificial layers 24a...27b...29b are not distinguished) are alternately deposited one layer at a time on a semiconductor substrate Y to form a laminate. These insulating layers 40 and sacrificial layers 20 are deposited, for example, using a CVD apparatus. The alternately laminated insulating layers 40 and sacrificial layers 20 are formed to be in contact with each other. The insulating layers 40 and sacrificial layers 20 are periodically laminated in a direction perpendicular to the main surface of the semiconductor substrate Y. In this embodiment, the material of the insulating layer 40 may be a silicon dioxide film (SiO2). The material of the sacrificial layer 20 may be a silicon nitride film (SiN). However, the material of the sacrificial layer 20 is not limited to these, and may be silicon, or a metal such as tungsten.

[0040] As shown in Figure 7, the laminate of the insulating layer 40 and the sacrificial layer 20 is formed in a stepped structure so as to expose the lower sacrificial layer 20. The region forming the laminated wiring structure 17 includes a first region 1, a second region 2, and a third region 3 in the Y direction. The region that will later become the bridge portion 18 includes a fourth region 4 and a fifth region 5 in the Y direction. The first region 1, the second region 2, and the fourth region 4 are step regions of the stepped structure, where the sacrificial layer 20 is exposed and formed approximately parallel to the semiconductor substrate Y. The first region 1 is lower in height from the semiconductor substrate Y than the fourth region 4, and the second region 2 is lower in height from the semiconductor substrate Y than the first region 1. For example, the first region 1 exposes the sacrificial layer 27b, the second region 2 exposes the sacrificial layer 24a below the sacrificial layer 27b (on the semiconductor substrate Y side), and the fourth region 4 exposes the sacrificial layer 29b above the sacrificial layer 27b (on the opposite side from the semiconductor substrate Y). The step difference of the step regions of the staircase structure is not particularly limited. For example, it is preferable to arrange 6 to 24 sacrificial layers 20 between the sacrificial layer 24a and the sacrificial layer 27b.

[0041] The third region 3 and the fifth region 5 are tapered regions that connect the step regions of the staircase structure in the Y direction, and the insulating layer 40 is exposed. The third region 3 connects the first region 1 and the second region 2, and the fifth region 5 connects the first region 1 and the fourth region 4. For example, the insulating layer 47b below the sacrificial layer 27b (on the semiconductor substrate Y side) is exposed in the third region 3, and the insulating layer 49b below the sacrificial layer 29b (on the semiconductor substrate Y side) is exposed in the fifth region 5. The staircase structure of the laminate of insulating layer 40 and sacrificial layer 20 is formed by RIE (Reactive Ion Etching) using a mask with a pattern formed by photolithography. However, the method of forming the staircase structure is not particularly limited.

[0042] The sacrificial layer 27b exposed in the first region 1, the sacrificial layer 24a exposed in the second region 2, and the sacrificial layer 29b exposed in the fourth region 4 are thickened in the Z direction (lamination direction) by depositing silicon nitride (SiN) using a CVD apparatus. As a result, the thickness of the sacrificial layer 27b exposed in the first region 1 is thicker than the thickness of the sacrificial layer 27b exposed in the fourth region 4, and the thickness of the sacrificial layer 24a exposed in the second region 2 is thicker than the thickness of the sacrificial layer 24a exposed in the first region 1. An insulator 30 that embeds the step structure is formed on top of the laminate of the insulating layer 40 and the sacrificial layer 20.

[0043] As shown in Figure 8, contact holes Ha and Hb (referred to as contact hole H when no distinction is made between contact holes Ha and Hb) are formed in a stepped laminate. Contact holes H are formed to extend in the stacking direction (Z direction) of the laminate, penetrating the insulator 30 and the laminate of the insulating layer 40 and sacrificial layer 20 to reach the semiconductor substrate Y. Contact hole Ha is formed in the second region 2. Contact holes Hb are formed in the first region 1 and the third region 3. The width of the second region 2 in the Y direction is approximately the same as the sum of the width of the first region 1 in the Y direction and the width of the third region 3 in the Y direction. Therefore, contact holes Hb may be formed at the boundary (dotted arrow) between the first region 1 and the third region 3. Contact holes H are formed by RIE using a mask having a pattern formed by photolithography. The pattern of the mask has an opening that exposes the insulator 30 in the region where contact holes H are formed. However, the method of forming contact holes H is not particularly limited.

[0044] As shown in Figure 9, the sacrificial layer 20 exposed on the inner surface of the contact hole H is etched. The etching of the sacrificial layer 20 exposed on the inner surface of the contact hole H is preferably selective etching of the silicon nitride (SiN) film, and may be wet etching using phosphoric acid, for example. By etching the sacrificial layer 20, a groove is formed on the inner surface of the contact hole H that protrudes outward from the contact hole H. Here, the sacrificial layer 27b exposed on the inner surface of the contact hole Hb and the sacrificial layer 24a exposed on the inner surface of the contact hole Ha are thickened in the Z direction (stacking direction), so a groove larger in the Z direction (stacking direction) is formed than the sacrificial layer 20 of the respective lower layer.

[0045] As shown in Figure 10, an insulating film 31 is deposited on a laminate having contact holes H. The material of the insulating film 31 may be, for example, a silicon dioxide film (SiO2). The silicon dioxide film (SiO2) is deposited, for example, using a CVD apparatus. By depositing the insulating film 31 on the inner surface of the contact holes H, most of the grooves formed by etching the sacrificial layer 20 exposed on the inner surface of the contact holes H are filled with the insulating film 31. On the other hand, the groove b formed by etching the sacrificial layer 27b formed on the inner surface of the contact hole Hb and the groove a formed by etching the sacrificial layer 24a formed on the inner surface of the contact hole Ha are large in the Z direction (lamination direction), so grooves a and b remain on the inner surfaces of the contact holes Ha and Hb, respectively.

[0046] As shown in Figure 11, the insulating film 31 exposed on the surface of the laminate having contact holes H is etched. The etching of the insulating film 31 exposed on the surface of the laminate is preferably selective etching of the silicon dioxide film (SiO2), and may be wet etching using DHF or BHF, for example. By etching the insulating film 31 exposed on the surface of the laminate, the diameter of the contact hole H and the groove b formed by etching of the sacrificial layer 27b formed on the inner surface of the contact hole Hb and the groove a formed by etching of the sacrificial layer 24a formed on the inner surface of the contact hole Ha become larger. On the other hand, the grooves of the sacrificial layer 20 below the sacrificial layer 27b exposed on the inner surface of the contact hole Hb, which is filled with insulating film 31, and the grooves of the sacrificial layer 20 below the sacrificial layer 24a exposed on the inner surface of the contact hole Ha are small in the Z direction (lamination direction), so the insulating film 31 remains unetched and remains as a spacer between the inner surfaces of the contact holes Ha and Hb and the sacrificial layer 20.

[0047] As shown in Figure 12, an insulator 32 is formed inside the contact hole H. The material of the insulator 32 may be, for example, a double structure of a silicon dioxide film (SiO2) and an amorphous silicon film. The silicon dioxide film (SiO2) and amorphous silicon film are deposited, for example, using a CVD apparatus.

[0048] A conductive layer 70 is formed in the region where the sacrificial layer 20 is located. A slit (not shown) is dug in a predetermined region of the laminate, and the sacrificial layer 20 contained in the laminate is removed all at once through the slit. As a result, a cavity is created in the area where the sacrificial layer 20 was located. Then, a conductive layer 70 is formed by filling this cavity with a metal such as tungsten.

[0049] Next, the insulator 32 inside the contact hole H is removed by anisotropic etching such as RIE. The etching of the insulator 32 is preferably selective etching of the amorphous silicon film, and may be RIE using CF4 and oxygen, for example. By removing the insulator 32, the groove b formed by etching the sacrificial layer 27b on the inner surface of the contact hole Hb exposes the conductive layer 77b, and the groove a formed by etching the sacrificial layer 24a on the inner surface of the contact hole Ha exposes the conductive layer 74a.

[0050] By embedding a metal such as tungsten inside the contact holes Ha and Hb, contact plugs 54a and 54b shown in Figure 6 are formed. Grooves b formed by etching the sacrificial layer 27b on the inner surface of contact hole Hb and groove a formed by etching the sacrificial layer 24a on the inner surface of contact hole Ha form widened portions A and B of contact plug 54b, respectively. As a result, widened portion A of contact plug 54a is connected to the conductive layer 74a, and widened portion B of contact plug 54b is connected to the conductive layer 77b.

[0051] As described above, the manufacturing method of the laminated wiring structure according to this embodiment provides a semiconductor device 10 with improved reliability because, even when a contact hole Hb is formed in the tapered region of the stepped structure, a spacer remains between the conductive layer 70 below the conductive layer 77b and the inner surface of the contact hole Hb, ensuring a secure connection between the contact plug 54b and the conductive layer 77b.

[0052] The Y-direction width of the second region 2 forming the contact plug 54a can be designed to be approximately the same as the sum of the Y-direction width of the first region 1 forming the contact plug 54b and the Y-direction width of the third region 3, thereby reducing the Y-direction width of the multilayer wiring structure 17. As a result, the Y-direction width of the bridge portion 18 can be increased, and the increase in resistance of the bridge portion 18 can be suppressed, making it possible to provide a semiconductor device with improved operating speed (read and program operation speed).

[0053] [Second Embodiment] [Overall configuration of semiconductor device] The overall configuration of the semiconductor device according to the second embodiment is the same as the overall configuration of the semiconductor device according to the first embodiment. The configuration of the stacked wiring structure according to the second embodiment is the same as the configuration of the stacked wiring structure according to the first embodiment, except for the configuration of the contact plug. The explanation of the sameness as the first embodiment will be omitted, and here we will explain the parts that differ from the configuration of the contact plug according to the first embodiment.

[0054] [Contact plug configuration] The configuration of the contact plug in this embodiment will be explained using Figure 13. Figure 13 corresponds to a cross-sectional view obtained by cutting the contact region HUR shown in Figure 4 along line B-B'.

[0055] As shown in Figure 13, the contact plug 50c (corresponding to the contact plug 50a in Figure 4; here, when contact plugs 51c to 55c are not distinguished, it is referred to as contact plug 50c) and the contact plug 50d (corresponding to the contact plug 50b in Figure 4; here, when contact plugs 51d to 55d are not distinguished, it is referred to as contact plug 50d, and when contact plugs 50c and 50d are not distinguished, it is referred to as contact plug 50) extend in the stacking direction (Z direction) of the laminate and are connected to the conductive layer 70 exposed in the step region of the staircase structure.

[0056] The contact plug 50c is positioned in the second region 2. The contact plug 50d is positioned in the first region 1 and the third region 3. The width of the second region 2 in the Y direction is approximately the same as the sum of the width of the first region 1 in the Y direction and the width of the third region 3 in the Y direction. Therefore, the contact plug 50d is positioned at the boundary (dotted arrow) between the first region 1 and the third region 3.

[0057] The contact plug 50c connects to the upper surface of the conductive layer 70 that is exposed in the step region of the staircase structure in the second region 2. For example, the contact plug 54c connects to the upper surface of the conductive layer 74a in the Z direction in the second region 2.

[0058] The contact plug 50d connects to the end of the conductive layer 70 exposed in the step region of the staircase structure at the boundary between the first region 1 and the third region 3 (dotted arrow). For example, the contact plug 54d connects to the end of the conductive layer 77b in the Y direction at the boundary between the first region 1 and the third region 3.

[0059] An insulating film 31 is placed between the contact plug 50 and the underlying conductive layer 70 other than the conductive layer 70 connected to the contact plug 50. The contact plug 50 and the underlying conductive layer 70 other than the conductive layer 70 connected to the contact plug 50 can be insulated from each other via the insulating film 31.

[0060] As described above, even when the contact plug 54d is placed in the tapered region of the stepped structure of the laminated wiring structure according to this embodiment, it is insulated from the conductive layer 70 below the conductive layer 77b, and the contact plug 54d and the conductive layer 77b can be reliably connected, thus providing a semiconductor device 10 with improved reliability.

[0061] The Y-direction width of the second region 2 forming the contact plug 54c can be designed to be approximately the same as the sum of the Y-direction width of the first region 1 forming the contact plug 54d and the Y-direction width of the third region 3, thereby reducing the Y-direction width of the multilayer wiring structure 17. As a result, the Y-direction width of the bridge portion 18 can be increased, and the increase in resistance of the bridge portion 18 can be suppressed, making it possible to provide a semiconductor device with improved operating speed (read and program operating speed).

[0062] [Manufacturing method for stacked wiring structures] The manufacturing method of the stacked wiring structure 17 according to this embodiment will be described with reference to Figures 7, 8, and 14 to 17.

[0063] As shown in Figure 7, the laminate of the insulating layer 40 and the sacrificial layer 20 is formed in a stepped structure so as to expose the lower sacrificial layer 20, and contact holes Hc and contact holes Hd (contact holes H when not distinguished from contact holes Hc and contact holes Hd are referred to as contact holes H) are formed in the stepped laminate, similar to Figure 8. Contact holes Hc are formed in the second region 2, and contact holes Hd are formed in the first region 1 and the third region 3.

[0064] As shown in Figure 14, the insulating layer 40 exposed on the inner surface of the contact hole H is etched. The etching of the insulating layer 40 exposed on the inner surface of the contact hole H is preferably selective etching of the silicon dioxide film, and may be wet etching using DHF or BHF, for example. By etching the insulating layer 40, a sacrificial layer 20 protrudes from the inner surface of the contact hole H in the direction inward of the contact hole H.

[0065] As shown in Figure 15, an insulating film 31 is deposited on a laminate having contact holes H. The material of the insulating film 31 may be, for example, a silicon dioxide film (SiO2). The silicon dioxide film (SiO2) is deposited, for example, using a CVD apparatus. By depositing the insulating film 31 on the inner surface of the contact holes H, the protrusions of the sacrificial layer 20 formed by etching the insulating layer 40 exposed on the inner surface of the contact holes H are filled with the insulating film 31.

[0066] As shown in Figure 16, the insulating film 31 exposed on the surface of the laminate having contact holes H is etched. The etching of the insulating film 31 exposed on the surface of the laminate is preferably selective etching of the silicon dioxide film (SiO2), and may be wet etching using DHF or BHF, for example. By etching the insulating film 31 exposed on the surface of the laminate, the upper part of the contact hole H, the protrusion d of the sacrificial layer 27 formed on the inner surface of the contact hole Hd, and the protrusion c of the sacrificial layer 24 formed on the inner surface of the contact hole Hc are exposed. On the other hand, the insulating film 31 remains as a spacer in the lower part of the contact hole Hd and the lower part of the contact hole Hc that were filled with the insulating film 31, without being etched.

[0067] As shown in Figure 17, an insulator 32 is formed inside the contact hole H. The material of the insulator 32 may be, for example, a double structure of a silicon dioxide film (SiO2) and an amorphous silicon film. The silicon dioxide film (SiO2) and amorphous silicon film are deposited, for example, using a CVD apparatus.

[0068] A conductive layer 70 is formed in the region where the sacrificial layer 20 is located. A slit (not shown) is dug in a predetermined region of the laminate, and the sacrificial layer 20 contained in the laminate is removed all at once through the slit. As a result, a cavity is created in the area where the sacrificial layer 20 was located. Then, a conductive layer 70 is formed by filling this cavity with a metal such as tungsten.

[0069] Next, the insulator 32 inside the contact hole H is removed by anisotropic etching such as RIE. The etching of the insulator 32 is preferably selective etching of the amorphous silicon film, and may be RIE using CF4 and oxygen, for example. By removing the insulator 32, the conductive layer 77b protruding from the inner surface of the contact hole Hd is exposed, and the conductive layer 74a protruding from the inner surface of the contact hole Hc is exposed.

[0070] By embedding a metal such as tungsten inside the contact holes Hc and Hd, the contact plugs 54c and 54d shown in Figure 13 are formed. As a result, contact plug 54c is connected to the conductive layer 74a, and contact plug 54d is connected to the conductive layer 77b.

[0071] As described above, the manufacturing method of the stacked wiring structure according to this embodiment provides a semiconductor device 10 with improved reliability because, even if contact holes Hd are formed in the tapered region of the stepped structure, a spacer remains between the conductive layer 70 below the conductive layer 77b and the contact plug 54d, ensuring a reliable connection between the contact plug 54d and the conductive layer 77b.

[0072] The Y-direction width of the second region 2 forming the contact plug 54c can be designed to be approximately the same as the sum of the Y-direction width of the first region 1 forming the contact plug 54d and the Y-direction width of the third region 3, thereby reducing the Y-direction width of the multilayer wiring structure 17. As a result, the Y-direction width of the bridge portion 18 can be increased, and the increase in resistance of the bridge portion 18 can be suppressed, making it possible to provide a semiconductor device with improved operating speed (read and program operating speed).

[0073] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0074] 1 First region, 2 Second region, 3 Third region, 4 Fourth region, 5 Fifth region, 7 Conductive layer, 10 Semiconductor device, 11 Source, 16 Memory cell array, 17 Stacked wiring structure, 18 Bridge section, 50 Contact plug, 70 Conductive layer, Groove a, Groove b, Protrusion c, Protrusion d

Claims

1. Source and, An insulator positioned above the source, A first conductive layer in contact with the insulator in the first region, A second conductive layer is disposed between the source and the first conductive layer, and is in contact with the insulator in a second region where the height from the source is lower than that of the first region. A first insulating layer is disposed between the first conductive layer and the second conductive layer, and in contact with the insulator in a third region that connects the first region and the second region in a first direction, A first columnar conductive portion is positioned at the boundary between the first region and the third region, extends in a second direction perpendicular to the first direction, and is connected to the first conductive layer, Semiconductor equipment, including

2. A second columnar conductive portion is arranged in the second region, extends in the second direction, and is connected to the second conductive layer. The semiconductor device according to claim 1, further comprising:

3. The semiconductor device according to claim 2, wherein the width of the second region in the first direction is the sum of the width of the first region in the first direction and the width of the third region in the first direction.

4. A third conductive layer is positioned on the opposite side of the first conductive layer from the source and is in contact with the insulator in a fourth region that is higher in height from the source than the first region, A second insulating layer is disposed between the first conductive layer and the third conductive layer, and is in contact with the insulator in a fifth region that connects the first region and the fourth region in the first direction, The semiconductor device according to claim 1, further comprising:

5. The semiconductor device according to claim 1, wherein the first columnar conductive portion has a first widened portion in the first portion facing the first conductive layer, the width in the first direction being greater than that of the second portion facing the first insulating layer.

6. The semiconductor device according to claim 5, wherein the first widened portion of the first columnar conductive portion is connected to the first conductive layer.

7. The semiconductor device according to claim 4, wherein the thickness of the first conductive layer in the first region is greater than the thickness of the first region.

8. The present invention further includes a third insulating layer disposed between the source and the second conductive layer, The semiconductor device according to claim 2, wherein the second columnar conductive portion has a second widened portion in the third portion facing the second conductive layer, the width in the first direction being greater than that of the fourth portion facing the third insulating layer.

9. The semiconductor device according to claim 8, wherein the second widened portion of the second columnar conductive portion is connected to the second conductive layer.

10. The semiconductor device according to claim 1, wherein the second conductive layer has a thickness in the second region that is greater than the thickness in the first region.

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