Semiconductor equipment

Abstract

The present invention provides a semiconductor device having a stacked structure that allows for easy connection of semiconductor elements. [Solution] The semiconductor device 1 has a first structure 10, a second structure 20 arranged adjacent to the first structure, a third structure 30 stacked on top of the first and second structures, and first and second wiring members 40 and 50 stacked on the bottom of the first and second structures, respectively. The first structure includes a first semiconductor element 120 bonded to the lower surface of a first insulating substrate 100 and a first wiring arranged on the upper surface of the first insulating substrate and electrically connected to the first insulating substrate and the first electrode. The second structure includes a second semiconductor element 220 bonded to the lower surface of a second insulating substrate 200 and a second wiring arranged on the upper surface of the second insulating substrate and electrically connected to the third electrode. The third structure includes a third insulating substrate 300 and the third wiring. The first wiring member becomes part of a path that electrically connects the second electrode and the third wiring, and the second wiring member becomes part of a path that electrically connects the fourth electrode and the first wiring.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Conventionally, as a semiconductor device, a semiconductor element is attached to a resin film via an adhesive layer, and a wiring layer is formed on a surface opposite to the adhesive layer of the resin film (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a semiconductor device having a low-inductance laminated structure with a plurality of semiconductor elements, a structure that can easily connect the semiconductor elements to each other is desired.

[0005] An object of this disclosure is to provide a semiconductor device having a laminated structure that can easily connect semiconductor elements to each other.

Means for Solving the Problems

[0006] A semiconductor device according to one embodiment of the present disclosure comprises a first structure, a second structure disposed adjacent to the first structure, a third structure laminated above the first structure and above the second structure, a first wiring member laminated below the first structure, and a second wiring member laminated below the second structure, wherein the first structure comprises a first insulating substrate, a first electrode, and a second electrode located on the opposite side in the thickness direction from the first electrode, a first semiconductor element bonded to the lower surface of the first insulating substrate via a first adhesive layer with the first electrode facing the first insulating substrate, and a first wiring disposed on the upper surface of the first insulating substrate and electrically connected to the first electrode via a first via wiring that penetrates the first insulating substrate and the first adhesive layer, and the second structure comprises a second insulating substrate The third structure includes a third semiconductor element having a third electrode and a fourth electrode located on the opposite side of the thickness direction from the third electrode, with the third electrode facing the second insulating substrate and bonded to the lower surface of the second insulating substrate via a second adhesive layer, and a second wiring disposed on the upper surface of the second insulating substrate and electrically connected to the third electrode via a second via wiring that penetrates the second insulating substrate and the second adhesive layer, wherein the third structure includes a third insulating substrate whose lower surface is bonded to the upper surface of the first wiring and the upper surface of the second wiring via a third adhesive layer, and a third wiring disposed on the upper surface of the third insulating substrate, wherein the first wiring member becomes part of a path electrically connecting the second electrode and the third wiring, and the second wiring member becomes part of a path electrically connecting the fourth electrode and the first wiring. [Effects of the Invention]

[0007] According to this disclosure, it is possible to provide a semiconductor device having a stacked structure that allows for easy connection of semiconductor elements. [Brief explanation of the drawing]

[0008] [Figure 1] This figure illustrates a semiconductor device according to the first embodiment. [Figure 2] This figure illustrates the basic circuit of a semiconductor device according to the first embodiment. [Figure 3]This figure illustrates the current flow in a semiconductor device according to the first embodiment. [Figure 4] This is a diagram (part 1) illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 5] This is a diagram (part 2) illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 6] This is a diagram (part 3) illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 7] This is a diagram (part 4) illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 8] This is a diagram (part 5) illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 9] This is a diagram (6) illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 10] This is a diagram (7) illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 11] This is a diagram (number 8) illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Modes for carrying out the invention]

[0009] Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configuration will be denoted by the same reference numerals to avoid redundant descriptions.

[0010] (First Embodiment) [Configuration of semiconductor device] Figure 1 is a diagram illustrating a semiconductor device according to the first embodiment, where Figure 1(a) is a plan view and Figure 1(b) is a cross-sectional view along line AA in Figure 1(a). As shown in Figure 1, the semiconductor device 1 according to the first embodiment includes a first structure 10, a second structure 20 arranged adjacent to the first structure 10, a third structure 30 stacked on the upper side of the first structure 10 and the upper side of the second structure 20, a first wiring member 40 stacked on the lower side of the first structure 10, and a second wiring member 50 stacked on the lower side of the second structure 20.

[0011] In the first embodiment, for convenience, the wiring layer 340 side of the semiconductor device 1 is considered the upper side, and the first wiring member 40 and second wiring member 50 side is considered the lower side. Also, the surface of each part facing the wiring layer 340 is considered the upper surface, and the surface facing the first wiring member 40 and second wiring member 50 is considered the lower surface. However, the semiconductor device 1 can be used upside down or positioned at any angle. Furthermore, "planar view" refers to viewing the object from the direction normal to the upper surface 300b of the third insulating substrate 300, and "planar shape" refers to the shape of the object viewed from the direction normal to the upper surface 300b of the third insulating substrate 300.

[0012] The first structure 10 includes a first insulating substrate 100, a first adhesive layer 110, a first semiconductor element 120, conductive members 131 and 132, and a wiring layer 140. In the illustrated example, the first structure 10 has two first semiconductor elements 120 connected in parallel to each other. When the first semiconductor elements 120 are arranged in parallel, they may be arranged in a direction parallel to the longitudinal direction of the semiconductor device 1 or in a direction perpendicular to it. Also, the number of first semiconductor elements 120 may be one or three or more.

[0013] The first insulating substrate 100 has a lower surface 100a and an upper surface 100b located on the opposite side of the lower surface 100a in the thickness direction. As the first insulating substrate 100, for example, a resin film or the like can be used. As the material of the resin film, an insulating resin such as a polyimide-based resin, a polyethylene-based resin, or an epoxy-based resin can be used. The first insulating substrate 100, for example, has flexibility. Here, flexibility refers to the property of being able to be bent or flexed. The first insulating substrate 100 can have an arbitrary shape and an arbitrary size. The planar shape of the first insulating substrate 100 is, for example, rectangular. The thickness of the first insulating substrate 100 can be, for example, about 50 μm to 100 μm.

[0014] The first adhesive layer 110 is laminated on the lower surface 100a of the first insulating substrate 100. The first adhesive layer 110 may be disposed over the entire lower surface 100a of the first insulating substrate 100, or may be disposed only at necessary locations. As the material of the first adhesive layer 110, for example, an adhesive such as an epoxy-based, polyimide-based, or silicone-based adhesive can be used. The thickness of the first adhesive layer 110 can be, for example, about 20 μm to 40 μm.

[0015] The first semiconductor element 120 is, for example, a device using silicon (Si) or silicon carbide (SiC). The first semiconductor element 120 can also be a device using, for example, gallium nitride (GaN) or gallium arsenide (GaAs). For example, the first semiconductor element 120 can be an active semiconductor element (e.g., a silicon chip such as a CPU), an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a diode. The first semiconductor element 120 in this embodiment is a semiconductor element with electrodes on both its front and back surfaces. The first semiconductor element 120 can have any shape and size. The planar shape of the first semiconductor element 120 is, for example, rectangular. The thickness of the first semiconductor element 120 can be, for example, about 50 μm to 500 μm.

[0016] The first semiconductor element 120 has a main body 121, electrodes 122 and 123 located on one side of the main body 121 in the thickness direction, and an electrode 124 located on the opposite side of the thickness direction from electrodes 122 and 123. The first semiconductor element 120 is bonded to the lower surface 100a of the first insulating substrate 100 via a first adhesive layer 110, with electrodes 122 and 123 facing the first insulating substrate 100. Electrodes 122, 123, and 124 can be, for example, a source electrode, a gate electrode, and a drain electrode, respectively.

[0017] As materials for the electrode 122, the electrode 123, and the electrode 124 (hereinafter, these may be collectively referred to as "electrodes"), for example, metals such as aluminum (Al) and copper (Cu), or alloys containing at least one metal selected from these metals can be used. In addition, if necessary, a surface treatment layer may be formed on the surface of the electrode. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer in which the Ni layer and the Au layer are laminated in this order), a Ni layer / palladium (Pd) layer / Au layer (a metal layer in which the Ni layer, the Pd layer, and the Au layer are laminated in this order), and the like. As these Au layer, Ni layer, and Pd layer, for example, a metal layer formed by electroless plating (electroless plating metal layer) can be used. Further, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or a Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy.

[0018] The conductive members 131 and 132 are adhered to the lower surface 100a of the first insulating substrate 100 via the first adhesive layer 110. In the illustrated example, the conductive members 131 and 132 are arranged to face each other with the two first semiconductor elements 120 interposed therebetween in a plan view. The conductive members 131 and 132 can be made of, for example, copper or a copper alloy.

[0019] The conductive members 131 and 132 can have an arbitrary shape and an arbitrary size. The planar shape of the conductive members 131 and 132 is, for example, rectangular. The conductive members 131 and 132 may have the same size or different sizes. The conductive members 131 and 132 have the same thickness. The thickness of the conductive members 131 and 132 is equal to the thicknesses of the first semiconductor element 120 and the second semiconductor element 220, and can be, for example, about 50 μm to 500 μm. In the present application, the thicknesses being equal includes cases where the difference in thickness between the objects is 10 μm or less.

[0020] The wiring layer 140 includes wiring 141, via wiring 142 formed integrally with wiring 141, wiring 143, and via wiring 144 formed integrally with wiring 143. Wirings 141 and 143 are arranged on the upper surface 100b of the first insulating substrate 100. The thickness of wirings 141 and 143 can be, for example, about 50 μm to 150 μm.

[0021] Via wiring 142 is located in a through-hole 105 that penetrates the first insulating substrate 100 and the first adhesive layer 110, exposing the upper surface of the electrode 122 of the first semiconductor element 120. Via wiring 142 is also located in a through-hole 107 that penetrates the first insulating substrate 100 and the first adhesive layer 110, exposing the upper surface of the conductive member 131. Via wiring 144 is located in a through-hole 106 that penetrates the first insulating substrate 100 and the first adhesive layer 110, exposing the electrode 123 of the first semiconductor element 120. In the illustrated example, multiple through-holes 105 to 107 are provided. The number of through-holes 105 to 107 may be one or more.

[0022] Wiring 141 is electrically connected to electrode 122 of the first semiconductor element 120 via via wiring 142. Wiring 141 is also electrically connected to conductive member 131 via via wiring 142. Wiring 143 is electrically connected to electrode 123 of the first semiconductor element 120 via via wiring 144. Note that conductive member 132 does not necessarily have to be electrically connected to wirings 141 and 143. In this case, conductive member 132 functions as a spacer or support member.

[0023] The wiring layer 140 can have a structure in which a metal layer is laminated on a seed layer, for example. In this case, a metal film (sputtered film) formed by sputtering can be used as the seed layer. As a seed layer formed by sputtering, for example, a two-layer metal film in which a titanium layer and a copper layer are laminated in order can be used. In this case, the thickness of the Ti layer can be, for example, about 10 nm to 300 nm, and the thickness of the Cu layer can be, for example, about 100 nm to 1000 nm. The Ti layer functions as an adhesion layer that improves the adhesion between the first insulating substrate 100 and electrodes, etc., and the seed layer. The Ti layer also functions as a metal barrier layer that suppresses the diffusion of copper from the Cu layer, etc., to the first insulating substrate 100, etc. In addition to Ti, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), chromium (Cr), etc. can be used as materials for the metal film that functions as such an adhesion layer and metal barrier layer. As materials for the metal layer, for example, copper or copper alloys can be used. As the metal layer, for example, a metal layer formed by electroplating (electroplated metal layer) can be used.

[0024] The second structure 20 includes a second insulating substrate 200, a second adhesive layer 210, a second semiconductor element 220, a conductive member 231, and a wiring layer 240. The overall thickness of the second structure 20 can be, for example, equal to the overall thickness of the first structure 10.

[0025] In the illustrated example, the second structure 20 has two second semiconductor elements 220 connected in parallel to each other. When the second semiconductor elements 220 are arranged in parallel, they may be arranged in a direction parallel to the longitudinal direction of the semiconductor device 1 or in a direction perpendicular to it. Also, the number of second semiconductor elements 220 may be one or three or more.

[0026] The second insulating substrate 200 has a lower surface 200a and an upper surface 200b located on the opposite side of the thickness direction from the lower surface 200a. The material and thickness of the second insulating substrate 200 can be the same as, for example, the first insulating substrate 100.

[0027] The second adhesive layer 210 is laminated on the lower surface 200a of the second insulating substrate 200. The second adhesive layer 210 may be placed over the entire lower surface 200a of the second insulating substrate 200, or only where necessary. The material and thickness of the second adhesive layer 210 can be the same as, for example, the first adhesive layer 110.

[0028] The second semiconductor element 220 is a device similar to the first semiconductor element 120. The second semiconductor element 220 can be connected in series with the first semiconductor element 120, for example. The material and thickness of the second semiconductor element 220 can be the same as those of the first semiconductor element 120. The second semiconductor element 220 can have any shape and size. The planar shape of the second semiconductor element 220 is, for example, rectangular. The planar shape of the second semiconductor element 220 can be, for example, the same as that of the first semiconductor element 120.

[0029] The second semiconductor element 220 has a main body 221, electrodes 222 and 223 located on one side of the main body 221 in the thickness direction, and an electrode 224 located on the opposite side of the thickness direction from electrodes 222 and 223. The second semiconductor element 220 is bonded to the lower surface 200a of the second insulating substrate 200 via a second adhesive layer 210, with electrodes 222 and 223 facing the second insulating substrate 200. Electrodes 222, 223, and 224 can be, for example, a source electrode, a gate electrode, and a drain electrode, respectively. The materials and surface treatments of electrodes 222, 223, and 224 can be, for example, the same as those of electrodes 122, 123, and 124.

[0030] The conductive member 231 can be made of, for example, copper or a copper alloy. The conductive member 231 can have any shape and size. The planar shape of the conductive member 231 is, for example, rectangular. The thickness of the conductive member 231 is equal to the thickness of the second semiconductor element 220, and can be, for example, about 50 μm to 500 μm. The conductive member 231 does not have to be electrically connected to the wiring 241 and 243. In this case, the conductive member 231 functions as a spacer or support member.

[0031] The wiring layer 240 includes wiring 241, via wiring 242 formed integrally with wiring 241, wiring 243, and via wiring 244 formed integrally with wiring 243. Wirings 241 and 243 are arranged on the upper surface 200b of the second insulating substrate 200. The thickness of wirings 241 and 243 is equal to the thickness of wirings 141 and 143, and can be, for example, about 50 μm to 150 μm.

[0032] Via wiring 242 is located in a through-hole 205 that penetrates the second insulating substrate 200 and the second adhesive layer 210, exposing the electrode 222 of the second semiconductor element 220. Via wiring 244 is located in a through-hole 206 that penetrates the second insulating substrate 200 and the second adhesive layer 210, exposing the electrode 223 of the second semiconductor element 220. In the illustrated example, multiple through-holes 205 and 206 are provided. The number of through-holes 205 and 206 may be any number of one or more.

[0033] Wiring 241 is electrically connected to electrode 222 of the second semiconductor element 220 via via wiring 242. Wiring 243 is electrically connected to electrode 223 of the second semiconductor element 220 via via wiring 244. The wiring layer 240 can have a structure in which a metal layer is laminated on a seed layer, for example, similar to the wiring layer 140.

[0034] The third structure 30 includes a third insulating substrate 300, a third adhesive layer 310, a conductive member 331, and a wiring layer 340.

[0035] The third insulating substrate 300 has a lower surface 300a and an upper surface 300b located on the opposite side of the thickness direction from the lower surface 300a. The material and thickness of the third insulating substrate 300 can be the same as, for example, the first insulating substrate 100.

[0036] The third adhesive layer 310 is laminated on the lower surface 300a of the third insulating substrate 300. The lower surface of the third insulating substrate 300 is bonded to the upper surfaces of the wirings 141 and 143, and the upper surfaces of the wirings 241 and 243, via the third adhesive layer 310. The third adhesive layer 310 may be placed over the entire lower surface 300a of the third insulating substrate 300, or only where necessary. The material and thickness of the third adhesive layer 310 can be the same as, for example, the first adhesive layer 110.

[0037] The conductive member 331 can be made of, for example, copper or a copper alloy. The conductive member 331 can have any shape and size. The planar shape of the conductive member 331 is, for example, rectangular. The thickness of the conductive member 331 can be, for example, equal to the total thickness of the first structure 10 and the total thickness of the second structure 20.

[0038] The wiring layer 340 includes wiring 341, via wiring 342 formed integrally with wiring 341, wiring 343, via wiring 344 formed integrally with wiring 343, wiring 345, and via wiring 346 formed integrally with wiring 345. Wirings 341, 343, and 345 are arranged on the upper surface 300b of the third insulating substrate 300. The thickness of wirings 341, 343, and 345 is equal to the thickness of wirings 141 and 143, and can be, for example, about 50 μm to 150 μm.

[0039] Via wiring 342 is located in a through-hole 305 that penetrates the third insulating substrate 300 and the third adhesive layer 310, exposing the upper surface of the conductive member 331. Via wiring 344 is located in a through-hole 306 that penetrates the third insulating substrate 300 and the third adhesive layer 310, exposing the upper surface of the wiring 143. Via wiring 346 is located in a through-hole 307 that penetrates the third insulating substrate 300 and the third adhesive layer 310, exposing the upper surface of the wiring 243. In the illustrated example, multiple through-holes 305 to 307 are provided. The number of through-holes 305 to 307 may be one or more.

[0040] Wiring 341 is electrically connected to the conductive member 331 via via wiring 342. Wiring 343 is electrically connected to wiring 143 via via wiring 344. Wiring 345 is electrically connected to wiring 243 via via wiring 346. Wiring layer 340 can have a structure in which a metal layer is laminated on a seed layer, for example, similar to wiring layer 140.

[0041] The first wiring member 40 is electrically connected to each electrode 124 of the first semiconductor element 120 and the conductive member 331 via a conductive adhesive layer 45. The first wiring member 40 is part of the path that electrically connects the electrodes 124 and the wiring 341. In the illustrated example, the first wiring member 40 has a region facing the third structure 30, and the conductive member 331 is positioned in this region. The lower surface of the conductive member 331 is electrically connected to the first wiring member 40 via the conductive adhesive layer 45, and the upper surface of the conductive member 331 is electrically connected to the wiring 341 via a via wiring 342 that penetrates the third insulating substrate 300 and the third adhesive layer 310.

[0042] In the illustrated example, the first structure 10 has a through-hole 109 that penetrates the first insulating substrate 100 and the first adhesive layer 110, and the through-hole 109 is located in a position that overlaps with the region where the first wiring member 40 and the third structure 30 face each other in a plan view. The conductive member 331 is located inside the through-hole 109 in a plan view. The conductive member 331 can be placed, for example, between the opposing first semiconductor element 120 and the second semiconductor element 220. The conductive member 331 and the first insulating substrate 100 and the first adhesive layer 110 may or may not be in contact.

[0043] In this way, by using a conductive member 331 with the same thickness as the first structure 10 and the second structure 20, the first wiring member 40 and the wiring 341 can be connected more easily compared to the case where a stacked via structure is adopted. In other words, since a stacked via structure, which is formed by filling the inside of a large-diameter via hole that can carry a large current with copper or the like, is difficult to manufacture, it is advantageous to use a conductive member 331 that does not involve such difficulties.

[0044] The second wiring member 50 is electrically connected to each electrode 224, conductive member 131, and conductive member 231 of the second semiconductor element 220 via a conductive adhesive layer 45. The second wiring member 50 is part of the path that electrically connects the electrode 224 and the wiring 141. In the illustrated example, the second wiring member 50 has a region facing the first structure 10, and the conductive member 131 is arranged in this region. The lower surface of the conductive member 131 is electrically connected to the second wiring member 50 via the conductive adhesive layer 45, and the upper surface of the conductive member 131 is electrically connected to the wiring 141 via a via wiring 142 that penetrates the first insulating substrate 100 and the first adhesive layer 110. The conductive member 131 can be arranged, for example, between the opposing first semiconductor element 120 and the second semiconductor element 220. The first wiring member 40 and the second wiring member 50 can be made of, for example, copper or a copper alloy. The first wiring member 40 and the second wiring member 50 may be components that make up a wiring board, such as a ceramic substrate.

[0045] The conductive member 60 is electrically connected to the conductive member 132 via a conductive adhesive layer 45. The conductive member 60 can be made of, for example, copper or a copper alloy. The conductive adhesive layer 45 is, for example, a solder layer or a sintered metal layer. The conductive adhesive layer 45 may also be made of a conductive paste such as silver paste.

[0046] The sealing resin 70 is formed to expose the entire upper surfaces of the wirings 341, 343, and 345, parts of the upper surfaces of the wirings 141 and 241, the entire lower surfaces of the first wiring member 40, the second wiring member 50, and the conductive member 60, while covering the other parts. As the sealing resin 70, for example, an insulating resin such as a thermosetting epoxy resin containing a filler can be used. Note that in Figure 1(a), the sealing resin 70 is shown as a dot pattern for convenience.

[0047] Thus, the semiconductor device 1 comprises a first structure 10 including a first semiconductor element 120, a second structure 20 including a second semiconductor element 220, and a third structure 30. The second structure 20 is placed alongside the first structure 10, and the third structure 30 is stacked on top of the first structure 10 and the second structure 20. A first wiring member 40 is stacked on the bottom of the first structure 10, and a second wiring member 50 is stacked on the bottom of the second structure 20. The first wiring member 40 forms part of the path that electrically connects the electrode 124 of the first semiconductor element 120 and the wiring 341, and the second wiring member 50 forms part of the path that electrically connects the electrode 224 and the wiring 241.

[0048] In semiconductor device 1, the first structure 10, the second structure 20, and the third structure 30 have the same basic structure. That is, in each structure, an adhesive layer is provided on the lower surface of an insulating substrate, semiconductor elements and conductive members are provided on the lower surface of the insulating substrate via the adhesive layer, and a wiring layer is provided on the upper surface of the insulating substrate that penetrates the insulating substrate and the adhesive layer and is electrically connected to the semiconductor elements and conductive members. By arranging and stacking structures with the same basic structure, semiconductor device 1 with a stacked structure that allows for easy connection of semiconductor elements can be realized. Furthermore, such a structure enables miniaturization of semiconductor device 1.

[0049] While it is possible to combine the first structure 10 and the second structure 20 into a single structure, separating them into two structures increases design flexibility. Furthermore, separating them into two structures allows for the selection of good products at the structure level during manufacturing, thus improving yield. It is also easy to arrange the structures in a multi-phase configuration of three or more (for example, a three-phase inverter).

[0050] Here, an example of the circuit configuration of the semiconductor device 1 according to the first embodiment will be described. Figure 2 is a diagram illustrating the basic circuit of the semiconductor device according to the first embodiment. In Figure 2, one first semiconductor element 120 and one second semiconductor element 220 are shown, whereas in Figure 1, two first semiconductor elements 120 are connected in parallel and two second semiconductor elements 220 are connected in parallel. In Figure 2, protective diodes may be connected in parallel with each of the first semiconductor element 120 and the second semiconductor element 220.

[0051] As shown in Figure 2, the first semiconductor element 120 and the second semiconductor element 220 can be connected in series. Specifically, electrode 124 of the first semiconductor element 120 is electrically connected to the P terminal, and electrode 123 is electrically connected to the G1 terminal. Also, electrode 222 of the second semiconductor element 220 is electrically connected to the N terminal, and electrode 223 is electrically connected to the G2 terminal. Furthermore, electrode 122 of the first semiconductor element 120 and electrode 224 of the second semiconductor element 220 are electrically connected to the O terminal. The P terminal is the positive input terminal, the N terminal is the negative input terminal, and the O terminal is the output terminal. The G1 and G2 terminals are control terminals. In the circuit shown in Figure 2, high-speed switching operation is possible using the first semiconductor element 120 and the second semiconductor element 220.

[0052] Figure 3 illustrates the current flow in the semiconductor device according to the first embodiment. In Figure 3, terminals P, N, O, G1, and G2 correspond to the circuit diagram in Figure 2. In Figure 3, solid arrows schematically show the current path from terminal P to terminal O. Dashed arrows schematically show the current path from terminal O to terminal N.

[0053] As shown in Figure 3, in semiconductor device 1, current flows from the P terminal to the N terminal, but current flows in opposite directions through the first wiring member 40 and wiring 141, and current flows in opposite directions through the second wiring member 50 and wiring 241 and wiring 341. In other words, the P-side current path, which flows from the P terminal to the O terminal, and the N-side current path, which flows from the O terminal to the N terminal, are generally arranged opposite each other vertically, and current flows in opposite directions through them, thus reducing inductance. In semiconductor device 1, the gap in the thickness direction between the P-side current path and the N-side current path is narrow, about several hundred μm, so the effect of reducing inductance is significant.

[0054] [Manufacturing method for semiconductor devices] Next, a method for manufacturing a semiconductor device according to the first embodiment will be described. Figures 4 to 11 illustrate the manufacturing process of a semiconductor device according to the first embodiment. In the following description, an example of manufacturing one semiconductor device is shown, but it is also possible to manufacture a so-called multi-cavity manufacturing method in which the parts that will become the semiconductor device 1 are manufactured all at once, and then separated into individual pieces to manufacture a large number of semiconductor devices 1. For the sake of explanation, the parts that will ultimately become each component of the semiconductor device 1 will be denoted by the reference numeral of the final component.

[0055] First, as shown in Figure 4(a), a first insulating substrate 100 having a lower surface 100a and an upper surface 100b, and a first adhesive layer 110 are prepared. The lower surface 100a of the first insulating substrate 100 is provided with an insulating first adhesive layer 110 that covers the entire lower surface 100a.

[0056] Next, as shown in Figure 4(b), through holes 105-107 and 109 are formed at required locations in the first insulating substrate 100 and the first adhesive layer 110, penetrating the first insulating substrate 100 and the first adhesive layer 110 in the thickness direction. The through holes 105-107 and 109 can be formed, for example, by laser processing using a CO2 laser or UV-YAG laser, or by punching. Through hole 105 is formed at a position where the electrode 122 of the first semiconductor element 120 will be exposed in a later process, through hole 106 is formed at a position where the electrode 123 of the first semiconductor element 120 will be exposed in a later process, and through hole 107 is formed at a position where the upper surface of the conductive member 131 will be exposed in a later process. Through hole 109 is formed at a position where the conductive member 331 can be placed in a later process. The number of through holes 105-107 can be any number of one or more.

[0057] Next, as shown in Figures 5(a) and 5(b), the first semiconductor element 120 and the conductive member 131 are bonded to the first insulating substrate 100 by the first adhesive layer 110. At this time, the electrodes 122 and 123 of the first semiconductor element 120 are positioned facing the lower surface 100a of the first insulating substrate 100, and in a plan view, the electrode 122 overlaps the through hole 105 and the electrode 123 overlaps the through hole 106. Also, in a plan view, the upper surface of the conductive member 131 is positioned to overlap the through hole 107. Note that Figure 5(a) is a plan view, and Figure 5(b) is a cross-sectional view along the line BB in Figure 5(a).

[0058] Next, as shown in Figures 6(a) and 6(b), a wiring layer 140 is formed. The wiring layer 140 includes a wire 141, a via wire 142 formed integrally with the wire 141, a wire 143, and a via wire 144 formed integrally with the wire 143. Wires 141 and 143 are arranged on the upper surface 100b of the first insulating substrate 100. The via wire 142 is arranged in a through-hole 105 that penetrates the first insulating substrate 100 and the first adhesive layer 110 and exposes the electrode 122 of the first semiconductor element 120, and in a through-hole 107 that penetrates the first insulating substrate 100 and the first adhesive layer 110 and exposes the upper surface of the conductive member 131. The via wire 144 is arranged in a through-hole 106 that penetrates the first insulating substrate 100 and the first adhesive layer 110 and exposes the electrode 123 of the first semiconductor element 120.

[0059] The wiring layer 140 can be formed, for example, by a semi-additive method. Specifically, a seed layer is formed to cover the entire upper surface 100b of the first insulating substrate 100 and the entire inner surface of the through holes 105 to 107. The seed layer can be formed, for example, by sputtering or electroless plating. For example, when forming the seed layer by sputtering, first, a Ti layer is formed by depositing titanium by sputtering to cover the upper surface 100b of the first insulating substrate 100 and the inner surface of the through holes 105 to 107. Then, a Cu layer is formed by depositing copper on the Ti layer by sputtering. This allows for the formation of a two-layer seed layer (Ti layer / Cu layer). Alternatively, when forming the seed layer by electroless plating, for example, a seed layer consisting of a Cu layer (single-layer structure) can be formed by electroless copper plating.

[0060] Next, a plating resist layer is formed on the seed layer, with openings provided in the areas where the wiring layer 140 will be formed, i.e., the areas where wirings 141 and 143 will be formed. Subsequently, a metal layer made of copper or the like is formed in the openings of the plating resist layer by an electroplating method that uses the seed layer as a plating power supply path. After that, the plating resist layer is removed. Next, the seed layer is removed by wet etching using the metal layer as a mask. In this way, the wiring layer 140 including the seed layer and the metal layer can be formed. A flexible wiring board, for example, is constructed from the first insulating substrate 100, the first adhesive layer 110, and the wiring layer 140. Figure 6(a) is a plan view, and Figure 6(b) is a cross-sectional view along the CC line in Figure 6(a). The first structure 10 is completed in the steps shown in Figures 4 to 6.

[0061] Next, the second structure 20 is manufactured in the same manner as the first structure 10. First, as shown in Figures 7(a) and 7(b), a second insulating substrate 200 and a second adhesive layer 210 having a lower surface 200a and an upper surface 200b are prepared in the same manner as in Figure 4(a). The lower surface 200a of the second insulating substrate 200 is provided with an insulating second adhesive layer 210 that covers the entire lower surface 200a. Next, in the same manner as in Figure 4(b), through holes 205 and 206 are formed at required locations on the second insulating substrate 200 and the second adhesive layer 210, penetrating the second insulating substrate 200 and the second adhesive layer 210 in the thickness direction. The through hole 205 is formed at a position where the electrode 222 of the second semiconductor element 220 is exposed, and the through hole 206 is formed at a position where the electrode 223 of the second semiconductor element 220 is exposed. The number of through holes 205 and 206 can be any number of one or more.

[0062] Next, the second semiconductor element 220 and the conductive member 231 are bonded to the second insulating substrate 200 by the second adhesive layer 210, in the same manner as in Figures 5(a) and 5(b). At this time, the electrodes 222 and 223 of the second semiconductor element 220 are positioned facing the lower surface 200a of the second insulating substrate 200, and the electrodes are aligned so that, in a plan view, electrode 222 overlaps the through hole 205 and electrode 223 overlaps the through hole 206. Note that Figure 7(a) is a plan view, and Figure 7(b) is a cross-sectional view along the DD line in Figure 7(a).

[0063] Next, as shown in Figures 8(a) and 8(b), the wiring layer 240 is formed in the same manner as in Figures 6(a) and 6(b). The wiring layer 240 includes wiring 241, via wiring 242 formed integrally with wiring 241, wiring 243, and via wiring 244 formed integrally with wiring 243. Wirings 241 and 243 are arranged on the upper surface 200b of the second insulating substrate 200. Via wiring 242 is arranged in a through-hole 205 that penetrates the second insulating substrate 200 and the second adhesive layer 210 and exposes the electrode 222 of the second semiconductor element 220. Via wiring 244 is arranged in a through-hole 206 that penetrates the second insulating substrate 200 and the second adhesive layer 210 and exposes the electrode 223 of the second semiconductor element 220. The wiring layer 240 can be formed, for example, by a semi-additive method. Figure 8(a) is a plan view, and Figure 8(b) is a cross-sectional view along the EE line in Figure 8(a). The second structure 20 is completed in the process shown in Figures 7 and 8.

[0064] Next, the third structure 30 is manufactured in the same manner as the first structure 10. First, as shown in Figures 9(a) and 9(b), a third insulating substrate 300 and a third adhesive layer 310 having a lower surface 300a and an upper surface 300b are prepared in the same manner as in Figure 4(a). The lower surface 300a of the third insulating substrate 300 is provided with an insulating third adhesive layer 310 that covers the entire lower surface 300a. Next, in the same manner as in Figure 4(b), through holes 305 to 307 are formed at required locations in the third insulating substrate 300 and the third adhesive layer 310, penetrating the third insulating substrate 300 and the third adhesive layer 310 in the thickness direction. Through hole 305 is formed at a position where the upper surface of the conductive member 331 is exposed. Through hole 306 is formed at a position where the upper surface of the wiring 143 will be exposed in a later process. Through hole 307 is formed at a position where the upper surface of the wiring 243 will be exposed in a later process. The number of through holes 305 to 307 can be any number of one or more.

[0065] Next, the conductive member 331 is bonded to the third insulating substrate 300 by the third adhesive layer 310, in the same manner as in Figures 5(a) and 5(b). At this time, the conductive member 331 is positioned so that its upper surface overlaps the through hole 305 in a plan view. Figure 9(a) is a plan view, and Figure 9(b) is a cross-sectional view along the FF line in Figure 9(a).

[0066] Next, as shown in Figure 10(a), the second structure 20 is placed adjacent to the first structure 10. For example, the first structure 10 and the second structure 20 are arranged such that, in a plan view, the two first semiconductor elements 120 and the two second semiconductor elements 220 are aligned in a straight line along their longitudinal direction. Then, the structures fabricated in Figure 9 are laminated on the upper side of the first structure 10 and the upper side of the second structure 20 such that the third adhesive layer 310 faces the first structure 10 and the second structure 20, and the conductive member 331 is inserted into the through hole 109. The third insulating substrate 300 is bonded to the wiring layers 140 and 240 via the third adhesive layer 310. The upper surfaces of the wirings 141 and 143 and the upper surfaces of the wirings 241 and 243 are, for example, flush.

[0067] Next, as shown in Figure 10(b), the wiring layer 340 is formed in the same manner as in Figures 6(a) and 6(b). The wiring layer 340 includes a wire 341, a via wire 342 formed integrally with the wire 341, a wire 343, a via wire 344 formed integrally with the wire 343, a wire 345, and a via wire 346 formed integrally with the wire 345. Wires 341, 343, and 345 are arranged on the upper surface 300b of the third insulating substrate 300. The via wire 342 is arranged in a through hole 305 that penetrates the third insulating substrate 300 and the third adhesive layer 310 and exposes the upper surface of the conductive member 331. The via wire 344 is arranged in a through hole 306 that penetrates the third insulating substrate 300 and the third adhesive layer 310 and exposes the upper surface of the wire 143. The via wiring 346 penetrates the third insulating substrate 300 and the third adhesive layer 310 and is positioned in a through-hole 307 that exposes the upper surface of the wiring 243. The wiring layer 340 can be formed, for example, by a semi-additive method. Through the above steps, a structure is completed in which the third structure 30 is laminated on top of the first structure 10 and the second structure 20.

[0068] Next, in the process shown in Figure 11(a), the first wiring member 40 is bonded to the conductive member 331 and the electrodes 124 of each of the first semiconductor elements 120 by the conductive adhesive layer 45. The second wiring member 50 is also bonded to the conductive members 131 and 231 and the electrodes 224 of each of the second semiconductor elements 220 by the conductive adhesive layer 45. The conductive member 60 is also bonded to the conductive member 132 by the conductive adhesive layer 45.

[0069] Next, in the process shown in Figure 11(b), the sealing resin 70 is formed. The sealing resin 70 is formed so as to expose the entire upper surfaces of the wirings 341, 343, and 345, parts of the upper surfaces of the wirings 141 and 241, the entire lower surfaces of the first wiring member 40, the second wiring member 50, and the conductive member 60, and cover the other parts. As the sealing resin 70, for example, an insulating resin such as a thermosetting epoxy resin containing a filler can be used. The sealing resin 70 can be formed, for example, by a transfer molding method using a sealing mold. The shape of the sealing resin 70 as shown in Figure 11(b) can be achieved by adjusting the shape of the sealing mold.

[0070] As described above, semiconductor device 1 can be manufactured. In the manufacturing process of semiconductor device 1, the basic structure of the first structure 10, the second structure 20, and the third structure 30 are identical, and all structures are arranged so that the vertical positional relationship between the insulating substrate and the adhesive layer is the same. In other words, the process does not involve inverting any of the structures and connecting them, or bending any of the structures. Therefore, a simple manufacturing process can be achieved without complicated steps.

[0071] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. [Explanation of symbols]

[0072] 1 Semiconductor device 10 First structure 20 Second structure 30 Third structure 40 First wiring component 45 Conductive adhesive layer 50 Second wiring component 60 Conductive material 70 Sealing resin 100 First insulating substrate 100a,200a,300a Bottom surface 100b,200b,300b Top surface 105, 106, 107, 109, 205, 206, 305, 306, 307 Through holes 110 1st adhesive layer 120 First Semiconductor Device 121,221 Main body 122,123,124,222,223,224 electrode 131,132,231,331 Conductive members 140,240,340 wiring layer 141,143,241,243,341,343,345 Wiring 142,144,242,244,342,344,346 via wiring 200 Second insulating substrate 210 Second adhesive layer 220 Second semiconductor element 300 Third insulating substrate 310 Third adhesive layer

Claims

1. It comprises a first structure, a second structure arranged adjacent to the first structure, a third structure stacked above the first structure and above the second structure, a first wiring member stacked below the first structure, and a second wiring member stacked below the second structure. The first structure is, First insulating substrate and A first semiconductor element having a first electrode and a second electrode located on the opposite side of the thickness direction from the first electrode, wherein the first electrode is facing the first insulating substrate and is bonded to the lower surface of the first insulating substrate via a first adhesive layer, The first wiring is disposed on the upper surface of the first insulating substrate and is electrically connected to the first electrode via a first via wiring that penetrates the first insulating substrate and the first adhesive layer, The second structure described above is The second insulating substrate and A second semiconductor element having a third electrode and a fourth electrode located on the opposite side of the thickness direction from the third electrode, with the third electrode facing the second insulating substrate and bonded to the lower surface of the second insulating substrate via a second adhesive layer, The present invention includes a second wiring positioned on the upper surface of the second insulating substrate and electrically connected to the third electrode via a second via wiring that penetrates the second insulating substrate and the second adhesive layer, The aforementioned third structure is A third insulating substrate whose lower surface is bonded to the upper surface of the first wiring and the upper surface of the second wiring via a third adhesive layer, The third wiring is disposed on the upper surface of the third insulating substrate, The first wiring member becomes part of the path that electrically connects the second electrode and the third wiring. The second wiring member is part of a path that electrically connects the fourth electrode and the first wiring, and is a semiconductor device.

2. The first wiring member has a first region facing the third structure, A first conductive member is placed in the first region, The semiconductor device according to claim 1, wherein the lower surface of the first conductive member is electrically connected to the first wiring member via a conductive adhesive layer, and the upper surface of the first conductive member is electrically connected to the third wiring via a third via wiring that penetrates the third insulating substrate and the third adhesive layer.

3. The first structure has through holes penetrating the first insulating substrate and the first adhesive layer, The through hole is located in a position that overlaps with the first region in a plan view. The semiconductor device according to claim 2, wherein the first conductive member is located within the through hole in a plan view.

4. The semiconductor device according to claim 2, wherein the thickness of the first conductive member is equal to the overall thickness of the first structure and the overall thickness of the second structure.

5. The semiconductor device according to claim 2, wherein the first conductive member is disposed between the opposing first semiconductor element and the second semiconductor element.

6. The second wiring member has a second region facing the first structure, A second conductive member is placed in the second region. The semiconductor device according to any one of claims 1 to 5, wherein the lower surface of the second conductive member is electrically connected to the second wiring member via a conductive adhesive layer, and the upper surface of the second conductive member is electrically connected to the first wiring via a fourth via wiring that penetrates the first insulating substrate and the first adhesive layer.

7. The semiconductor device according to claim 6, wherein the thickness of the second conductive member is equal to the thickness of the second semiconductor element.

8. The semiconductor device according to claim 6, wherein the second conductive member is disposed between the opposing first semiconductor element and the second semiconductor element.

9. The semiconductor device according to any one of claims 1 to 5, wherein current flows in opposite directions through the first wiring member and the first wiring.

10. The semiconductor device according to any one of claims 1 to 5, wherein current flows in opposite directions through the second wiring member and the second and third wiring.

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