Semiconductor equipment

Abstract

To make semiconductor devices thinner. [Solution] The semiconductor device comprises an insulating substrate, a semiconductor element having a first electrode and a second electrode, with the first electrode and the second electrode facing the insulating substrate and bonded to the lower surface of the insulating substrate via an adhesive layer, a first wiring disposed on the upper surface of the insulating substrate and electrically connected to the first electrode via a first via wiring that penetrates the insulating substrate and the adhesive layer, a second wiring disposed on the upper surface of the insulating substrate and electrically connected to the second electrode via a second via wiring that penetrates the insulating substrate and the adhesive layer, an insulating layer disposed on the upper surface of the insulating substrate between the first wiring and the second wiring, a first wiring member disposed above the first wiring and the second wiring, a second wiring member disposed below the semiconductor element, and a sealing resin covering the semiconductor element, the first wiring, and the second wiring, wherein a portion of the first wiring and a portion of the second wiring protrude from the sealing resin in a plan view.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Conventionally, as a semiconductor device, a structure in which heat sinks are arranged on the upper surface side and the lower surface side of a semiconductor element and sealed with a sealing resin is known. In this semiconductor device, a part of the electrode of the semiconductor element is connected to a terminal via a bonding wire in the sealing resin, and a part of the terminal protrudes from the sealing resin. (For example, refer to Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the above semiconductor device, since a spacer for securing a layout space for bonding wires is arranged between the semiconductor element and the upper heat sink, it is difficult to make the device thinner.

[0005] The present disclosure aims to make a semiconductor device thinner.

Means for Solving the Problems

[0006] A semiconductor device according to one embodiment of the present disclosure comprises an insulating substrate, a semiconductor element having a first electrode and a second electrode, with the first electrode and the second electrode facing the insulating substrate and bonded to the lower surface of the insulating substrate via an adhesive layer, a first wiring disposed on the upper surface of the insulating substrate and electrically connected to the first electrode via a first via wiring that penetrates the insulating substrate and the adhesive layer, a second wiring disposed on the upper surface of the insulating substrate and electrically connected to the second electrode via a second via wiring that penetrates the insulating substrate and the adhesive layer, an insulating layer disposed on the upper surface of the insulating substrate between the first wiring and the second wiring, a first wiring member disposed above the first wiring and the second wiring, a second wiring member disposed below the semiconductor element, and a sealing resin covering the semiconductor element, the first wiring, and the second wiring, wherein a portion of the first wiring and a portion of the second wiring protrude from the sealing resin in a plan view. [Effects of the Invention]

[0007] According to this disclosure, semiconductor devices can be made thinner. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view illustrating a semiconductor device according to the first embodiment. [Figure 2] This is a cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 3] This is a diagram (part 1) illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 4] This is a diagram (part 2) illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 5] This is a diagram (part 3) illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 6] This is a diagram (part 4) illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 7] This is a diagram (part 5) illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Modes for carrying out the invention]

[0009] Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configuration will be denoted by the same reference numerals to avoid redundant descriptions.

[0010] (First Embodiment) [Configuration of semiconductor device] Figure 1 is a plan view illustrating a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view illustrating a semiconductor device according to the first embodiment, where Figure 2(a) shows a cross-section along line AA in Figure 1, and Figure 2(b) shows a cross-section along line BB in Figure 1.

[0011] As shown in Figures 1 and 2, the semiconductor device 1 according to the first embodiment includes an insulating substrate 100, an adhesive layer 110, a semiconductor element 120, a conductive member 130, a wiring layer 140, an insulating layer 150, a first wiring member 171, a second wiring member 172, and a sealing resin 180. The semiconductor device 1 may have a plurality of semiconductor elements 120. In Figure 1, for convenience, the insulating layer 150 exposed from the sealing resin 180 is shown as a dot pattern. In other figures, the insulating layer 150 may also be shown as a dot pattern.

[0012] In the first embodiment, for convenience, the side with the first wiring member 171 of the semiconductor device 1 is considered the upper side, and the side with the second wiring member 172 is considered the lower side. Also, the surface on the side with the first wiring member 171 of each part is considered the upper surface, and the surface on the side with the second wiring member 172 is considered the lower surface. However, the semiconductor device 1 can be used upside down or positioned at any angle. Furthermore, a plan view refers to viewing the object from the direction normal to the upper surface 100b of the insulating substrate 100, and a planar shape refers to the shape of the object when viewed from the direction normal to the upper surface 100b of the insulating substrate 100.

[0013] The insulating substrate 100 has a lower surface 100a and an upper surface 100b located on the opposite side of the thickness direction from the lower surface 100a. For example, a resin film can be used as the insulating substrate 100. As the material of the resin film, insulating resins such as polyimide resin, polyethylene resin, and epoxy resin can be used. The insulating substrate 100 has, for example, flexibility. Here, flexibility refers to the property of being able to be bent or flexed. The insulating substrate 100 can be any shape and any size. The planar shape of the insulating substrate 100 is, for example, rectangular. The thickness of the insulating substrate 100 can be, for example, about 50 μm to 100 μm.

[0014] The adhesive layer 110 is laminated on the lower surface 100a of the insulating substrate 100. The adhesive layer 110 may be placed over the entire lower surface 100a of the insulating substrate 100, or only where necessary. As the material for the adhesive layer 110, for example, epoxy-based, polyimide-based, or silicone-based adhesives can be used. The thickness of the adhesive layer 110 can be, for example, about 20 μm to 40 μm.

[0015] The semiconductor element 120 is, for example, a device made of silicon (Si) or silicon carbide (SiC). As the semiconductor element 120, devices made of, for example, gallium nitride (GaN) or gallium arsenide (GaAs) can also be used. For example, as the semiconductor element 120, active elements such as semiconductor elements (e.g., silicon chips for CPUs), insulated gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes can be used. The semiconductor element 120 in this embodiment is a semiconductor element with electrodes provided on both its front and back surfaces. The semiconductor element 120 can have any shape and size. The planar shape of the semiconductor element 120 is, for example, rectangular. The thickness of the semiconductor element 120 can be, for example, about 50 μm to 500 μm.

[0016] The semiconductor element 120 has a main body portion 121, a first electrode 122 and a second electrode 123 located on one side in the thickness direction of the main body portion 121, and a third electrode 124 located on the opposite side in the thickness direction to the first electrode 122 and the second electrode 123. The semiconductor element 120 is adhered to the lower surface 100a of the insulating substrate 100 via the adhesive layer 110 with the first electrode 122 and the second electrode 123 facing the insulating substrate 100 side. The first electrode 122, the second electrode 123, and the third electrode 124 can be, for example, a source electrode, a gate electrode, and a drain electrode, respectively.

[0017] As the materials of the first electrode 122, the second electrode 123, and the third electrode 124, for example, metals such as aluminum (Al) and copper (Cu), or alloys containing at least one metal selected from these metals can be used. Note that, if necessary, a surface treatment layer may be formed on the surface of the electrode. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer in which the Ni layer and the Au layer are laminated in this order), a Ni layer / palladium (Pd) layer / Au layer (a metal layer in which the Ni layer, the Pd layer, and the Au layer are laminated in this order), and the like. As these Au layer, Ni layer, and Pd layer, for example, metal layers formed by an electroless plating method (electroless plated metal layers) can be used. Also, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or a Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. In the following, the first electrode 122, the second electrode 123, and the third electrode 124 may be collectively referred to as "electrodes".

[0018] The conductive member 130 is adhered to the lower surface 100a of the insulating substrate 100 via the adhesive layer 110. The conductive member 130 can be composed of, for example, copper or a copper alloy. The conductive member 130 can have an arbitrary shape and an arbitrary size. The planar shape of the conductive member 130 is, for example, rectangular. The thickness of the conductive member 130 is equal to the thickness of the semiconductor element 120 and can be, for example, about 50 μm to 500 μm. In the present application, "equal thickness" includes cases where the difference in thickness between the objects is 10 μm or less.

[0019] The wiring layer 140 includes first wirings 141a and 141b, a first via wiring 142 formed integrally with each of the first wirings 141a and 141b, a second wiring 143, a second via wiring 144 formed integrally with the second wiring 143, a third wiring 145, and a third via wiring 146 formed integrally with the third wiring 145. The first wirings 141a and 141b, the second wiring 143, and the third wiring 145 are disposed on the upper surface 100b of the insulating base material 100. The thicknesses of the first wirings 141a and 141b, the second wiring 143, and the third wiring 145 can be, for example, about 50 μm to 150 μm.

[0020] The first via wiring 142 penetrates through the insulating base material 100 and the adhesive layer 110 and is disposed in a through hole 105 that exposes the upper surface of the first electrode 122 of the semiconductor element 120. The second via wiring 144 penetrates through the insulating base material 100 and the adhesive layer 110 and is disposed in a through hole 106 that exposes the second electrode 123 of the semiconductor element 120. The third via wiring 146 penetrates through the insulating base material 100 and the adhesive layer 110 and is disposed in a through hole 107 that exposes the upper surface of the conductive member 130. In the illustrated example, a plurality of through holes 105 and 107 are provided respectively. The number of through holes 105 to 107 can be any number of 1 or more respectively.

[0021] Each of the first wirings 141a and 141b is electrically connected to the first electrode 122 of the semiconductor element 120 via the first via wiring 142. The second wiring 143 is electrically connected to the second electrode 123 of the semiconductor element 120 via the second via wiring 144. The third wiring 145 is electrically connected to the conductive member 130 via the third via wiring 146. Note that since the first wirings 141a and 141b are at the same potential, they may be connected on the insulating base material 100. In this case, the through hole 106 may or may not be provided.

[0022] The wiring layer 140 can have a structure in which a metal layer is laminated on a seed layer, for example. In this case, a metal film (sputtered film) formed by sputtering can be used as the seed layer. As a seed layer formed by sputtering, for example, a two-layer metal film in which a titanium layer and a copper layer are laminated in order can be used. In this case, the thickness of the Ti layer can be, for example, about 10 nm to 300 nm, and the thickness of the Cu layer can be, for example, about 100 nm to 1000 nm. The Ti layer functions as an adhesion layer that improves the adhesion between the insulating substrate 100 and electrodes, etc., and the seed layer. The Ti layer also functions as a metal barrier layer that suppresses the diffusion of copper from the Cu layer, etc., to the insulating substrate 100. In addition to Ti, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), chromium (Cr), etc. can be used as materials for the metal film that functions as such an adhesion layer and metal barrier layer. As materials for the metal layer, for example, copper or copper alloys can be used. As the metal layer, for example, a metal layer formed by electroplating (electroplated metal layer) can be used.

[0023] The insulating layer 150 is disposed at least between the first wirings 141a and 141b and the second wiring 143 on the upper surface 100b of the insulating substrate 100. The insulating layer 150 may also be disposed between the first wirings 141a and 141b and the third wiring 145 on the upper surface 100b of the insulating substrate 100. The insulating layer 150 may extend from between the first wirings 141a and 141b and the second wiring 143 to the upper surface of the first wiring 141a, the upper surface of the first wiring 141b, the upper surface of the second wiring 143, and / or the upper surface of the third wiring 145.

[0024] The first wiring member 171 is positioned above the first wiring 141a, the first wiring 141b, and the second wiring 143. The first wiring member 171 may also be positioned above the third wiring 145. The first wiring member 171 is bonded to the insulating layer 150 extending over the upper surface of the second wiring 143 and to the first wiring 141a via the first conductive adhesive layer 161. Preferably, the first wiring member 171 is further bonded to the insulating layer 150 extending over the upper surface of the third wiring 145 via the first conductive adhesive layer 161.

[0025] The second wiring member 172 is positioned below the semiconductor element 120. Preferably, the second wiring member 172 is further positioned below the conductive member 130. In the illustrated example, the second wiring member 172 is electrically connected to the third electrode 124 of the semiconductor element 120 via the second conductive adhesive layer 162. The conductive member 130 is positioned on the second wiring member 172 via the third conductive adhesive layer 163. The conductive member 130 is electrically connected to the third wiring 145 via the third via wiring 146. In other words, the third electrode 124 is electrically connected to the third wiring 145 via the second conductive adhesive layer 162, the second wiring member 172, the third conductive adhesive layer 163, the conductive member 130, and the third via wiring 146.

[0026] The first wiring member 171 and the second wiring member 172 can be made of, for example, copper or a copper alloy. The first wiring member 171 and the second wiring member 172 may also be components that make up a wiring substrate, such as a ceramic substrate. The first wiring member 171 and the second wiring member 172 can function as heat dissipation components that release heat generated by the operation of the semiconductor element 120 to the outside.

[0027] The sealing resin 180 covers the insulating substrate 100, the adhesive layer 110, the semiconductor element 120, the conductive member 130, the first wiring 141a and 141b, the second wiring 143, and the third wiring 145. The sealing resin 180 may cover the side surfaces of the first wiring member 171 and the second wiring member 172, while exposing the upper surface of the first wiring member 171 and the lower surface of the second wiring member 172. The upper surface of the first wiring member 171 and / or the lower surface of the second wiring member 172 may be joined to a water-based cooler or the like.

[0028] A portion of the insulating substrate 100, a portion of the adhesive layer 110, a portion of the first wiring 141a and 141b, a portion of the second wiring 143, and a portion of the third wiring 145 protrude from the sealing resin 180 in a plan view. The portions of the first wiring 141a and 141b, the second wiring 143, and the third wiring 145 that protrude from the sealing resin 180 can be used as external connection terminals. As the sealing resin 180, for example, an insulating resin such as a thermosetting epoxy resin containing a filler can be used.

[0029] A portion of the insulating layer 150 is exposed from the sealing resin 180 and is located between the first wiring 141b and the second wiring 143, which protrude from the sealing resin 180. Furthermore, a portion of the insulating layer 150 is exposed from the sealing resin 180 and is located between the first wiring 141a and the third wiring 145, which protrude from the sealing resin 180. These arrangements enhance the insulation between adjacent wirings.

[0030] For example, in a plan view, the second wiring 143 protrudes to one side of the sealing resin 180, and the third wiring 145 protrudes to the other side of the sealing resin 180. In a plan view, one side and the other side of the sealing resin 180 are on opposite sides of the sealing resin 180. Also, in a plan view, the first wiring protrudes to both sides of the sealing resin 180. That is, the first wiring 141a and the first wiring 141b protrude to opposite sides of the sealing resin 180, for example. In this case, for example, in a plan view, the first wiring 141b protruding to one side of the sealing resin 180 is adjacent to the second wiring 143 across the insulating layer 150, and the first wiring 141a protruding to the other side of the sealing resin 180 is adjacent to the third wiring 145 across the insulating layer 150.

[0031] Since the first wiring protrudes from both sides of the sealing resin 180, the first wiring 141b protruding to one side can be used to obtain the reference potential of the signal (e.g., gate signal) passing through the second wiring 143. The first wiring 141a protruding to the other side can be used as the negative terminal (e.g., source terminal). The third wiring 145 adjacent to the first wiring 141a can be used as the positive terminal (e.g., drain terminal).

[0032] Thus, in the semiconductor device 1, the first wiring 141a and 141b, the second wiring 143, and the third wiring 145, which are located on the upper surface 100b of the insulating substrate 100, protrude directly outside the sealing resin 180 without the need for bonding wires, thereby becoming external connection terminals. Therefore, it becomes unnecessary to place spacers within the sealing resin 180 to secure space for bonding wires, making it possible to make the semiconductor device 1 thinner.

[0033] Furthermore, in conventional semiconductor devices, spacers are required to secure space for bonding wires, and since the spacers also serve as a path for electrically connecting the semiconductor element and the external connection terminal, the inductance tends to be high. In contrast, in semiconductor device 1, spacers are not required, which allows for a shortening of the path for electrically connecting the semiconductor element and the external connection terminal, thereby reducing the inductance.

[0034] Furthermore, since semiconductor device 1 does not require spacers, it is possible to reduce the number of parts and lower assembly costs. Also, because spacers are not required, the number of conductive adhesive layers in semiconductor device 1 can be reduced to only two layers, which improves connection reliability.

[0035] Furthermore, since the semiconductor device 1 has an insulating layer 150 placed between adjacent wirings, the insulation reliability between adjacent wirings can be improved.

[0036] Furthermore, by extending the insulating layer 150 to the upper surface of the second wiring 143, it becomes possible to place the first conductive adhesive layer 161 on the insulating layer 150 extending to the upper surface of the second wiring 143. This increases the contact area between the first wiring member 171, which functions as a heat dissipation component, and the first conductive adhesive layer 161, making it easier to dissipate the heat generated by the operation of the semiconductor element 120 to the first wiring member 171, thereby improving the heat dissipation performance of the semiconductor device 1. When the side surface of the first wiring member 171 is covered with sealing resin 180, there is a limit to how large the first wiring member 171 can be made, so it is effective to increase the contact area between the first wiring member 171 and the first conductive adhesive layer 161 to improve heat diffusion.

[0037] Furthermore, by extending the insulating layer 150 to the upper surface of the third wiring 145, it becomes possible to place the first conductive adhesive layer 161 on the insulating layer 150 extending to the upper surface of the third wiring 145. As a result, the contact area between the first wiring member 171 and the first conductive adhesive layer 161 is further increased, making it easier to dissipate the heat generated by the operation of the semiconductor element 120 to the first wiring member 171, thereby further improving the heat dissipation performance of the semiconductor device 1.

[0038] [Manufacturing method for semiconductor devices] Next, a method for manufacturing a semiconductor device according to the first embodiment will be described. Figures 3 to 7 illustrate the manufacturing process of a semiconductor device according to the first embodiment. In the following description, an example of manufacturing one semiconductor device is shown, but it is also possible to manufacture a so-called multi-cavity manufacturing method in which the parts that will become the semiconductor device 1 are manufactured all at once, and then separated into individual parts to manufacture a large number of semiconductor devices 1. For the sake of explanation, the parts that will ultimately become each component of the semiconductor device 1 will be denoted by the reference numeral of the final component.

[0039] First, as shown in Figure 3(a), an insulating substrate 100 having a lower surface 100a and an upper surface 100b, and an adhesive layer 110 are prepared. The lower surface 100a of the insulating substrate 100 is provided with an insulating adhesive layer 110 that covers the entire lower surface 100a.

[0040] Next, as shown in Figure 3(b), through-holes 105 to 107 are formed at required locations in the insulating substrate 100 and the adhesive layer 110, penetrating the insulating substrate 100 and the adhesive layer 110 in the thickness direction. The position of through-hole 106 is as shown in Figure 2. Through-holes 105 to 107 can be formed, for example, by laser processing using a CO2 laser or UV-YAG laser, or by punching. Through-hole 105 is formed at a position where the first electrode 122 of the semiconductor element 120 will be exposed in a later process, through-hole 106 is formed at a position where the second electrode 123 of the semiconductor element 120 will be exposed in a later process, and through-hole 107 is formed at a position where the upper surface of the conductive member 130 will be exposed in a later process. The number of through-holes 105 to 107 can be any number of one or more.

[0041] Next, as shown in Figures 4(a) and 4(b), the semiconductor element 120 and the conductive member 130 are bonded to the insulating substrate 100 by the adhesive layer 110. At this time, the first electrode 122 and the second electrode 123 of the semiconductor element 120 are positioned facing the lower surface 100a of the insulating substrate 100, and in a plan view, the first electrode 122 overlaps the through hole 105 and the second electrode 123 overlaps the through hole 106. Also, in a plan view, the upper surface of the conductive member 130 is positioned to overlap the through hole 107. Note that Figure 4(a) is a plan view, and Figure 4(b) is a cross-sectional view along the CC line in Figure 4(a).

[0042] Next, as shown in Figures 5(a) and 5(b), a wiring layer 140 is formed. The wiring layer 140 includes first wirings 141a and 141b, a first via wiring 142 formed integrally with each of the first wirings 141a and 141b, a second wiring 143, a second via wiring 144 formed integrally with the second wiring 143, a third wiring 145, and a third via wiring 146 formed integrally with the third wiring 145. The first wirings 141a and 141b, the second wiring 143, and the third wiring 145 are arranged on the upper surface 100b of the insulating substrate 100. The first via wiring 142 penetrates the insulating substrate 100 and the adhesive layer 110 and is positioned in a through-hole 105 that exposes the first electrode 122 of the semiconductor element 120. The second via wiring 144 penetrates the insulating substrate 100 and the adhesive layer 110 and is positioned in a through-hole 106 that exposes the second electrode 123 of the semiconductor element 120. The third via wiring 146 penetrates the insulating substrate 100 and the adhesive layer 110 and is positioned in a through-hole 107 that exposes the upper surface of the conductive member 130.

[0043] The wiring layer 140 can be formed, for example, by a semi-additive method. Specifically, a seed layer is formed so as to cover the entire upper surface 100b of the insulating substrate 100 and the entire inner surface of the through holes 105 to 107. The seed layer can be formed, for example, by sputtering or electroless plating. For example, when forming the seed layer by sputtering, first, a Ti layer is formed by depositing titanium by sputtering so as to cover the upper surface 100b of the insulating substrate 100 and the inner surface of the through holes 105 to 107. Then, a Cu layer is formed by depositing copper on the Ti layer by sputtering. This makes it possible to form a seed layer with a two-layer structure (Ti layer / Cu layer). Alternatively, when forming the seed layer by electroless plating, for example, a seed layer consisting of a Cu layer (single-layer structure) can be formed by electroless copper plating.

[0044] Next, a plating resist layer is formed on the seed layer, with openings provided in the areas where the wiring layer 140 will be formed, i.e., the areas where the first wirings 141a and 141b, the second wiring 143, and the third wiring 145 will be formed. Subsequently, a metal layer made of copper or the like is formed in the openings of the plating resist layer by an electroplating method that utilizes the seed layer as a plating power supply path. After that, the plating resist layer is removed. Next, the seed layer is removed by wet etching using the metal layer as a mask. In this way, the wiring layer 140 including the seed layer and the metal layer can be formed. A flexible wiring board, for example, is constructed from the insulating substrate 100, the adhesive layer 110, and the wiring layer 140. Figure 5(a) is a plan view, and Figure 5(b) is a cross-sectional view along the DD line in Figure 5(a).

[0045] Next, in the steps shown in Figures 6(a) and 6(b), an insulating layer 150 is formed on the upper surface 100b of the insulating substrate 100. The insulating layer 150 can be formed, for example, by applying a liquid or paste-like epoxy resin, etc., through a mask that has openings at predetermined positions by potting, and then curing it by heating or ultraviolet irradiation. Alternatively, the insulating layer 150 may be formed by applying a liquid or paste-like photosensitive epoxy resin, etc., to the entire upper surface 100b of the insulating substrate 100, and then shaping it by exposure and development. Or, instead of a liquid or paste-like epoxy resin, etc., a film-like epoxy resin, etc., may be laminated.

[0046] Here, as an example, the insulating layer 150 is formed between the first wirings 141a and 141b and the second wiring 143, and between the first wirings 141a and 141b and the third wiring 145. Furthermore, the insulating layer 150 is formed to extend to the upper surfaces of the first wiring 141a, the first wiring 141b, the second wiring 143, and the third wiring 145. Figure 6(a) is a plan view, and Figure 6(b) is a cross-sectional view along the EE line in Figure 6(a).

[0047] Next, in the steps shown in Figures 7(a) and 7(b), the first wiring member 171 is placed above the wiring layer 140 and the insulating layer 150 by the first conductive adhesive layer 161. The second wiring member 172 is placed below the semiconductor element 120 by the second conductive adhesive layer 162 and the third conductive adhesive layer 163. Here, as an example, the first wiring member 171 is bonded to the insulating layer 150 extending over the upper surface of the second wiring 143, the insulating layer 150 extending over the upper surface of the third wiring 145, and the first wiring 141a via the first conductive adhesive layer 161. The second wiring member 172 is bonded to the third electrode 124 of the semiconductor element 120 via the second conductive adhesive layer 162 and to the conductive member 130 via the third conductive adhesive layer 163. The first conductive adhesive layer 161, the second conductive adhesive layer 162, and the third conductive adhesive layer 163 can be, for example, a solder layer or a sintered metal layer containing silver or copper. The first conductive adhesive layer 161, the second conductive adhesive layer 162, and the third conductive adhesive layer 163 may be composed of a conductive paste such as silver paste. The first wiring member 171 and the second wiring member 172 may be joined simultaneously, or they may be joined sequentially using conductive adhesive layers with different melting points. When using conductive adhesive layers with different melting points, for example, solder can be used for the first conductive adhesive layer 161, and sintered metal (e.g., silver) can be used for the second conductive adhesive layer 162 and the third conductive adhesive layer 163, which have higher melting points, and then the first wiring member 171 can be joined via the first conductive adhesive layer 161. Figure 7(a) is a plan view, and Figure 7(b) is a cross-sectional view along the FF line in Figure 7(a).

[0048] Next, the semiconductor device 1 shown in Figures 1 and 2 is completed by forming the sealing resin 180. The sealing resin 180 is formed to cover, for example, the insulating substrate 100, the adhesive layer 110, the semiconductor element 120, the conductive member 130, the first wiring 141a and 141b, the second wiring 143, and the third wiring 145. The sealing resin 180 may be formed to cover the side surfaces of the first wiring member 171 and the second wiring member 172, while exposing the upper surface of the first wiring member 171 and the lower surface of the second wiring member 172.

[0049] A portion of the insulating substrate 100, a portion of the adhesive layer 110, a portion of the first wiring 141a and 141b, a portion of the second wiring 143, and a portion of the third wiring 145 protrude from the sealing resin 180 in a plan view. As the sealing resin 180, for example, an insulating resin such as a thermosetting epoxy resin containing a filler can be used. The sealing resin 180 can be formed, for example, by a transfer molding method using a sealing mold.

[0050] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. [Explanation of Symbols]

[0051] 1 Semiconductor device 100 Insulating substrate 100a bottom side 100b top surface 105, 106, 107 Through holes 110 Adhesive layer 120 Semiconductor Devices 121 Main body 122 1st electrode 123 2nd electrode 124 3rd electrode 130 Conductive material 140 wiring layer 141a, 141b First wiring 142 Via 1 wiring 143 2nd wiring 144 Second via wiring 145 3rd wiring 146 Third via wiring 150 Insulating layer 161 First conductive adhesive layer 162 Second conductive adhesive layer 163 Third conductive adhesive layer 171 First Wiring Member 172 Second Wiring Member 180 Sealing resin

Claims

1. insulating substrate and A semiconductor element having a first electrode and a second electrode, wherein the first electrode and the second electrode are facing the insulating substrate side and are bonded to the lower surface of the insulating substrate via an adhesive layer, A first wiring is disposed on the upper surface of the insulating substrate and is electrically connected to the first electrode via a first via wiring that penetrates the insulating substrate and the adhesive layer, A second wiring is disposed on the upper surface of the insulating substrate and electrically connected to the second electrode via a second via wiring that penetrates the insulating substrate and the adhesive layer, On the upper surface of the insulating substrate, an insulating layer is disposed between the first wiring and the second wiring, A first wiring member positioned above the first wiring and the second wiring, A second wiring member is positioned below the semiconductor element, The semiconductor element, the first wiring, and the sealing resin covering the second wiring are provided. A semiconductor device in which a portion of the first wiring and a portion of the second wiring protrude from the sealing resin in a plan view.

2. The insulating layer extends from between the first wiring and the second wiring to the upper surface of the second wiring. The semiconductor device according to claim 1, wherein the first wiring member is bonded to the insulating layer extending to the upper surface of the second wiring and to the first wiring via a first conductive adhesive layer.

3. The semiconductor device according to claim 2, wherein a portion of the insulating layer is exposed from the sealing resin and is located between the first wiring and the second wiring that protrude from the sealing resin.

4. The semiconductor device according to claim 2, wherein the sealing resin covers the side surface of the first wiring member and the side surface of the second wiring member, and exposes the upper surface of the first wiring member and the lower surface of the second wiring member.

5. The semiconductor device has a third electrode located on the opposite side in the thickness direction from the first electrode and the second electrode. The semiconductor device according to any one of claims 2 to 4, wherein the second wiring member is electrically connected to the third electrode via a second conductive adhesive layer.

6. A conductive member is disposed on the second wiring member via a third conductive adhesive layer, The third wiring is disposed on the upper surface of the insulating substrate and is electrically connected to the conductive member via a third via wiring that penetrates the insulating substrate and the adhesive layer, The semiconductor device according to claim 5, wherein a portion of the third wiring protrudes from the sealing resin in a plan view.

7. The semiconductor device according to claim 6, wherein the insulating layer is also disposed between the first wiring and the third wiring.

8. The insulating layer extends from between the first wiring and the third wiring to the upper surface of the third wiring. The semiconductor device according to claim 7, wherein the first wiring member is bonded to the insulating layer extending to the upper surface of the third wiring via the first conductive adhesive layer.

9. The semiconductor device according to claim 7, wherein a portion of the insulating layer is exposed from the sealing resin and is located between the first wiring and the third wiring that protrude from the sealing resin.

10. In a plan view, the second wiring protrudes to one side of the sealing resin, and the third wiring protrudes to the other side of the sealing resin. In a plan view, the first wiring protrudes from both sides of the sealing resin. The semiconductor device according to claim 7, wherein, in a plan view, the first wiring protruding from one side of the sealing resin is adjacent to the second wiring with the insulating layer in between, and the first wiring protruding from the other side of the sealing resin is adjacent to the third wiring with the insulating layer in between.

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