Semiconductor device and its manufacturing method

Abstract

This invention provides a technology to suppress the flow of solder into the gap between the outer surface of the plating layer and the inner surface of the protective layer. [Solution] The semiconductor device 1 comprises a semiconductor substrate 12, an upper electrode 14 disposed on the semiconductor substrate, a plating layer 16 disposed on the upper electrode inward from the outer edge of the upper electrode, a protective layer 18 that extends over the plating layer from the upper surface of the upper electrode and has an opening that exposes a part of the plating layer, and a solder layer 34 disposed on the plating layer exposed from the opening in the protective layer. The upper surface 16u of the plating layer has a first upper surface portion 17a and a second upper surface portion 17b having a rougher surface than the first upper surface portion. At least a part of the first upper surface portion is in contact with the solder layer. At least a part of the second upper surface portion is in contact with the protective layer.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A semiconductor device includes a top electrode disposed on a semiconductor substrate. The outer peripheral edge of the top electrode is covered with a protective layer. The top electrode located inside the protective layer is exposed from an opening of the protective layer, and a wiring is joined to the exposed top electrode via a plating layer and a solder layer. Patent Document 1 discloses an example of this type of semiconductor device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The outer peripheral surface of the plating layer disposed within the opening of the protective layer faces the inner peripheral surface of the protective layer that defines the opening of the protective layer in the plane direction of the semiconductor substrate. The plating layer shrinks in the plane direction when exposed to a thermal cycle. Therefore, when the semiconductor device is exposed to a thermal cycle, a gap is formed between the outer peripheral surface of the plating layer and the inner peripheral surface of the protective layer, and the solder layer that has flowed due to thermal stress flows into the gap. When the flowing solder layer reaches the semiconductor substrate through the top electrode, the electrical characteristics of the semiconductor device deteriorate.

[0005] Patent Document 1 discloses a technique of additionally disposing a protective layer so as to cover the gap between the outer peripheral surface of the plating layer and the inner peripheral surface of the protective layer. Thereby, it is possible to suppress the solder layer from flowing into the gap between the outer peripheral surface of the plating layer and the inner peripheral surface of the protective layer.

[0006] However, if the adhesion between the added protective layer and the plating layer is poor, there is a concern that the solder layer may penetrate along the interface between the protective layer and the plating layer, and flow into the gap between the outer surface of the plating layer and the inner surface of the protective layer. This specification provides a technique to suppress the flow of the solder layer into the gap between the outer surface of the plating layer and the inner surface of the protective layer. [Means for solving the problem]

[0007] A semiconductor device (1) disclosed herein may include a semiconductor substrate (12), an upper electrode (14) disposed on the semiconductor substrate, a plating layer (16) disposed on the upper electrode inward from the outer edge of the upper electrode, a protective layer (18) that extends over the plating layer from the upper surface of the upper electrode and has an opening that exposes a portion of the plating layer, and a solder layer (34) disposed on the plating layer that is exposed through the opening in the protective layer. The upper surface of the plating layer may have a first upper portion and a second upper portion having a rougher surface than the first upper portion. At least a portion of the second upper portion may be in contact with the protective layer. Here, for example, the expression "disposed on a semiconductor substrate" includes not only cases where it is directly disposed on the semiconductor substrate, but also cases where it is indirectly disposed on the semiconductor substrate via other components. In this specification, relationships between other components specified using similar expressions are interpreted similarly.

[0008] In the semiconductor device described above, the protective layer is in contact with at least a portion of the second upper surface area of ​​the plating layer, which has a relatively large surface roughness. As a result, the adhesion between the protective layer and the plating layer is improved by the anchoring effect. This suppresses the penetration of the solder layer along the interface between the protective layer and the plating layer. Consequently, even if a gap forms between the outer surface of the plating layer and the inner surface of the protective layer when the semiconductor device is exposed to thermal cycling, the solder layer is prevented from flowing into that gap.

[0009] A method for manufacturing a semiconductor device (1) disclosed herein may include the steps of: forming an upper electrode (14) on a semiconductor substrate (12); forming a first protective layer (18a) on the upper electrode having an opening that exposes a part of the upper electrode; forming a plating layer (16) on the upper electrode exposed through the opening of the first protective layer; increasing the surface roughness of a part of the upper surface of the plating layer, wherein a first upper portion and a second upper portion having a surface roughness greater than that of the first upper portion are formed; forming a second protective layer (18b) on the plating layer having an opening that exposes a part of the plating layer, wherein at least a part of the second upper portion is in contact with the second protective layer; and forming a solder layer (34) on the plating layer exposed through the opening of the second protective layer.

[0010] The above manufacturing method allows for the formation of a first upper surface portion with relatively low surface roughness and a second upper surface portion with relatively high surface roughness on the upper surface of the plating layer by performing a step to increase the surface roughness of a portion of the upper surface of the plating layer. Furthermore, in the step of forming the second protective layer on the plating layer, at least a portion of the second upper surface portion comes into contact with the second protective layer. As a result, the above manufacturing method can produce a semiconductor device with improved adhesion between the protective layer and the plating layer. [Brief explanation of the drawing]

[0011] [Figure 1] This is a schematic diagram showing a cross-section of a semiconductor device. [Figure 2] This is an enlarged cross-sectional view of the main part of a semiconductor element mounted on a semiconductor device of the first embodiment, and is an enlarged cross-sectional view of the main part corresponding to the area enclosed by the dashed line "II" in Figure 1. [Figure 3] This is an enlarged cross-sectional view of a key part of a semiconductor element mounted on a semiconductor device of a modified embodiment of the first embodiment, and is an enlarged cross-sectional view of a key part corresponding to the area enclosed by the dashed line "II" in Figure 1. [Figure 4] This diagram schematically shows a cross-sectional view of one process in the manufacturing of a semiconductor device. [Figure 5]This diagram schematically shows a cross-sectional view of one process in the manufacturing of a semiconductor device. [Figure 6] This diagram schematically shows a cross-sectional view of one process in the manufacturing of a semiconductor device. [Figure 7] This diagram schematically shows a cross-sectional view of one process in the manufacturing of a semiconductor device. [Figure 8] This diagram schematically shows a cross-sectional view of one process in the manufacturing of a semiconductor device. [Figure 9] This diagram schematically shows a cross-sectional view of one process in the manufacturing of a semiconductor device. [Figure 10] This is an enlarged cross-sectional view of the main part of a semiconductor element mounted on a semiconductor device of the second embodiment, and is an enlarged cross-sectional view of the main part corresponding to the area enclosed by the dashed line labeled "II" in Figure 1. [Modes for carrying out the invention]

[0012] In this specification, the terms "top," "bottom," "upper surface," and "lower surface" are merely for convenience to indicate relative positions in opposite directions and do not limit the orientation of the semiconductor device during use or manufacture. For example, the "upper surface" of a semiconductor substrate refers only to one of a pair of main surfaces of the semiconductor substrate, and the "lower surface" of a semiconductor substrate refers only to the other main surface of the semiconductor substrate located on the opposite side of the upper surface. Furthermore, in this specification, the terms "inside" and "outside" refer to the orientation toward the center of the semiconductor substrate and the orientation toward the periphery, respectively, when viewed from a direction perpendicular to the main surface of the semiconductor substrate.

[0013] Hereinafter, semiconductor devices to which the technology disclosed herein is applied will be described with reference to the drawings. The semiconductor devices disclosed herein are not particularly limited, but may be used, for example, in power conversion devices. In the semiconductor devices of each embodiment described below, common reference numerals are used for components that are common to each embodiment, and their descriptions are omitted.

[0014] (First Embodiment) As shown in FIG. 1, the semiconductor device 1 includes a semiconductor element 10 and a sealing body 20 that seals the semiconductor element 10. Note that, for the purpose of clarity of illustration, the hatching of the sealing body 20 is omitted. In this example, one semiconductor element 10 is sealed within the sealing body 20. Instead of this example, the semiconductor device 1 may include a plurality of semiconductor elements 10. In this case, the plurality of semiconductor elements 10 may be connected so as to form a parallel circuit or may be connected so as to form a series circuit.

[0015] The semiconductor element 10 includes a semiconductor substrate 12, a bottom electrode 11 disposed on the bottom surface 12b of the semiconductor substrate 12, a top electrode 14 disposed on a part of the top surface 12a of the semiconductor substrate 12, and a protective layer 18 disposed on the top surface 12a of the semiconductor substrate 12 and covering the outer peripheral edge of the top electrode 14.

[0016] The semiconductor element 10 is not particularly limited, but may be, for example, a power semiconductor element. Examples of the power semiconductor element include an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Various semiconductor regions and gate structures for forming the power semiconductor element are formed in the semiconductor substrate 12. The semiconductor substrate 12 is not particularly limited, but may be made of a semiconductor material such as silicon, silicon carbide, gallium nitride, gallium oxide, aluminum nitride, boron nitride, germanium dioxide, or diamond.

[0017] The sealing body 20 is made of an insulator material. The insulator material constituting the sealing body 20 is not particularly limited, but may be a thermosetting resin material such as an epoxy resin.

[0018] The semiconductor device 1 further includes a lower conductor plate 22, an upper conductor plate 24, a conductor block 26, and solder layers 32, 34, 36. The solder layers 32, 34, 36 are not particularly limited, and for example, a multi-component lead-free solder mainly composed of tin (Sn) may be used.

[0019] The lower conductor plate 22 is joined to the lower surface electrode 11 of the semiconductor element 10 by the solder layer 32. The lower conductor plate 22 is not particularly limited, and for example, it may be made of a metal such as copper. Thereby, the lower conductor plate 22 is electrically connected to the lower surface electrode 11 of the semiconductor element 10 and constitutes a part of the wiring. Also, the lower conductor plate 22 is exposed on the lower surface of the sealing body 20 and also functions as a heat radiating plate that releases the heat generated in the semiconductor element 10 to the outside of the sealing body 20.

[0020] The upper conductor plate 24 is joined to the upper surface electrode 14 of the semiconductor element 10 via the conductor block 26. Specifically, the upper conductor plate 24 and the conductor block 26 are joined by the solder layer 36, and the conductor block 26 and the upper surface electrode 14 of the semiconductor element 10 are joined by the solder layer 34. The upper conductor plate 24 and the conductor block 26 are not particularly limited, and for example, they may be made of a metal such as copper. Thereby, the upper conductor plate 24 is electrically connected to the upper surface electrode 14 of the semiconductor element 10 via the conductor block 26 and constitutes a part of the wiring. Also, the upper conductor plate 24 is exposed on the upper surface of the sealing body 20 and also functions as a heat radiating plate that releases the heat of the semiconductor element 10 to the outside.

[0021] FIG. 2 schematically shows an enlarged cross-sectional view of a main part that enlarges the range surrounded by the broken line of "II" in FIG. 1. On the upper surface portion of the semiconductor substrate 12, a surface structure constituting an IGBT or a MOSFET is formed.

[0022] The surface structure formed on the semiconductor substrate 12 includes an n-type drift region 42, a p-type body region 44 located on the drift region 42, and an emitter region 46 located on the body region 44 and separated from the drift region 42 by the body region 44. The body region 44 and the emitter region 46 include portions located at positions exposed to the upper surface 12a of the semiconductor substrate 12. The surface structure further includes a trench gate 50 formed in a trench that penetrates the emitter region 46 and the body region 44 from the upper surface 12a of the semiconductor substrate 12 to the drift region 42. The trench gate 50 includes a gate insulating film 52 and a gate electrode 54 insulated from the semiconductor substrate 12 by the gate insulating film 52. The trench gate 50 faces the portion of the body region 44 that separates the drift region 42 and the emitter region 46. A portion of the body region 44 facing the trench gate 50 functions as a channel. Since such surface structures are well known, a description of their operation will be omitted.

[0023] The top electrode 14, positioned on the upper surface 12a of the semiconductor substrate 12, is bonded to the solder layer 34 via a plating layer 16. The top electrode 14 is in contact with the upper surface 12a of the semiconductor substrate 12 and is positioned on a portion of the upper surface 12a of the semiconductor substrate 12 (see Figure 1). When the semiconductor substrate 12 is viewed from above, the top electrode 14 may have, for example, a rectangular shape. The top electrode 14 is in contact with the body region 44 and the emitter region 46 positioned on the upper surface 12a of the semiconductor substrate 12. The top electrode 14 is not particularly limited, but may be made of a metallic material including aluminum, for example. An example of a metallic material including aluminum is an aluminum-silicon (AlSi) alloy.

[0024] The plating layer 16 is in contact with the upper surface of the upper electrode 14 and is provided on a portion of the upper surface of the upper electrode 14. The plating layer 16 is provided to improve the wettability of the solder layer 34. The plating layer 16 is not particularly limited, but may be composed of a metallic material including nickel, for example. Specifically, the plating layer 16 may be nickel plating.

[0025] The plating layer 16 has an upper surface 16u and an outer peripheral surface 16s. The upper surface 16u of the plating layer 16 is a surface that extends parallel to the upper surface 12a of the semiconductor substrate 12. The outer peripheral surface 16s of the plating layer 16 is a surface that extends from the upper surface 16u toward the upper electrode 14, and in this example, is a surface that is inclined with respect to the upper surface 12a of the semiconductor substrate 12. An outer peripheral edge 16e exists between the upper surface 16u and the outer peripheral surface 16s. Note that the upper surface 16u and the outer peripheral surface 16s of the plating layer 16 may be coated with gold.

[0026] The upper surface 16u of the plating layer 16 has a first upper surface portion 17a and a second upper surface portion 17b which has a greater surface roughness than the first upper surface portion 17a. Surface roughness is defined by the arithmetic mean roughness. The first upper surface portion 17a is the portion of the upper surface 16u of the plating layer 16 that is located towards the center, including the geometric center. The second upper surface portion 17b is located on the side of the upper surface 16u of the plating layer 16 that is closer to the outer edge, and is the portion that encircles the first upper surface portion 17a.

[0027] The outer edge of the upper electrode 14 is covered with a protective layer 18 (see Figure 1). The protective layer 18 further extends from the upper surface of the upper electrode 14 over the outer edge 16e of the plating layer 16, covering a portion of the upper surface 16u of the plating layer 16. The protective layer 18 is not particularly limited, but may be made of polyimide, for example. The protective layer 18 has a first protective layer 18a and a second protective layer 18b. As will be explained in the manufacturing method described later, the first protective layer 18a and the second protective layer 18b are separate layers formed at different times. In this specification, when the first protective layer 18a and the second protective layer 18b are not distinguished, they are referred to as the protective layer 18.

[0028] The first protective layer 18a is arranged around the outer periphery of the upper electrode 14 along its outer edge. The second protective layer 18b extends from the upper surface of the first protective layer 18a to cover a portion of the upper surface 16u of the plating layer 16. That is, the second protective layer 18b is arranged to cover the space between the inner surface of the first protective layer 18a and the outer surface 16s of the plating layer 16. The second protective layer 18b is arranged around the outer periphery of the plating layer 16 along its outer edge 16e.

[0029] The second protective layer 18b is in contact with at least a portion of the second upper surface portion 17b of the upper surface 16u of the plating layer 16. In this example, the second protective layer 18b covers the entire second upper surface portion 17b. Alternatively, the second protective layer 18b may cover only a portion of the second upper surface portion 17b on the outer edge 16e side.

[0030] As explained in the background technology section, in semiconductor device 1, when exposed to thermal cycling, the plating layer 16 shrinks as if being pulled inward in the planar direction of the semiconductor substrate 12. This creates a gap between the outer peripheral surface 16s of the plating layer 16 and the inner peripheral surface 18s of the protective layer 18. If only the first protective layer 18a of the protective layer 18 is provided and the second protective layer 18b is not provided, the solder layer 34 that has flowed due to thermal stress may flow into the gap, pass through the upper electrode 14, and reach the semiconductor substrate 12. If the solder layer 34 reaches the semiconductor substrate 12, there is a concern that, for example, the contact between the body region 44 and the upper electrode 14 will deteriorate, and the latch-up tolerance will decrease.

[0031] On the other hand, the semiconductor device 1 is provided with a second protective layer 18b. Therefore, even if a gap forms between the outer surface 16s of the plating layer 16 and the inner surface 18s of the protective layer 18 when the semiconductor device 1 is exposed to a thermal cycle, the gap remains covered by the second protective layer 18b, thus preventing the solder layer 34 from flowing into that gap. As a result, in the semiconductor device 1, the solder layer 34 is prevented from exceeding the upper electrode 14 and reaching the semiconductor substrate 12.

[0032] In particular, in semiconductor device 1, the second protective layer 18b is in contact with the second upper surface portion 17b of the upper surface 16u of the plating layer 16, which has a relatively large surface roughness. As a result, the adhesion between the second protective layer 18b and the plating layer 16 is improved by the anchoring effect. This suppresses the penetration of the solder layer 34 along the interface between the second protective layer 18b and the plating layer 16. Therefore, even if a gap is formed between the outer surface 16s of the plating layer 16 and the inner surface 18s of the protective layer 18 when semiconductor device 1 is exposed to thermal cycling, the solder layer 34 is prevented from flowing into that gap.

[0033] Furthermore, in semiconductor device 1, the solder layer 34 is in contact with the first upper surface portion 17a of the upper surface 16u of the plating layer 16, which has a relatively small surface roughness. As a result, deterioration of the wettability of the solder layer 34 is suppressed.

[0034] Figure 3 shows a modified example of the semiconductor device 1. In this example, the emitter region 46 constituting the surface structure is not located in a predetermined range that includes the area below where the outer peripheral surface 16s of the plating layer 16 and the inner peripheral surface 18s of the protective layer 18 face each other in the planar direction. As a result, even if the solder layer 34 passes through the upper electrode 14 and reaches the semiconductor substrate 12, there is no NPN transistor composed of a drift region 42, a body region 44, and an emitter region 46, so latch-up is suppressed.

[0035] The following describes the process of forming the upper electrode 14, the plating layer 16, and the protective layer 18, which are included in the manufacturing method of the semiconductor device 1, with reference to Figures 4 to 9. For the other processes, known manufacturing methods can be appropriately adopted.

[0036] First, as shown in Figure 4, an upper electrode 14 is formed on the entire surface of the semiconductor substrate 12, for example, using sputtering technology.

[0037] Next, as shown in Figure 5, for example, etching technology is used to remove a portion of the top electrode 14, and the top electrode 14 is formed on a portion of the top surface 12a of the semiconductor substrate 12.

[0038] Next, as shown in Figure 6, a first protective layer 18a is formed on the upper surface 12a of the semiconductor substrate 12 so as to cover the entire upper electrode 14. Then, for example, an opening is formed by removing a part of the first protective layer 18a using etching technology, and a part of the upper electrode 14 is exposed through the opening.

[0039] Next, as shown in Figure 7, a plating layer 16 is formed on the upper surface of the upper electrode 14 exposed through the opening of the first protective layer 18a, for example, using plating technology.

[0040] Next, as shown in Figure 8, the surface roughness of a portion of the upper surface 16u of the plating layer 16 is increased to form a first upper surface portion 17a and a second upper surface portion 17b. This step may be performed, for example, by forming a mask on the plating layer 16 that exposes a portion of the upper surface 16u of the plating layer 16, and then using dry etching technology to increase the surface roughness of a portion of the upper surface 16u of the plating layer 16. Alternatively, a laser may be irradiated onto a portion of the upper surface 16u of the plating layer 16 to increase the surface roughness of a portion of the upper surface 16u of the plating layer 16.

[0041] Next, as shown in Figure 9, a second protective layer 18b is formed to cover the entire first protective layer 18a and the plating layer 16. Then, for example, using etching technology, an opening is formed by removing a portion of the second protective layer 18b, and the first upper surface portion 17a of the upper surface 16u of the plating layer 16 is exposed through this opening. The semiconductor device 1 is manufactured through these steps.

[0042] (Second Embodiment) Figure 10 shows a semiconductor device 2 of the second embodiment. Compared to the semiconductor device 1 shown in Figure 2, the semiconductor device 2 is characterized in that the top electrode 14 has a metal layer 13 and a barrier layer 15. Here, the metal layer 13 is a layer made of a metallic material including, for example, aluminum, and corresponds to the top electrode of the first embodiment. That is, the semiconductor device 2 is characterized in that it has an additional barrier layer 15 compared to the semiconductor device 1 shown in Figure 2. The barrier layer 15 may be formed on the metal layer 13 after the metal layer 13 is formed on the semiconductor substrate 12 (see Figure 4).

[0043] The barrier layer 15 is in contact with the upper surface of the metal layer 13 and is positioned on the upper surface of the metal layer 13. The barrier layer 15 is made of a metallic material that reduces the diffusion rate of the metal constituting the solder layer 34. As will be described later, the barrier layer 15 is a layer that prevents the solder layer 34 from penetrating into the metal layer 13, and its properties are defined in comparison to the metal layer 13. That is, the barrier layer 15 may be configured such that the diffusion rate of the metal constituting the solder layer 34 is lower than that of the metal layer 13. Specifically, the interdiffusion coefficient of the metal constituting the solder layer 34 with respect to the barrier layer 15 may be smaller than the interdiffusion coefficient of the metal constituting the solder layer 34 with respect to the metal layer 13. For example, in the case of a multicomponent lead-free solder with tin (Sn) as the main component, the barrier layer 15 is not particularly limited, but may include at least one metallic material selected from the group consisting of nickel, tantalum, tungsten, molybdenum, and titanium. The barrier layer 15 may be a single metal of these metallic materials, or it may be an alloy containing at least one of these metallic materials. The barrier layer 15 may be composed of the same metallic material as the plating layer 16. If the barrier layer 15 and the plating layer 16 are made of the same metallic material, the adhesion between the barrier layer 15 and the plating layer 16 is improved.

[0044] The barrier layer 15 is positioned at least below the point where the outer peripheral surface 16s of the plating layer 16 and the inner peripheral surface 18s of the protective layer 18 face each other in the planar direction. The barrier layer 15 is a metallic material that does not easily allow the metal constituting the solder layer 34 to diffuse. Therefore, even if a gap is formed between the outer peripheral surface 16s of the plating layer 16 and the inner peripheral surface 18s of the protective layer 18 when the semiconductor device 1 is exposed to a thermal cycle, and the solder layer 34 flows into that gap, the barrier layer 15 prevents the solder layer 34 from penetrating the metal layer 13. As a result, in the semiconductor device 1, the solder layer 34 is prevented from passing through the metal layer 13 and reaching the semiconductor substrate 12.

[0045] In the above example, the barrier layer 15 was formed over the entire surface of the metal layer 13. Alternatively, the barrier layer 15 may be positioned extending from the lower edge of the outer circumferential surface 16s of the plating layer 16 (or the lower edge of the inner circumferential surface 18s of the protective layer 18) by an arbitrary distance below the plating layer 16 and below the protective layer 18. That is, the barrier layer 15 may be positioned partially on the upper surface of the metal layer 13, including the area below where the outer circumferential surface 16s of the plating layer 16 and the inner circumferential surface 18s of the protective layer 18 face each other in the planar direction. Even in this example, if the solder layer 34 flows into the gap between the outer circumferential surface 16s of the plating layer 16 and the inner circumferential surface 18s of the protective layer 18, the barrier layer 15 will prevent the solder layer 34 from penetrating into the metal layer 13.

[0046] The above example describes a technique for preventing the solder layer 34 from penetrating the metal layer 13, which is the emitter pad. The techniques disclosed herein are not limited to this example. For example, the techniques disclosed herein may be applied to signal pads.

[0047] The specific examples of the technology disclosed in this specification have been described in detail above, but these are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples described above. The technical elements described in this specification or in the drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technology illustrated in this specification or in the drawings can achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness. [Explanation of Symbols]

[0048] 1,2: Semiconductor device, 10: Semiconductor element, 11: Bottom electrode, 12: Semiconductor substrate, 13: Metal layer, 14: Top electrode, 15: Barrier layer, 16: Plating layer, 17a: First top portion, 17b: Second top portion, 18: Protective layer, 20: Encapsulation, 22: Lower conductor plate, 24: Upper conductor plate, 26: Conductor block, 32,34,36: Solder layer

Claims

1. A semiconductor substrate (12) and The upper electrode (14) is disposed on the semiconductor substrate, A plating layer (16) is disposed on the upper electrode inward from the outer edge of the upper electrode, A protective layer (18) is positioned to overlap the plating layer from the upper surface of the upper electrode and has an opening formed therein that exposes a part of the plating layer, The protective layer comprises a solder layer (34) disposed on the plating layer exposed through the opening, The upper surface (16u) of the plating layer has a first upper surface portion (17a) and a second upper surface portion (17b) having a rougher surface than the first upper surface portion. A semiconductor device in which at least a portion of the second upper surface portion is in contact with the protective layer.

2. The semiconductor device according to claim 1, wherein at least a portion of the first upper surface portion is in contact with the solder layer.

3. The semiconductor device according to claim 2, wherein the second upper portion is arranged around the periphery of the first upper portion.

4. The upper electrode has a metal layer (13) disposed on the semiconductor substrate and a barrier layer (15) disposed on the metal layer. The semiconductor device according to any one of claims 1 to 3, wherein the interdiffusion coefficient of the metal constituting the solder layer with respect to the barrier layer is smaller than the interdiffusion coefficient of the metal constituting the solder layer with respect to the metal layer.

5. A step of forming an upper electrode (14) on a semiconductor substrate (12), A step of forming a first protective layer (18a) on the upper electrode, which has an opening that exposes a part of the upper electrode, A step of forming a plating layer (16) on the upper electrode exposed from the opening of the first protective layer, A step of increasing the surface roughness of a portion of the upper surface (16u) of the plating layer, wherein a first upper surface portion (17a) and a second upper surface portion (17b) having a greater surface roughness than the first upper surface portion are formed. A step of forming a second protective layer (18b) on the plating layer, the second protective layer having an opening that exposes a portion of the plating layer, wherein at least a portion of the second upper surface portion is in contact with the second protective layer. A method for manufacturing a semiconductor device, comprising the step of forming a solder layer (34) on the plating layer exposed from the opening of the second protective layer.

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