Semiconductor device and its manufacturing method

Abstract

This technology provides a way to prevent the solder layer from extending beyond the metal layer and reaching the semiconductor substrate. [Solution] The semiconductor device 1 comprises a semiconductor substrate 12, a metal layer 13 disposed on the semiconductor substrate, a barrier layer 14 disposed on the metal layer, a protective layer 18 disposed on the barrier layer and having an opening that exposes a part of the barrier layer, a plating layer 15 disposed on the barrier layer that is exposed through the opening in the protective layer, and a solder layer 34 disposed on the plating layer. The interdiffusion coefficient of the metal constituting the solder layer with respect to the barrier layer is smaller than the interdiffusion coefficient of the metal constituting the solder layer with respect to the metal layer.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A semiconductor device includes a metal layer disposed on a semiconductor substrate. The outer peripheral edge of the metal layer is covered with a protective layer. The metal layer located inside the protective layer is exposed from the opening of the protective layer, and a wiring is joined to the exposed metal layer through a plating layer and a solder layer. Patent Document 1 discloses an example of this type of semiconductor device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The outer peripheral surface of the plating layer disposed within the opening of the protective layer faces the inner peripheral surface of the protective layer that defines the opening of the protective layer in the plane direction of the semiconductor substrate. The plating layer shrinks in the plane direction when exposed to a thermal cycle. Therefore, when the semiconductor device is exposed to a thermal cycle, a gap is formed between the outer peripheral surface of the plating layer and the inner peripheral surface of the protective layer, and the solder layer that has flowed due to thermal stress flows into the gap. When the flowing solder layer passes through the metal layer and reaches the semiconductor substrate, the electrical characteristics of the semiconductor device deteriorate.

[0005] This specification provides a technique for suppressing the solder layer from passing through the metal layer and reaching the semiconductor substrate.

Means for Solving the Problems

[0006] The semiconductor device (1) disclosed herein may include a semiconductor substrate (12), a metal layer (13) disposed on the semiconductor substrate, a barrier layer (14) disposed on the metal layer, a protective layer (18) disposed on the barrier layer and having an opening that exposes a part of the barrier layer, a plating layer (15) disposed on the barrier layer that is exposed through the opening in the protective layer, and a solder layer (34) disposed on the plating layer. The interdiffusion coefficient of the metal constituting the solder layer with respect to the barrier layer is smaller than the interdiffusion coefficient of the metal constituting the solder layer with respect to the metal layer. Here, for example, the expression "disposed on a semiconductor substrate" includes not only cases where it is directly disposed on the semiconductor substrate, but also cases where it is indirectly disposed on the semiconductor substrate via other components. In this specification, relationships between other components identified using similar expressions are interpreted similarly.

[0007] In the semiconductor device described above, a barrier layer is positioned on a metal layer located below the area where the plating layer and the protective layer face each other in the planar direction of the semiconductor substrate. Therefore, when the semiconductor device is exposed to thermal cycling, a gap is formed between the plating layer and the protective layer, and even if the solder layer flows into this gap, the barrier layer prevents the solder layer from penetrating the metal layer. As a result, in the semiconductor device described above, the solder layer is prevented from passing through the metal layer and reaching the semiconductor substrate.

[0008] A method for manufacturing a semiconductor device (1) disclosed herein may include the steps of: forming a metal layer (13) on a semiconductor substrate (12); forming a barrier layer (14) on the metal layer; forming a protective layer (18) on the barrier layer having an opening that exposes a part of the barrier layer; forming a plating layer (15) on the barrier layer exposed through the opening in the protective layer; and forming a solder layer (34) on the plating layer. The interdiffusion coefficient of the metal constituting the solder layer with respect to the barrier layer is smaller than the interdiffusion coefficient of the metal constituting the solder layer with respect to the metal layer.

[0009] The above manufacturing method can produce a semiconductor device in which a barrier layer is placed on a metal layer located below the area where the plating layer and the protective layer face each other in the planar direction of the semiconductor substrate. Therefore, even if a gap is formed between the plating layer and the protective layer when the semiconductor device is exposed to thermal cycling, and solder flows into that gap, the barrier layer prevents the solder layer from penetrating into the metal layer. The above manufacturing method can produce a semiconductor device in which the solder layer is prevented from passing through the metal layer and reaching the semiconductor substrate. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic diagram showing a cross-section of a semiconductor device. [Figure 2] This is an enlarged cross-sectional view of the main part of a semiconductor element mounted on a semiconductor device of the first embodiment, and is an enlarged cross-sectional view of the main part corresponding to the area enclosed by the dashed line "II" in Figure 1. [Figure 3] This is an enlarged cross-sectional view of a key part of a semiconductor element mounted on a semiconductor device of a modified embodiment of the first embodiment, and is an enlarged cross-sectional view of a key part corresponding to the area enclosed by the dashed line "II" in Figure 1. [Figure 4] This diagram schematically shows a cross-sectional view of one process in the manufacturing of a semiconductor device. [Figure 5] This diagram schematically shows a cross-sectional view of one process in the manufacturing of a semiconductor device. [Figure 6] This diagram schematically shows a cross-sectional view of one process in the manufacturing of a semiconductor device. [Figure 7] This diagram schematically shows a cross-sectional view of one process in the manufacturing of a semiconductor device. [Figure 8] This diagram schematically shows a cross-sectional view of one process in the manufacturing of a semiconductor device. [Figure 9] This diagram schematically shows a cross-sectional view of one process in the manufacturing of a semiconductor device. [Figure 10] This is an enlarged cross-sectional view of the main part of a semiconductor element mounted on a semiconductor device of the second embodiment, and is an enlarged cross-sectional view of the main part corresponding to the area enclosed by the dashed line labeled "II" in Figure 1. [Figure 11]This is an enlarged cross-sectional view of a key part of a semiconductor element mounted on a semiconductor device of a modified example of the second embodiment, and is an enlarged cross-sectional view of a key part corresponding to the area enclosed by the dashed line labeled "II" in Figure 1. [Modes for carrying out the invention]

[0011] In this specification, the terms "top," "bottom," "upper surface," and "lower surface" are merely for convenience to indicate relative positions in opposite directions and do not limit the orientation of the semiconductor device during use or manufacture. For example, the "upper surface" of a semiconductor substrate refers only to one of a pair of main surfaces of the semiconductor substrate, and the "lower surface" of a semiconductor substrate refers only to the other main surface of the semiconductor substrate located on the opposite side of the upper surface. Furthermore, in this specification, the terms "inside" and "outside" refer to the orientation toward the center of the semiconductor substrate and the orientation toward the periphery, respectively, when viewed from a direction perpendicular to the main surface of the semiconductor substrate.

[0012] Hereinafter, semiconductor devices to which the technology disclosed herein is applied will be described with reference to the drawings. The semiconductor devices disclosed herein are not particularly limited, but may be used, for example, in power conversion devices. In the semiconductor devices of each embodiment described below, common reference numerals are used for components that are common to each embodiment, and their descriptions are omitted.

[0013] (First Embodiment) As shown in Figure 1, the semiconductor device 1 comprises a semiconductor element 10 and a encapsulant 20 that encloses the semiconductor element 10. Note that the hatching of the encapsulant 20 has been omitted for clarity in the illustration. In this example, one semiconductor element 10 is encapsulated within the encapsulant 20. Alternatively, the semiconductor device 1 may comprise multiple semiconductor elements 10. In this case, the multiple semiconductor elements 10 may be connected to form a parallel circuit or a series circuit.

[0014] The semiconductor device 10 includes a semiconductor substrate 12, a bottom electrode 11 disposed on the bottom surface 12b of the semiconductor substrate 12, a top electrode 16 disposed on a part of the top surface 12a of the semiconductor substrate 12, and a protective layer 18 disposed on the top surface 12a of the semiconductor substrate 12 and covering the outer peripheral edge of the top electrode 16.

[0015] The semiconductor device 10 is not particularly limited, and may be, for example, a power semiconductor device. Examples of the power semiconductor device include an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Various semiconductor regions and gate structures for constituting the power semiconductor device are formed in the semiconductor substrate 12. The semiconductor substrate 12 is not particularly limited, and may be made of a semiconductor material such as silicon, silicon carbide, gallium nitride, gallium oxide, aluminum nitride, boron nitride, germanium dioxide, or diamond.

[0016] The encapsulant 20 is made of an insulating material. The insulating material constituting the encapsulant 20 is not particularly limited, and may be a thermosetting resin material such as an epoxy resin.

[0017] The semiconductor device 1 further includes a lower conductor plate 22, an upper conductor plate 24, a conductor block 26, and solder layers 32, 34, 36. The solder layers 32, 34, 36 are not particularly limited, and may be, for example, a multi-component lead-free solder mainly composed of tin (Sn).

[0018] The lower conductor plate 22 is joined to the lower surface electrode 11 of the semiconductor element 10 by the solder layer 32. The lower conductor plate 22 is not particularly limited, and may be made of a metal such as copper, for example. Thereby, the lower conductor plate 22 is electrically connected to the lower surface electrode 11 of the semiconductor element 10 and constitutes a part of the wiring. Further, the lower conductor plate 22 is exposed on the lower surface of the sealing body 20 and also functions as a heat radiating plate that releases the heat generated in the semiconductor element 10 to the outside of the sealing body 20.

[0019] The upper conductor plate 24 is joined to the upper surface electrode 16 of the semiconductor element 10 via the conductor block 26. Specifically, the upper conductor plate 24 and the conductor block 26 are joined by the solder layer 36, and the conductor block 26 and the upper surface electrode 16 of the semiconductor element 10 are joined by the solder layer 34. The upper conductor plate 24 and the conductor block 26 are not particularly limited, and may be made of a metal such as copper, for example. Thereby, the upper conductor plate 24 is electrically connected to the upper surface electrode 16 of the semiconductor element 10 via the conductor block 26 and constitutes a part of the wiring. Further, the upper conductor plate 24 is exposed on the upper surface of the sealing body 20 and also functions as a heat radiating plate that releases the heat of the semiconductor element 10 to the outside.

[0020] FIG. 2 schematically shows an enlarged cross-sectional view of a main part obtained by enlarging the range surrounded by the broken line of “II” in FIG. 1. On the upper surface portion of the semiconductor substrate 12, a surface structure constituting an IGBT or a MOSFET is formed.

[0021] The surface structure formed on the semiconductor substrate 12 includes an n-type drift region 42, a p-type body region 44 located on the drift region 42, and an emitter region 46 located on the body region 44 and separated from the drift region 42 by the body region 44. The body region 44 and the emitter region 46 include portions located at positions exposed to the upper surface 12a of the semiconductor substrate 12. The surface structure further includes a trench gate 50 formed in a trench that penetrates the emitter region 46 and the body region 44 from the upper surface 12a of the semiconductor substrate 12 to the drift region 42. The trench gate 50 includes a gate insulating film 52 and a gate electrode 54 insulated from the semiconductor substrate 12 by the gate insulating film 52. The trench gate 50 faces the portion of the body region 44 that separates the drift region 42 and the emitter region 46. A portion of the body region 44 facing the trench gate 50 functions as a channel. Since such surface structures are well known, a description of their operation will be omitted.

[0022] The top electrode 16, positioned on the upper surface 12a of the semiconductor substrate 12, is constructed by laminating a metal layer 13 and a barrier layer 14. The top electrode 16 is bonded to the solder layer 34 via a plating layer 15.

[0023] The metal layer 13 is in contact with the upper surface 12a of the semiconductor substrate 12 and is located on a portion of the upper surface 12a of the semiconductor substrate 12 (see Figure 1). When the semiconductor substrate 12 is viewed from above, the metal layer 13 may have, for example, a rectangular shape. The metal layer 13 is in contact with the body region 44 and the emitter region 46 located on the upper surface 12a of the semiconductor substrate 12. The metal layer 13 is not particularly limited, but may be composed of a metallic material including, for example, aluminum. An example of a metallic material including aluminum is an aluminum-silicon (AlSi) alloy.

[0024] The barrier layer 14 is in contact with the upper surface of the metal layer 13 and is positioned on the upper surface of the metal layer 13. The barrier layer 14 is made of a metallic material that reduces the diffusion rate of the metal constituting the solder layer 34. As will be described later, the barrier layer 14 is a layer that prevents the solder layer 34 from penetrating into the metal layer 13, and its properties are defined in comparison to the metal layer 13. That is, the barrier layer 14 may be configured such that the diffusion rate of the metal constituting the solder layer 34 is lower than that of the metal layer 13. Specifically, the interdiffusion coefficient of the metal constituting the solder layer 34 with respect to the barrier layer 14 may be smaller than the interdiffusion coefficient of the metal constituting the solder layer 34 with respect to the metal layer 13. For example, in the case of a multicomponent lead-free solder with tin (Sn) as the main component, the barrier layer 14 is not particularly limited, but may include at least one metallic material selected from the group consisting of nickel, tantalum, tungsten, molybdenum, and titanium. The barrier layer 14 may be a single metal of these metallic materials, or it may be an alloy containing at least one of these metallic materials. The barrier layer 14 may be composed of the same metallic material as the plating layer 15. If the barrier layer 14 and the plating layer 15 are made of the same metallic material, the adhesion between the barrier layer 14 and the plating layer 15 is improved.

[0025] The plating layer 15 is in contact with the upper surface of the barrier layer 14 and is provided on a portion of the upper surface of the barrier layer 14. The plating layer 15 is provided to improve the wettability of the solder layer 34. The plating layer 15 is not particularly limited, but may be composed of a metallic material including nickel, for example. Specifically, the plating layer 15 may be nickel plating. The upper surface of the plating layer 15 may also be coated with gold.

[0026] The outer edge of the barrier layer 14 of the upper electrode 16 is covered with a protective layer 18 (see Figure 1). The protective layer 18 is not particularly limited, but may be made of polyimide, for example. The protective layer 18 is arranged around the periphery of the barrier layer 14 along its outer edge. As a result, an opening is formed in the protective layer 18, and the central part of the barrier layer 14 is exposed through this opening. The part of the barrier layer 14 exposed through the opening in the protective layer 18 is not covered by the protective layer 18, and its upper surface is covered with the plating layer 15. As shown in Figure 2, the inner circumferential surface 18s that defines the opening in the protective layer 18 faces the outer circumferential surface 15s of the plating layer 15 in the planar direction of the semiconductor substrate 12.

[0027] As explained in the background technology section, in semiconductor device 1, when exposed to thermal cycling, the plating layer 15 shrinks as if being pulled inward in the planar direction of the semiconductor substrate 12. This creates a gap between the outer peripheral surface 15s of the plating layer 15 and the inner peripheral surface 18s of the protective layer 18, allowing the solder layer 34, which has flowed due to thermal stress, to flow into this gap. If a barrier layer 14 is not provided, the flowing solder layer 34 may penetrate the metal layer 13 and reach the semiconductor substrate 12 beyond the metal layer 13. If the solder layer 34 reaches the semiconductor substrate 12, there is a concern that, for example, the contact between the body region 44 and the metal layer 13 will deteriorate, reducing the latch-up tolerance.

[0028] On the other hand, in semiconductor device 1, a barrier layer 14 is arranged on the metal layer 13. In particular, the barrier layer 14 is positioned at least below the area where the outer peripheral surface 15s of the plating layer 15 and the inner peripheral surface 18s of the protective layer 18 face each other in the planar direction. The barrier layer 14 is a metallic material that does not easily allow the metal constituting the solder layer 34 to diffuse. Therefore, when semiconductor device 1 is exposed to thermal cycling, a gap is formed between the outer peripheral surface 15s of the plating layer 15 and the inner peripheral surface 18s of the protective layer 18, and even if the solder layer 34 flows into that gap, the barrier layer 14 prevents the solder layer 34 from penetrating the metal layer 13. As a result, in semiconductor device 1, the solder layer 34 is prevented from passing through the metal layer 13 and reaching the semiconductor substrate 12.

[0029] In the above example, the barrier layer 14 was formed over the entire surface of the metal layer 13. Alternatively, the barrier layer 14 may be positioned extending from the lower edge of the outer peripheral surface 15s of the plating layer 15 (or the lower edge of the inner peripheral surface 18s of the protective layer 18) by an arbitrary distance below the plating layer 15 and below the protective layer 18. That is, the barrier layer 14 may be positioned partially on the upper surface of the metal layer 13, including the area below where the outer peripheral surface 15s of the plating layer 15 and the inner peripheral surface 18s of the protective layer 18 face each other in the planar direction. Even in this example, if the solder layer 34 flows into the gap between the outer peripheral surface 15s of the plating layer 15 and the inner peripheral surface 18s of the protective layer 18, the barrier layer 14 will prevent the solder layer 34 from penetrating the metal layer 13.

[0030] Figure 3 shows a modified example of the semiconductor device 1. In this example, the emitter region 46 constituting the surface structure is not located in a predetermined range that includes the area below where the outer peripheral surface 15s of the plating layer 15 and the inner peripheral surface 18s of the protective layer 18 face each other in the planar direction. As a result, even if the solder layer 34 extends beyond the metal layer 13 to the semiconductor substrate 12, there is no NPN transistor composed of a drift region 42, a body region 44, and an emitter region 46, so latch-up is suppressed.

[0031] The following describes the process of forming the metal layer 13, barrier layer 14, plating layer 15, and protective layer 18, which are included in the manufacturing method of the semiconductor device 1, with reference to Figures 4 to 9. For the other processes, known manufacturing methods can be appropriately adopted.

[0032] First, as shown in Figure 4, a metal layer 13 is formed on the entire surface of the semiconductor substrate 12, for example, using sputtering technology.

[0033] Next, as shown in Figure 5, a barrier layer 14 is formed on the entire surface of the metal layer 13 using, for example, sputtering or plating technology.

[0034] Next, as shown in Figure 6, for example, etching technology is used to remove a portion of the metal layer 13 and the barrier layer 14, forming a laminated structure in which the metal layer 13 and the barrier layer 14 are stacked on a portion of the upper surface 12a of the semiconductor substrate 12.

[0035] Next, as shown in Figure 7, a protective layer 18 is formed on the upper surface 12a of the semiconductor substrate 12 so as to cover the entire laminated structure of the metal layer 13 and the barrier layer 14.

[0036] Next, as shown in Figure 8, an opening is formed by removing a portion of the protective layer 18 using, for example, etching technology, and the barrier layer 14 is exposed through this opening.

[0037] Next, as shown in Figure 9, a plating layer 15 is formed on the upper surface of the barrier layer 14 exposed through the opening of the protective layer 18, for example, using plating technology.

[0038] In this way, by forming the barrier layer 14 on the upper surface of the metal layer 13 prior to forming the protective layer 18, the barrier layer 14 can be positioned below the areas where the plating layer 15 and the protective layer 18 face each other in the planar direction.

[0039] (Second Embodiment) Figure 10 shows a semiconductor device 2 of the second embodiment. Compared to the semiconductor device 1 shown in Figure 2, the semiconductor device 2 is characterized in that the protective layer 18 has a first protective layer 18a and a second protective layer 18b. Here, the first protective layer 18a corresponds to the protective layer of the first embodiment. That is, compared to the semiconductor device 1 shown in Figure 2, the semiconductor device 2 is characterized in that it additionally has a second protective layer 18b. The second protective layer 18b is formed after the plating layer 15 is formed so as to cover the first protective layer 18a and a part of the plating layer 15.

[0040] In the semiconductor device 2, the protective layer 18 overlaps the outer edge 15e of the plating layer 15 and covers a portion of the upper surface 15u of the plating layer 15. Here, the upper surface 15u of the plating layer 15 is a surface that extends parallel to the upper surface 12a of the semiconductor substrate 12. The outer edge 15e exists between the upper surface 15u and the outer surface 15s.

[0041] In the semiconductor device 2, when exposed to thermal cycling, the plating layer 15 shrinks as if being pulled inward in the planar direction, and even if a gap is formed between the outer peripheral surface 15s of the plating layer 15 and the inner peripheral surface 18s of the protective layer 18, the gap is covered by the second protective layer 18b, thus preventing the solder layer 34 from flowing into that gap.

[0042] Figure 11 shows a modified example of the semiconductor device 2. In this example, the upper surface 15u of the plating layer 15 has a first upper surface portion 17a and a second upper surface portion 17b which has a rougher surface than the first upper surface portion 17a. Surface roughness is defined as the arithmetic mean roughness. The first upper surface portion 17a is the portion of the upper surface 15u of the plating layer 15 that is located towards the center, including the geometric center. The second upper surface portion 17b is located on the upper surface 15u of the plating layer 15 that is closer to the outer edge 15e, and is the portion that encircles the first upper surface portion 17a. The first upper surface portion 17a and the second upper surface portion 17b may be formed after forming the plating layer 15 on the barrier layer 14, for example, by forming a mask on the plating layer 15 that exposes a part of the upper surface 15u of the plating layer 15, and then increasing the surface roughness of a part of the upper surface 15u of the plating layer 15 using dry etching technology. Alternatively, the first upper portion 17a and the second upper portion 17b may be formed after forming the plating layer 15 on the barrier layer 14, for example by irradiating a part of the upper surface 15u of the plating layer 15 with a laser to increase the surface roughness of that part of the upper surface 15u of the plating layer 15.

[0043] The second protective layer 18b is in contact with at least a portion of the second upper surface portion 17b of the upper surface 15u of the plating layer 15. In this example, the second protective layer 18b covers the entire second upper surface portion 17b. Alternatively, the second protective layer 18b may cover only a portion of the second upper surface portion 17b on the outer edge 15e side.

[0044] In a modified example of the semiconductor device 2, the second protective layer 18b is in contact with the second upper surface portion 17b of the upper surface 15u of the plating layer 15, which has a relatively large surface roughness. As a result, the adhesion between the second protective layer 18b and the plating layer 15 is improved by the anchoring effect. This suppresses the penetration of the solder layer 34 along the interface between the second protective layer 18b and the plating layer 15. Therefore, even if a gap is formed between the outer surface 15s of the plating layer 15 and the inner surface 18s of the protective layer 18 when the semiconductor device 2 is subjected to a thermal cycle, the solder layer 34 is prevented from flowing into that gap.

[0045] Furthermore, in the semiconductor device 2, the solder layer 34 is in contact with the first upper surface portion 17a of the upper surface 15u of the plating layer 15, which has a relatively small surface roughness. As a result, deterioration of the wettability of the solder layer 34 is suppressed.

[0046] The above example describes a technique for preventing the solder layer 34 from penetrating the metal layer 13, which is the emitter pad. The techniques disclosed herein are not limited to this example. For example, the techniques disclosed herein may be applied to signal pads.

[0047] The specific examples of the technology disclosed in this specification have been described in detail above, but these are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples described above. The technical elements described in this specification or in the drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technology illustrated in this specification or in the drawings can achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness. [Explanation of Symbols]

[0048] 1,2: Semiconductor device, 10: Semiconductor element, 11: Bottom electrode, 12: Semiconductor substrate, 13: First metal layer, 14: Barrier layer, 15: Plating layer, 16: Top electrode, 18: Protective layer, 20: Encapsulation, 22: Lower conductor plate, 24: Upper conductor plate, 26: Conductor block, 32,34,36: Solder layer

Claims

1. A semiconductor substrate (12) and A metal layer (13) disposed on the semiconductor substrate, A barrier layer (14) is disposed on the metal layer, A protective layer (18) is disposed on the barrier layer and has an opening formed therein that exposes a part of the barrier layer, A plating layer (15) is disposed on the barrier layer exposed from the opening of the protective layer, The system comprises a solder layer (34) disposed on the aforementioned plating layer, A semiconductor device wherein the interdiffusion coefficient of the metal constituting the solder layer with respect to the barrier layer is smaller than the interdiffusion coefficient of the metal constituting the solder layer with respect to the metal layer.

2. The semiconductor device according to claim 1, wherein the barrier layer is disposed on the entire surface of the metal layer.

3. The barrier layer and the plating layer are in contact, The semiconductor device according to claim 1, wherein the barrier layer and the plating layer contain the same type of metal.

4. The aforementioned metal layer contains an aluminum-silicon alloy. The aforementioned plating layer includes nickel plating. The semiconductor device according to claim 1, wherein the barrier layer comprises at least one selected from the group consisting of nickel, tantalum, tungsten, molybdenum, and titanium.

5. The semiconductor device according to any one of claims 1 to 4, wherein the protective layer extends over the outer edge of the plating layer.

6. A step of forming a first metal layer (13) on a semiconductor substrate (12), The steps include forming a barrier layer (14) on the metal layer, A step of forming a protective layer (18) on the barrier layer, having an opening that exposes a part of the barrier layer, A step of forming a plating layer (15) on the barrier layer exposed from the opening of the protective layer, The process includes the step of forming a solder layer (34) on the aforementioned plating layer, A method for manufacturing a semiconductor device, wherein the interdiffusion coefficient of the metal constituting the solder layer with respect to the barrier layer is smaller than the interdiffusion coefficient of the metal constituting the solder layer with respect to the metal layer.

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