Insulated gate semiconductor device

Abstract

To provide an insulated gate semiconductor device that can suppress the decrease in breakdown resistance. [Solution] A drift layer of a first conductivity type, a base region 5 of a second conductivity type provided on the upper side of the drift layer, a main electrode region 6 of a first conductivity type provided on the upper side of the base region, a base contact region 7 of a second conductivity type provided on the upper side of the base region, having a higher impurity concentration than the base region and adjacent to the main electrode region, a plurality of trenches penetrating the main electrode region and the base region and arranged with a first spacing in a plan view, a gate electrode embedded inside the trenches with a gate insulating film interposed therebetween and forming an inversion layer in a region away from the interface with the trenches in the base region in response to the applied voltage, and a first semiconductor region of a first conductivity type provided in the part of the base region that overlaps with the base contact region in a plan view and divides the base region along the vertical direction. Domain 16 It is equipped with the following.

Description

[Technical Field]

[0001] This disclosure relates to an insulated gate type semiconductor device. [Background technology]

[0002] Non-patent document 1 and patent document 1 below describe a vertical SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field-effect transistor with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor) with a trench gate structure in which FinFET unit cells (functional units of the element) are arranged. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 6631632 [Non-patent literature]

[0004] [Non-Patent Document 1] F.Udrea et al., "Experimental demonstration, challenges, and prospects of the vertical SiC FinFET", 2022 IEEE 34th ISPSD, May 2022 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, in Non-Patent Document 1 and Patent Document 1 mentioned above, the fin width (the width between adjacent gate trenches) is narrow. Therefore, the breakdown withstand capability when a large current is passed through may be lower compared to a normal FET with a wider gate trench width.

[0006] This disclosure is made in view of these circumstances and aims to provide an insulated gate semiconductor device that can suppress the decrease in fracture resistance. [Means for solving the problem]

[0007] To solve the above problems, an insulated gate semiconductor device according to one aspect of the present disclosure comprises: a drift layer of a first conductivity type; a base region of a second conductivity type provided on the upper side of the drift layer; a main electrode region of a first conductivity type provided on the upper side of the base region; a base contact region of a second conductivity type provided on the upper side of the base region, having a higher impurity concentration than the base region and adjacent to the main electrode region; a plurality of trenches penetrating the main electrode region and the base region and arranged with a first spacing in a plan view; a gate electrode embedded inside the trenches with a gate insulating film interposed therebetween, and forming an inversion layer in a region of the base region away from the interface with the trenches in response to an applied voltage; and a first semiconductor region of a first conductivity type provided in the portion of the base region that overlaps with the base contact region in a plan view and divides the base region along the vertical direction.

[0008] Furthermore, the main electrode region and the base contact region are adjacent to each other along a first direction perpendicular to the arrangement direction of the trenches, and the first semiconductor region may divide the base region along the vertical direction and the arrangement direction.

[0009] Furthermore, the thickness of the first semiconductor region along the first direction may be 0.1 μm or more and 0.3 μm or less.

[0010] Furthermore, if the dimension of the base contact region along the first direction is denoted as d1, the thickness of the first semiconductor region along the first direction may be 0.1 μm or more and d1 / 2 or less.

[0011] Furthermore, the main electrode region and the base contact region may be arranged alternately along the first direction, and the first semiconductor region may be provided for each base contact region.

[0012] Further, a gate bottom protection region of a second conductivity type that contacts the lower surface of the trench and is electrically connected to the base region may be provided.

[0013] Also, the first interval may be 0.3 μm or less.

[0014] Also, the drift layer, the base region, and the main electrode region may be made of silicon carbide or silicon.

[0015] Note that the above summary of the disclosure does not list all of the necessary features of the present disclosure. Also, sub-combinations of these feature groups may also be disclosed.

Effects of the Invention

[0016] According to the present disclosure, an insulated gate semiconductor device capable of suppressing a decrease in breakdown voltage can be provided.

Brief Description of the Drawings

[0017] [Figure 1] It is a diagram for explaining the positional relationship in plan view of a gate electrode, a source region, and a base contact region included in an insulated gate semiconductor device according to a first embodiment. [Figure 2] It is a longitudinal sectional view showing a sectional configuration when viewed in cross section along the A-A cut line of FIG. 1. [Figure 3] It is a longitudinal sectional view showing an enlarged part of one unit cell of FIG. 2. [Figure 4] It is a diagram for explaining the sectional configuration when viewed in cross section along the B-B cut line of FIG. 1. [Figure 5] It is a longitudinal sectional view showing a sectional configuration when viewed in cross section along the C-C cut line of FIG. 4. [Figure 6] It is a transverse sectional view showing a sectional configuration when viewed in cross section along the D-D cut line of FIG. 4. [Figure 7] It is a diagram for explaining the sectional configuration of an insulated gate semiconductor device according to a comparative example. [Modes for carrying out the invention]

[0018] The first embodiment of this disclosure will be described below with reference to the drawings. In the drawings, identical or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings. In addition, the first embodiment shown below is an example of an apparatus or method for embodying the technical idea of ​​this disclosure, and the technical idea of ​​this disclosure does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0019] In this specification, the source region of a field-effect transistor (FET) is "one main electrode region (first main electrode region)" which can be selected as the emitter region of an insulated-gate bipolar transistor (IGBT). In thyristors such as MOS-controlled electrostatic induction thyristors (SI thyristors), "one main electrode region" can be selected as the cathode region. The drain region of an FET is "the other main electrode region (second main electrode region)" of the semiconductor device which can be selected as the collector region in the case of an IGBT, or as the anode region in the case of a thyristor. In this specification, when simply referred to as "main electrode region," it means either the first main electrode region or the second main electrode region which is reasonable according to the common technical knowledge of those skilled in the art.

[0020] Furthermore, the definitions of directions such as "up" and "down" in the following explanation are merely for explanatory convenience and do not limit the technical concept of this disclosure. For example, if an object is rotated 90° and observed, "up" will be converted to "left" and read accordingly, and if it is rotated 180° and observed, "up" will be reversed and read accordingly. Also, "top surface" may be read as "front surface," and "bottom surface" may be read as "back surface." In addition, the directions described in this disclosure include directions parallel to the said directions.

[0021] Furthermore, the following explanation uses the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. However, it is also acceptable to choose the conductivity types in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. The + and - attached to n and p indicate semiconductor regions with relatively higher or lower impurity concentrations compared to semiconductor regions without + and - markings. However, even if two semiconductor regions are marked with the same n, this does not mean that the impurity concentrations in each semiconductor region are exactly the same.

[0022] [First Embodiment] <Structure of an insulated gate semiconductor device> Figures 1 to 6 show examples of the configuration of an insulated-gate semiconductor device (MISFET) according to Embodiment 1 of this disclosure. The MISFET according to the first embodiment is a power device and includes a trench-gate type FET as an active element. The semiconductor layer of the MISFET according to the first embodiment may be made of silicon carbide (SiC) or silicon (Si). The fact that the semiconductor layer of the MISFET consists of SiC or Si may include being mainly composed of SiC or Si. In this embodiment, the case in which the semiconductor layer of the MISFET consists of SiC will be described. Furthermore, in this embodiment, the case in which this technology is applied to a unit cell of a FinFET structure will be described. Figure 2 shows examples of unit cells (functional units of the element) C1, C2, and C3 of a FinFET structure. Each of the unit cells C1, C2, and C3 of the FinFET structure includes a Fin section 15. The number of unit cells is not limited to Figure 2 and is arranged in a large number periodically.

[0023] The insulated gate type semiconductor device according to the first embodiment is a first conductivity type (n - It comprises a drift layer 2 of type (type). The drift layer 2 is composed of, for example, an epitaxial growth layer made of SiC. The impurity concentration of the drift layer 2 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 5 x 10 16 cm -3It is as follows. The impurity concentration and thickness of the drift layer 2 can be appropriately adjusted according to the breakdown voltage specification and the like.

[0024] On the upper surface side of the drift layer 2, a current spreading layer (CSL) 3 of the first conductivity type (n-type) with a higher impurity concentration than the drift layer 2 is selectively provided. The lower surface of the current spreading layer 3 is in contact with the upper surface of the drift layer 2. The current spreading layer 3 is composed of, for example, an epitaxial growth layer made of SiC. The impurity concentration of the current spreading layer 3 is, for example, 5×10 16 cm -3 or more and 5×10 17 cm -3 or less. Note that the current spreading layer 3 does not necessarily have to be provided. When the current spreading layer 3 is not provided, the drift layer 2 may be extended to the region of the current spreading layer 3.

[0025] On the upper surface side of the current spreading layer 3, a base region 5 of the second conductivity type (p-type) is provided. The lower surface of the base region 5 is in contact with the upper surface of the current spreading layer 3. When the current spreading layer 3 is not provided, the lower surface of the base region 5 is in contact with the upper surface of the drift layer 2. The base region 5 is composed of, for example, an epitaxial growth layer made of SiC. The base region 5 may be a region in which p-type impurities are ion-implanted into the current spreading layer 3. The impurity concentration of the base region 5 is, for example, 1×10 17 cm -3 or more and 1×10 18 cm -3 or less.

[0026] On the upper surface side of the base region 5, a first main electrode region (source region) 6 of the first conductivity type (n + type) with a higher impurity concentration than the drift layer 2 is selectively provided. The source region 6 is, for example, a region made of SiC formed by ion-implanting n-type impurities into the base region 5. The lower surface of the source region 6 is in contact with the upper surface of the base region 5. The impurity concentration of the source region 6 is, for example, 1×10 17 cm -3 or more and 5×10 18 cm -3 or less.

[0027] Although not shown in Figure 2, the upper surface of base region 5 has a second conductivity type (p) with a higher impurity concentration than base region 5. + A base contact region 7 of type p is selectively provided. The base contact region 7 is, for example, a region made of SiC formed by ion implanting p-type impurities into the base region 5. The lower surface of the base contact region 7 is in contact with the upper surface of the base region 5. The impurity concentration of the base contact region 7 is, for example, 5 × 10⁻¹⁶. 19 cm -3 The above 5 x 10 20 cm -3 It is approximately as follows.

[0028] As shown in Figure 1, the base contact region 7 is adjacent to the source region 6. For example, the base contact region 7 is provided adjacent to the source region 6 along a first direction perpendicular to the arrangement direction of the trenches 8. More specifically, the base contact region 7 and the source region 6 are provided alternately along the first direction. The source region 6 and the base contact region 7 may or may not be in contact with each other. In this embodiment, the arrangement direction of the trenches 8 is the X direction, and the first direction is the Y direction.

[0029] Multiple trenches 8 are provided that penetrate the base contact region 7, source region 6, and base region 5, extending from the upper surfaces of the base contact region 7 and source region 6 in the direction normal to the upper surfaces of the base contact region 7 and source region 6 (depth direction, Z direction). The trenches 8 have a striped planar pattern. For example, the trenches 8 are long in the Y direction in a plan view and are arranged with a gap (first interval) between them in the X direction. The width w2 of the trenches 8 in the arrangement direction (short side direction) is, for example, about 0.3 μm or more and 1.0 μm or less. As shown in Figure 2, the left and right sides of the trenches 8 are in contact with the source region 6, base region 5, and current diffusion layer 3, and the bottom surface of the trenches 8 reaches the current diffusion layer 3. If the current diffusion layer 3 is not provided, the left and right sides of the trenches 8 are in contact with the drift layer 2 instead of the current diffusion layer 3, and the bottom surface of the trenches 8 reaches the drift layer 2. The depth of the trenches 8 is, for example, about 1 μm. The semiconductor regions located between adjacent trenches 8 constitute the fin region 15. The fin region 15 may be, for example, a long stripe in the depth direction and the front direction of the paper in Figure 2. Between adjacent trenches 8 are the base contact region 7, the source region 6, the base region 5, and the current diffusion layer 3. If the current diffusion layer 3 is not provided, the drift layer 2 is located between adjacent trenches 8. The trenches 8 may have a dot-like planar pattern instead of a stripe pattern.

[0030] A gate insulating film 9 is provided along the inner surface of the trench 8, more specifically along the bottom surface and both sides of the trench 8. The gate insulating film 9 is thicker on the bottom surface than on the sides of the trench 8. A gate electrode 10 is embedded inside the trench 8 with the gate insulating film 9 interposed between them. The gate insulating film 9 and the gate electrode 10 constitute a trench gate type insulated gate electrode structure (9,10). In the drawing, the top surface of the gate electrode 10 is at the same depth as the top surface of the source region 6, but the top surface of the gate electrode 10 may be slightly recessed and located deeper than the top surface of the source region 6.

[0031] As the gate insulating film 9, in addition to silicon oxide film (SiO2 film), any single layer film of silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, aluminum oxide (Al2O3) film, magnesium oxide (MgO) film, yttrium oxide (Y2O3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, or bismuth oxide (Bi2O3) film, or a composite film made by stacking multiple of these, can be used. As the material for the gate electrode 10, for example, a polysilicon layer (doped polysilicon layer) with high impurity concentrations of p-type or n-type impurities, or a high-melting-point metal such as titanium (Ti), tungsten (W), or nickel (Ni) can be used. The thickness of the gate insulating film 9 is, for example, about 30 nm or more and 100 nm or less.

[0032] Inside the current diffusion layer 3, and at the bottom of the trench 8, there is a second conductive type (p + A gate bottom protection region 4 of type (type) is provided. The upper surface of the gate bottom protection region 4 is in contact with the lower surface of the trench 8. The impurity concentration of the gate bottom protection region 4 is, for example, 1 × 10⁻⁶. 17 cm -3 The above is 1 x 10 19 cm -3 The extent is as follows. Note that if the current diffusion layer 3 is not provided, a gate bottom protection area 4 is provided within the drift layer 2.

[0033] The configurations of unit cells C1, C2, and C3 shown in Figure 2 are similar. Therefore, using unit cell C2 as an example, the configuration of the unit cells of the FinFET structure will be further explained with reference to Figure 3. The trench 8, gate insulating film 9, and gate electrode 10 located on the left side of the Fin portion 15 of unit cell C2 are sometimes referred to as trench 8L, gate insulating film 9L, and gate electrode 10L. The trench 8, gate insulating film 9, and gate electrode 10 located on the right side of the Fin portion 15 of unit cell C2 are sometimes referred to as trench 8R, gate insulating film 9R, and gate electrode 10R.

[0034] The width w1 of the fin portion 15 is the distance between trenches 8L and 8R, i.e., the first spacing. The width w1 of the fin portion 15 is also the width of the base region 5, source region 6, and current diffusion layer 3 located between trenches 8L and 8R. The width w1 of the fin portion 15 is, for example, about 0.3 μm or less. More preferably, the width w1 of the fin portion 15 is, for example, about 50 nm or more and 0.2 μm or less. The width w1 of the fin portion 15 may be about 0.1 μm or more and 0.2 μm or less, or about 50 nm or more and 0.1 μm or less. One of the features of a FinFET is that the width w1 can be made small in this way.

[0035] The following describes the operation of a conventional FET with a sufficiently large width w1 and the FinFET shown in Figure 3. First, a gate voltage above a threshold is applied to the gate electrodes 10L and 10R. In a conventional FET, when a gate voltage above a threshold is applied to the gate electrode 10, an inversion layer CH is formed along the interface between the base region 5 and the gate insulating film 9. In contrast, in the FinFET shown in Figure 3, because the width w1 of the Fin portion 15 is sufficiently narrow, the voltage from both the gate electrodes 10L and 10R is applied to the entire base region 5. As a result, an inversion layer CH is formed in the base region 5 in a region (bulk region) away from the interface between the base region 5 and the gate insulating films 9L and 9R. For example, the inversion layer CH is formed at a position approximately 0.05 μm to 0.1 μm away from the interface. Alternatively, for example, the inversion layer CH is formed in the center of the base region 5 in the left-right direction of the paper. Therefore, compared to a conventional FET, in a FinFET, electrons moving within the inversion layer CH are less affected by the interface state density between the gate insulating films 9L and 9R and the base region 5. This allows for increased electron mobility and suppression of conduction resistance (ON resistance). SiC is a compound, and the density of interface states beneath the oxide film is about an order of magnitude higher than that of Si. Therefore, gate-type semiconductor devices constructed using SiC are more susceptible to the influence of interface state density on electron mobility than gate-type semiconductor devices constructed using Si. For this reason, applying a FinFET structure to gate-type semiconductor devices constructed using SiC is a countermeasure against the interface state density.

[0036] As shown in Figure 2, an interlayer insulating film 11 is provided on the upper surface of the gate electrode 10. The interlayer insulating film 11 covers the gate electrode 10. The interlayer insulating film 11 is composed of single-layer films such as silicon oxide films doped with boron (B) and phosphorus (P) (BPSG films), silicon oxide films doped with phosphorus (P) (PSG films), undoped silicon oxide films that do not contain phosphorus (P) or boron (B) and are called "NSG", silicon oxide films doped with boron (B) (BSG films), and silicon nitride films (Si3N4 films), or multilayer films of these. The interlayer insulating film 11 is provided with openings 11a so as to expose the upper surfaces of the source region 6 and the base contact region 7. The surface of the interlayer insulating film is not shown in the figure, but it is preferable to cover it with a barrier metal film such as titanium or titanium nitride.

[0037] A contact electrode 12 is embedded inside the opening 11a. The lower surface of the contact electrode 12 is in contact with, for example, the upper surfaces of the source region 6 and the base contact region 7. The contact electrode 12 has a lower layer 12a that is in direct contact with the upper surfaces of the source region 6 and the base contact region 7, and an upper layer 12b that is in contact with the upper surface of the lower layer. The lower layer 12a is a known ohmic metal layer, for example, made of nickel (Ni) or nickel containing silicide. The lower layer 12a may be a single layer or a multilayer film of multiple types of metals. The lower layer 12a makes ohmic contact with the source region 6 and the base contact region 7 with low resistance. The upper layer 12b is made of a conductor such as metal, for example, made of tungsten (W).

[0038] A first main electrode (source electrode) 13 is provided so as to cover the interlayer insulating film 11 and the upper surface of the contact electrode 12. The source electrode 13 is in contact with the contact electrode 12 and is electrically connected to it. The source electrode 13 is made of a metal such as aluminum (Al), aluminum-silicon (Al-Si), aluminum-silicon-copper (Al-Si-Cu), or aluminum-copper (Al-Cu). Since the interlayer insulating film 11 is exposed between the contact electrodes 12, the adhesion between the source electrode 13 and the substrate can be improved.

[0039] On the lower side of the drift layer 2, a first conductivity type (n) with a higher impurity concentration than the drift layer 2 is present. + A second main electrode region (drain region) 1 of type 1 is provided. The drain region 1 is made of a semiconductor substrate (SiC substrate), for example, SiC. The impurity concentration of the drain region 1 is, for example, 1 × 10⁻⁶. 19 cm -3 The above is 3 x 10 20 cm -3 The following is an example: The thickness of the drain region 1 is, for example, 30 μm or more and 500 μm or less. A dislocation conversion layer or a recombination promotion layer, which is an n-type buffer layer with a higher impurity concentration than the drift layer 2 and a lower impurity concentration than the drain region 1, may be provided between the drift layer 2 and the drain region 1.

[0040] A second main electrode (drain electrode) 14 is provided on the lower side of the drain region 1. For the drain electrode 14, a single layer film made of gold (Au), or a metal film laminated in the order of titanium (Ti), nickel (Ni), and Au from the drain region 1 side can be used, and a metal film of molybdenum (Mo), tungsten (W), etc. may be laminated as the bottom layer. Furthermore, nickel silicide (NiSi) is provided between the drain region 1 and the drain electrode 14 for ohmic contact. x A drain contact layer such as a film may be provided. In this specification, when the term "main electrode" is used, it means either the first main electrode or the second main electrode, which is appropriate according to the common technical knowledge of those skilled in the art.

[0041] Figure 4 is a diagram illustrating the cross-sectional configuration when viewed in a plane along the BB cutting line of Figure 1. Figure 5 is a diagram illustrating the cross-sectional configuration when viewed in a plane along the CC cutting line of Figure 4. Note that the scales of Figures 2, 4, and 5 are different from each other. As shown in Figure 4, a first semiconductor region 16 of the first conductivity type (n-type) is provided in the portion of the base region 5 that overlaps with the base contact region 7 in a plan view, dividing the base region 5 along the vertical direction. As shown in Figure 5, the first semiconductor region 16 divides the base region 5 not only in the vertical direction but also along the arrangement direction of the trenches 8. The first semiconductor region 16 may be provided only in the portion of the base region 5 that overlaps with the base contact region 7 in a plan view, or in the portion that overlaps with the source region 6. Alternatively, the first semiconductor region 16 may be provided for each base contact region 7. The first semiconductor region 16 is composed of a part of the current diffusion layer 3. By providing the first semiconductor region 16, a portion of the lower surface of the base contact region 7 can directly contact the upper surface of the current diffusion layer 3, and since holes are directly extracted in the contact region 7, which has a higher impurity concentration than the base region 5, the amount of hole (current) extracted can be increased.

[0042] To prevent the source region 6 from short-circuiting with the current diffusion layer 3, it is desirable to provide the first semiconductor region 16 at a position sufficiently far from the source region 6. Although not limited to this, for example, the first semiconductor region 16 may be provided so as to be located in the central part along the first direction (Y direction) of the base contact region 7.

[0043] The dimension d2 of the first semiconductor region 16 along the first direction is preferably about 0.1 μm or more and 0.3 μm or less, more preferably about 0.2 μm. The maximum value of the dimension d2 of the first semiconductor region 16 may be about half (d1 / 2) of the dimension d1 of the base contact region 7 in the first direction. More specifically, the dimension d2 may be about 0.1 μm or more and d1 / 2 or less. The dimension d1 of the base contact region 7 is, for example, about 7 μm or more and 13 μm or less.

[0044] Figure 6 shows the cross-sectional configuration of the base region 5 when viewed in a plane along the DD cutting line in Figure 4. The portion of the base region 5 that overlaps with the source region 6 in a plan view is called base region 5a, and the portion that overlaps with the base contact region 7 in a plan view is called base region 5b, and these are distinguished from each other. Figure 6 shows the cross-sectional configuration of the base region 5 where the inversion layer CH is formed. The inversion layer CH formed in base region 5a and the inversion layer CH formed in base region 5b are connected to each other along the X direction. Furthermore, the inversion layer CH formed in base region 5b is connected to the first semiconductor region 16 along the X direction. In this way, the inversion layer CH is formed not only from the side of the trench but also along the first semiconductor region 16, and the interference of electrons increases the electron density and reduces the resistance.

[0045] If the current diffusion layer 3 is not provided, the first semiconductor region 16 is composed of a part of the drift layer 2. In that case, a part of the lower surface of the base region 5 is in direct contact with the upper surface of the drift layer 2. Alternatively, the first semiconductor region 16 may be formed by ion implantation of n-type impurities into the base region 5. In that case, a part of the lower surface of the base region 5 is connected to the current diffusion layer 3 or the drift layer 2 via the first semiconductor region 16.

[0046] During operation of the insulated gate semiconductor device according to the first embodiment, the source electrode 13 is set to ground potential, and a positive voltage is applied to the drain electrode 14. When a positive voltage above a threshold is applied to the gate electrode 10 in this state, an inversion layer (channel) CH is formed in the base region 5, away from the interface between the base region 5 and the trench 8, as shown in Figure 3, and the device enters an ON state. In the ON state, current flows from the drain electrode 14 to the source electrode 13 via the drain region 1, drift layer 2, current diffusion layer 3, the inversion layer CH in the base region 5, the source region 6, and the contact electrode 12. On the other hand, when the voltage applied to the gate electrode 10 is below the threshold, the inversion layer CH is not formed in the base region 5, resulting in an OFF state, and no current flows from the drain electrode 14 to the source electrode 13.

[0047] <Main effects of the first embodiment> The main effects of the first embodiment will be described below, but before that, an overview and a comparative example of an insulated gate semiconductor device shown in Figure 7 will be explained. It is generally known that parasitic NPN transistors may malfunction due to holes generated by dV / dt during transistor switching. It is also known that when a parasitic NPN transistor malfunctions, its breakdown withstand capability may decrease. In some cases, a parasitic NPN transistor is composed of an n-type current diffusion layer 3, a p-type base region 5, and an n-type source region 6.

[0048] As shown in Figure 7, the insulated gate semiconductor device according to the comparative example does not have a first semiconductor region 16, and the base region 5 is provided continuously along the Y direction. More specifically, the entire lower surface of the base contact region 7 is in contact with the upper surface of the base region 5, which has a lower impurity concentration than the base contact region 7. Therefore, holes released into the current diffusion layer 3 due to dV / dt had to pass through the base region 5 with its lower impurity concentration before being extracted by the base contact region 7. Thus, in the insulated gate semiconductor device according to the comparative example, the base region 5 is always interposed between the base contact region 7 and the current diffusion layer 3, so the amount of hole extraction was suppressed.

[0049] In contrast, according to the insulated gate semiconductor device of the first embodiment of this technology, there is an n-type first semiconductor region 16 provided in the portion of the base region 5 that overlaps with the base contact region 7 in a plan view, and which divides the base region 5 along the vertical direction. By intentionally providing a region below the base contact region 7 where the base region 5 is absent, the base contact region 7 can directly contact the current diffusion layer 3. As a result, at least a portion of the holes released into the current diffusion layer 3 are extracted directly by the base contact region 7 without passing through the base region 5 with a low impurity concentration. Since the holes are extracted directly by the contact region 7, which has a higher impurity concentration than the base region 5, the amount of holes extracted can be increased, and the conduction resistance can be suppressed. Furthermore, this can suppress the voltage between the source and drain, making it difficult for parasitic NPN transistors to turn on. Therefore, a decrease in breakdown withstand capability can be suppressed.

[0050] Furthermore, according to the insulated gate type semiconductor device of the first embodiment of this technology, the source region 6 and the base contact region 7 are adjacent to each other along a first direction perpendicular to the arrangement direction of the trenches 8, and the first semiconductor region 16 divides the base region 5 along the vertical direction and the arrangement direction of the trenches 8. Therefore, even if the width w1 of the fin portion 15 is narrow, the area of ​​the structure that extracts holes along the first direction can be increased, making it more difficult for parasitic NPN transistors to turn on. As a result, a decrease in breakdown withstand capability can be suppressed.

[0051] Furthermore, according to the insulated gate type semiconductor device of the first embodiment of this technology, the thickness d2 of the first semiconductor region 16 along the first direction is 0.1 μm or more and 0.3 μm or less. If the thickness d2 is too narrow, less than 0.1 μm, the contact resistance deteriorates. If the thickness d2 is too wide, exceeding 0.3 μm, the switching breakdown withstand capability decreases, especially at -55°C. By setting the thickness d2 to 0.1 μm or more and 0.3 μm or less, the depletion layer extending laterally from the base region 5 is connected, and the decrease in breakdown withstand capability can be suppressed.

[0052] Furthermore, according to the insulated gate type semiconductor device of the first embodiment of this technology, when the dimension of the base contact region 7 along the first direction is d1, the thickness d2 of the first semiconductor region 16 along the first direction is 0.1 μm or more and d1 / 2 or less. By setting the thickness d2 to the above value, the contact area between the base contact region 7 and the current diffusion layer 3 can be increased, the amount of hole extraction can be increased, and the decrease in fracture resistance can be suppressed.

[0053] Furthermore, according to the insulated gate type semiconductor device of the first embodiment of this technology, the source region 6 and the base contact region 7 are alternately arranged along the first direction, and the first semiconductor region 16 is provided for each base contact region 7. Therefore, even if the width w1 of the fin portion 15 is narrow, the area in direct contact between the base contact region 7 and the current diffusion layer 3 can be increased. This increases the area of ​​the structure that extracts holes along the first direction, making it more difficult for parasitic NPN transistors to turn on. Therefore, a decrease in breakdown withstand capability can be suppressed.

[0054] <Modification 1 of the first embodiment> In the insulated gate type semiconductor device according to Modification 1 of the first embodiment of this technology, the gate bottom protection region 4 is connected to the base region 5 via a second semiconductor region of the second conductivity type (p-type). This allows the potential of the gate bottom protection region 4 to be fixed, and the gate insulating film at the bottom of the trench can be protected.

[0055] [Other embodiments] As described above, a first embodiment of this disclosure has been presented, but the statements and drawings that constitute part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0056] For example, although an FET was given as an example of a semiconductor device according to the first embodiment, n + Instead of drain region 1 of type p +This method is also applicable to insulated-gate bipolar transistors (IGBTs) with a collector region of a specific type. In addition to IGBTs alone, it is also applicable to reverse-conducting IGBTs (RC-IGBTs) and reverse-blocking insulated-gate bipolar transistors (RB-IGBTs).

[0057] Furthermore, the configurations disclosed in the first embodiment can be combined as appropriate, within the bounds of consistency. Thus, this disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of this disclosure is determined solely by the inventive features relating to the claims that are appropriate based on the above description. [Explanation of Symbols]

[0058] 1…Drain region (SiC substrate) 2…Drift layer 3…Current diffusion layer 4…Gate bottom protection area 5, 5a, 5b... Base region 6…Source region (first main electrode region) 7…Base contact area 8, 8L, 8R... Trench 9, 9L, 9R… Gate Insulator 10, 10L, 10R… Gate stop 11…Interlayer insulating film 11a...Opening 12… Contact electrodes 12a…lower layer 12b…upper layer 13…Source electrode (first main electrode) 14…Second main electrode (drain electrode) 15...Fin part 16…First Semiconductor Area C1, C2, C3... Unit cells CH... Inversion layer (channel) w1…Width (1st interval) w2... width d1, d2… Dimensions

Claims

1. A first conductive drift layer, A second conductivity type base region provided on the upper surface side of the drift layer, A first conductivity type main electrode region is provided on the upper surface side of the base region, A second conductivity type base contact region is provided on the upper surface side of the base region, has a higher impurity concentration than the base region, and is adjacent to the main electrode region. A plurality of trenches that penetrate the main electrode region and the base region and are arranged with a first spacing in a plan view, A gate electrode embedded inside the trench with a gate insulating film interposed therebetween, and which forms an inversion layer in a region away from the interface with the trench within the base region in response to the applied voltage, A first semiconductor region of a first conductivity type is provided in the portion of the base region that overlaps with the base contact region in a plan view, and divides the base region along the vertical direction. An insulated gate semiconductor device equipped with the following features.

2. The main electrode region and the base contact region are adjacent to each other along a first direction perpendicular to the arrangement direction of the trenches. The first semiconductor region divides the base region along the vertical direction and the arrangement direction. The insulated gate semiconductor device according to claim 1.

3. The thickness of the first semiconductor region along the first direction is 0.1 μm or more and 0.3 μm or less. The insulated gate semiconductor device according to claim 2.

4. When the dimension of the base contact region along the first direction is denoted as d1, the thickness of the first semiconductor region along the first direction is 0.1 μm or more and d1 / 2 or less. The insulated gate semiconductor device according to claim 2.

5. The main electrode region and the base contact region are arranged alternately along the first direction. The first semiconductor region is provided for each of the base contact regions, An insulated gate semiconductor device according to any one of claims 2 to 4.

6. The gate bottom protection region comprises a second conductive type that is in contact with the lower surface of the trench and electrically connected to the base region. An insulated gate semiconductor device according to any one of claims 1 to 4.

7. The first interval is 0.3 μm or less. An insulated gate semiconductor device according to any one of claims 1 to 4.

8. The drift layer, the base region, and the main electrode region are made of silicon carbide or silicon. An insulated gate semiconductor device according to any one of claims 1 to 4.

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