Gallium nitride semiconductor device and method for manufacturing the same
The GaN semiconductor device with a multi-stage JTE structure, featuring constituent and adjustment regions with controlled impurity distributions, addresses the issue of floating p-type regions, effectively suppressing electric field concentration.
Patent Information
- Application Number
- JP2025021814
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-13
- Publication Date
- 2026-08-25
AI Technical Summary
In existing GaN semiconductor devices with a multi-stage JTE structure, regions where n-type layers are placed between adjacent p-type regions lead to floating p-type regions, resulting in insufficient suppression of electric field concentration.
A GaN semiconductor device with a multi-stage JTE structure composed of constituent regions and adjustment regions, where p-type impurity concentration is progressively lower from the cell region side, and the adjustment regions have a more spread distribution in the depth direction, preventing floating states and suppressing electric field concentration.
The solution effectively suppresses the floating state of p-type regions, preventing the formation of regions with significantly high p-type impurity concentrations and thereby reducing electric field concentration in the outer peripheral region.
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Figure 2026135964000001_ABST
Abstract
Description
[Technical Field]
[0001] This disclosure relates to a GaN semiconductor device comprising gallium nitride (hereinafter also simply referred to as GaN) and a method for manufacturing the same. [Background technology]
[0002] Conventionally, for example, Patent Document 1 proposes a semiconductor device equipped with a multi-stage JTE (Junction Termination Extension) structure in the outer peripheral region to suppress electric field concentration in the outer peripheral region. Specifically, this semiconductor device comprises a semiconductor substrate having a cell region and an outer peripheral region surrounding the cell region, and a diode element having a pn junction is formed in the cell region. In this semiconductor device, the diode element is constructed by forming a p-type layer on the surface of an n-type layer.
[0003] In the outer region, a multi-stage JTE structure is arranged, consisting of multiple p-type regions formed along the plane direction of the semiconductor substrate on the surface of the n-type layer. Specifically, each p-type region is configured such that the impurity concentration decreases sequentially from the cell region side to the opposite side. Furthermore, the p-type region located closest to the cell region is electrically connected to the p-type layer in the cell region. However, in this multi-stage JTE structure of the semiconductor device, there are portions where an n-type layer is arranged between adjacent p-type regions in the plane direction.
[0004] The p-type regions constituting such a multi-stage JTE structure are formed by sequentially arranging multiple masks, each with an opening in a different region, and implanting p-type impurities using ions. In this case, mask misalignment can potentially create regions with a higher implantation concentration of p-type impurities. Therefore, in the above semiconductor device, the shape of the mask is adjusted to prevent ion implantation of p-type impurities in regions where mask misalignment could lead to a higher implantation concentration. For this reason, in the above semiconductor device, there are regions where an n-type layer is positioned between adjacent p-type regions in the planar direction. [Prior art documents] [Patent Documents]
[0005] [Patent Document 1] Japanese Patent Publication No. 2016-25300 [Overview of the Initiative] [Problems that the invention aims to solve]
[0006] In the multi-stage JTE structure of the semiconductor device described above, there are regions where n-type layers are placed between adjacent p-type regions. Therefore, some p-type regions in the multi-stage JTE structure become floating and prone to instability. Consequently, electric field concentration in the outer region may not be sufficiently suppressed.
[0007] The present disclosure aims to provide a GaN semiconductor device and a method for manufacturing the same that can suppress the floating state of p-type regions constituting the JTE structure. [Means for solving the problem]
[0008] According to one aspect of this disclosure, a semiconductor device having a multi-stage JTE structure comprises a semiconductor substrate (10) having an n-type layer (11) and a cell region (RS) on which a semiconductor element is formed and an outer peripheral region (RO) surrounding the cell region, and a plurality of constituent regions (21-27) arranged along the plane direction of the semiconductor substrate on one side (10a) of the outer peripheral region of the semiconductor substrate, wherein the p-type impurity concentration is progressively lower from the cell region side toward the opposite side of the cell region, and between adjacent constituent regions in the plane direction there is a portion where adjustment regions (31-33) composed of p-type are arranged, and the constituent regions and adjustment regions are in contact with adjacent regions in the plane direction, and the multi-stage JTE structure is composed including the constituent regions and adjustment regions, and in the depth direction of the semiconductor substrate, the distribution of p-type impurity concentration in the portion including the adjustment regions is more spread in the depth direction than the distribution of p-type impurity concentration in the portion including the constituent regions.
[0009] According to this, the multi-stage JTE structure in a GaN semiconductor device is composed of multiple component regions and adjustment regions. These multiple component regions and adjustment regions are formed to be in contact with adjacent regions in the planar direction. Therefore, for example, when the component region closest to the cell region is connected to the p-type layer of the cell region, it is possible to suppress the floating state of the component regions constituting the multi-stage JTE structure.
[0010] According to another aspect of this disclosure, the method for manufacturing the GaN semiconductor device involves preparing a semiconductor substrate including the planned configuration region and the planned adjustment region, with the region where the configuration region is formed being designated as the planned configuration region (210-270) and the region where the adjustment region is formed being designated as the planned adjustment region (310-330); using a mask (110, 150-170) with openings in the planned configuration region, ion implanting nitrogen such that the implantation concentration in the planned configuration region is higher than that in the planned adjustment region; and forming an opening on one surface of the semiconductor substrate (120-14) that exposes at least a portion of the planned configuration region. The process involves arranging (0, 150~170) and ion implanting p-type impurities using a mask, repeating this process while changing the mask with different openings when arranging the mask. P-type impurities are ion-implanted so that the implantation concentration in the planned constituent region decreases sequentially from the cell region side to the opposite side of the cell region. Additionally, p-type impurities are ion-implanted into the planned adjustment region, and heat treatment is performed to activate the p-type impurities and constitute the constituent region and adjustment region. The planned adjustment region is defined as a region where the implantation concentration of p-type impurities is more easily changed than in the planned constituent region.
[0011] According to this, it is possible to manufacture GaN semiconductor devices in which the constituent regions of the multi-stage JTE structure are suppressed from becoming floating. Furthermore, since the planned adjustment region is considered to be a region in which the p-type impurity concentration implantation concentration is more easily changed than that of the planned constituent region, it is suppressed that the p-type impurity concentration in the adjustment region becomes significantly higher than that of the constituent region. In other words, it is suppressed that a region with a significantly high p-type impurity concentration is formed within the multi-stage JTE structure. Therefore, it is possible to suppress the occurrence of electric field concentration in the outer region.
[0012] Note that the reference numerals with parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.
Brief Description of the Drawings
[0013] [Figure 1] It is a cross-sectional view of the GaN semiconductor device in the first embodiment. [Figure 2] It is an enlarged view of a portion including the second constituent region, the first adjustment region, and the third constituent region shown in FIG. 1. [Figure 3] It is a diagram showing the impurity concentration along line III-III in FIG. 2. [Figure 4] It is a diagram showing the impurity concentration along line IV-IV in FIG. 2. [Figure 5] It is a diagram showing the impurity concentration along line V-V in FIG. 2. [Figure 6A] It is a cross-sectional view showing the manufacturing process of the GaN semiconductor device shown in FIG. 1. [Figure 6B] It is a cross-sectional view showing the manufacturing process of the GaN semiconductor device following FIG. 6A. [Figure 6C] It is a cross-sectional view showing the manufacturing process of the GaN semiconductor device following FIG. 6B. [Figure 6D] It is a cross-sectional view showing the manufacturing process of the GaN semiconductor device following FIG. 6C. [Figure 6E] It is a cross-sectional view showing the manufacturing process of the GaN semiconductor device following FIG. 6D. [Figure 7A] It is a cross-sectional view showing the manufacturing process of the GaN semiconductor device in the second embodiment. [Figure 7B] It is a cross-sectional view showing the manufacturing process of the GaN semiconductor device following FIG. 7A. [Figure 7C] It is a cross-sectional view showing the manufacturing process of the GaN semiconductor device following FIG. 7B. [Figure 7D] It is a cross-sectional view showing the manufacturing process of the GaN semiconductor device following FIG. 7C. [Figure 7E] It is a cross-sectional view showing the manufacturing process of the GaN semiconductor device following FIG. 7D. [Figure 7F] This is a cross-sectional view showing the manufacturing process of GaN semiconductor devices, following Figure 7E. [Figure 8] This is a cross-sectional view of a GaN semiconductor device in a third embodiment. [Modes for carrying out the invention]
[0014] The embodiments of this disclosure will be described below with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.
[0015] (First Embodiment) The first embodiment will be described with reference to the drawings. First, the configuration of the GaN semiconductor device of this embodiment will be described.
[0016] As shown in Figure 1, the GaN semiconductor device is made of GaN and has one surface 10a and n - The semiconductor substrate 10 has a mold layer 11. The semiconductor substrate 10 (i.e., GaN semiconductor device) has a cell region RS and an outer peripheral region RO surrounding the cell region RS.
[0017] In this embodiment, a diode element is formed in the cell region RS as a semiconductor element. In this embodiment, n - On the surface of the mold layer 11 (i.e., on the side of surface 10a), p + A mold layer 12 is placed, n - The mold layer 11 is used as the cathode layer, and p + A diode element is formed with the mold layer 12 as the anode layer. + The mold layer 12 extends from the cell region RS to the portion of the outer peripheral region RO that is on the cell region RS side. In this embodiment, p + The mold layer 12 can also be described as the part that connects to the JTE structure in the semiconductor device.
[0018] On one surface 10a of the semiconductor substrate 10, an insulating film 13 is disposed in the cell region RS and the outer peripheral region RO. This insulating film 13 may be shared by the cell region RS and the outer peripheral region RO, or may have different configurations in the cell region RS and the outer peripheral region RO.
[0019] On the one surface 10a side of the outer peripheral region RO, a multi-stage JTE structure composed of a plurality of p-type regions is disposed. Specifically, on the one surface 10a side of the outer peripheral region RO, along the plane direction of the semiconductor substrate 10 (hereinafter, also simply referred to as the plane direction), in order from the cell region RS side, the first configuration region 21, the second configuration region 22, the third configuration region 23, the fourth configuration region 24, the fifth configuration region 25, the sixth configuration region 26, and the seventh configuration region 27 are disposed. In the present embodiment, in the first to seventh configuration regions 21 to 27, the p-type impurity concentration of the first configuration region 21 is the highest, and the p-type impurity concentration is decreased in order from the first configuration region 21 to the seventh configuration region 27. And the first configuration region 21 is electrically connected to a p + type layer 12 extending from the cell region RS side. Note that the first configuration region 21 has a lower impurity concentration than the p + type layer 12.
[0020] Also, in the present embodiment, a first adjustment region 31 of p-type is disposed between the second configuration region 22 and the third configuration region 23. A second adjustment region 32 of p-type is disposed between the fourth configuration region 24 and the fifth configuration region 25. A third adjustment region 33 of p-type is disposed between the sixth configuration region 26 and the seventh configuration region 27. And the multi-stage JTE structure of the present embodiment is configured to include the first to seventh configuration regions 21 to 27 and the first to third adjustment regions 31 to 33. In the present embodiment, the multi-stage JTE structure is formed so as to surround the cell region RS.
[0021] Note that the first to seventh configuration regions 21 to 27 and the first to third adjustment regions 31 to 33 are formed so as to contact any one of the adjacent configuration regions and adjustment regions in the plane direction. That is, the first to seventh configuration regions 21 to 27 and the first to third adjustment regions 31 to 33 have n between adjacent regions in the plane direction -The mold layer 11 is formed so that it is not arranged. Therefore, in the JTE structure of this embodiment, the first constituent region 21 is p + By connecting to mold layer 12, the configuration eliminates any floating regions.
[0022] Furthermore, the first to third adjustment regions 31 to 33 are regions where the injection concentration of p-type impurities is likely to change due to mask misalignment in the manufacturing method described later. For this reason, the p-type impurity concentration in the first adjustment region 31 may be higher than the p-type impurity concentrations in the adjacent second and fourth component regions 22 and 24, or lower than the p-type impurity concentrations in the second and fourth component regions 24, or it may fall between the p-type impurity concentrations in the second component region 22 and the fourth component region 24. Similarly, the p-type impurity concentration in the second adjustment region 32 may be higher than the p-type impurity concentrations in the adjacent fourth and fifth component regions 24 and 25, or lower than the p-type impurity concentrations in the fourth and fifth component regions 24, or it may fall between the p-type impurity concentrations in the fourth component region 24 and the fifth component region 25. The p-type impurity concentration in the third adjustment region 33 may be higher than the p-type impurity concentrations in the adjacent sixth and seventh constituent regions 26 and 27, or lower than the p-type impurity concentrations in the sixth and seventh constituent regions 26 and 27, or it may fall between the p-type impurity concentrations in the sixth constituent region 26 and the seventh constituent region 27. Furthermore, the first to third adjustment regions 31 to 33 are regions in which the nitrogen (N) injection concentration is lower than that in the first to seventh constituent regions 21 to 27 in the manufacturing method described later.
[0023] Here, the relationship between the impurity concentrations of the first to seventh constituent regions 21 to 27 and the first to third adjustment regions 31 to 33 will be explained with reference to Figures 2 to 5. In the following, it is assumed that the second and third constituent regions 22 and 23 and the first adjustment region 31 are formed from one surface 10a of the semiconductor substrate 10 to a depth d, as shown in Figure 2. Figures 3 to 5 show the concentrations of Mg (magnesium) ion-implanted as p-type impurities. In Figures 3 to 5, the implantation concentration at the time of implantation is shown before the impurities are ion-implanted and activated, and the impurity concentration after heat treatment is shown after the impurities have been activated. Furthermore, Figure 5 shows a state in which mask misalignment occurs in the manufacturing method described later, and the first adjustment region 31 contains a portion in which a large amount of Mg as a p-type impurity has been ion-implanted.
[0024] Furthermore, the following explanation will use Figures 3 and 4 as an example to illustrate the distribution of p-type impurity concentrations along the depth direction. However, the relationship between the distribution of p-type impurity concentrations in the depth direction between the first, third to seventh constituent regions 21, 23 to 27 and the second and third adjustment regions 32, 33 is similar to the relationship between the distribution of p-type impurity concentrations between the second constituent region 22 and the first adjustment region 31, although the peak concentrations of p-type impurity concentrations differ.
[0025] First, when nitrogen and p-type impurities are ion-implanted into a semiconductor substrate 10 made of GaN and then subjected to heat treatment, although the exact principle is not clear, it is known that the activation rate and diffusion method of the p-type impurities change depending on the nitrogen implantation concentration. Specifically, it is known that the higher the nitrogen implantation concentration, the higher the activation rate of the p-type impurities and the less likely they are to diffuse.
[0026] As described above, the first to third adjustment regions 31 to 33 are regions in which the nitrogen injection concentration is lower than that of the first to seventh constituent regions 21 to 27 in the manufacturing method described later. Therefore, as shown in Figures 3 and 4, after heat treatment, it can be confirmed that Mg as a p-type impurity is more diffused in the depth direction in the first adjustment region 31 than in the second constituent region 22. As described above, the relationship between the distribution of p-type impurity concentrations in the depth direction between the first and third to seventh constituent regions 21, 23 to 27 and the second and third adjustment regions 32, 33 is the same as the relationship between the distribution of p-type impurity concentrations in the depth direction between the second constituent region 22 and the first adjustment region 31. Therefore, after heat treatment, the first to third adjustment regions 31 to 33 are in a state where Mg as a p-type impurity is more diffused in the depth direction than in the first to seventh constituent regions 21 to 27.
[0027] The above describes the configuration of the GaN semiconductor device in this embodiment. Next, the manufacturing method of the multi-stage JTE structure in the GaN semiconductor device of this embodiment will be explained with reference to Figures 6A to 6E. Figures 6A to 6E show cross-sectional views of the outer peripheral region RO in Figure 1. In the following, the region where the first to seventh constituent regions 21 to 27 are planned to be located will be referred to as the first planned constituent region 210 to 270, and the region where the first to third adjustment regions 31 to 33 are planned to be located will be referred to as the first to third planned adjustment regions 310 to 330. Furthermore, as will be described later, the first to third planned adjustment regions 310 to 330 are regions where the p-type impurity implantation concentration is more likely to change than that of the first to seventh planned constituent regions 210 to 270.
[0028] First, a semiconductor substrate 10 made of GaN is prepared, as shown in Figure 6A. Then, an insulating film 13 is placed on one surface 10a of the semiconductor substrate 10. The insulating film 13 is used as a through-film, but it may not be placed at this step, but rather after the JTE structure has been formed. Alternatively, another through-film may be used instead of the insulating film 13.
[0029] Next, a first mask 110, made of resist or the like, is placed on one surface 10a of the semiconductor substrate 10 and patterned. Specifically, the first mask 110 is patterned so that the first to seventh planned configuration regions 210 to 270 are open and the first to third planned adjustment regions 310 to 330 are covered. Then, nitrogen is ion-implanted using the first mask 110. As a result, nitrogen is implanted into the first to seventh planned configuration regions 210 to 270, while nitrogen is not implanted into the first to third planned adjustment regions 310 to 330. In other words, the first to seventh planned configuration regions 210 to 270 have more nitrogen implanted than the first to third planned adjustment regions 310 to 330. After that, the first mask 110 is removed by ashing or the like. In this embodiment, nitrogen is ion-implanted in such a way that, when the process up to Figure 6D described later is performed, the nitrogen concentration is equal to or greater than the implantation concentration of p-type impurities in the first planned structural region 210, in order to facilitate the activation of p-type impurities implanted in the first to seventh planned structural regions 210 to 270 and to make them less likely to diffuse.
[0030] Next, as shown in Figure 6B, the second mask 120 is placed on one surface 10a of the semiconductor substrate 10 and patterned. Specifically, the second mask 120 is patterned so that the first to fourth planned configuration regions 210 to 240 and the first and second planned adjustment regions 310 and 320 are open, and the fifth to seventh planned configuration regions 250 to 270 and the third planned adjustment region 330 are covered. Then, Mg as a p-type impurity is ion-implanted using the second mask 120. At this time, the second planned adjustment region 320 is the part where the open end of the second mask 120 is located, and it is a region where the implanted Mg concentration is easily changed by displacement of the second mask 120. After that, the second mask 120 is removed by ashing or the like.
[0031] Next, as shown in Figure 6C, the third mask 130 is placed on one surface 10a of the semiconductor substrate 10 and patterned. Specifically, the third mask 130 is patterned so that the first, second, fifth, and sixth planned configuration regions 210, 220, 250, and 260 and the first and third planned adjustment regions 310 and 330 are opened, and the third, fourth, and seventh planned configuration regions 230, 240, and 270 and the second planned adjustment region 320 are covered. Then, Mg is ion-implanted using the third mask 130. At this time, the first to third planned adjustment regions 310 to 330 are the areas where the opening ends of the third mask 130 are located, and these are areas where the implanted Mg concentration is likely to change due to displacement of the third mask 130. In this embodiment, in the process shown in Figure 6C, half the dose of Mg to be ion-implanted in the process shown in Figure 6B is implanted. Subsequently, the third mask 130 is removed by ashing or other methods.
[0032] Next, as shown in Figure 6D, the fourth mask 140 is placed on one surface 10a of the semiconductor substrate 10 and patterned. Specifically, the fourth mask 140 is patterned so that the first, third, fifth, and seventh planned configuration regions 210, 230, 250, and 270 and the first to third planned adjustment regions 310 to 330 are opened, and the second, fourth, and sixth planned configuration regions 220, 240, and 260 are covered. Then, Mg is ion-implanted using the fourth mask 140. At this time, the first to third planned adjustment regions 310 to 330 are the areas where the opening ends of the fourth mask 140 are located, and these are areas where the Mg implantation concentration is likely to change due to displacement of the fourth mask 140. After that, the fourth mask 140 is removed by ashing or the like. In this embodiment, in the step shown in Figure 6D, a dose of Mg equivalent to 1 / 4 of the dose implanted in the step shown in Figure 6B is implanted. Also, in this embodiment, nitrogen is not ion-implanted into the first to third planned adjustment regions 310 to 330 in the step shown in Figure 6A. Therefore, it can be said that the implantation concentration of p-type impurities in the first to third planned adjustment regions 310 to 330 is higher than the implantation concentration of nitrogen that is ion-implanted.
[0033] Subsequently, as shown in Figure 6E, a heat treatment of approximately 1300-1500°C is performed to activate the p-type impurities, forming the first to seventh constituent regions 21-27 and the first to third adjustment regions 31-33. Here, as described above, the activation rate of p-type impurities (i.e., Mg in this embodiment) increases and they become less diffusive as the nitrogen injection concentration increases. In other words, the activation rate of p-type impurities decreases and they become more diffusive as the nitrogen injection concentration decreases.
[0034] Furthermore, in this embodiment, nitrogen is not injected into the first to third planned adjustment regions 310 to 330 in the process shown in Figure 6A. Therefore, in the first to third adjustment regions 31 to 33, where the injection concentration of Mg as a p-type impurity is easily changed due to mask shift, the activation rate of Mg becomes lower and it diffuses more easily, thus suppressing a disproportionately high concentration of p-type impurities compared to the first to seventh constituent regions 21 to 27. In other words, even if the injection concentration of Mg increases due to mask shift in the first to third adjustment regions 31 to 33, a disproportionately high concentration of p-type impurities compared to the first to seventh constituent regions 21 to 27 is suppressed.
[0035] In this embodiment, as described above, in the step shown in Figure 6C, half the dose of Mg implanted in the step shown in Figure 6B is implanted, and in the step shown in Figure 6D, one-quarter the dose of Mg implanted in the step shown in Figure 6B is implanted. Therefore, using the p-type impurity concentration of the seventh constituent region 27 as a reference, the p-type impurity concentration of the sixth constituent region 26 is twice that of the seventh constituent region 27, the p-type impurity concentration of the fifth constituent region 25 is three times that of the seventh constituent region 27, and the p-type impurity concentration of the fourth constituent region 24 is four times that of the seventh constituent region 27. The p-type impurity concentration in the third constituent region 23 is five times that of the seventh constituent region 27, the p-type impurity concentration in the second constituent region 22 is six times that of the seventh constituent region 27, and the p-type impurity concentration in the first constituent region 21 is seven times that of the seventh constituent region 27. Therefore, a multi-stage JTE structure is formed, comprising seven p-type regions with different impurity concentrations.
[0036] And, although not specifically shown in the diagram, for example, after the process in Figure 6E is completed, p connects to the first constituent region 21. + By forming the mold layer 12, a diode element is formed in the cell region RS. In the multi-stage JTE structure of this embodiment, the first to seventh constituent regions 21 to 27 and the first to third adjustment regions 31 to 33 are all p-type, and no n-type regions are placed in between, so that any part does not become floating.
[0037] According to the embodiment described above, the multi-stage JTE structure in the GaN semiconductor device is composed of first to seventh constituent regions 21 to 27 and first to third adjustment regions 31 to 33. The first to seventh constituent regions 21 to 27 and the first to third adjustment regions 31 to 33 are formed to be in contact with adjacent regions in the planar direction, and between adjacent regions n - The mold layer 11 is not present. Therefore, it is possible to suppress the floating state of the p-type regions that constitute the multi-stage JTE structure.
[0038] Furthermore, in this embodiment, when manufacturing a GaN semiconductor device, the nitrogen implantation concentration in the first to third planned adjustment regions 310 to 330, where the p-type impurity implantation concentration is easily affected by mask misalignment, is set to be lower than that in the first to seventh planned configuration regions 210 to 270. Therefore, when heat treatment is performed to construct the first to seventh configuration regions 21 to 27 and the first to third adjustment regions 31 to 33, the p-type impurity concentration in the first to third adjustment regions 31 to 33 is suppressed to be significantly higher than that in the first to seventh configuration regions 21 to 27. In other words, the formation of regions with significantly higher p-type impurity concentrations within the multi-stage JTE structure is suppressed. Consequently, electric field concentration in the outer peripheral region RO can be suppressed.
[0039] (1) In this embodiment, the nitrogen injection concentration in the first to third planned adjustment regions 310 to 330 is lower than the p-type impurity injection concentration. Therefore, when the first to third adjustment regions 31 to 33 are formed, Mg becomes less likely to be activated and more likely to diffuse. Consequently, it is possible to suppress the p-type impurity concentration in the first to third adjustment regions 31 to 33 from becoming significantly higher than the p-type impurity concentration in the first to seventh constituent regions 21 to 27.
[0040] (2) In this embodiment, when ion implanting nitrogen, a first mask 110 is used, in which the first to seventh planned structural regions 210 to 270 are open and the first to third planned adjustment regions 310 to 330 are covered. Therefore, nitrogen can be ion implanted into the first to seventh planned structural regions 210 to 270 in a single step.
[0041] (Second Embodiment) A second embodiment will now be described. This embodiment differs from the first embodiment in that the manufacturing method is modified. Other aspects are the same as in the first embodiment, so a detailed explanation will be omitted here.
[0042] In the manufacturing method of the GaN semiconductor device of this embodiment, as shown in Figure 7A, a semiconductor substrate 10 made of GaN is prepared, and then a first mask 150 is placed on one surface 10a of the semiconductor substrate 10 and patterned. Specifically, the first mask 150 is patterned so that the first, third, fifth, and seventh planned configuration regions 210, 230, 250, and 270 are opened, and the second, fourth, and sixth planned configuration regions 220, 240, and 260 and the first to third planned adjustment regions 310 to 330 are covered. In this embodiment, a slit 151 is formed in the portion that covers the first to third planned adjustment regions 310 to 330. Then, using the first mask 150, nitrogen is ion-implanted from a direction inclined with respect to the normal direction (hereinafter simply referred to as the normal direction) to one surface 10a of the semiconductor substrate 10. As a result, nitrogen is injected into the first, third, fifth, and seventh planned structural regions 210, 230, 250, and 270. In addition, although slits 151 are formed in the first mask 150 that covers the first to third planned adjustment regions 310 to 330, the injection of nitrogen ions from a direction inclined with respect to the normal direction is suppressed.
[0043] Next, as shown in Figure 7B, the first mask 150 is used as is, and Mg is ion-implanted as a p-type impurity from the direction normal to one surface 10a of the semiconductor substrate 10. As a result, Mg is ion-implanted into the first, third, fifth, and seventh planned configuration regions 210, 230, 250, and 270. In addition, Mg is ion-implanted into the first to third planned adjustment regions 310 to 330 through the slit 151. Note that in the first to third planned adjustment regions 310 to 330, the Mg implantation concentration is lower than in the first to fourth configuration regions 21 to 24 because Mg is ion-implanted through the slit 151. Furthermore, the first to third planned adjustment regions 310 to 330 are the areas where the opening end of the first mask 150 is located, and the Mg implantation concentration in these regions is easily affected by displacement of the first mask 150. After that, the first mask 150 is removed by ashing or the like.
[0044] Next, as shown in Figure 7C, the second mask 160 is placed on one surface 10a of the semiconductor substrate 10 and patterned. Specifically, the second mask 160 is patterned so that the first, second, fifth, and sixth planned configuration regions 210, 220, 250, and 260 are opened, and the third, fourth, and seventh planned configuration regions 230, 240, and 270 and the first to third planned adjustment regions 310 to 330 are covered. In this embodiment, a slit 161 is formed in the portion that covers the first to third planned adjustment regions 310 to 330. Then, nitrogen is ion-implanted using the second mask 160 from a direction inclined with respect to the normal direction. As a result, nitrogen is implanted into the first, second, fifth, and sixth planned configuration regions 210, 220, 250, and 260. Furthermore, in the first to third planned adjustment regions 310 to 330, slits 161 are formed in the second mask 160 that covers the first to third planned adjustment regions 310 to 330. However, since nitrogen is ion-implanted from a direction inclined with respect to the normal direction, the implantation of large amounts of nitrogen is suppressed.
[0045] Next, as shown in Figure 7D, the second mask 160 is used as is to ion implant Mg from the direction normal to one surface 10a of the semiconductor substrate 10. As a result, Mg is ion-implanted into the first, second, fifth, and sixth planned configuration regions 210, 220, 250, and 260. In addition, Mg is ion-implanted into the first to third planned adjustment regions 310 to 330 through the slit 161. Note that in the first to third planned adjustment regions 310 to 330, the Mg implantation concentration is lower than in the first, second, fifth, and sixth planned configuration regions 210, 220, 250, and 260 because Mg is ion-implanted through the slit 161. Furthermore, the first to third planned adjustment regions 310 to 330 are the areas where the opening end of the second mask 160 is located, and the Mg implantation concentration in these regions is easily affected by the displacement of the second mask 160. In this embodiment, in the step shown in Figure 7D, twice the amount of Mg used for ion implantation in the step shown in Figure 7B is injected. Subsequently, the second mask 160 is removed by ashing or the like.
[0046] Next, as shown in Figure 7E, the third mask 170 is placed on one surface 10a of the semiconductor substrate 10 and patterned. Specifically, the third mask 170 is patterned so that the first to fourth planned configuration regions 210 to 240 are opened and the fifth to seventh planned configuration regions 250 to 270 and the first to third planned adjustment regions 310 to 330 are covered. In this embodiment, slits 171 are formed in the portion that covers the first and second planned adjustment regions 310 and 320. Then, nitrogen is ion-implanted using the third mask 170 from a direction inclined with respect to the normal direction body. This implants nitrogen into the first to fourth planned configuration regions 210 to 240. Furthermore, in the first and second planned adjustment regions 310 and 320, slits 171 are formed in the third mask 170 that covers the first and second planned adjustment regions 310 and 320. However, since nitrogen is ion-implanted from a direction inclined with respect to the normal direction, the implantation of large amounts of nitrogen is suppressed.
[0047] Next, as shown in Figure 7F, the third mask 170 is used as is, and Mg is ion-implanted from the direction normal to one surface 10a of the semiconductor substrate 10. This ion-implants Mg into the first to fourth planned configuration regions 210 to 240. In addition, Mg is ion-implanted into the first and second planned adjustment regions 310 and 320 through the slit 171. Note that in the first and second planned adjustment regions 310 and 320, Mg is ion-implanted through the slit 171, so the Mg implantation concentration in this step is lower than in the first to fourth planned configuration regions 210 to 240. Furthermore, the first and second planned adjustment regions 310 and 320 are the areas where the opening end of the third mask 170 is located, and the Mg implantation concentration in these regions is easily affected by the displacement of the third mask 170. In this embodiment, in the step shown in Figure 7F, a dose of Mg four times the dose of Mg ion-implanted in the step shown in Figure 7B is implanted. Subsequently, the third mask 170 is removed by ashing or other methods.
[0048] Subsequently, although not specifically shown in the diagram, the first to seventh constituent regions 21 to 27 and the first to third adjustment regions 31 to 33 are formed by performing a heat treatment of approximately 1300 to 1500°C, similar to the first embodiment described above, to activate the p-type impurities.
[0049] According to the embodiment described above, the first to seventh constituent regions 21 to 27 and the first to third adjustment regions 31 to 33 are formed to be in contact with adjacent regions in the planar direction, and between adjacent regions n - The mold layer 11 is not present. Therefore, the same effects as in the first embodiment can be obtained.
[0050] (1) In this embodiment, by changing the direction of ion implantation, the first to third masks 150 to 170 used for ion implantation of nitrogen and the first to third masks 150 to 170 used for ion implantation of p-type impurities are shared. Therefore, the number of masks can be reduced.
[0051] (Third embodiment) A third embodiment will now be described. This embodiment adds the first to third lower layers to the first to third adjustment regions 31 to 33 at a deeper position than the first to third adjustment regions 31 to 33 compared to the first embodiment. Other aspects are the same as in the first embodiment, so a detailed explanation will be omitted here.
[0052] As shown in Figure 8, the GaN semiconductor device of this embodiment has first to third lower layer regions 41 to 43 located below the first to third adjustment regions 31 to 33, respectively, which are connected to the first to third adjustment regions 31 to 33 and have a lower p-type impurity concentration than the first to third adjustment regions 31 to 33. Furthermore, the first to third lower layer regions 41 to 43 are located at a deeper position than the first to seventh constituent regions 21 to 27.
[0053] Such a GaN semiconductor device is manufactured in the same manner as the first embodiment described above. In this case, as described above, the nitrogen injection concentration in the first to third adjustment regions 31 to 33 is lower compared to the first to seventh constituent regions 21 to 27, and when heat treatment is performed, p-type impurities diffuse more easily in the depth direction. For this reason, the dose amount (i.e., injection concentration) of p-type impurities injected into the first to third adjustment regions 31 to 33, and the nitrogen injection concentration into which the p-type impurities are injected are important. -By adjusting the n-type impurity concentration in the mold layer 11, the first to third lower layer regions 41 to 43 are formed by p-type impurities that constitute the first to third adjustment regions 31 to 33.
[0054] According to the embodiment described above, the first to seventh constituent regions 21 to 27 and the first to third adjustment regions 31 to 33 are formed to be in contact with adjacent regions in the planar direction, and between adjacent regions n - The mold layer 11 is not present. Therefore, the same effects as in the first embodiment can be obtained.
[0055] (1) In this embodiment, the first to third lower layers 41 to 43, which have a lower p-type impurity concentration than the first to third adjustment regions 31 to 33, are located below the first to third adjustment regions 31 to 33. This makes it easier to further smooth the electric field distribution in the outer region RO.
[0056] (Other embodiments) This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and idea of this disclosure.
[0057] In each of the above embodiments, examples of constructing a multi-stage JTE structure including the first to seventh constituent regions 21 to 27 and the first to third adjustment regions 31 to 33 have been described, but the number and location of these can be changed as appropriate. In addition, the number of masks used when manufacturing each of the above embodiments, the position where the openings in the masks are formed, the dose amount of p-type impurities, etc., can be changed as appropriate.
[0058] Furthermore, in each of the above embodiments, examples were described in which a diode element as a semiconductor element is formed in the cell region RS. However, the semiconductor element formed in the cell region RS may be a MOSFET, IGBT element, or the like, instead of a diode element.
[0059] In each of the above embodiments, the first constituent region 21 is p + Although an example of connection to the mold layer 12 has been described, the first constituent region 21 may also be electrically connected to, for example, an electrode or the like that is placed on one side 10a of the semiconductor substrate 10.
[0060] Furthermore, although Mg was used as an example of a p-type impurity in the above embodiments, the p-type impurity may also be Ca (calcium), Be (beryllium), Zn (zinc), etc.
[0061] Furthermore, the above embodiments can be combined. For example, the second embodiment may be combined with the third embodiment to provide the first to third lower layers 41 to 43. [Explanation of Symbols]
[0062] 10 Semiconductor substrates 10a one side 21~27 1st~7th component area 31~33 1st~3rd adjustment area RS cell area RS outer area
Claims
1. A gallium nitride semiconductor device having a multi-stage JTE structure, A semiconductor substrate (10) made of gallium nitride, having an n-type layer (11), a cell region (RS) on which a semiconductor element is formed, and an outer peripheral region (RO) surrounding the cell region, The semiconductor substrate comprises, on one side (10a) of the outer peripheral region, a plurality of constituent regions (21 to 27) arranged along the plane direction of the semiconductor substrate, wherein the concentration of p-type impurities is progressively lower from the cell region side toward the opposite side of the cell region, Between adjacent constituent regions in the aforementioned planar direction, there is a portion where p-shaped adjustment regions (31 to 33) are arranged. The aforementioned constituent region and the aforementioned adjustment region are in contact with adjacent regions in the plane direction, The multi-stage JTE structure is configured to include the configuration region and the adjustment region, A gallium nitride semiconductor device wherein, in the depth direction of the semiconductor substrate, the distribution of p-type impurity concentration in the portion including the adjustment region is wider in the depth direction than the distribution of p-type impurity concentration in the portion including the constituent region.
2. The gallium nitride semiconductor device according to claim 1, having a lower layer region (41-43) connected to the adjustment region in the depth direction of the semiconductor substrate, wherein the p-type impurity concentration is lower than that of the adjustment region.
3. A semiconductor substrate (10) made of gallium nitride, having an n-type layer (11), a cell region (RS) on which a semiconductor element is formed, and an outer peripheral region (RO) surrounding the cell region, The semiconductor substrate comprises, on one side (10a) of the outer peripheral region, a plurality of constituent regions (21 to 27) arranged along the plane direction of the semiconductor substrate, wherein the concentration of p-type impurities is progressively lower from the cell region side toward the opposite side of the cell region, Between adjacent constituent regions in the aforementioned planar direction, there is a portion where p-shaped adjustment regions (31-33) are arranged. The aforementioned constituent region and the aforementioned adjustment region are in contact with adjacent regions in the plane direction, The multi-stage JTE structure is configured to include the aforementioned configuration region and the aforementioned adjustment region, A method for manufacturing a gallium nitride semiconductor device, wherein, in the depth direction of the semiconductor substrate, the distribution of p-type impurity concentration in the portion including the adjustment region is wider in the depth direction than the distribution of p-type impurity concentration in the portion including the constituent region, The region in which the above-mentioned constituent region is formed is designated as the planned constituent region (210-270), and the region in which the above-mentioned adjustment region is formed is designated as the planned adjustment region (310-330), and the semiconductor substrate including the planned constituent region and the planned adjustment region is prepared. Using a mask (110, 150-170) with an opening in the aforementioned planned configuration region, nitrogen is ion-implanted such that the injection concentration in the aforementioned planned configuration region is higher than that in the aforementioned planned adjustment region. The process involves placing a mask (120-140, 150-170) on one surface of the semiconductor substrate, having an opening that exposes at least a portion of the planned configuration region, and then ion-implanting p-type impurities using the mask, repeating this process while changing the masks with different openings when placing them, so that the p-type impurities are ion-implanted in the planned configuration region so that the implantation concentration decreases sequentially from the cell region side toward the opposite side of the cell region, and also ion-implanting the p-type impurities into the planned adjustment region. By performing a heat treatment, the p-type impurities are activated, and the constituent region and the adjusted region are formed. A method for manufacturing a gallium nitride semiconductor device, wherein the aforementioned planned adjustment region is a region in which the implantation concentration of the p-type impurity is more likely to change than that of the aforementioned planned configuration region.
4. The method for manufacturing a gallium nitride semiconductor device according to claim 3, wherein the ion implantation of nitrogen is performed such that the implantation concentration of nitrogen is less than the implantation concentration of the p-type impurity that can be implanted in the planned adjustment region.
5. The method for manufacturing a gallium nitride semiconductor device according to claim 3 or 4, wherein the ion implantation of nitrogen is performed using a mask covering the planned adjustment region.
6. The nitrogen is ion-implanted using a mask (150-170) having slits (151-171) formed in the portion covering the planned adjustment area, and the nitrogen is ion-implanted from a direction inclined with respect to the normal direction to one surface of the semiconductor substrate. The method for manufacturing a gallium nitride semiconductor device according to claim 3 or 4, wherein the ion implantation of the p-type impurity is performed using the mask used when ion implanting the nitrogen, and the p-type impurity is ion implanted from the direction normal to one surface of the semiconductor substrate.
Citation Information
Patent Citations
High withstanding voltage semiconductor device
JP2016025300A