Semiconductor equipment

Abstract

To provide a semiconductor device that can minimize the fragmentation defects that occur during the cutting process. [Solution] The semiconductor device includes a chip region CHR1 and a scribe lane region SR1, the scribe lane region includes a substrate including a chip adjacent region NR1, a chip adjacent cross region OCR1 and a peripheral cross region ICR1, a passivation layer on the substrate, a first boundary 101 between the chip adjacent cross region and the peripheral cross region, a row trench RTH1 arranged in a direction intersecting the first boundary, located in a region other than the peripheral cross region and arranged within the passivation layer, and a second boundary 102 of the boundary between the chip adjacent cross region and the peripheral cross region that intersects the first boundary, and a row trench CTH1 arranged between the chip adjacent cross region and the boundary of the chip adjacent region in a direction intersecting the second boundary, located in a region other than the peripheral cross region and arranged within the passivation layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor devices.

[0002] (Cross-reference to related applications) This application claims priority based on 35 U.S.C.§ 119(a) to Korean Patent Application No. 10-2025-0018520, filed on February 13, 2025, the entire content of which is incorporated herein by reference.

Background Art

[0003] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing cost, semiconductor chips have been in the spotlight as an important element in the electronics industry. As the electronics industry has developed highly, semiconductor chips are becoming more and more highly integrated. As semiconductor chips become more highly integrated, the size of the chips is gradually decreasing, and the number of semiconductor chips formed on one wafer is increasing.

[0004] On the other hand, after being manufactured from one wafer, semiconductor chips are separated into individual semiconductor chips through a cutting process such as sawing or dicing. However, as semiconductor chips become more highly integrated, the difficulty of the process of cutting semiconductor chips is increasing.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Embodiments of the present disclosure can provide a semiconductor device capable of minimizing a breaking defect occurring during a cutting process.

[0006] The problems of the embodiments of the present disclosure are not limited to the problems mentioned herein, and further problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0007] Embodiments of the present disclosure can provide a semiconductor device comprising a chip region and a scribe lane region, wherein the scribe lane region includes a substrate including a chip adjacent region, a chip adjacent cross region adjacent to the chip adjacent region, and a peripheral cross region adjacent to the chip adjacent cross region and separated from the chip adjacent region; a passivation layer on the substrate; a first boundary between the chip adjacent cross region and the peripheral cross region; a row trench positioned between the chip adjacent cross region and the boundary of the chip adjacent region in a direction intersecting the first boundary, located in a region other than the peripheral cross region, and positioned within the passivation layer; a second boundary between the chip adjacent cross region and the peripheral cross region that intersects the first boundary; and a column trench positioned between the chip adjacent cross region and the boundary of the chip adjacent region in a direction intersecting the second boundary, located in a region other than the peripheral cross region, and positioned within the passivation layer.

[0008] Embodiments of the present disclosure provide a semiconductor device comprising a chip region and a scribe lane region, wherein the scribe lane region includes a chip adjacent region, a chip adjacent cross region adjacent to the chip adjacent region, and a peripheral cross region adjacent to the chip adjacent cross region and separated from the chip adjacent region; row trenches located in the chip adjacent cross region in a direction intersecting the first boundary and in a region other than the peripheral cross region; and column trenches located in the chip adjacent cross region in a direction intersecting the second boundary intersecting the first boundary and in a region other than the peripheral cross region, wherein each of the row trenches and each of the column trenches do not intersect each other. [Effects of the Invention]

[0009] According to embodiments of this disclosure, it is possible to provide a semiconductor device that can minimize fragmentation defects that occur during the cutting process.

[0010] The effects of the embodiments of this disclosure are not limited to those described above, and any further effects not mentioned will be clearly understood by those skilled in the art from the claims. [Brief explanation of the drawing]

[0011] The contents of this disclosure will be better understood from the detailed description and accompanying drawings provided below. The detailed description and accompanying drawings are provided for illustrative purposes only and do not limit the contents of this disclosure.

[0012] [Figure 1] This figure shows an example of a planar structure of a semiconductor device according to an embodiment of the present disclosure.

[0013] [Figure 2] This figure shows an example of the cross-sectional structure of part II' in Figure 1.

[0014] [Figure 3] This figure shows an example of the cross-sectional structure of section II-II' in Figure 1.

[0015] [Figure 4] This figure shows another example of the cross-sectional structure of part II' in Figure 1. [Figure 5] This figure shows another example of the cross-sectional structure of part II' in Figure 1. [Figure 6] This figure shows another example of the cross-sectional structure of part II' in Figure 1.

[0016] [Figure 7] This figure shows another example of a planar structure of a semiconductor device according to an embodiment of the present disclosure.

[0017] [Figure 8] This figure shows an example of the cross-sectional structure of section III-III' in Figure 7.

[0018] [Figure 9] This figure shows another example of a planar structure of a semiconductor device according to an embodiment of the present disclosure.

[0019] [Figure 10] It is a diagram showing an example of the cross-sectional structure of the IV-IV' portion of FIG. 9.

Embodiments for Carrying Out the Invention

[0020] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to exemplary drawings. When adding reference numerals to the components of each drawing, for the same components, even if they are shown on other drawings, they may be given the same reference numerals as much as possible. In addition, when explaining the present invention, if it is determined that a specific description of related known configurations or functions may obscure the gist of the present disclosure, the detailed description thereof will be omitted. When terms such as "including", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it can include the case of including a plurality unless there are particularly explicit descriptions.

[0021] Also, when explaining the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. can be used. These terms are only for distinguishing the components from other components, and the essence, order, sequence, number, etc. of the components are not limited by these terms.

[0022] In the description of the positional relationship of components, when it is described that two or more components are "connected", "coupled", or "joined", it should be understood that two or more components can be directly "connected", "coupled", or "joined", but it is also possible that two or more components and other components are further "interposed" and "connected", "coupled", or "joined". Here, the other components may be included in one or more of the two or more components that are "connected", "coupled", or "joined" to each other.

[0023] In descriptions of temporal relationships concerning constituent elements, operating methods, or manufacturing methods, when temporal order or sequential relationships are described using phrases such as "after," "following," "next," or "before," unless "immediately" or "directly" is used, this can include cases that are not continuous.

[0024] On the other hand, if numerical values ​​or corresponding information (e.g., levels) relating to components are mentioned, even without further explicit mention, these numerical values ​​or corresponding information may be interpreted as including a range of errors that can occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0025] Various embodiments of this disclosure will be described in detail below with reference to the attached drawings.

[0026] Figure 1 shows an example of a planar structure of a semiconductor device according to an embodiment of the present disclosure.

[0027] Referring to Figure 1, the first chip region CHR1, the second chip region CHR2, the third chip region CHR3, and the fourth chip region CHR4 are arranged spaced apart from each other. The first chip region CHR1, the second chip region CHR2, the third chip region CHR3, and the fourth chip region CHR4 can each represent regions included in different semiconductor devices. For example, a semiconductor device according to an embodiment of the present disclosure may include the first chip region CHR1. Figure 1 may be a diagram showing a semiconductor device after it has been formed on a wafer and before it is separated into individual chips.

[0028] The first scribe lane region SR1 is located around the first chip region CHR1. The first scribe lane region SR1 can surround the first chip region CHR1. Similarly, the second scribe lane region SR2, the third scribe lane region SR3, and the fourth scribe lane region SR4 are located around the second chip region CHR2, the third chip region CHR3, and the fourth chip region CHR4, respectively, and can surround the second chip region CHR2, the third chip region CHR3, and the fourth chip region CHR4. The first scribe lane region SR1, the second scribe lane region SR2, the third scribe lane region SR3, and the fourth scribe lane region SR4 may be regions from which a single scribe lane region has been separated by a cutting process (e.g., dicing or sawing) that separates the semiconductor chip.

[0029] The first chip region CHR1 and the first scribe lane region SR1 may be regions included in a single semiconductor device. For example, a semiconductor device according to an embodiment of the present disclosure may include the first chip region CHR1 and the first scribe lane region SR1. Figure 1 shows only a portion of the first chip region CHR1 and the first scribe lane region SR1. Similarly, the second chip region CHR2 and the second scribe lane region SR2, the third chip region CHR3 and the third scribe lane region SR3, and the fourth chip region CHR4 and the fourth scribe lane region SR4 may each be regions included in different semiconductor devices.

[0030] The first scribe lane region SR1 includes the first chip adjacency region NR1 and the first intersection region CR1. The first chip adjacency region NR1 can mean the region adjacent to the corner of the first chip region CHR1. The first intersection region CR1 can mean the region located around the first chip adjacency region NR1 and adjacent to the first chip adjacency region NR1.

[0031] Similarly, the second scribe lane region SR2, the third scribe lane region SR3, and the fourth scribe lane region SR4 each include the second chip adjacent region NR2 and the second intersection region CR2, the third chip adjacent region NR3 and the third intersection region CR3, and the fourth chip adjacent region NR4 and the fourth intersection region CR4, respectively.

[0032] The first cross region CR1 includes the first chip adjacent cross region OCR1 and the first peripheral cross region ICR1. The first chip adjacent cross region OCR1 can mean the region outside the first chip adjacent cross region NR1 that is adjacent to the first chip adjacent cross region NR1. The first chip adjacent cross region OCR1 may not overlap with the first chip region CHR1.

[0033] The first peripheral crossing region ICR1 can mean a region adjacent to the first chip adjacent crossing region OCR1 and separated from the first chip adjacent region NR1. In one embodiment, the first peripheral crossing region ICR1 may be a region including the intersection of the boundary line between the first chip adjacent region NR1 and the third chip adjacent region NR3, and the boundary line between the first chip adjacent region NR1 and the second chip adjacent region NR2. In one embodiment, the first peripheral crossing region ICR1 may be a region including the intersection of cutting lines that separate semiconductor chips formed on a wafer. For example, the point where a cutting line separating a semiconductor device including the first chip region CHR1 from a semiconductor device including the third chip region CHR3 intersects with another cutting line separating a semiconductor device including the first chip region CHR1 from a semiconductor device including the third chip region CHR3 may be included within the first peripheral crossing region ICR1.

[0034] Similarly, the second cross region CR2, the third cross region CR3, and the fourth cross region CR4 each include the second chip-adjacent cross region OCR2 and the second peripheral cross region ICR2, the third chip-adjacent cross region OCR3 and the third peripheral cross region ICR3, and the fourth chip-adjacent cross region OCR4 and the fourth peripheral cross region ICR4, respectively.

[0035] The first scribe lane region SR1 contains the first column trench CTH1, the first row trench RTH1, the first chip-adjacent column trench NCTH1, and the first chip-adjacent row trench NRTH1. The second scribe lane region SR2 contains the second column trench CTH2, the second row trench RTH2, the second chip-adjacent column trench NCTH2, and the second chip-adjacent row trench NRTH2. The third scribe lane region SR3 contains the third column trench CTH3, the third row trench RTH3, the third chip-adjacent column trench NCTH3, and the third chip-adjacent row trench NRTH3. The fourth scribe lane region SR4 contains the fourth column trench CTH4, the fourth row trench RTH4, the fourth chip-adjacent column trench NCTH4, and the fourth chip-adjacent row trench NRTH4.

[0036] The first column trench CTH1 may be substantially identical to the second column trenches CTH2 to the fourth column trenches CTH4. The first row trench RTH1 may be substantially identical to the second row trenches RTH2 to the fourth row trenches RTH4. The first chip-adjacent column trench NCTH1 may be substantially identical to the second chip-adjacent column trenches NCTH2 to the fourth chip-adjacent column trenches NCTH4. The first chip-adjacent row trench NRTH1 may be substantially identical to the second chip-adjacent row trenches NRTH2 to the fourth chip-adjacent row trenches NRTH4. In the following explanation, for the sake of clarity, we will focus on describing the configuration included in the first scribe lane region SR1.

[0037] The first chip adjacent region NR1 may contain at least one first chip adjacent column trench NCTH1 and at least one first chip adjacent row trench NRTH1. The first chip adjacent column trench NCTH1 may be located in the first chip adjacent region NR1 between the first chip region CHR1 and the second chip region CHR2. The first chip adjacent column trench NCTH1 may be located in a direction intersecting the second boundary 102. The first chip adjacent column trenches NCTH1 may be spaced apart from each other in a direction intersecting the first boundary 101. In this specification, the direction intersecting the first boundary 101 may be referred to as the row direction. The direction intersecting the second boundary 102 may be referred to as the column direction. The first boundary 101 and the second boundary 102 may mean two intersecting boundaries of the first chip adjacent intersection region OCR1 and the first peripheral intersection region ICR1.

[0038] The first chip adjacent row trench NRTH1 may be located in the first chip adjacent region NR1 between the first chip region CHR1 and the third chip region CHR3. The first chip adjacent row trench NRTH1 may be located in the row direction. The first chip adjacent row trenches NRTH1 may be spaced apart from each other in the column direction. The number of the first chip adjacent row trenches NRTH1 and the first chip adjacent column trenches NCTH1 is not limited to the number shown in Figure 1.

[0039] The first chip adjacent cross region OCR1 may contain at least one first column trench CTH1 and at least one first row trench RTH1. In one embodiment, the first column trench CTH1 and the first row trench RTH1 may be located in the first chip adjacent cross region OCR1 but not in the first peripheral cross region ICR1. That is, the first column trench CTH1 may be located in a region other than the first peripheral cross region ICR1. Similarly, the first row trench RTH1 may be located in a region other than the first peripheral cross region ICR1.

[0040] The first column trenches CTH1 may be arranged in the column direction. The first column trenches CTH1 may be spaced apart from each other in the row direction. The first row trenches RTH1 may be arranged in the row direction. The first row trenches RTH1 may be spaced apart from each other in the column direction. The number of first row trenches RTH1 and first column trenches CTH1 is not limited to the number shown in Figure 1.

[0041] The first row trench RTH1 can be located between the boundary between the first chip adjacent cross region OCR1 and the first chip adjacent region NR1 and the first boundary 101 between the first chip adjacent cross region OCR1 and the first peripheral cross region ICR1. In one embodiment, the first row trench RTH1 can be located even closer to the first chip adjacent region NR1 in the row direction than the first boundary 101.

[0042] The first column trench CTH1 can be located between the boundary between the first chip adjacent cross region OCR1 and the first chip adjacent region NR1, and the second boundary 102 between the first chip adjacent cross region OCR1 and the first peripheral cross region ICR1. In one embodiment, the first column trench CTH1 can be located even closer to the first chip adjacent region NR1 in the column direction than the second boundary 102.

[0043] In one embodiment, each of the first row trenches RTH1 and each of the first column trenches CTH1 may not intersect with each other. In one embodiment, each of the first row trenches RTH1 and each of the first column trenches CTH1 may not overlap with each other.

[0044] In one embodiment, each of the first row trenches RTH1 may be spaced apart from the first chip-adjacent row trenches NRTH1. Each of the first column trenches CTH1 may be spaced apart from the first chip-adjacent column trenches NCTH1.

[0045] Figure 2 shows an example of the cross-sectional structure of part II' of Figure 1. Figure 2 may show the semiconductor device after it has been formed on a single wafer and before it is separated into individual chips. The semiconductor device shown in Figure 2 can be divided based on the boundary between the first chip adjacent cross region OCR1 and the second chip adjacent cross region OCR2. Hereinafter, a semiconductor device that includes the first chip region CHR1 will be referred to as the first semiconductor device, and a semiconductor device that includes the second chip region CHR2 will be referred to as the second semiconductor device.

[0046] Referring to Figure 2, the first semiconductor device may include a first substrate 200, a first insulating layer 201, a first guard ring GR1, a first interlayer insulating layer 204, a second insulating layer 211, a second interlayer insulating layer 214, a third insulating layer 221, a third interlayer insulating layer 224, a fourth insulating layer 231, a first passivation layer 240, a first dummy pattern 213a, a first dummy contact 222a, a second dummy pattern 223a, a second dummy contact 232a, a third dummy pattern 233a, and a first column trench CTH1. The first guard ring GR1 may include a first contact 202, a first wiring 203, a second contact 212, a second wiring 213, a third contact 222, a third wiring 223, a fourth contact 232, and a fourth wiring 233. The first passivation layer 240 may include a first lower passivation layer 241 and a first upper passivation layer 242.

[0047] Referring to Figures 1 and 2, the first substrate 200 may include a first chip region CHR1 and a first scribedane region SR1. For example, as shown in Figure 2, the first substrate 200 may include a first chip adjacent cross region OCR1 of the first chip region CHR1 and the first scribedane region SR1. The first substrate 200 may include a semiconductor substrate such as a silicon wafer or an SOI (Silicon On Insulator) wafer. The first substrate 200 may include a III-V semiconductor substrate, such as a compound semiconductor substrate such as GaAs. The first substrate 200 may include single-crystal silicon, polysilicon, amorphous silicon, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof.

[0048] A first insulating layer 201 and the first contacts 202 and first wiring 203 of the first guard ring GR1 are arranged on the first substrate 200. The first guard ring GR1 may be arranged within the first chip region CHR1. The first insulating layer 201 may include silicon oxide, silicon nitride, silicon oxynitride, low-K dielectrics, high-K dielectrics, or a combination thereof. In one embodiment, the first insulating layer 201 may include an oxide such as TEOS (Tetraethyl Orthosilicate). The first contacts 202 and the first wiring 203 may include conductive materials such as metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof. The first contact 202 and the first wiring 203 may include tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), aluminum (Al), copper (Cu), tantalum (Ta), tantalum nitride (TaN), gold (Au), or a combination thereof.

[0049] A first interlayer insulating layer 204 is placed on the first wiring 203. The first interlayer insulating layer 204 may include silicon oxide, silicon nitride, silicon oxynitride, low-K dielectrics, high-K dielectrics, or a combination thereof. In one embodiment, the first interlayer insulating layer 204 may include silicon nitride.

[0050] A second insulating layer 211 is placed on the first interlayer insulating layer 204. The second contact 212 and second wiring 213 of the first guard ring GR1 are placed within the second insulating layer 211. The second contact 212 may be connected to the first wiring 203 by penetrating the second insulating layer 211 and the first interlayer insulating layer 204. The second insulating layer 211, the second contact 212, and the second wiring 213 may each contain the same material as the first insulating layer 201, the first contact 202, and the first wiring 203.

[0051] In the first chip adjacent crossover region OCR1, a first dummy pattern 213a is placed within the second insulating layer 211. The first dummy pattern 213a may contain the same material as the second wiring 213. A second interlayer insulating layer 214 is placed on the first dummy pattern 213a, the second wiring 213, and the second insulating layer 211. The second interlayer insulating layer 214 may contain the same material as the first interlayer insulating layer 204.

[0052] A third insulating layer 221 is placed on the second interlayer insulating layer 214. The third contact 222 and the third wiring 223 of the first guard ring GR1 are placed within the third insulating layer 221. The third contact 222 may be connected to the second wiring 213 by penetrating the third insulating layer 221 and the second interlayer insulating layer 214. The third insulating layer 221, the third contact 222, and the third wiring 223 may each contain the same material as the first insulating layer 201, the first contact 202, and the first wiring 203.

[0053] In the first chip adjacent cross region OCR1, a first dummy contact 222a and a second dummy pattern 223a are arranged within the third insulating layer 221. The first dummy contact 222a may be connected to the first dummy pattern 213a, and the second dummy pattern 223a may be connected to the first dummy contact 222a. The first dummy contact 222a may contain the same material as the third contact 222, and the second dummy pattern 223a may contain the same material as the third wiring 223. A third interlayer insulating layer 224 is arranged on the second dummy pattern 223a, the third wiring 223, and the third insulating layer 221. The third interlayer insulating layer 224 may contain the same material as the first interlayer insulating layer 204.

[0054] A fourth insulating layer 231 is placed on the third interlayer insulating layer 224. The fourth contact 232 of the first guard ring GR1 is placed within the fourth insulating layer 231. The fourth contact 232 may be connected to the third wiring 223 by penetrating the fourth insulating layer 231 and the third interlayer insulating layer 224. The fourth insulating layer 231 and the fourth contact 232 may each contain the same material as the first insulating layer 201 and the first contact 202, respectively.

[0055] In the first chip adjacent crossover region OCR1, a second dummy contact 232a is positioned within the fourth insulating layer 231. The second dummy contact 232a may be connected to a second dummy pattern 223a. The second dummy contact 232a may contain the same material as the fourth contact 232.

[0056] A third dummy pattern 233a is placed on the second dummy contact 232a and the fourth insulating layer 231. The third dummy pattern 233a may be connected to the second dummy contact 232a. The third dummy pattern 233a may contain the same material as the fourth wiring 233.

[0057] A first lower passivation layer 241 is positioned on the third dummy pattern 233a, the fourth wiring 233, and the fourth insulating layer 231. The first lower passivation layer 241 can cover the top and side surfaces of the fourth wiring 233 and the third dummy pattern 233a. The first lower passivation layer 241 may include silicon oxide, silicon nitride, silicon oxynitride, low-K dielectrics, high-K dielectrics, or a combination thereof. In one embodiment, the first lower passivation layer 241 may include a high-density plasma (HDP) oxide.

[0058] A first upper passivation layer 242 is placed on the first lower passivation layer 241. In one embodiment, the first upper passivation layer 242 may include silicon nitride.

[0059] The first row trench CTH1 may be located within the first chip adjacent intersection region OCR1. The first row trench CTH1 may be located within the first passivation layer 240. In one embodiment, the first row trench CTH1 may be superimposed on the first dummy pattern 213a, the second dummy pattern 223a, and the third dummy pattern 233a. In one embodiment, the first row trench CTH1 may expose the upper surface of the third dummy pattern 233a. In one embodiment, the first row trench CTH1 may expose the side surface of the first passivation layer 240.

[0060] In the above description, the first column trench CTH1 was illustrated with reference to Figure 2, but the above description can also be applied to the first row trench RTH1 described with reference to Figure 1. For example, the first row trench RTH1 can be located within the first chip adjacent intersection region OCR1. The first row trench RTH1 can be placed within the first passivation layer 240 in Figure 2. The first dummy pattern 213a, the second dummy pattern 223a, and the third dummy pattern 233a in Figure 2 can also be placed beneath the first row trench RTH1. In one embodiment, the first row trench RTH1 can be superimposed on the first dummy pattern 213a, the second dummy pattern 223a, and the third dummy pattern 233a. In one embodiment, the top surface of the third dummy pattern 233a can be exposed by the first row trench RTH1.

[0061] The second semiconductor device may include a second substrate 300, a fifth insulating layer 301, a second guard ring GR2, a fourth interlayer insulating layer 304, a sixth insulating layer 311, a fifth interlayer insulating layer 314, a seventh insulating layer 321, a sixth interlayer insulating layer 324, an eighth insulating layer 331, a second passivation layer 340, a fourth dummy pattern 313a, a fourth dummy contact 322a, a fifth dummy pattern 323a, a fifth dummy contact 332a, a sixth dummy pattern 333a, and a second row trench CTH2. The second guard ring GR2 may include a fifth contact 302, a fifth wiring 303, a sixth contact 312, a sixth wiring 313, a seventh contact 322, a seventh wiring 323, an eighth contact 332, and an eighth wiring 333. The second passivation layer 340 may include a second lower passivation layer 341 and a second upper passivation layer 342. The configuration included in the second semiconductor device may be substantially identical to the configuration of the first semiconductor device described with reference to Figures 1 and 2.

[0062] Figure 3 shows an example of the cross-sectional structure of section II-II' in Figure 1.

[0063] Referring to Figure 3, the first dummy pattern 213a, the first dummy contact 222a, the second dummy pattern 223a, the second dummy contact 232a, and the third dummy pattern 233a may be located in the first chip adjacent region NR1. In one embodiment, the first dummy pattern 213a, the first dummy contact 222a, the second dummy pattern 223a, the second dummy contact 232a, and the third dummy pattern 233a may extend from the first chip adjacent intersection region OCR1 to the first chip adjacent region NR1.

[0064] The first semiconductor device may include a first adjacent chip trench NCTH1. The first adjacent chip trench NCTH1 is located in a first adjacent chip region NR1. The first adjacent chip trench NCTH1 may be located within a first passivation layer 240. In one embodiment, the first adjacent chip trench NCTH1 may be superimposed on a first dummy pattern 213a, a second dummy pattern 223a, and a third dummy pattern 233a.

[0065] In the above description, the first chip adjacent row trench NCTH1 was illustrated with reference to Figure 3, but the above description can also be applied to the first chip adjacent row trench NRTH1 described with reference to Figure 1. For example, the first chip adjacent row trench NRTH1 can be located within the first chip adjacent region NR1. The first chip adjacent row trench NRTH1 can be placed within the first passivation layer 240 in Figure 3. The first dummy pattern 213a, the second dummy pattern 223a, and the third dummy pattern 233a in Figure 3 can also be placed below the first chip adjacent row trench NRTH1. In one embodiment, the first chip adjacent row trench NRTH1 can be superimposed on the first dummy pattern 213a, the second dummy pattern 223a, and the third dummy pattern 233a.

[0066] Figures 4 to 6 show another example of the cross-sectional structure of part II' in Figure 1.

[0067] Referring to Figure 4, the first row trench CTH1 may be located within the first chip adjacent intersection region OCR1. The first row trench CTH1 may be located within the first passivation layer 240. In one embodiment, the first row trench CTH1 may not expose the upper surface of the third dummy pattern 233a. The lower surface of the first row trench CTH1 may be separated from the upper surface of the third dummy pattern 233a. For example, at least a portion of the first lower passivation layer 241 may remain between the lower surface of the first row trench CTH1 and the upper surface of the third dummy pattern 233a.

[0068] The above description can also be applied to the first row trench RTH1, as explained with reference to Figure 1. For example, the lower surface of the first row trench RTH1 can be separated from the upper surface of the third dummy pattern 233a.

[0069] Referring to Figure 5, a third dummy pattern 233a may be placed on the fourth insulating layer 231. The third dummy pattern 233a may be placed within the first chip adjacent cross region OCR1. The first row trench CTH1 may be superimposed on the third dummy pattern 233a. In one embodiment, the upper surface of the third dummy pattern 233a may be exposed by the first row trench CTH1.

[0070] Referring to Figure 6, the first semiconductor device may include a first element isolation layer 601. The first element isolation layer 601 may be located within the first substrate 200. In one embodiment, the upper surface of the first element isolation layer 601 may form a substantially the same plane as the upper surface of the first substrate 200. The first element isolation layer 601 may be formed using trench element isolation techniques such as Shallow Trench Isolation (STI). The first element isolation layer 601 may include silicon oxide, silicon nitride, silicon oxynitride, low-K dielectrics, high-K dielectrics, or a combination thereof.

[0071] In one embodiment, the wafer can be easily divided by arranging the first element isolation layer 601 within the first substrate 200. Therefore, defects in the semiconductor device due to improper division can be prevented.

[0072] The second semiconductor device may include a second element isolation layer 602. The second element isolation layer 602 may contain the same material as the first element isolation layer 601.

[0073] Figure 7 shows another example of a planar structure of a semiconductor device according to an embodiment of the present disclosure.

[0074] Referring to Figure 7, the first semiconductor device may include at least one first column trench CTH1 and at least one first row trench RTH1. The first column trench CTH1 and the first row trench RTH1 may be located in a first chip adjacent cross region OCR1. In one embodiment, the first column trench CTH1 and the first row trench RTH1 may be located in the first chip adjacent cross region OCR1 and not in the first peripheral cross region ICR1. The first column trench CTH1 may be arranged in the column direction. The first row trench RTH1 may be arranged in the row direction. The number of first row trench RTH1 and first column trench CTH1 is not limited to the number shown in Figure 7.

[0075] The first row trench RTH1 can be located between the boundary between the first chip adjacent cross region OCR1 and the first chip adjacent region NR1 and the first boundary 101 between the first chip adjacent cross region OCR1 and the first peripheral cross region ICR1. In one embodiment, the first row trench RTH1 can be located even closer to the first chip adjacent region NR1 in the row direction than the first boundary 101.

[0076] The first column trench CTH1 can be located between the boundary between the first chip adjacent cross region OCR1 and the first chip adjacent region NR1, and the second boundary 102 between the first chip adjacent cross region OCR1 and the first peripheral cross region ICR1. In one embodiment, the first column trench CTH1 can be located even closer to the first chip adjacent region NR1 in the column direction than the second boundary 102.

[0077] In one embodiment, the first row trench RTH1 and the first column trench CTH1 do not have to intersect each other. In one embodiment, at least one of the first row trenches RTH1 and at least one of the first column trenches CTH1 can be in contact with each other. For example, the first row trench RTH1 located closest to the first chip region CHR1 can be in contact with the first column trench CTH1 located closest to the first chip region CHR1.

[0078] In one embodiment, the first row trench RTH1 may be spaced apart from the first chip-adjacent row trench NRTH1. The first column trench CTH1 may be spaced apart from the first chip-adjacent column trench NCTH1.

[0079] In one embodiment, at least a portion of the first row trench RTH1 may overlap with the first column trench CTH1.

[0080] Figure 8 shows an example of the cross-sectional structure of the III-III' section in Figure 7.

[0081] Referring to Figure 8, the first semiconductor device may include a first substrate 200, a first insulating layer 201, a first guard ring GR1, a first interlayer insulating layer 204, a second insulating layer 211, a second interlayer insulating layer 214, a third insulating layer 221, a third interlayer insulating layer 224, a fourth insulating layer 231, a first passivation layer 240, a first dummy pattern 213a, a first dummy contact 222a, a second dummy pattern 223a, a second dummy contact 232a, a third dummy pattern 233a, and a first column trench CTH1. The first guard ring GR1 may include a first contact 202, a first wiring 203, a second contact 212, a second wiring 213, a third contact 222, a third wiring 223, a fourth contact 232, and a fourth wiring 233. The first passivation layer 240 may include a first lower passivation layer 241 and a first upper passivation layer 242.

[0082] The first row trench CTH1 may be located within the first chip adjacent intersection region OCR1. The first row trench CTH1 may be located within the first passivation layer 240. In one embodiment, the first row trench CTH1 may be superimposed on the first dummy pattern 213a, the second dummy pattern 223a, and the third dummy pattern 233a. In one embodiment, the first row trench CTH1 may expose the upper surface of the third dummy pattern 233a. In one embodiment, the first row trench CTH1 may expose the side surface of the first passivation layer 240.

[0083] In the above description, the first column trench CTH1 was illustrated with reference to Figure 8, but the above description can also be applied to the first row trench RTH1 described with reference to Figure 7. For example, the first row trench RTH1 can be located within the first chip adjacent intersection region OCR1. The first row trench RTH1 can be placed within the first passivation layer 240. The first dummy pattern 213a, the second dummy pattern 223a, and the third dummy pattern 233a can also be placed beneath the first row trench RTH1. In one embodiment, the first row trench RTH1 can be superimposed on the first dummy pattern 213a, the second dummy pattern 223a, and the third dummy pattern 233a. In one embodiment, the top surface of the third dummy pattern 233a can be exposed by the first row trench RTH1.

[0084] The second semiconductor device may include a second substrate 300, a fifth insulating layer 301, a second guard ring GR2, a fourth interlayer insulating layer 304, a sixth insulating layer 311, a fifth interlayer insulating layer 314, a seventh insulating layer 321, a sixth interlayer insulating layer 324, an eighth insulating layer 331, a second passivation layer 340, a fourth dummy pattern 313a, a fourth dummy contact 322a, a fifth dummy pattern 323a, a fifth dummy contact 332a, a sixth dummy pattern 333a, and a second row trench CTH2. The second guard ring GR2 may include a fifth contact 302, a fifth wiring 303, a sixth contact 312, a sixth wiring 313, a seventh contact 322, a seventh wiring 323, an eighth contact 332, and an eighth wiring 333. The second passivation layer 340 may include a second lower passivation layer 341 and a second upper passivation layer 342. The configuration included in the second semiconductor device may be substantially identical to the configuration of the first semiconductor device described with reference to Figures 7 and 8.

[0085] Figure 9 shows another example of a planar structure of a semiconductor device according to an embodiment of the present disclosure.

[0086] Referring to Figure 9, the first semiconductor device may include at least one first column trench CTH1 and at least one first row trench RTH1. The first column trench CTH1 and the first row trench RTH1 may be located in a first chip adjacent cross region OCR1. In one embodiment, at least a portion of the first column trench CTH1 and at least a portion of the first row trench RTH1 may be located in a first peripheral cross region ICR1. The first column trench CTH1 may be arranged in the column direction. The first row trench RTH1 may be arranged in the row direction. At least a portion of the first column trench CTH1 may extend from the first chip adjacent cross region OCR1 to the first peripheral cross region ICR1. At least a portion of the first row trench RTH1 may extend from the first chip adjacent cross region OCR1 to the first peripheral cross region ICR1. The number of first row trenches RTH1 and first column trenches CTH1 is not limited to the numbers shown in Figure 9.

[0087] In one embodiment, the first row trench RTH1 and the first column trench CTH1 do not have to intersect each other. In one embodiment, each of the first row trenches RTH1 can be in contact with the corresponding first column trench CTH1.

[0088] In one embodiment, the first row trench RTH1 may be spaced apart from the first chip-adjacent row trench NRTH1. The first column trench CTH1 may be spaced apart from the first chip-adjacent column trench NCTH1.

[0089] In one embodiment, at least a portion of the first row trench RTH1 may overlap with the first column trench CTH1.

[0090] Figure 10 shows an example of the cross-sectional structure of the IV-IV' portion in Figure 9.

[0091] Referring to Figure 10, the first semiconductor device may include a first substrate 200, a first insulating layer 201, a first guard ring GR1, a first interlayer insulating layer 204, a second insulating layer 211, a second interlayer insulating layer 214, a third insulating layer 221, a third interlayer insulating layer 224, a fourth insulating layer 231, a first passivation layer 240, a first dummy pattern 213a, a first dummy contact 222a, a second dummy pattern 223a, a second dummy contact 232a, a third dummy pattern 233a, and a first column trench CTH1. The first guard ring GR1 may include a first contact 202, a first wiring 203, a second contact 212, a second wiring 213, a third contact 222, a third wiring 223, a fourth contact 232, and a fourth wiring 233. The first passivation layer 240 may include a first lower passivation layer 241 and a first upper passivation layer 242.

[0092] The first row trench CTH1 may be located within the first chip adjacent intersection region OCR1. The first row trench CTH1 may be located within the first passivation layer 240. In one embodiment, the first row trench CTH1 may be superimposed on the first dummy pattern 213a, the second dummy pattern 223a, and the third dummy pattern 233a. In one embodiment, the first row trench CTH1 may expose the upper surface of the third dummy pattern 233a. In one embodiment, the first row trench CTH1 may expose the side surface of the first passivation layer 240.

[0093] In the above description, the first column trench CTH1 was illustrated with reference to Figure 10, but the above description can also be applied to the first row trench RTH1 described with reference to Figure 9. For example, the first row trench RTH1 can be located within the first chip adjacent intersection region OCR1. The first row trench RTH1 can be placed within the first passivation layer 240. The first dummy pattern 213a, the second dummy pattern 223a, and the third dummy pattern 233a can also be placed below the first row trench RTH1. In one embodiment, the first row trench RTH1 can be superimposed on the first dummy pattern 213a, the second dummy pattern 223a, and the third dummy pattern 233a. In one embodiment, the top surface of the third dummy pattern 233a can be exposed by the first row trench RTH1.

[0094] The second semiconductor device may include a second substrate 300, a fifth insulating layer 301, a second guard ring GR2, a fourth interlayer insulating layer 304, a sixth insulating layer 311, a fifth interlayer insulating layer 314, a seventh insulating layer 321, a sixth interlayer insulating layer 324, an eighth insulating layer 331, a second passivation layer 340, a fourth dummy pattern 313a, a fourth dummy contact 322a, a fifth dummy pattern 323a, a fifth dummy contact 332a, a sixth dummy pattern 333a, and a second row trench CTH2. The second guard ring GR2 may include a fifth contact 302, a fifth wiring 303, a sixth contact 312, a sixth wiring 313, a seventh contact 322, a seventh wiring 323, an eighth contact 332, and an eighth wiring 333. The second passivation layer 340 may include a second lower passivation layer 341 and a second upper passivation layer 342. The configurations included in the second semiconductor device may be substantially identical to those of the first semiconductor device described with reference to Figures 9 and 10.

[0095] A conductive layer (not shown) may be further disposed in at least a portion of the first column trench CTH1 and the first row trench RTH1, as described with reference to Figures 2, 4-6, 8, and 10. The conductive layer may be located on the underside and sides of the first column trench CTH1 and the first row trench RTH1. In one embodiment, the conductive layer may contain the same material as the pads for connecting the semiconductor device to the outside. The conductive layer may consist of at least one metal or metal alloy selected from the group consisting of, for example, copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C). In one embodiment, the conductive layer may contain aluminum (Al).

[0096] Referring again to Figures 1 and 2, the first row trench RTH1 can be located between the first boundary 101 of the first chip adjacent intersection region OCR1 and the first peripheral intersection region ICR1, and between the boundary of the first chip adjacent intersection region OCR1 and the first chip adjacent intersection region NR1. The first column trench CTH1 can be located between the second boundary 102 of the first chip adjacent intersection region OCR1 and the first peripheral intersection region ICR1, and between the boundary of the first chip adjacent intersection region OCR1 and the first chip adjacent intersection region NR1. The first row trench RTH1 and the first column trench CTH1 do not have to intersect each other. The first row trench RTH1 and the first column trench CTH1 do not have to be located in the first peripheral intersection region ICR1.

[0097] According to embodiments of this disclosure, the first column trench CTH1 and the first row trench RTH1 are arranged in the first chip adjacent intersection region OCR1, thereby minimizing fragmentation defects that occur during the cutting process. This is explained in detail as follows.

[0098] The first row trench RTH1 is positioned in the region through which the boundary line separating the first semiconductor device and the third semiconductor device passes, and in the direction through which the boundary line passes. Therefore, the first row trench RTH1 can function to induce separation when the process of cutting the two semiconductor devices after forming the first and third semiconductor devices on the wafer is carried out. Furthermore, the first row trench RTH1 is not positioned in the region through which the boundary line separating the first and second semiconductor devices passes. Therefore, when the process of cutting the two semiconductor devices after forming the first and second semiconductor devices is carried out, the straightness of the separation can be enhanced.

[0099] Similarly, the first row trench CTH1 is positioned in the region through which the boundary line separating the first semiconductor device and the second semiconductor device passes, in the direction through which the boundary line passes. Therefore, the first row trench RTH1 can function to induce separation when the process of cutting the two semiconductor devices proceeds after the first and second semiconductor devices have been formed on the wafer. Furthermore, the first row trench CTH1 is not positioned in the region through which the boundary line separating the first semiconductor device and the third semiconductor device passes. Therefore, the straightness of separation can be enhanced when the process of cutting the two semiconductor devices proceeds after the first and third semiconductor devices have been formed.

[0100] According to embodiments of this disclosure, the first row trench RTH1 and the first column trench CTH1 can each play a role in inducing separation and reinforcing the straightness of the separation, thereby minimizing separation defects that occur during the cutting process.

[0101] The above description is merely illustrative of the technical concept of this disclosure, and any person with ordinary skill in the art to which this disclosure belongs could make various modifications and variations without departing from the essential characteristics of this disclosure. Furthermore, the embodiments of this disclosure are for illustrative purposes only and not to limit the technical concept of this disclosure, and these embodiments do not limit the scope of the technical concept of this disclosure.

Claims

1. A substrate including a chip region and a scribe lane region, wherein the scribe lane region includes a chip adjacent region, a chip adjacent cross region adjacent to the chip adjacent region, and a peripheral cross region adjacent to the chip adjacent cross region and separated from the chip adjacent region; A passivation layer on the aforementioned substrate; Row trenches are arranged in a direction intersecting the first boundary between the chip adjacent intersection region and the peripheral intersection region, between the chip adjacent intersection region and the boundary of the chip adjacent region, located in a region other than the peripheral intersection region, and within the passivation layer; and A semiconductor device comprising a second boundary that intersects the first boundary among the boundaries of the chip adjacent intersection region and the peripheral intersection region, and a column trench that is arranged in a direction intersecting the second boundary between the chip adjacent intersection region and the boundary of the chip adjacent region, located in a region other than the peripheral intersection region, and arranged within the passivation layer.

2. The semiconductor device according to claim 1, wherein each of the row trenches and each of the column trenches do not intersect with each other.

3. Chip-adjacent row trenches located within the passivation layer and arranged in a direction intersecting the first boundary in the chip-adjacent region; and The chip adjacent region includes a chip adjacent row trench arranged in a direction intersecting the second boundary and located within the passivation layer, The semiconductor device according to claim 1, wherein the row trench is spaced apart from the chip-adjacent row trench, and the column trench is spaced apart from the chip-adjacent column trench.

4. The semiconductor device according to claim 1, further comprising a dummy pattern located in the chip adjacent intersection region and superimposed on the row trench and the column trench, respectively.

5. The semiconductor device according to claim 4, wherein the lower surfaces of the row trenches and the column trenches are separated from the upper surfaces of the dummy patterns.

6. The semiconductor device according to claim 4, wherein the upper surface of the dummy pattern is exposed by the row trench and the column trench.

7. The semiconductor device according to claim 1, wherein the row trench located closest to the chip region is in contact with the column trench located closest to the chip region among the column trenches.

8. The semiconductor device according to claim 1, wherein each of the row trenches is in contact with a corresponding one of the column trenches.

9. The substrate further includes an element isolation layer, The semiconductor device according to claim 1, wherein the element isolation layer is disposed in the chip adjacent cross region and the peripheral cross region.

10. The semiconductor device according to claim 1, wherein the passivation layer comprises a high-density plasma oxide, a nitride, or a combination thereof.

11. A substrate including a chip region and a scribe lane region, wherein the scribe lane region includes a chip adjacent region, a chip adjacent cross region adjacent to the chip adjacent region, and a peripheral cross region adjacent to the chip adjacent cross region and separated from the chip adjacent region; Row trenches arranged in a direction intersecting the first boundary in the chip adjacent intersection region and located in a region other than the peripheral intersection region; and The chip adjacent intersection region includes a row of trenches arranged in a direction intersecting the second boundary that intersects the first boundary, and located in a region other than the peripheral intersection region. Each of the row trenches and each of the column trenches are a semiconductor device that does not intersect with each other.

12. The substrate further includes a passivation layer, The semiconductor device according to claim 11, wherein the row trenches and the column trenches are arranged within the passivation layer.

13. The semiconductor device according to claim 12, wherein the row trench is located between the first boundary between the chip adjacent intersection region and the peripheral intersection region and the boundary between the chip adjacent intersection region and the chip adjacent region, and the column trench is located between the second boundary between the chip adjacent intersection region and the peripheral intersection region and the boundary between the chip adjacent intersection region and the chip adjacent region.

14. In the chip-adjacent region, chip-adjacent row trenches are arranged in a direction intersecting the first boundary and located within the passivation layer; and The chip-adjacent region includes a chip-adjacent row trench arranged in a direction intersecting the second boundary and located within the passivation layer, The semiconductor device according to claim 12, wherein the row trench is spaced apart from the chip-adjacent row trench, and the column trench is spaced apart from the chip-adjacent column trench.

15. The semiconductor device according to claim 11, further comprising a dummy pattern located in the chip adjacent intersection region and superimposed on the row trench and the column trench, respectively.

16. The semiconductor device according to claim 11, wherein the row trench located closest to the chip region is in contact with the column trench located closest to the chip region among the column trenches.

17. The semiconductor device according to claim 11, wherein each of the row trenches is in contact with a corresponding one of the column trenches.

18. The substrate further includes an element isolation layer, The semiconductor device according to claim 11, wherein the element isolation layer is disposed in the chip adjacent cross region and the peripheral cross region.

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