Metal, insulator, and metal capacitors with multiple electrodes and double-sided deposition.

Abstract

To provide a device with increased capacitance and improved reliability, and a method for forming the same. [Solution] Several embodiments relate to a device comprising a semiconductor substrate and a wiring structure disposed on the semiconductor substrate. The wiring structure includes a lower metal wire, an intermediate metal wire, and an upper metal wire, as well as a plurality of metal vias. A first electrode disposed on the wiring structure includes a first side portion and a projection extending downward from the first side portion. The first side portion is located on the upper surface of the upper metal wire, and the projection extends below the lower surface of the lower metal wire. A second electrode is disposed on the wiring structure, mating and engaging with the first electrode, and having a lower surface that is lower than the lower surface of the first electrode. A dielectric laterally surrounds the inner wall structure of the second electrode, separating the second electrode from the outer wall structure of the first electrode.

Description

Technical Field

[0001] The present invention relates to a MIM capacitor with increased capacitance and improved reliability.

Background Art

[0002] A capacitor is a passive circuit component used in imaging, memory, and many other applications. One common type of capacitor in integrated circuits is a metal-insulator-metal (MIM) capacitor. An MIM capacitor has a metal bottom layer, a metal top layer, and a dielectric layer separating the metal bottom layer from the metal top layer.

Summary of the Invention

Problems to be Solved by the Invention

[0003] However, MIM capacitors have problems with reliability caused by insufficient capacitance and etching defects.

Means for Solving the Problems

[0004] According to embodiments of the present invention, the device includes a semiconductor substrate and a wiring structure disposed on the semiconductor substrate. The wiring structure includes a lower metal feature and an upper metal feature above the lower metal feature. A first electrode is disposed within the wiring structure. The first electrode includes a base portion disposed on the upper surface of the lower metal feature, a first peripheral portion extending upward from the peripheral portion of the base portion, and a central portion extending upward from the central region of the base portion. The central portion of the first electrode is laterally surrounded by the first peripheral portion of the first electrode. A second electrode is disposed within the wiring structure above the first electrode and coupled to the upper metal feature. The second electrode includes a plurality of tubes or pillars extending into an opening in the central portion of the first electrode, and a ring-shaped valley structure laterally surrounding the plurality of tubes or pillars and laterally surrounding the central portion of the first electrode. A capacitor dielectric is disposed along the outer walls of the plurality of tubes or pillars and along the inner and outer walls of the ring-shaped valley structure. The capacitor dielectric separates the first electrode from the second electrode.

[0005] According to embodiments of the present invention, the integrated circuit includes a semiconductor substrate and a wiring structure disposed on the semiconductor substrate. The wiring structure includes a first metal feature and a second metal feature spaced apart in a first direction measured perpendicular to the upper surface of the semiconductor substrate. A first electrode is disposed within the wiring structure and coupled to the first metal feature. The first electrode includes a central region and a peripheral region laterally surrounding the central region. The central region includes a continuous cylindrical opening whose respective axes extend in the first direction. A trench structure laterally surrounds the central region and separates the central region of the first electrode from its peripheral region. A second electrode is disposed within the wiring structure and coupled to a second metal feature. The second electrode includes a plurality of tubes or pillars matingly engaging with the cylindrical opening in the central region of the first electrode and a valley structure matingly engaging with the trench structure. A dielectric separates the first electrode from the second electrode.

[0006] According to embodiments of the present invention, a method is provided. In this method, a conductive feature is formed on a substrate, and a plurality of metal wires and vias are formed within a dielectric structure on the conductive feature. A recess is etched into the dielectric structure. The recess includes a plurality of cylindrical openings and a ring-shaped opening that laterally surrounds the cylindrical openings. The recess extends beyond the plurality of metal wires and vias, exposing the upper surface of the conductive feature. A first capacitor bottom metal layer is formed along the side walls of the recess and on the upper surface of the conductive feature. The upper part of the first capacitor bottom metal layer and the upper part of the dielectric structure are removed, leaving the lower part of the first capacitor bottom metal layer and the lower part of the dielectric structure intact. Dielectric material is removed from inside the cylindrical openings to form a hollow cylindrical tube. A capacitor dielectric is formed along the inner and outer walls of the hollow cylindrical tube and along the side walls of the ring-shaped openings. A capacitor top metal layer is formed on the capacitor dielectric along the side walls of the hollow cylindrical tube and along the side walls of the ring-shaped openings to construct a metal-insulator-metal (MIM) capacitor within the recess. [Effects of the Invention]

[0007] Embodiments of the present invention can provide devices, integrated circuits, and methods having increased capacitance and improved reliability. [Brief explanation of the drawing]

[0008] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of discussion. [Figure 1] This is a cross-sectional view of several embodiments of a device including an MIM capacitor according to several embodiments. [Figure 2A] Figure 1 is a top view of several embodiments of the capacitor according to several embodiments. [Figure 2B] Figures 1 and 2A are perspective exploded views of several embodiments of the MIM capacitor according to several embodiments. [Figure 2C] This is an exploded perspective view of several embodiments of an MIM capacitor according to several other embodiments. [Figure 3] This is a cross-sectional view of several embodiments of a device including an MIM capacitor according to several embodiments. [Figure 4] Figure 3 is a top view of several embodiments of the capacitor according to several embodiments. [Figure 5] This is a cross-sectional view of several embodiments of a device including an MIM capacitor according to several embodiments. [Figure 6] Figure 5 is a top view of several embodiments of the capacitor according to several embodiments. [Figure 7] Alternative top views of the capacitor in Figures 1, 3, or 5 according to several embodiments. [Figure 8] Alternative top views of the capacitor in Figures 1, 3, or 5 according to several embodiments. [Figure 9] Alternative top views of the capacitor in Figures 1, 3, or 5 according to several embodiments. [Figure 10] Alternative top views of the capacitor in Figures 1, 3, or 5 according to several embodiments. [Figure 11] Alternative top views of the capacitor in Figures 1, 3, or 5 according to several embodiments. [Figure 12] Alternative top views of the capacitor in Figures 1, 3, or 5 according to several embodiments. [Figure 13A] This is a cross-sectional view of a manufacturing flow for fabricating capacitors according to several embodiments. [Figure 13B] This is a top view of the manufacturing flow for producing a capacitor according to several embodiments. [Figure 14A] This is a cross-sectional view of a manufacturing flow for fabricating capacitors according to several embodiments. [Figure 14B] It is a top view of a manufacturing flow for fabricating a capacitor according to some embodiments. [Figure 15A] It is a cross-sectional view of a manufacturing flow for fabricating a capacitor according to some embodiments. [Figure 15B] It is a top view of a manufacturing flow for fabricating a capacitor according to some embodiments. [Figure 16A] It is a cross-sectional view of a manufacturing flow for fabricating a capacitor according to some embodiments. [Figure 16B] It is a top view of a manufacturing flow for fabricating a capacitor according to some embodiments. [Figure 17A] It is a cross-sectional view of a manufacturing flow for fabricating a capacitor according to some embodiments. [Figure 17B] It is a top view of a manufacturing flow for fabricating a capacitor according to some embodiments. [Figure 18] It is a cross-sectional view of a manufacturing flow for fabricating a capacitor according to some embodiments. [Figure 19A] It is a cross-sectional view showing an alternative manufacturing flow following FIGS. 15A - 15B or FIGS. 16A - 16B according to some embodiments. [Figure 19B] It is a top view showing an alternative manufacturing flow following FIGS. 15A - 15B or FIGS. 16A - 16B according to some embodiments. [Figure 20] It is a top view showing an alternative manufacturing flow following FIGS. 15A - 15B or FIGS. 16A - 16B according to some embodiments. [Figure 21] It is a flowchart of some embodiments of a method for forming a device including a MIM capacitor.

Best Mode for Carrying Out the Invention

[0009] The present invention provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the invention. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or above a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, or in embodiments in which an additional feature is formed between the first and second features so that the first and second features are not in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity and does not, in itself, determine the relationships between the various embodiments and / or configurations discussed.

[0010] Furthermore, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein for ease of description to describe the relationship of one element or feature to other elements or other features, as shown in the figure. Spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figure. The device may be in other orientations (90-degree rotation or other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0011] A MIM capacitor comprises a lower metal layer, an upper metal layer, and a capacitor dielectric that separates the lower metal layer from the upper metal layer. The MIM capacitor may have interlayer dielectric (ILD) layers extending horizontally and may penetrate the ILD layers vertically. The present invention provides an MIM capacitor with increased surface area between the lower and upper metal layers to provide increased capacitance compared to conventional approaches. Some embodiments of the present invention include a lower electrode having a central region and peripheral regions laterally surrounding the central region. The central region of the lower electrode includes a series of openings. The upper electrode includes a plurality of tubes or pillars and valley structures laterally surrounding the tubes or pillars. The tubes or pillars of the second electrode mate into the openings in the central region of the first electrode, and the valley structures of the second electrode mate into trenches of the first electrode, the trenches separating the central region of the lower electrode from the peripheral region of the lower electrode. The mate intonation of the trenches and valley structures helps prevent etching defects that may occur in conventional approaches, thereby providing a more reliable device than conventional approaches.

[0012] Figure 1 shows cross-sectional views of several embodiments of a device 100 including a MIM capacitor 124, according to several embodiments. The device 100 includes a semiconductor substrate 106 and a wiring structure 108 on the semiconductor substrate 106. The semiconductor substrate 106 includes a capacitor region 122 and, in some examples, may not have semiconductor devices in the substrate. The semiconductor substrate 106 may also include a logic region 118 containing semiconductor devices (e.g., transistors 121) connected to each other by conductive features in the wiring structure 108. Generally, the wiring structure 108 includes a number of metal wire / pad layers (e.g., 126, 128, 130) and via layers (e.g., 132, 134) arranged within an interlayer dielectric (ILD) structure 136. The metal wire layer may include a lower metal layer 126 (e.g., lower metal features 140, 148), one or more intermediate metal layers (e.g., intermediate metal features 144, 145), and an upper metal layer (e.g., upper metal features / pads 114a, 114b). Etching stop layers 138, 139 are located above and / or below the various metal wire layers and / or via layers. In some embodiments, the semiconductor device includes a transistor device 121 (e.g., a planar field-effect transistor (FET), a FinFET, a gate-all-around (GAA) device, a bipolar junction transistor (BJT)), but may also include diodes and the like.

[0013] Within the capacitor region 122, the wiring structure 108 includes a lower metal feature 148 and an upper metal feature 147, which includes upper vias 146b and upper metal wires 114b. The upper metal feature 147 is positioned on top of the lower metal feature 148. In some embodiments, the upper metal feature 147 and the lower metal feature are neighboring metal layers, but more often there is an additional metal layer (e.g., 128) between the upper metal feature 147 and the lower metal feature 148.

[0014] The MIM capacitor 124 includes a first electrode 150 coupled to a lower metal feature 148 and a second electrode 156 coupled to an upper metal feature 147. The capacitor dielectric 158 separates the first electrode 150 from the second electrode 156. In some embodiments, the depth of the first electrode 150 and / or the second electrode 156 is greater than the combined height of the lower metal layer 126 and the lower via layer 132. Thus, the depth of the first electrode 150 and / or the second electrode 156 exceeds the height required to separate two, three, four, five, six, seven, or even more etching stop layers 138. Furthermore, in some embodiments, the depth of the first and / or second electrode can be between 1.5 micrometers (μm) and 2.0 μm. In other cases, the depth of the first electrode 150 and / or the second electrode 156 can be between 3 μm and 4 μm. Because this depth is greater than that of conventional MIM capacitors, the MIM capacitor 124 in Figure 1 can provide increased capacitance compared to conventional capacitors.

[0015] In some embodiments, the first electrode 150 and the second electrode 156 are made of the same material. For example, the first electrode 150 and the second electrode 156 may include titanium or tantalum. Although not shown in Figure 1, in some examples, the first electrode 150 includes a barrier layer positioned along the inner wall of the recess in which the MIM capacitor is formed, and a first capacitor bottom electrode layer along the inner wall of the barrier layer. The barrier layer may be tantalum or tantalum nitride, or may include these. The first capacitor bottom electrode layer may be titanium nitride, or may include titanium nitride.

[0016] The capacitor dielectric 158 is arranged along the side walls of the first and / or second electrodes. The capacitor dielectric 158 can be silicon dioxide or a high-k dielectric material. A dielectric 164, such as silicon dioxide, can optionally be present between the innermost walls of the upward portion of the second electrode 156. A dielectric capping structure 160 can cover the upper surface of the second electrode 156, and the dielectric capping structure 160 may be a hard mask such as silicon nitride. Vias 146b extend downward from the upper metal wire 114b (or bonding pad) to the second electrode 156 and extend through the dielectric capping structure 160.

[0017] In some examples, the lower etching stop layer 139 has a different composition from the upper etching stop layer 138. This allows the upper etching stop layer 138 to have an etching rate similar to that of the second electrode 156 material for a given etching, while the lower etching stop layer 139 can have an etching rate different from that of the second electrode material for a given etching.

[0018] Figure 2A shows a top view corresponding to device 100 in Figure 1, and Figure 2B shows an exploded perspective view corresponding to a portion of device 100. Figure 2B shows the lower conductive feature 148, the first electrode 150, the second electrode 156, the capacitor dielectric 158, and the upper conductive features 114b / 146b, which will be described in conjunction with Figure 2A. The first electrode 150 includes a base portion 202 positioned on the upper surface of the lower metal feature 148. The first electrode 150 further includes a central portion 204 extending upward from the central region of the base portion 202 and a peripheral portion 206 extending upward from the peripheral portion of the base portion 202. The central portion 204 of the first electrode includes a plurality of openings 208, which are laterally surrounded by the peripheral portion 206 of the first electrode 150. The openings 208 are cylindrical in shape and each has an axis 207 extending in a first direction perpendicular to the upper surface of the substrate. The trench structure 210 laterally separates the central portion 204 of the first electrode from the peripheral portion 206 of the first electrode. The opening 208 and the trench structure 210 have side walls lined with the capacitor dielectric 158. In the example of Figures 2A and 2B, the opening 208 has a circular perimeter when viewed from above, but the opening 208 may also have a square, rounded square, rectangular, rounded rectangle, ellipse, other polygonal shape, or other rounded polygonal shape perimeter when viewed from above. Thus, the term “cylindrical” as used herein may include any / all of these shapes.

[0019] As shown in Figure 2B, the second electrode 156 includes an upper plate 216 having a plurality of tubes 212 extending downward from the upper plate 216. The tubes 212 engage with an opening 208 in the central portion 204 of the first electrode 150. The ring-shaped valley structure 214 laterally surrounds the plurality of tubes 212 and laterally surrounds the central portion 204 of the first electrode 150. The tubes 212 are typically located within the opening 208 and are geometrically similar to the opening 208. Thus, in the examples of Figures 2A and 2B, the tubes 212 have a circular perimeter when viewed from above, but the tubes 212 can also have a square, rounded square, rectangular, rounded rectangle, ellipse, other polygonal shape, or other polygonal shape with rounded corners when viewed from above.

[0020] As shown in Figure 2A, the opening 208 in the central part of the first electrode has a diameter (d) or width greater than 0.08 μm and less than 0.2 μm. The ring-shaped valley structure 214 may further have a width w1 between its opposing side walls. In some examples, the ratio of width w1:d can range from 0.5:1 to 2:1. Furthermore, the minimum distance s1 between two adjacent openings 208 can range, for example, from 0.08 μm to 0.2 μm. The minimum distance s2 between the inner edge of the ring-shaped valley structure 214 and the adjacent opening 208 can range, for example, from 0.08 μm to 0.2 μm. Thus, in some cases s1 and s2 can be equal, but the ratio s1:s2 can also range from 0.9:1.1 to 1.1:0.9 in some examples.

[0021] Figure 2C shows another example in which the second electrode 156 includes multiple pillars 212, each being a solid and / or continuous metallic body between the outer walls of each pillar, rather than the "hollow" pillars 212 previously shown in Figure 2B. Figure 2B offers the advantage that having a dielectric (see Figure 1, 164) at the center of the tube brings the overall hardness of the MIM capacitor 124 closer to the overall hardness of other areas of the integrated circuit (e.g., the logic area 118), thus limiting "dishing" when chemical mechanical planarization (CMP) is performed. On the other hand, because the example in Figure 2C has "solid" metallic pillars, the MIM capacitor area of ​​the device in Figure 2C may be "harder" than the logic area of ​​the device, causing dishing in the logic area when CMP is performed, but in many respects it is still a viable solution.

[0022] Figure 3 shows a cross-sectional view of a device including another MIM capacitor, and Figure 4 shows a top view consistent with Figure 3 according to several other embodiments. In this example, the MIM capacitor 124b includes a first capacitor dielectric 158 covering the inner wall of a first electrode 150, and a second capacitor electrode 156 covering the inner wall of the first capacitor dielectric 158. Furthermore, the second capacitor dielectric 302 covers the inner wall of the second capacitor electrode 156, constructing a cylindrical opening and a trench structure corresponding to the inner wall of the second capacitor dielectric 302. The first electrode 150 also includes an upper part 150a having pillar-shaped projections 304 and ring-shaped valley-structure projections 306, which extend downward along the side wall of the second capacitor dielectric 302. In particular, the upper part of the first electrode includes a lip 150b and a conductive capping structure 150c, the conductive capping structure 150c extending upward from the lip 150b and extending above the edges of the first capacitor dielectric 158 and the second capacitor dielectric 302 and above the edge of the second capacitor electrode 156, adjacent to the upper side portion 150d of the first electrode. In some embodiments, the first capacitor dielectric 158 and the second capacitor dielectric 302 are made of the same material, such as silicon dioxide or a high dielectric constant dielectric. However, in other embodiments, the first capacitor dielectric 158 is a first dielectric material and the second capacitor dielectric 302 is a second dielectric material, which can be useful when integrating various types of devices in a single process flow. Thus, the MIM capacitors in Figures 3-4 are "double-sided" capacitors. This is because the bottom and outermost parts of the first electrode 150, the first capacitor dielectric 158, and the second capacitor electrode 156 define the first capacitance, while the top and protrusions 304, 306 of the first electrode 150a, the second capacitor dielectric 302, and the second capacitor electrode 156 define the second capacitance in parallel with the first capacitance. Therefore, the MIM capacitor 124 in Figures 3-4 has increased capacitance in a given footprint compared to conventional implementations.

[0023] Figure 5 shows a cross-sectional view of device 500 including another MIM capacitor, and Figure 6 shows a top view consistent with Figure 5 according to several other embodiments. Compared to the examples in Figures 1, 2A, and 2B, where the central portion 204 of the first electrode 150 has substantially the same height / depth as the tube / pillar 212 and valley structure 214 (for example, the height of the first electrode is within 10%, 5%, 2%, or 1% of the height of the tube / pillar), in the examples of Figures 5 and 6, the central portion 204 of the first electrode 150 has a different height / length from the tube / pillar 212 and valley structure 214 (see height difference Δh). In Figures 5 and 6, this height difference Δh is the distance between the nearest adjacent etching stop layers 138,139, but in other cases the height difference Δh can span multiple etching stop layers. Therefore, the tube 212 extends downward from via 146b of the second metal feature 147 to the first metal feature 148, while the central portion 204 of the first electrode 150 stops at the etching stop layer 138. Furthermore, in comparison to the example in Figure 1, the first electrode 150 includes a barrier layer 502 positioned along the inner wall of the recess where the MIM capacitor is formed, and a first capacitor bottom electrode layer 504 along the inner wall of the barrier layer. The barrier layer 502 may be tantalum or tantalum nitride, or may contain them. The first capacitor bottom electrode layer 504 may be titanium nitride, or may contain them. Furthermore, the capacitor dielectric 158 in this example includes a first dielectric layer 506 and a second dielectric layer 508. The first dielectric layer 506 may be a different dielectric material from the second dielectric layer 508. A hard mask layer 160 may also be present, and sidewall spacers 562, which can be made of silicon nitride for example, may also be present along the outer wall of the hard mask layer 160.

[0024] Figures 7–12 show various top views of the central portion of the first electrode and the peripheral portion of the first electrode that laterally surrounds the central portion of the first electrode. Again, the opening 208 is located in the central portion of the first electrode, and the trench structure 210 laterally surrounds the central portion of the first electrode. For clarity, the capacitor dielectric and the second capacitor electrode are omitted from these figures, but it will be understood that they can be present as described elsewhere in this application. Thus, although the trench structure 210 in the embodiments previously illustrated and described was shown as a continuous, uninterrupted ring-shaped structure laterally surrounding the central portion of the first electrode, the trench structure 210 can also be as shown in Figures 7–12 in alternative embodiments.

[0025] In Figures 7, 8, and 9, the top view shows the intermediate manufacturing stage of the structure immediately after the photoresist has been exposed and developed, but before etching is performed (so-called post-development inspection (ADI)). On the other hand, in Figures 10, 11, and 12, the top view shows the stage of the structure after etching has been performed on the structure, relative to Figures 7, 8, and 9, respectively (so-called post-etching inspection (AEI)).

[0026] Therefore, Figures 7 and 10 show examples where the trench structure (e.g., 210 in Figure 2B) is a ring-shaped structure that laterally surrounds the central region of the first electrode and the opening. When viewed from above, the ring-shaped structure has a square or rectangular shape and extends between its side walls in a continuous and uninterrupted manner with a constant width. In some examples, the distance between the inner wall of the trench structure and the nearest opening is 70 nanometers (nm) or less.

[0027] Figures 8 and 11 show another example where the trench structure (e.g., 210 in Figure 2B) is again a ring-shaped structure that laterally surrounds the first electrode and the central region of the opening. However, here the ring-shaped structure includes a series of discrete linear segments that, when viewed from above, have a square or rectangular shape and thus a constant width between their side walls, but are discontinuous at linear segments with ends when they enter within a predetermined distance of the opening. In some examples, the distance between the ends of two linear segments is 70 nm or less, and the minimum distance between a linear segment and an adjacent opening is 70 nm or less.

[0028] Figures 9 and 12 show another example where the trench structure (e.g., 210 in Figure 2B) is again a ring-shaped structure that laterally surrounds the central region of the first electrode and the opening, very similar to Figures 8 and 11. However, here the discrete linear segments have a serif shape, meaning that short lines are regularly attached to the ends of the linear segments. The serif features are placed on the mask to help obtain the desired shape using optical proximity correction (OPC) techniques. In other cases, corner rounding may potentially occur for metal wires. To minimize corner rounding, hammer heads can also be added to the ends of the wires.

[0029] Figures 13A, 13B–18 show a series of cross-sectional views (Figures 10A–18) and corresponding top views (Figures 10B–17B) illustrating a method for forming a wafer and / or die containing a MIM capacitor according to several embodiments. Although these figures are described as a series of operations, it will be understood that these operations can be rearranged in other embodiments, and that the disclosed methods are not limiting in that they are applicable to other structures. In other embodiments, some of the operations shown and / or described may be omitted in whole or in part.

[0030] As shown in Figures 13A to 13B, a wiring structure including a first conductive feature 140 and a second conductive feature 148 is formed within a dielectric structure 130 on the surface of a semiconductor substrate. Although not shown in Figures 13A to 13B for simplicity, the substrate may be any suitable type of substrate. For example, the substrate may be a semiconductor wafer, one or more dies on a wafer, or any other suitable type of semiconductor body and / or epitaxial layer. In some embodiments, the substrate is single-crystal silicon, sapphire, etc., or any combination thereof, or includes these. The substrate may be a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. In some embodiments, the first metallic wire 140 and the second metallic wire 148 are conductive materials such as copper (Cu), titanium (Ti), aluminum (Al), tungsten, etc., or combinations thereof, or include these. In some embodiments, the dielectric structure includes a plurality of interlayer dielectric layers 136 and various etching stop layers 138, 139. The interlayer dielectric layer 136 is an insulator such as a low-k dielectric material or silicon dioxide (SiO2), or contains these. The etching stop layer 138 is a nitride or carbide such as silicon nitride (Si3N4), silicon carbide (SiC), or silicon oxynitride, or contains these.

[0031] As shown in the cross-sectional view of Figure 13A, a first masking layer 1300 is formed on top of the uppermost ILD layer 136. The first masking layer 1300 can be spun-on onto the substrate as a liquid, cured, and then patterned. In some embodiments, the first masking layer 1300 is or contains a photoresist, and / or the first masking layer 1300 is patterned using photolithography. After the first masking layer 1300 is patterned, a first etching process is performed with the first masking layer 1300 in place to construct a plurality of MIM capacitor recesses within the ILD structure. The MIM capacitor recess includes an opening 1302 and a ring-shaped opening 1304 that laterally surrounds the opening 1302. The opening 1302 may be a cylindrical opening with a circular circumference when viewed from above. In other examples, the opening 1302 may be an ellipse, rectangle, square, or other polygon, any of which may have rounded or square corners when viewed from above. After etching is complete, the first masking layer can be removed, for example, by an ashing process or a plasma etching / stripping process.

[0032] As shown in the cross-sectional and top views of Figures 14A and 14B, after the opening 1302 and the ring-shaped opening 1304 are formed, a barrier layer 1402, such as a tantalum or tantalum nitride layer, is formed on the top surface of the ILD layer 136 along the exposed surface of the opening 1302 and along the exposed surface of the ring-shaped opening 1304. Thus, the barrier layer 1402 extends over the second conductive feature and along the inner wall of the dielectric structure. Next, a first capacitor bottom metal layer 1404, such as titanium nitride, is conformally formed on the barrier layer 1402. Then, a second masking layer 1406 is formed on the structure. The second masking layer 1406 can be spun on as a liquid, cured, and then patterned. In some embodiments, the second masking layer 1406 is or contains a photoresist, and / or the second masking layer 1406 is patterned using photolithography.

[0033] As shown in the cross-sectional and top views of Figures 15A and 15B, etching is performed with the second masking layer 1406 in place. The etching can include wet etching or dry etching (e.g., plasma etching) and removes the uppermost portion of the ILD structure that remains exposed by the second masking layer, as well as the uppermost portions of the first capacitor bottom metal layer 1404 and barrier layer 1402. See 1502. In some cases, etching can leave the capacitor bottom metal layer 1404 and barrier layer 1402 at the bottom of the trench intact. After etching is complete, the second masking layer 1406 can be removed by, for example, an ashing process or a plasma etching / stripping process.

[0034] As shown in the cross-sectional and top views of Figures 16A and 16B, another etching is performed to remove at least a portion of the remaining interior of the ILD structure from within the opening 1302. For example, the upper ILD dielectric layer 136 can be removed using wet etching with an acid such as hydrofluoric acid, where the etching stop layer 138 acts as an etching stop layer.

[0035] As shown in the cross-sectional and top views of Figures 17A and 17B, the capacitor dielectric is then formed on the structure. The capacitor dielectric may include a first capacitor dielectric layer 1602 conformally formed within a cylindrical opening and a ring-shaped opening. Next, a second capacitor bottom metal layer 1604, such as titanium nitride, is conformally formed on the first capacitor dielectric layer 1602 in the recess. The second capacitor bottom metal layer 1604 may have the same material composition as the first capacitor bottom metal layer 1404, and / or a different material composition from the first capacitor bottom metal layer 1404. Next, a second capacitor dielectric layer 1606 is formed on the second capacitor bottom metal layer 1604, and an upper first electrode metal layer 1608 is formed on the second capacitor dielectric layer 1606. The upper first electrode metal layer 1608 may have the same material composition as the first capacitor bottom metal layer 1404 and / or the second capacitor bottom metal layer 1604. In some examples, the first capacitor dielectric layer 1602 and / or the second capacitor dielectric layer 1606 are high dielectric constant dielectric materials, and the second capacitor bottom metal layer 1604 and the upper first electrode metal layer 1608 are titanium nitride or contain titanium nitride.

[0036] As shown in the cross-sectional view of Figure 18, the dielectric layer 1802 and hard mask 1804 are formed on the upper first electrode metal layer 1608 and patterned using photolithography and etching. Next, conformal dielectric liner and conformal spacer layers are formed and then etched back to form sidewall spacers 1806 on the second capacitor dielectric layer 1606, with the bottom surface resting on top. Next, an interlayer (ILD) dielectric 136 is formed on the device, and via openings are formed through the ILD dielectric, hard mask, and dielectric. Next, conductive via material is formed to construct the upper contact / via 146b, and the upper metal wire 114b is formed on the upper contact / via.

[0037] Figures 19A-19B and 20 show an alternative embodiment in which additional etching is performed and the recess extends through the entire height of the tube. Thus, compared to Figure 16A in which the etching stops at the etching stop layer 138, the etching in Figures 19A-19B continues until the surface of the first capacitor bottom metal layer 1404, which defines the bottom of the recess, is exposed, removing the additional ILD material and etching stop material. Next, in Figure 20, the first capacitor dielectric layer 1602, the second capacitor bottom metal layer 1604, the second capacitor dielectric layer 1606, the upper first electrode metal layer 1608, the upper contact / via and upper metal wire are formed in the same manner as in Figures 17A-17B.

[0038] Figure 21 shows flowcharts of several embodiments of a method for forming a capacitor having a partial bottom landing on contact wiring. Although this method and other methods illustrated and / or described herein are illustrated as a sequence of operations or events, it will be understood that the present invention is not limited to the illustrated order or operations. Thus, in some embodiments, operations may be performed in a different order than those illustrated and / or simultaneously. Furthermore, in some embodiments, the illustrated operations or events may be subdivided into multiple operations or events, which may be performed at separate times or simultaneously with other operations or sub-operations. In some embodiments, some illustrated operations or events may be omitted and other operations or events not illustrated may be included.

[0039] In 2102, a conductive feature is formed on the substrate. The conductive feature may be a metal wire, such as the top layer metal wire in a wiring structure, or a conductive gate or other conductive feature in a wiring structure on the substrate. Multiple metal wires and vias are formed within a dielectric structure on the conductive feature. In some embodiments, the conductive feature is formed on the capacitor region of the substrate, and the multiple metal wires and vias are formed on the logic region of the substrate. See, for example, Figures 13A to 13B.

[0040] In 2104, a recess is etched into the dielectric structure. The recess includes a cylindrical opening and a ring-shaped opening that laterally surrounds the cylindrical opening. The recess exposes the top surface of the conductive feature. See, for example, Figures 13A and 13B.

[0041] In 2106, the first capacitor bottom metal layer is formed along the side wall of the recess and on the upper surface of the conductive feature. See, for example, Figures 14A to 14B.

[0042] In 2108, the lower part of the metal layer at the bottom of the first capacitor and the lower part of the dielectric structure are left intact, while the upper part of the metal layer at the bottom of the first capacitor and the upper part of the dielectric structure are removed. See, for example, Figures 15A to 15B.

[0043] In step 2110, the dielectric material is removed from the inside of the cylindrical opening to form a hollow cylindrical tube. See, for example, Figures 16A to 16B.

[0044] In 2112, the capacitor dielectric is formed along the side walls of the multiple cylindrical tubes and along the side walls of the ring-shaped opening. See, for example, Figures 17A to 17B.

[0045] In 2116, a capacitor top metal layer is formed along the side walls of multiple tubes and along the side walls of the ring-shaped opening, thereby establishing a metal-insulator-metal (MIM) capacitor within the recess. See, for example, Figures 17A and 17B.

[0046] In 2118, vias are formed above the capacitor top metal layer and electrically coupled to the capacitor top metal layer. See, for example, Figure 18.

[0047] Accordingly, some embodiments relate to a device comprising a semiconductor substrate and a wiring structure disposed on the semiconductor substrate. The wiring structure includes a lower metal feature and an upper metal feature above the lower metal feature. A first electrode is disposed within the wiring structure. The first electrode includes a base portion disposed on the upper surface of the lower metal feature, a first peripheral portion extending upward from the peripheral portion of the base portion, and a central portion extending upward from the central region of the base portion. The central portion of the first electrode is laterally surrounded by the first peripheral portion of the first electrode. A second electrode is disposed within the wiring structure above the first electrode and coupled to the upper metal feature. The second electrode includes a plurality of tubes or pillars extending into an opening in the central portion of the first electrode, and a ring-shaped valley structure laterally surrounding the plurality of tubes or pillars and laterally surrounding the central portion of the first electrode. A capacitor dielectric is disposed along the outer walls of the plurality of tubes or pillars and along the inner and outer walls of the ring-shaped valley structure. The capacitor dielectric separates the first electrode from the second electrode.

[0048] Other embodiments relate to an integrated circuit including a semiconductor substrate and a wiring structure disposed on the semiconductor substrate. The wiring structure includes a first metal feature and a second metal feature spaced apart in a first direction measured perpendicular to the upper surface of the semiconductor substrate. A first electrode is disposed within the wiring structure and coupled to the first metal feature. The first electrode includes a central region and a peripheral region laterally surrounding the central region. The central region includes a continuous cylindrical opening whose respective axes extend in the first direction. A trench structure laterally surrounds the central region and separates the central region of the first electrode from its peripheral region. A second electrode is disposed within the wiring structure and coupled to a second metal feature. The second electrode includes a plurality of tubes or pillars that mate and engage with the cylindrical opening in the central region of the first electrode, and a valley structure that mate and engage with the trench structure. A dielectric separates the first electrode from the second electrode.

[0049] Further embodiments relate to a method. In this method, a conductive feature is formed on a substrate, and a plurality of metal wires and vias are formed within a dielectric structure above the conductive feature. A recess is etched into the dielectric structure. The recess includes a plurality of cylindrical openings and a ring-shaped opening that laterally surrounds the cylindrical openings. The recess extends beyond the plurality of metal wires and vias, exposing the top surface of the conductive feature. A first capacitor bottom metal layer is formed along the side walls of the recess and above the top surface of the conductive feature. The top of the first capacitor bottom metal layer and the top of the dielectric structure are removed, leaving the bottom of the first capacitor bottom metal layer and the bottom of the dielectric structure intact. Dielectric material is removed from inside the cylindrical openings to form a hollow cylindrical tube. A capacitor dielectric is formed along the inner and outer walls of the hollow cylindrical tube and along the side walls of the ring-shaped openings. A capacitor top metal layer is formed on top of the capacitor dielectric along the side walls of the hollow cylindrical tube and along the side walls of the ring-shaped openings to construct a metal-insulator-metal (MIM) capacitor within the recess.

[0050] In this description and the following claims, terms such as “first,” “second,” and “third” are to be understood as merely general identifiers used for the convenience of description to distinguish different elements of a figure or series of figures. These terms themselves do not imply any temporal order or structural proximity to these elements and are not intended to describe corresponding elements in different illustrated embodiments and / or unillustrated embodiments. For example, “first dielectric layer” as described in relation to Figure 1 does not necessarily correspond to “first dielectric layer” as described in relation to another figure, nor does it necessarily correspond to “first dielectric layer” in an unillustrated embodiment. Also, in some embodiments, the terms “about” and / or “approximately” may be interpreted as meaning + / - 10%, and in other embodiments, the terms “about” and / or “approximately” may be interpreted as meaning within the normal manufacturing tolerances of a given fab manufacturing flow.

[0051] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should understand that the present invention can be readily used as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention. [Industrial applicability]

[0052] The devices, integrated circuits, and methods of the present invention can be applied to metal, insulator, and metal capacitors. [Explanation of symbols]

[0053] 100: Device 114b,146b: Upper conductive feature 124: MIM Capacitor 136: Interlayer dielectric layer 148: Lower conductive feature 150: 1st electrode 156:Second electrode 158: Capacitor Dielectric 164: Dielectric 202: Base section 204: Central part 206: Peripheral area 207: Axis 208: Opening 210: Trench structure 212: Tube 214: Ring-shaped valley structure 216: Top plate d: Diameter s1, s2: Minimum distance w1:width

Claims

1. Semiconductor substrate and A wiring structure disposed on the semiconductor substrate and comprising a lower metal feature and an upper metal feature above the lower metal feature, A first electrode disposed within the aforementioned wiring structure, A base portion is positioned on the upper surface of the lower metal feature, A first peripheral portion extending upward from the peripheral portion of the base portion, A central portion extending upward from the central region of the base portion, Includes, The central portion of the first electrode is laterally surrounded by the first peripheral portion of the first electrode. The first electrode and, Within the wiring structure, a second electrode is positioned on the first electrode and coupled to the upper metal feature, A plurality of tubes or pillars extending into the opening in the central part of the first electrode, A ring-shaped valley structure that laterally surrounds a plurality of the tubes or pillars and laterally surrounds the central portion of the first electrode, The two preceding electrodes, A capacitor dielectric arranged along the outer walls of a plurality of tubes or pillars, and along the inner and outer walls of the ring-shaped valley structure, The capacitor dielectric separates the first electrode from the second electrode. The capacitor dielectric and, A device equipped with the following features.

2. Each of the plurality of tubes or pillars has an outer circumference that, when viewed from above, is circular, square, square with rounded corners, rectangular, elliptical, or rectangular with rounded corners. The device according to claim 1.

3. The lower metal feature is a first metal wire, The aforementioned upper metal feature is a second metal wire. The device according to claim 1.

4. The semiconductor substrate further comprises at least one additional metal wire positioned at a certain height, The height of the at least one additional metal wire is between the first height of the first metal wire and the second height of the second metal wire, and the first electrode or the second electrode has an overall height greater than the minimum height that separates the nearest metal layer on the semiconductor substrate. The device according to claim 3.

5. The opening in the central part of the first electrode has a diameter or width greater than 0.08 μm and less than 0.2 μm. The device according to claim 1.

6. The ratio of the width measured perpendicular to the nearest adjacent side wall of the ring-shaped valley structure to the width or diameter of one of the openings in the central part of the first electrode is in the range of 0.5:1 to 2:

1. The device according to claim 1.

7. The central region of the first electrode has a first height, Each of the plurality of tubes or pillars has a second height of no more than 10% of the first height. The device according to claim 1.

8. Semiconductor substrate and A wiring structure disposed on the semiconductor substrate, The wiring structure includes a first metal feature and a second metal feature spaced apart in a first direction measured perpendicular to the upper surface of the semiconductor substrate, The aforementioned wiring structure, A first electrode, which is arranged within the wiring structure and coupled to the first metal feature, A central region including a continuous cylindrical opening in which each axis extends in the first direction, The peripheral region that surrounds the aforementioned central region to the sides, Includes, The trench structure surrounds the central region laterally and separates the central region of the first electrode from the peripheral region of the first electrode. The first electrode and, A second electrode disposed within the wiring structure and coupled to the second metal feature, The second electrode is A plurality of tubes or pillars that fit and engage with the cylindrical opening in the central region of the first electrode, A valley structure that fits and engages with the trench structure, including, The two preceding electrodes, A dielectric material separates the first electrode from the second electrode, An integrated circuit equipped with the following features.

9. Each of the plurality of tubes or pillars has an outer circumference that, when viewed from above, is circular, square, rounded square, rectangular, or rounded rectangle. The integrated circuit according to claim 8.

10. The trench structure, when viewed from above, is rectangular or square. The integrated circuit according to claim 9.

11. The dielectric is arranged along the side wall of the tube or pillar. The integrated circuit according to claim 8.

12. The tube or pillar extends upward and crosses at least three etching stop layers within the wiring structure. The integrated circuit according to claim 8.

13. The central region of the first electrode has a first height, Each of the plurality of tubes or pillars has a second height different from the first height. The integrated circuit according to claim 8.

14. The trench structure has the first height, The integrated circuit according to claim 13.

15. The plurality of tubes or pillars include a plurality of tubes, Furthermore, the plurality of tubes include a dielectric capping structure on the upper surface, wherein silicon dioxide is disposed within the plurality of tubes. The integrated circuit according to claim 8.

16. The first metal feature and the second metal feature contain copper, The integrated circuit according to claim 13.

17. The dielectric is a high-dielectric-constant dielectric having a high dielectric constant that is greater than the dielectric constant of silicon. The integrated circuit according to claim 8.

18. Forming conductive features on a substrate, and forming multiple metal wirings and vias within a dielectric structure on the conductive features, Etching recesses into the dielectric structure, The recess includes a plurality of cylindrical openings and a ring-shaped opening that laterally surrounds the cylindrical openings. The recess extends beyond the plurality of metal wirings and vias, exposing the upper surface of the conductive feature. Etching the recess within the dielectric structure, A first capacitor bottom metal layer is formed along the side wall of the recess and on the upper surface of the conductive feature. Removing the upper part of the metal layer at the bottom of the first capacitor and the upper part of the dielectric structure while leaving the lower part of the metal layer at the bottom of the first capacitor and the lower part of the dielectric structure intact, In order to form a hollow cylindrical tube, the dielectric material is removed from the inside of the cylindrical opening, A capacitor dielectric is formed along the inner and outer walls of the hollow cylindrical tube, and along the side walls of the ring-shaped opening. In order to establish a metal-insulator-metal (MIM) capacitor within the recess, a capacitor top metal layer is formed on the capacitor dielectric along the side wall of the hollow cylindrical tube and along the side wall of the ring-shaped opening, A method that includes [a certain feature].

19. Forming vias electrically coupled to the capacitor top metal layer on the capacitor top metal layer. The method according to claim 18, further comprising:

20. Forming the capacitor dielectric includes forming a first capacitor dielectric layer and a second capacitor dielectric layer within the recess. The first capacitor dielectric layer and the second capacitor dielectric layer have different material compositions. The method according to claim 18.

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