Wiring board, semiconductor device, and method for manufacturing a wiring board

Abstract

To provide a wiring board that can improve the mountability of electronic components on the wiring board. [Solution] The wiring board 10 has a wiring layer 20, an N-layer insulating layer 30, 31, 32 including an insulating layer 30 formed to cover the wiring layer 20, and a cavity 40 formed to penetrate the insulating layers 30, 31, 32 in the thickness direction. The wiring board 10 has an electronic component 50 having a first electrode 52 and disposed in the cavity 40, and an insulating layer 33 filling the cavity 40 and covering the electronic component 50. The wiring layer 20 is provided in a position that does not overlap with the cavity 40 in a plan view. The wiring layer 20 has a mounting surface 20A exposed from the insulating layer 33. The first electrode 52 has a mounting surface 52A exposed from the insulating layer 30. The mounting surface 52A is provided on the same plane as the mounting surface 20A.

Description

Technical Field

[0004] , , ,

[0005] , , , ,

[0001] The present invention relates to a wiring board, a semiconductor device, and a method for manufacturing a wiring board.

Background Art

[0002] Conventionally, as a wiring board for mounting electronic components such as semiconductor chips, a wiring board incorporating circuit elements electrically connected to the electronic components is known (see, for example, Patent Document 1). In this type of wiring board, circuit elements such as chip capacitors are mounted in cavities formed in an insulating layer, and a filling insulating layer for filling the cavities so as to cover the circuit elements is formed. Further, the wiring board has a conductive pad that the uppermost wiring layer has and that protrudes upward from the upper surface of the uppermost insulating layer, and an electrode pad that is formed on the upper surface of the circuit element and is located below the upper surface of the uppermost insulating layer. In such a wiring board, an electronic component is mounted on the conductive pad and the electrode pad so as to straddle the conductive pad and the electrode pad.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in the above wiring board, improvement in the mountability of electronic components is desired.

Means for Solving the Problems

[0005] According to one aspect of the present invention, a wiring substrate having the form of a coreless substrate comprises: a first wiring layer; an N-layer (N is a natural number of 1 or more) insulating layer including a first insulating layer formed to cover the first wiring layer; a cavity formed to penetrate the N-layer insulating layer in the thickness direction; a first electronic component having a first electrode and disposed within the cavity; and a filling insulating layer filling the cavity and covering the first electronic component, wherein the first wiring layer is provided in a position that does not overlap with the cavity in a plan view; the first wiring layer has a first mounting surface exposed from the first insulating layer; the first electrode has a second mounting surface exposed from the filling insulating layer; and the second mounting surface is provided on the same plane as the first mounting surface. [Effects of the Invention]

[0006] According to one aspect of the present invention, it has the effect of improving the mountability of electronic components on a wiring board. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a cross-sectional view showing a wiring board of the first embodiment. [Figure 2] Figure 2 is an enlarged cross-sectional view showing a portion of the wiring board of the first embodiment. [Figure 3] Figure 3 is a cross-sectional view showing a semiconductor device of the first embodiment. [Figure 4] Figure 4 is a cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 5] Figure 5 is a cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 7] Figure 7 is a cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 8] Figure 8 is a cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 9] Figure 9 is a cross-sectional view showing a method for manufacturing a wiring board according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a method of manufacturing a wiring board according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a method of manufacturing a wiring board according to the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing a method of manufacturing a wiring board according to the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a method of manufacturing a wiring board according to the first embodiment. [Figure 14] FIG. 14 is a cross-sectional view showing a method of manufacturing a wiring board according to the first embodiment. [Figure 15] FIG. 15 is a cross-sectional view showing a method of manufacturing a wiring board according to the first embodiment. [Figure 16] FIG. 16 is a cross-sectional view showing a method of manufacturing a wiring board according to the first embodiment. [Figure 17] FIG. 17 is a cross-sectional view showing a method of manufacturing a wiring board according to the first embodiment. [Figure 18] FIG. 18 is a cross-sectional view showing a method of manufacturing a wiring board according to the first embodiment. [Figure 19] FIG. 19 is a cross-sectional view showing a method of manufacturing a wiring board according to the first embodiment. [Figure 20] FIG. 20 is a cross-sectional view showing a method of manufacturing a wiring board according to the first embodiment. [Figure 21] FIG. 21 is a cross-sectional view showing a method of manufacturing a wiring board according to the first embodiment. [Figure 22] FIG. 22 is a cross-sectional view showing a method of manufacturing a wiring board according to the first embodiment. [Figure 23] FIG. 23 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 24] FIG. 24 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 25] FIG. 25 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 26] FIG. 26 is a cross-sectional view showing a wiring board according to the second embodiment. [Figure 27]FIG. 27 is a cross-sectional view showing a part of the wiring board of the second embodiment in an enlarged manner. [Figure 28] FIG. 28 is a cross-sectional view showing a method of manufacturing the wiring board of the second embodiment. [Figure 29] FIG. 29 is a cross-sectional view showing a method of manufacturing the wiring board of the second embodiment. [Figure 30] FIG. 30 is a cross-sectional view showing a method of manufacturing the wiring board of the second embodiment. [Figure 31] FIG. 31 is a cross-sectional view showing a method of manufacturing the wiring board of the second embodiment. [Figure 32] FIG. 32 is a cross-sectional view showing a method of manufacturing the wiring board of the second embodiment. [Figure 33] FIG. 33 is a cross-sectional view showing a method of manufacturing the wiring board of the second embodiment. [Figure 34] FIG. 34 is a cross-sectional view showing a method of manufacturing the wiring board of the second embodiment. [Figure 35] FIG. 35 is a cross-sectional view showing a method of manufacturing the wiring board of the second embodiment. [Figure 36] FIG. 36 is a cross-sectional view showing a method of manufacturing the wiring board of the second embodiment. [Figure 37] FIG. 37 is a cross-sectional view showing a method of manufacturing the wiring board of the second embodiment. [Figure 38] FIG. 38 is a cross-sectional view showing a method of manufacturing the wiring board of the second embodiment. [Figure 39] FIG. 39 is a cross-sectional view showing an application example of the wiring board of the second embodiment. [Figure 40] FIG. 40 is a cross-sectional view showing the wiring board of the third embodiment. [Figure 41] FIG. 41 is a cross-sectional view showing a part of the wiring board of the third embodiment in an enlarged manner. [Figure 42] FIG. 42 is a cross-sectional view showing a method of manufacturing the wiring board of the third embodiment. [Figure 43] FIG. 43 is a cross-sectional view showing a method of manufacturing the wiring board of the third embodiment. [Figure 44] FIG. 44 is a cross-sectional view showing a method of manufacturing the wiring board of the third embodiment. [Figure 45] Figure 45 is a cross-sectional view showing a method for manufacturing a wiring board according to the third embodiment. [Figure 46] Figure 46 is a cross-sectional view showing a method for manufacturing a wiring board according to the third embodiment. [Figure 47] Figure 47 is a cross-sectional view showing a method for manufacturing a wiring board according to the third embodiment. [Figure 48] Figure 48 is a cross-sectional view showing a method for manufacturing a wiring board according to the third embodiment. [Figure 49] Figure 49 is a cross-sectional view showing a method for manufacturing a wiring board according to the third embodiment. [Figure 50] Figure 50 is a cross-sectional view showing a method for manufacturing a wiring board according to the third embodiment. [Figure 51] Figure 51 is a cross-sectional view showing a method for manufacturing a wiring board according to the third embodiment. [Figure 52] Figure 52 is a cross-sectional view showing a method for manufacturing a wiring board according to the third embodiment. [Figure 53] Figure 53 is a cross-sectional view showing an example of the application of the wiring board according to the third embodiment. [Figure 54] Figure 54 is a cross-sectional view showing a modified wiring board. [Figure 55] Figure 55 is a cross-sectional view showing a magnified portion of the modified wiring board. [Modes for carrying out the invention]

[0008] The embodiments will be described below with reference to the attached drawings. Note that, for convenience, the attached drawings may show enlarged versions of characteristic parts to make the features easier to understand, and the dimensional ratios of each component may differ in each drawing. Furthermore, in the cross-sectional views, to make the cross-sectional structure of each member easier to understand, the hatching of some members may be replaced with a textured pattern, and the hatching of some members may be omitted. In this specification, "plan view" refers to viewing the object from the vertical direction (up and down direction in the drawing), as shown in Figure 1. Also, in this specification, "planar shape" refers to the shape of the object as viewed from the vertical direction, as shown in Figure 1. Furthermore, "up and down direction" and "left and right direction" in this specification refer to the direction in which the symbols indicating each member in each drawing can be correctly read, with the correct position being considered the orientation. Also, unless otherwise stated, the numerical range "X1~X2" defined by the upper limit X1 and lower limit X2 in this disclosure refers to a range of X1 to X2. In this specification, "facing" means that two surfaces or members are in a position where they are directly in front of each other. In this specification, "facing" includes not only cases where they are completely in front of each other, but also cases where they are partially in front of each other. In this specification, "facing" includes not only cases where two members are separated from each other, but also cases where two members are in contact with each other.

[0009] (First Embodiment) The first embodiment will be described below with reference to Figures 1 to 25. (Overall configuration of the wiring board 10) As shown in Figure 1, the wiring board 10 has a wiring structure 11, one or more (two in this embodiment) cavities 40 formed in the wiring structure 11, and one or more (two in this embodiment) electronic components 50 arranged in the cavities 40. The wiring board 10 is a wiring board with the electronic components 50 built in. Note that the directions in each drawing do not necessarily represent the orientation of the wiring board 10 when in use.

[0010] (Structure of wiring structure 11) As shown in Figure 2, the wiring structure 11 has a structure in which a wiring layer 20, an insulating layer 30, a wiring layer 21, an insulating layer 31, a wiring layer 22, an insulating layer 32, an insulating layer 33, a wiring layer 23, an insulating layer 34, a wiring layer 24, and a solder resist layer 35 are sequentially stacked. The wiring substrate 10 of this embodiment has the form of a so-called coreless substrate that does not include a support substrate.

[0011] For example, copper or copper alloys can be used as the material for the wiring layers 20, 21, 22, 23, and 24. The thickness of each of the wiring layers 20, 21, 22, 23, and 24 can be, for example, about 1 μm to 35 μm.

[0012] The insulating layers 30, 31, 32, 33, and 34 are insulating layers mainly composed of, for example, a non-photosensitive resin. The insulating layers 30, 31, 32, 33, and 34 can be mainly composed of, for example, thermosetting non-photosensitive resins such as epoxy resins, imide resins, phenolic resins, and cyanate resins. The solder resist layer 35 is an insulating layer mainly composed of, for example, a photosensitive resin. As the material for the solder resist layer 35, for example, a photosensitive insulating resin mainly composed of phenolic resins or polyimide resins can be used.

[0013] The wiring layer 20 is formed to protrude downward (in the first direction) from the lower surface (third surface) of the insulating layer 30. A portion of the wiring layer 20, specifically the upper part of the wiring layer 20, is embedded in the insulating layer 30. The wiring layer 20 is positioned so as not to overlap with the cavity 40 in a plan view. The wiring layer 20 is, for example, the outermost layer (in this case, the bottom layer) of the wiring substrate 10. The wiring layer 20 functions as a component mounting pad for electrically connecting to electronic components such as a semiconductor chip 110 (see Figure 3). The wiring layer 20 has a mounting surface 20A (lower surface in Figure 2) on which electronic components such as a semiconductor chip 110 are mounted. The mounting surface 20A of the wiring layer 20 is positioned below the lower surface of the insulating layer 30. The amount of protrusion of the wiring layer 20 from the lower surface of the insulating layer 30, that is, the thickness from the lower surface of the insulating layer 30 to the mounting surface 20A, can be, for example, about 5 μm to 10 μm.

[0014] Furthermore, if necessary, a surface treatment layer 60 may be formed on the surface of the wiring layer 20 (mounting surface 20A and side surfaces, or mounting surface 20A only). In this embodiment, the surface treatment layer 60 is formed to cover only the mounting surface 20A of the wiring layer 20. Examples of surface treatment layers 60 include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer in which Ni and Au layers are stacked in this order), and a Ni layer / palladium (Pd) layer / Au layer (a metal layer in which Ni, Pd, and Au layers are stacked in this order). Other examples of surface treatment layers 60 include a Ni layer / tin (Sn) layer (a metal layer in which Ni and Sn layers are stacked in this order), a Ni layer / Sn layer / indium (In) layer (a metal layer in which Ni, Sn, and In layers are stacked in this order), and a bismuth (Bi) layer. Here, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or a Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. Furthermore, the Sn layer is a metal layer made of Sn or a Sn alloy, the In layer is a metal layer made of In or an In alloy, and the Bi layer is a metal layer made of Bi or a Bi alloy. These Au, Ni, Pd, Sn, In, and Bi layers can be, for example, metal layers formed by electroless plating (electroless plated metal layers) or metal layers formed by electroplating (electroplated metal layers). Additionally, as the surface treatment layer 60, an OSP (Organic Solderability Preservative) film formed by applying an anti-oxidation treatment such as OSP treatment to the surface of the wiring layer 20 can be used. As the OSP film, for example, an organic film such as an azole compound or an imidazole compound can be used.

[0015] The insulating layer 30 is formed to cover the upper surface of the wiring layer 20. The insulating layer 30 is formed to cover a portion of the side surface of the wiring layer 20 while leaving the rest of the side surface of the wiring layer 20 exposed. The insulating layer 30 is formed to cover the upper side surface of the wiring layer 20. The insulating layer 30 is, for example, the outermost layer (in this case, the bottom layer) insulating layer of the wiring board 10. The thickness from the upper surface of the wiring layer 20 to the upper surface of the insulating layer 30 can be, for example, about 15 μm to 60 μm.

[0016] The wiring layer 21 is laminated on the upper surface of the insulating layer 30. The wiring layer 21 is electrically connected to the insulating layer 30 via via wiring that penetrates the insulating layer 30 in the thickness direction. The wiring layer 21 is positioned so as not to overlap with the cavity 40 in a plan view.

[0017] The insulating layer 31 is formed on the upper surface of the insulating layer 30 so as to cover the wiring layer 21. The insulating layer 31 is formed so as to cover the upper and side surfaces of the wiring layer 21. The thickness from the upper surface of the wiring layer 21 to the upper surface of the insulating layer 31 can be, for example, about 15 μm to 60 μm.

[0018] The wiring layer 22 is laminated on the upper surface of the insulating layer 31. The wiring layer 22 is electrically connected to the insulating layer 31 via via wiring that penetrates the insulating layer 31 in the thickness direction. The wiring layer 22 is positioned so as not to overlap with the cavity 40 in a plan view.

[0019] The insulating layer 32 is formed on the upper surface of the insulating layer 31 so as to cover the wiring layer 22. The insulating layer 32 is formed so as to cover the upper and side surfaces of the wiring layer 22. The thickness from the upper surface of the wiring layer 22 to the upper surface of the insulating layer 32 can be, for example, about 10 μm to 40 μm.

[0020] Each cavity 40 is formed in the insulating layers 30, 31, and 32. Each cavity 40 is formed to be recessed downward from the upper surface of the insulating layer 32. Each cavity 40 is formed to penetrate the insulating layers 30, 31, and 32 in the thickness direction. Each cavity 40 is formed to correspond to the embedded electronic component 50. That is, each cavity 40 is formed at the mounting position of the electronic component 50.

[0021] The cavity 40 is formed in a tapered shape, for example, in Figure 2, where the opening width decreases from the top (top side of the insulating layer 32) to the bottom (bottom side of the insulating layer 30). That is, the cavity 40 is formed so that the upper opening widens relative to the lower opening. The internal space of the cavity 40 becomes a housing space for accommodating the electronic components 50. In the wiring board 10 of this embodiment, the three insulating layers 30, 31, and 32 serve as insulating layers for cavity formation.

[0022] (Structure of electronic component 50) Here, each electronic component 50 has a main body 51, a first electrode 52 provided at the bottom of the electronic component 50, a second electrode 53 provided at the top of the electronic component 50, and a through electrode 54. Each electronic component 50 has, for example, an insulating resin 55. The electronic component 50 in this embodiment has a plurality of first electrodes 52, a plurality of second electrodes 53, and a plurality of through electrodes 54.

[0023] Examples of electronic components 50 include semiconductor elements, crystal oscillators, chip components, and silicon bridges. Examples of chip components include chip capacitors, chip resistors, and chip inductors. The electronic components 50 embedded in the wiring board 10 are not limited to one type, but may include multiple types of electronic components 50.

[0024] The main body 51 is formed, for example, in the shape of a rectangular parallelepiped. The thickness of the main body 51 can be, for example, about 50 μm to 200 μm. The main body 51 is formed from, for example, silicon (Si) or silicon carbide (SiC).

[0025] For the materials of the first electrode 52, the second electrode 53, and the through electrode 54, for example, metals such as aluminum (Al) and copper (Cu), or alloys containing at least one metal selected from these metals can be used.

[0026] Each first electrode 52 is formed to protrude downward (in a first direction) from, for example, the lower surface (first surface) of the main body 51. Each first electrode 52 is formed to protrude downward (in a first direction) from, for example, the lower surface (second surface) of the insulating resin 55. Each first electrode 52 is formed to protrude downward from, for example, the lower surface of the insulating layer 30. A part of the first electrode 52, specifically the upper part of the first electrode 52, is embedded in the insulating resin 55. The first electrode 52 functions as a component mounting pad for electrically connecting to electronic components such as a semiconductor chip 110 (see Figure 3). The first electrode 52 has a mounting surface 52A (lower surface in Figure 2) on which electronic components such as a semiconductor chip 110 are mounted. The mounting surface 52A of the first electrode 52 is provided on the same plane as the mounting surface 20A of the wiring layer 20. The thickness of the first electrode 52 can be, for example, about 2 μm to 20 μm. Furthermore, each first electrode 52 may be formed such that a portion of it is embedded in the main body 51.

[0027] A surface treatment layer 60 is formed on the surface of the first electrode 52 (mounting surface 52A and side surfaces, or mounting surface 52A only), as needed. In this embodiment, the surface treatment layer 60 is formed to cover only the mounting surface 52A of the first electrode 52. The thickness of the surface treatment layer 60 formed on the mounting surface 52A is the same as the thickness of the surface treatment layer 60 formed on the mounting surface 20A. Therefore, the lower surface of the surface treatment layer 60 formed on the mounting surface 52A is on the same plane as the lower surface of the surface treatment layer 60 formed on the mounting surface 20A.

[0028] The insulating resin 55 is provided on the lower surface of the main body 51. The insulating resin 55 is formed to cover, for example, the entire lower surface of the main body 51 that is exposed from the first electrode 52. The insulating resin 55 is formed to cover a part of the side surface of the first electrode 52, while leaving the rest of the side surface of the first electrode 52 exposed. The insulating resin 55 is formed to cover the upper side surface of the first electrode 52. The lower surface of the insulating resin 55 is provided on the same plane as, for example, the lower surface of the insulating layer 30.

[0029] The insulating resin 55 is, for example, an insulating layer mainly composed of a non-photosensitive resin. The insulating resin 55 can be mainly composed of thermosetting non-photosensitive resins such as epoxy resins, imide resins, phenolic resins, and cyanate resins. As the insulating resin 55, for example, an adhesive can be used in which a filler is mixed into a base resin such as an epoxy resin.

[0030] Each second electrode 53 is provided on the opposite side of the first electrode 52. Each second electrode 53 is formed to protrude upward from the upper surface of the main body 51, for example. The thickness of the second electrode 53 can be, for example, about 2 μm to 20 μm. Each second electrode 53 may also be formed to be embedded in the main body 51.

[0031] Each through electrode 54 is formed to penetrate the main body 51 in the thickness direction. Each through electrode 54 extends linearly along the thickness direction of the main body 51, for example. Each through electrode 54 electrically connects the first electrode 52 and the second electrode 53 to each other.

[0032] The insulating layer 33 is a filling insulating layer that fills the cavity 40. The insulating layer 33 is formed to fill the cavity 40 and cover the electronic component 50. The insulating layer 33 is formed to cover the entire inner wall surface of the cavity 40. The insulating layer 33 is formed to cover the electronic component 50 overall, for example. The insulating layer 33 is formed to cover the side surface of the insulating resin 55, for example. The insulating layer 33 is formed to cover the top and side surfaces of the main body 51, for example. The insulating layer 33 is formed to cover the top and side surfaces of the second electrode 53, for example.

[0033] The lower surface of the insulating layer 33 in the portion filled in the cavity 40 is formed to be exposed, for example, from the lower surface of the insulating layer 30 and the lower surface of the insulating resin 55. The lower surface of the insulating layer 33 in the portion filled in the cavity 40 is formed to be flush with, for example, the lower surface of the insulating layer 30 and the lower surface of the insulating resin 55.

[0034] The insulating layer 33 is formed to cover the upper surface of the insulating layer 32. For example, the insulating layer 33 is formed to cover the entire upper surface of the insulating layer 32. Through-holes VH1 are formed in the insulating layers 32 and 33 at required locations, penetrating them in the thickness direction and exposing a portion of the upper surface of the wiring layer 22. Through-holes VH2 are formed in the insulating layer 33 at required locations, penetrating it in the thickness direction and exposing a portion of the upper surface of the second electrode 53. The through-holes VH1 and VH2 are formed in a tapered shape, for example, in Figure 2, where the diameter (opening width) decreases from the top (top surface side of insulating layer 33) to the bottom. The through-holes VH1 and VH2 are formed in an inverted frustoconical shape, for example, where the opening diameter of the lower opening end is smaller than the opening diameter of the upper opening end. The thickness from the top surface of insulating layer 32 to the top surface of insulating layer 33 can be, for example, about 5 μm to 30 μm.

[0035] The wiring layer 23 is formed on the upper surface of the insulating layer 33. The wiring layer 23 has a wiring layer that is electrically connected to the wiring layer 22 via a via wiring filled in a through hole VH1, for example. The wiring layer 23 also has a wiring layer that is electrically connected to the second electrode 53 via a via wiring filled in a through hole VH2, for example. The wiring layer 23 is formed integrally with the via wiring filled in the through hole VH1 or VH2. The wiring layer 23 may be routed in a planar direction on the upper surface of the insulating layer 33 (specifically, in a direction perpendicular to the stacking direction of the wiring board 10). Furthermore, the wiring layer 23 routed in this planar direction may electrically connect the wiring layer 23 connected to the wiring layer 22 and the wiring layer 23 connected to the second electrode 53 to each other.

[0036] The insulating layer 34 is formed on the upper surface of the insulating layer 33 so as to cover the wiring layer 23. The insulating layer 34 is formed so as to cover the upper and side surfaces of the wiring layer 23. The thickness from the upper surface of the wiring layer 23 to the upper surface of the insulating layer 34 can be, for example, about 15 μm to 60 μm.

[0037] The wiring layer 24 is laminated on the upper surface of the insulating layer 34. The wiring layer 24 is electrically connected to the wiring layer 23 via via wiring that penetrates the insulating layer 34 in the thickness direction. The wiring layer 24 is, for example, the outermost (in this case, the topmost) wiring layer of the wiring board 10.

[0038] The solder resist layer 35 is formed on the upper surface of the insulating layer 34 so as to cover the wiring layer 24. The solder resist layer 35 is formed so as to cover the upper and side surfaces of the wiring layer 24. The solder resist layer 35 is the outermost insulating layer provided on the outermost layer (in this case, the top layer) of the wiring substrate 10. The thickness from the upper surface of the wiring layer 24 to the upper surface of the solder resist layer 35 can be, for example, about 12 μm to 50 μm.

[0039] The solder resist layer 35 has an opening 35X formed therein to expose a portion of the upper surface of the top wiring layer 24 as a connection pad. The opening 35X is formed in a tapered shape, for example, in Figure 2, where the diameter (opening width) decreases from the top (top surface side of the solder resist layer 35) to the bottom. The opening 35X is formed in an inverted frustoconical shape, for example, where the opening diameter at the lower opening end is smaller than the opening diameter at the upper opening end.

[0040] A surface treatment layer 61 is formed on the wiring layer 24 exposed through the opening 35X, if necessary. As the surface treatment layer 61, metal layers such as an Au layer, Ni layer / Au layer, Ni layer / Pd layer / Au layer, Ni layer / Sn layer, Ni layer / Sn layer / In layer, or Bi layer, or an OSP film can be used.

[0041] (Structure of semiconductor device 1) Next, the structure of the semiconductor device 1 will be described according to Figure 3. The semiconductor device 1 comprises a substrate 70, a wiring board 10 mounted on the substrate 70, an underfill resin 100, one or more (three in this embodiment) semiconductor chips 110 mounted on the wiring board 10, and an underfill resin 120. Note that in Figure 3, the wiring board 10 shown in Figure 1 is shown rotated by 180°.

[0042] (Configuration of circuit board 70) The substrate 70 has a core substrate 71. As the core substrate 71, for example, a so-called glass epoxy substrate can be used, which is made by impregnating glass cloth with a thermosetting insulating resin such as epoxy resin. As the core substrate 71, for example, a substrate may be used in which woven or nonwoven fabrics such as glass fibers, carbon fibers, or aramid fibers are impregnated with a thermosetting insulating resin such as epoxy resin. Note that the illustration of glass cloth, etc. is omitted in each figure.

[0043] The core substrate 71 has a plurality of through holes 72 that penetrate the core substrate 71 in the thickness direction. Through electrodes 73 that penetrate the core substrate 71 in the thickness direction are formed on the inner wall surface of the through holes 72. The center of the through holes 72, specifically the through holes 72 inside the through electrodes 73, is filled with a resin portion 74. For example, copper or a copper alloy can be used as the material for the through electrodes 73. For example, an insulating resin such as epoxy resin can be used as the material for the resin portion 74.

[0044] The core substrate 71 has one or more (two in this embodiment) openings 75 that penetrate the core substrate 71 in the thickness direction. Electronic components 76 are housed inside the openings 75. The openings 75 are filled with a resin portion 77 so as to cover the electronic components 76. The resin portion 77 is formed to cover, for example, the bottom and sides of the electronic components 76. Examples of electronic components 76 include semiconductor elements, crystal oscillators, chip components, and silicon bridges. Examples of chip components include chip capacitors, chip resistors, and chip inductors. Note that the electronic components 76 embedded in the substrate 70 are not limited to one type, but may be multiple types of electronic components 76. As the material for the resin portion 77, for example, an insulating resin such as epoxy resin can be used.

[0045] The substrate 70 has a wiring structure on the lower surface of the core substrate 71 in which a wiring layer 81, an insulating layer 82, a wiring layer 83, an insulating layer 84, a wiring layer 85, an insulating layer 86, a wiring layer 87, and a solder resist layer 88 are sequentially stacked. The substrate 70 also has a wiring structure on the upper surface of the core substrate 71 in which a wiring layer 91, an insulating layer 92, a wiring layer 93, an insulating layer 94, a wiring layer 95, an insulating layer 96, a wiring layer 97, and a solder resist layer 98 are sequentially stacked.

[0046] For the wiring layers 81, 83, 85, 87, 91, 93, 95, and 97, for example, copper or copper alloys can be used as materials. The thickness of each wiring layer 81, 83, 85, 87, 91, 93, 95, and 97 can be, for example, about 8 μm to 40 μm. The insulating layers 82, 84, 86, 92, 94, and 96 are insulating layers mainly composed of non-photosensitive resins. The insulating layers 82, 84, 86, 92, 94, and 96 can be mainly composed of thermosetting non-photosensitive resins such as epoxy resins, imide resins, phenolic resins, and cyanate resins. The thickness of each insulating layer 82, 84, 86, 92, 94, and 96 can be, for example, about 15 μm to 100 μm. The solder resist layers 88 and 98 are insulating layers mainly composed of photosensitive resins. For example, a photosensitive insulating resin mainly composed of phenolic resin or polyimide resin can be used as the material for the solder resist layers 88 and 98. The thickness of the solder resist layers 88 and 98 can be, for example, about 12 μm to 50 μm.

[0047] The wiring layer 81 is laminated on the lower surface of the core substrate 71. The wiring layer 81 is electrically connected to the through-electrode 73. The insulating layer 82 is formed on the lower surface of the core substrate 71 to cover the wiring layer 81. The wiring layer 83 is laminated on the lower surface of the insulating layer 82. The wiring layer 83 is electrically connected to the wiring layer 81 via via wiring that penetrates the insulating layer 82 in the thickness direction. The insulating layer 84 is formed on the lower surface of the insulating layer 82 to cover the wiring layer 83. The wiring layer 85 is laminated on the lower surface of the insulating layer 84. The wiring layer 85 is electrically connected to the wiring layer 83 via via wiring that penetrates the insulating layer 84 in the thickness direction. The insulating layer 86 is formed on the lower surface of the insulating layer 84 to cover the wiring layer 85. The wiring layer 87 is laminated on the lower surface of the insulating layer 86. The wiring layer 87 is electrically connected to the wiring layer 85 via via wiring that penetrates the insulating layer 86 in the thickness direction.

[0048] The solder resist layer 88 is formed on the underside of the insulating layer 86 so as to cover the wiring layer 87. The solder resist layer 88 has an opening 88X formed therein to expose a portion of the underside of the bottommost wiring layer 87 as an external connection pad. An external connection terminal 89 is provided on the underside of the wiring layer 87 exposed through the opening 88X. For example, a solder ball can be used as the external connection terminal 89.

[0049] The wiring layer 91 is laminated on the upper surface of the core substrate 71. The wiring layer 91 is electrically connected to the wiring layer 81 via through electrodes 73. Some of the wiring layers 91 are electrically connected to electronic components 76. The insulating layer 92 is formed on the upper surface of the core substrate 71 to cover the wiring layer 91. The wiring layer 93 is laminated on the upper surface of the insulating layer 92. The wiring layer 93 is electrically connected to the wiring layer 91 via via wiring that penetrates the insulating layer 92 in the thickness direction. The insulating layer 94 is formed on the upper surface of the insulating layer 92 to cover the wiring layer 93. The wiring layer 95 is laminated on the upper surface of the insulating layer 94. The wiring layer 95 is electrically connected to the wiring layer 93 via via wiring that penetrates the insulating layer 94 in the thickness direction. The insulating layer 96 is formed on the upper surface of the insulating layer 94 to cover the wiring layer 95. The wiring layer 97 is laminated on the upper surface of the insulating layer 96. The wiring layer 97 is electrically connected to the wiring layer 95 via via wiring that penetrates the insulating layer 96 in the thickness direction.

[0050] The solder resist layer 98 is formed on the upper surface of the insulating layer 96 so as to cover the wiring layer 97. The solder resist layer 98 has an opening 98X formed therein to expose a portion of the upper surface of the topmost wiring layer 97 as a connection pad. The opening 98X is provided so as to overlap in a plan view with the opening 35X of the solder resist layer 35 of the wiring board 10.

[0051] (Structure of the wiring board 10) The wiring board 10 is mounted on the upper surface of the substrate 70. The wiring board 10 is mounted on the upper surface of the substrate 70 with the wiring layer 24 and the solder resist layer 35 facing the upper surface of the substrate 70. More specifically, the wiring layer 24 exposed through the opening 35X of the solder resist layer 35 and the wiring layer 97 exposed through the opening 98X of the solder resist layer 98 are joined to each other by a joining member 99. The joining member 99 is joined to the wiring layer 24 (specifically, the surface treatment layer 61) exposed through the opening 35X and to the wiring layer 97 exposed through the opening 98X. For example, a solder layer can be used as the joining member 99. For example, Sn-Ag, Sn-Cu, or Sn-Ag-Cu Pb-free solder can be used as the material for the solder layer. Alternatively, for example, a Cu-Ni-Sn electroplated metal layer or a copper-based ink paste can be used as the joining member 99.

[0052] In this way, a semiconductor device 1 with a POP (Package on Package) structure is formed by laminating and bonding the substrate 70 and the wiring board 10 via a bonding member 99. Here, the electronic components 76 embedded in the substrate 70 may be electrically connected to the electronic components 50 embedded in the wiring board 10 through wiring layers 91, 93, 95, 97, 24, 23, etc.

[0053] (Structure of underfill resin 100) The underfill resin 100 is provided to fill the gap between the substrate 70 and the wiring board 10. The underfill resin 100 is provided, for example, to fill the gap between the solder resist layer 98 and the solder resist layer 35. As the material for the underfill resin 100, an insulating resin such as epoxy resin can be used.

[0054] (Structure of semiconductor chip 110) Each semiconductor chip 110 is flip-chip mounted on the wiring layer 20 and the first electrode 52 of the wiring substrate 10. Each semiconductor chip 110 is electrically connected to the wiring layer 20 and the first electrode 52 via a bonding member 62 and a surface treatment layer 60. Each semiconductor chip 110 is mounted on the wiring substrate 10 so as to straddle the wiring layer 20 and the first electrode 52. The bonding member 62 is bonded to the surface treatment layer 60 formed on the wiring layer 20. For example, a solder layer can be used as the bonding member 62. For example, Sn-Ag, Sn-Cu, or Sn-Ag-Cu lead-free solder can be used as the material for the solder layer.

[0055] As the semiconductor chip 110, for example, logic chips such as CPU (Central Processing Unit) chips and GPU (Graphics Processing Unit) chips can be used. In addition, as the semiconductor chip 110, memory chips such as DRAM (Dynamic Random Access Memory) chips, SRAM (Static Random Access Memory) chips and flash memory chips can be used. When mounting multiple semiconductor chips 110 on the wiring board 10, logic chips and memory chips may be combined and mounted on the wiring board 10.

[0056] (Structure of underfill resin 120) The underfill resin 120 is provided to fill the gap between the wiring board 10 and the semiconductor chip 110. For example, the underfill resin 120 is provided to fill the gap between multiple semiconductor chips 110. As the material for the underfill resin 120, an insulating resin such as epoxy resin can be used.

[0057] (Manufacturing method for wiring board 10) Next, the manufacturing method of the wiring board 10 will be described. For the sake of clarity, the parts that will ultimately become components of the wiring board 10 will be denoted by their final component reference numerals.

[0058] First, in the process shown in Figure 4, a support 200 is prepared. The support 200 has a structure in which a metal film 202 and a metal film 203 are sequentially laminated on both the upper and lower surfaces of a substrate 201. The substrate 201 is a prepreg made by impregnating a reinforcing material such as glass, aramid, or LCP fiber woven or nonwoven fabric with a thermosetting resin such as epoxy resin or polyimide resin. The metal film 202 is, for example, a Cu film. The metal film 203 is formed to cover the side surface of the metal film 202. The metal film 203 is formed to cover the upper or lower surface of the substrate 201 that is exposed from the metal film 202. The metal film 203 is, for example, a Cu plating film. Note that the material of the metal film 202 is not limited to copper, and may be a metal other than copper. The material of the metal film 203 is not limited to copper, and may be a metal other than copper.

[0059] In this embodiment, although structures corresponding to a part of the wiring board 10 are formed on both the upper and lower surfaces of the support 200, for the sake of simplicity, only the structure formed on the upper surface of the support 200 will be illustrated and described.

[0060] Next, in the process shown in Figure 5, a resist layer 210 having opening patterns 210X and 210Y is formed on the upper surface of the metal film 203 of the support 200. The opening pattern 210X is formed to expose the upper surface of the metal film 203 in the portion corresponding to the formation area of ​​the wiring layer 20 shown in Figure 2. The opening pattern 210Y is formed to expose the upper surface of the metal film 203 in the portion corresponding to the mounting area of ​​the electronic component 50 shown in Figure 2. As the material for the resist layer 210, for example, a material that is resistant to plating in the next plating process can be used. As the material for the resist layer 210, for example, a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist or liquid resist such as a novolac resin or acrylic resin) can be used. When using a photosensitive dry film resist, the dry film is laminated to the upper surface of the metal film 203 by thermocompression, and then the dry film is patterned by photolithography to form the resist layer 210 having the opening pattern 210X. Furthermore, when using liquid photoresist, the resist layer 210 can be formed through a similar process.

[0061] Next, using the resist layer 210 as a plating mask, an electrolytic plating method is applied to the metal film 203, utilizing the metal film 203 as the plating power supply layer. More specifically, an electrolytic plating method, in this case an electrolytic nickel plating method, is applied to the upper surface of the metal film 203 exposed from the opening patterns 210X and 210Y of the resist layer 210. As a result, a metal layer 211 is formed on the upper surface of the metal film 203 exposed from the opening pattern 210X, and a metal layer 212 is formed on the upper surface of the metal film 203 exposed from the opening pattern 210Y. At this time, the upper surfaces of metal layer 211 and metal layer 212 are formed on the same plane. Note that the material of metal layers 211 and 212 may be a conductive material other than nickel, as long as it can be selectively etched away from the wiring layer 20 (see Figure 2) formed in a later process.

[0062] Next, in the step shown in Figure 6, a resist layer 213 is formed to cover the entire upper surface of the metal layer 212 formed within the opening pattern 210Y. As the material for the resist layer 213, for example, a material that is resistant to plating in the subsequent plating process can be used. As the material for the resist layer 213, for example, the same material as the resist layer 210 can be used. The resist layer 213 can be formed, for example, by the same method as the resist layer 210.

[0063] Next, using the resist layers 210 and 213 as a plating mask, an electrolytic plating method, specifically electrolytic Cu plating, is applied to the metal layer 211, utilizing the metal film 203 as the plating power supply layer. This forms a wiring layer 20 on the metal layer 211 formed within the opening pattern 210X. At this time, the mounting surface 20A (the bottom surface in this case) of the wiring layer 20 is formed to be in contact with the top surface of the metal layer 211. Furthermore, the wiring layer 20 is not formed on the metal layer 212 covered by the resist layer 213.

[0064] Next, in the process shown in Figure 7, the resist layers 210 and 213 shown in Figure 6 are removed using an alkaline stripping solution (for example, an organic amine-based stripping solution, caustic soda, acetone, or ethanol).

[0065] Next, in the process shown in Figure 8, an insulating layer 30 is formed on the upper surface of the metal film 203 to cover the wiring layer 20. At this time, the insulating layer 30 is formed to cover the entire side surfaces of the metal layers 211 and 212, as well as the entire side surfaces of the wiring layer 20. The insulating layer 30 is also formed to cover the entire upper surface of the metal layer 212. When a resin film is used as the insulating layer 30, for example, the resin film is laminated onto the upper surface of the metal film 203. Then, the insulating layer 30 can be formed by heat-treating the resin film at a temperature above the curing temperature (for example, around 130°C to 200°C) while pressing it down and curing it. As the resin film, for example, a thermosetting resin film mainly composed of epoxy resin can be used. When a liquid or paste-like insulating resin is used as the insulating layer 30, the liquid or paste-like insulating resin is applied to the upper surface of the metal film 203 by a spin-coating method or the like. Then, by heat-treating the applied insulating resin at a temperature above the curing temperature to cure it, an insulating layer 30 can be formed. As the liquid or paste-like insulating resin, for example, a thermosetting resin mainly composed of epoxy resin can be used.

[0066] Next, through-holes 30X are formed at predetermined locations in the insulating layer 30 so that a portion of the upper surface of the wiring layer 20 is exposed. The through-holes 30X can be formed, for example, by a laser processing method using a CO2 laser or a UV-YAG laser.

[0067] Next, if the through-hole 30X is formed by laser processing, a desmear treatment is performed to remove the resin smear adhering to the exposed surface of the wiring layer 20 exposed at the bottom of the through-hole 30X. Examples of desmear treatments in this step include wet desmear treatment using a potassium permanganate solution or the like.

[0068] Next, in the process shown in Figure 9, a seed layer (not shown) is formed so as to cover the entire upper surface of the insulating layer 30 and the entire inner surface of the through-hole 30X. The seed layer can be formed, for example, by sputtering or electroless plating. Subsequently, a resist layer 214 having an opening pattern 214X at a predetermined location is formed on the seed layer by performing the same process as shown in Figure 5. The opening pattern 214X is formed so as to expose the upper surface of the seed layer in the area corresponding to the formation region of the wiring layer 21. Then, using the resist layer 214 as a plating mask, an electroplating method is applied to the seed layer, using the seed layer as a plating power supply layer. As a result, via wiring that fills the through-hole 30X is formed, and the wiring layer 21 is formed within the opening pattern 214X.

[0069] Next, in the process shown in Figure 10, the resist layer 214 shown in Figure 9 is removed using an alkaline stripping solution (for example, an organic amine-based stripping solution, caustic soda, acetone, or ethanol). After that, the unnecessary seed layer is removed by etching.

[0070] Next, in the process shown in Figure 11, the same process as in Figures 8 to 10 is performed to sequentially laminate the insulating layer 31 and the wiring layer 22 on the upper surface of the insulating layer 30. Furthermore, an insulating layer 32 that covers the wiring layer 22 is laminated on the upper surface of the insulating layer 31. At this time, the insulating layer 32 is formed to cover the entire upper surface and the entire side surface of the wiring layer 22.

[0071] Next, in the process shown in Figure 12, a cavity 40 is formed that is recessed from the upper surface of the insulating layer 32 toward the metal layer 212, such that a portion of the upper surface of the metal layer 212 is exposed. The cavity 40 is formed so as to penetrate the insulating layers 30, 31, and 32 in the thickness direction. The cavity 40 can be formed by laser processing, for example, using a CO2 laser or a UV-YAG laser.

[0072] Subsequently, if the cavity 40 is formed by laser processing, desmear treatment is performed to remove the resin smear adhering to the exposed surface of the metal layer 212 exposed at the bottom of the cavity 40.

[0073] Next, in the process shown in Figure 13, an electronic component 50 having a main body 51, a first electrode 52, a second electrode 53, and a through electrode 54 is prepared. Subsequently, using a mounter, the electronic component 50 is fixed to the upper surface of the metal layer 212 exposed from the cavity 40 via an adhesive insulating resin 55. At this time, the insulating resin 55 is formed to cover the entire side surface of the first electrode 52. The lower surface of the insulating resin 55 is bonded to the upper surface of the metal layer 212. The mounting surface 52A (in this case, the lower surface) of the first electrode 52 is in contact with the upper surface of the metal layer 212. As a result, the mounting surface 52A of the first electrode 52 is provided on the same plane as the mounting surface 20A of the wiring layer 20. As the insulating resin 55, for example, an adhesive in which a filler is mixed into a base resin such as an epoxy resin can be used.

[0074] Next, in the process shown in Figure 14, an insulating layer 33 is formed to cover the upper surface of the insulating layer 32 and fill the cavity 40 by performing the same process as in Figure 8. The insulating layer 33 is formed to cover the entire side surface of the insulating resin 55 and the entire surface of the electronic component 50 exposed from the insulating resin 55. The insulating layer 33 is formed to cover the entire upper surface of the metal layer 212 exposed from the insulating resin 55.

[0075] Next, in the process shown in Figure 15, through-holes VH1 are formed at predetermined locations in the insulating layers 32 and 33, penetrating the insulating layers 32 and 33 in the thickness direction and exposing a portion of the upper surface of the wiring layer 22. The through-holes VH1 can be formed, for example, by a laser processing method using a CO2 laser. In addition, through-holes VH2 are formed at predetermined locations in the insulating layer 33, penetrating the insulating layer 33 in the thickness direction and exposing a portion of the upper surface of the second electrode 53. The through-holes VH2 can be formed, for example, by a laser processing method using a CO2 laser. The through-holes VH2 may be formed in the same process as the through-holes VH1, or in a separate process from the through-holes VH1.

[0076] Next, in the process shown in Figure 16, a via wiring that fills the through hole VH1 is formed by performing the same process as in Figures 9 and 10, and a wiring layer 23 that is electrically connected to the wiring layer 22 via the via wiring is laminated on the upper surface of the insulating layer 33. In addition, a via wiring that fills the through hole VH2 is formed, and a wiring layer 23 that is electrically connected to the second electrode 53 via the via wiring is laminated on the upper surface of the insulating layer 33.

[0077] Next, in the process shown in Figure 17, the insulating layer 34 and the wiring layer 24 are sequentially laminated on the upper surface of the insulating layer 33 by performing the same process as shown in Figures 8 to 10. Next, in the process shown in Figure 18, a solder resist layer 35 is formed on the upper surface of the insulating layer 34, having an opening 35X for exposing a portion of the upper surface of the wiring layer 24 as an external connection pad. The solder resist layer 35 can be formed, for example, by laminating a photosensitive solder resist film or by applying a liquid solder resist and then patterning the resist into the required shape.

[0078] Next, the outer peripheral region of the support 200 is cut using a slicer or the like. The outer peripheral region of the support 200 is the part that protrudes outward from the outer surfaces of the insulating layers 30, 31, 32, 33, and 34 and the outer surface of the solder resist layer 35. Subsequently, the cut support 200 is removed. First, the substrate 201 of the support 200 is removed. For example, the substrate 201 is mechanically peeled off from the metal films 202 and 203. Next, the metal films 202 and 203 are removed. For example, the metal films 202 and 203, which are Cu films, are selectively etched off from the metal layers 211 and 212, which are Ni layers. As a result, the lower surface of the insulating layer 30 and the lower surface of the metal layers 211 and 212 are exposed to the outside, as shown in Figure 19.

[0079] Next, the metal layers 211 and 212 are removed. The metal layers 211 and 212 are selectively etched away, for example, from the wiring layer 20 and the first electrode 52. As a result, as shown in Figure 20, the mounting surface 20A (in this case, the bottom surface) of the wiring layer 20, the mounting surface 52A (in this case, the bottom surface) of the first electrode 52, the bottom surface of the insulating resin 55, and the bottom surface of the insulating layer 33 in the portion filled in the cavity 40 are exposed to the outside. At this time, the mounting surface 20A of the wiring layer 20 and the mounting surface 52A of the first electrode 52 are located on the same plane.

[0080] Next, in the process shown in Figure 21, the insulating layers 30, 33 and insulating resin 55 are thinned from the bottom side. That is, the insulating layers 30, 33 and insulating resin 55, which are exposed by the removal of the metal layers 211, 212 (see Figure 19), are thinned from the bottom side. Specifically, the insulating layers 30, 33 and insulating resin 55 are thinned from the bottom side so that the lower parts of the wiring layer 20 and the first electrode 52 protrude below the bottom surface of the insulating layers 30, 33 and insulating resin 55. The bottom surface of the thinned insulating layer 30, the bottom surface of the thinned insulating layer 33, and the bottom surface of the thinned insulating resin 55 are formed flush, for example. The thinning of the insulating layers 30, 33 and insulating resin 55 can be carried out, for example, by ashing (dry etching using oxygen plasma).

[0081] Next, in the process shown in Figure 22, a surface treatment layer 60 is formed on the mounting surface 20A of the wiring layer 20 and the mounting surface 52A of the first electrode 52, and a surface treatment layer 61 is formed on the upper surface of the wiring layer 24 exposed through the opening 35X of the solder resist layer 35. The surface treatment layers 60 and 61 can be formed, for example, by electroless plating.

[0082] The wiring board 10 of this embodiment can be manufactured through the above manufacturing process. (Method of manufacturing semiconductor device 1) Next, the manufacturing method of the semiconductor device 1 will be described with reference to Figures 23 to 25. Note that in Figures 23 to 25, the wiring board 10 shown in Figure 22 is shown rotated by 180°.

[0083] First, in the process shown in Figure 23, multiple (three in this embodiment) semiconductor chips 110 are mounted on the wiring board 10. Specifically, three semiconductor chips 110 are flip-chip mounted on the wiring layer 20 and the first electrode 52 of the wiring board 10. More specifically, each semiconductor chip 110 is electrically connected to the wiring layer 20 and the first electrode 52 via a bonding member 62 and a surface treatment layer 60. Each semiconductor chip 110 is mounted on the wiring board 10 so as to straddle the wiring layer 20 and the first electrode 52. At this time, the mounting surface 20A of the wiring layer 20 (top surface in Figure 23) and the mounting surface 52A of the first electrode 52 (top surface in Figure 23) are formed on the same plane. That is, the heights of the mounting surface 20A of the wiring layer 20 and the mounting surface 52A of the first electrode 52 are the same. Therefore, the mountability of the semiconductor chips 110 on the wiring layer 20 and the first electrode 52 of the wiring board 10 can be improved.

[0084] Next, in the process shown in Figure 24, underfill resin 120 is filled into the gap between the semiconductor chip 110 and the wiring board 10, and then the underfill resin 120 is cured. Furthermore, in the process shown in Figure 24, a substrate 70 containing electronic components 76 is manufactured. Since the substrate 70 can be manufactured by known manufacturing methods, a detailed explanation is omitted here. A bonding member 99 is formed on the wiring layer 97 exposed through the opening 98X of the solder resist layer 98 of the substrate 70.

[0085] Next, a wiring board 10 on which a semiconductor chip 110 is mounted is placed above the substrate 70. At this time, the wiring board 10 is positioned so that the solder resist layer 35 faces the solder resist layer 98 of the substrate 70. Also, the wiring board 10 is positioned so that each surface treatment layer 61 faces each bonding member 99.

[0086] Next, in the process shown in Figure 25, the wiring board 10 is mounted on the substrate 70. More specifically, the surface treatment layer 61 of the wiring board 10 is bonded to the bonding member 99 of the substrate 70. As a result, the wiring layer 24 of the wiring board 10 and the wiring layer 97 of the substrate 70 are electrically connected to each other via the surface treatment layer 61 and the bonding member 99.

[0087] Next, underfill resin 100 (Figure 3) is filled into the gap between the bonded substrate 70 and the wiring board 10, and then the underfill resin 100 is cured. By following the above manufacturing process, the semiconductor device 1 shown in Figure 3 can be manufactured.

[0088] In this embodiment, the wiring layer 20 is an example of a first wiring layer, the wiring layer 23 is an example of a second wiring layer, the insulating layer 30 is an example of a first insulating layer, the insulating layers 30, 31, and 32 are examples of N-layer insulating layers, and the insulating layer 33 is an example of a filled insulating layer. Also, the electronic component 50 is an example of a first electronic component, the semiconductor chip 110 is an example of a second electronic component, the mounting surface 20A is an example of a first mounting surface, the mounting surface 52A is an example of a second mounting surface, and the support 200 and metal layers 211 and 212 are examples of supports.

[0089] (Effects of the first embodiment) Next, the effects and advantages of the first embodiment will be explained. (1-1) The wiring layer 20 has a mounting surface 20A that is exposed from the insulating layer 30. The first electrode 52 of the electronic component 50 has a mounting surface 52A that is exposed from the insulating layer 33 that fills the cavity 40. The mounting surface 52A is provided on the same plane as the mounting surface 20A. With this configuration, when a semiconductor chip 110 is mounted on the mounting surface 20A and the mounting surface 52A, the heights of the mounting surfaces 20A and 52A on which the semiconductor chip 110 is mounted are the same. For this reason, the mountability of the semiconductor chip 110 on the wiring layer 20 and the first electrode 52 of the wiring board 10 can be improved compared to the case where the mounting surface 20A and the mounting surface 52A are provided on different planes.

[0090] (1-2) The wiring board 10 has the form of a coreless board. Therefore, the entire wiring board 10 can be made thinner compared to a structure with a core board. (1-3) The wiring layer 20 is formed to protrude downward from the lower surface (third surface) of the insulating layer 30 facing downward (first direction), and the first electrode 52 is formed to protrude downward from the lower surface (second surface) of the insulating resin 55 facing downward. With this configuration, the wiring layer 20 and the first electrode 52 are formed to extend in a columnar shape downward from the lower surfaces of the insulating layer 30 and the insulating resin 55. This makes it easy to meet the demand for miniaturization of the wiring layer 20 and the first electrode 52 that accompanies the high integration and high functionality of semiconductor chips 110, for example.

[0091] (Second Embodiment) The second embodiment will be described below with reference to Figures 26 to 39. The following description will focus on the differences from the first embodiment. Components identical to those shown in Figures 1 to 25 will be denoted by the same reference numerals, and detailed explanations of each of these elements will be omitted.

[0092] (Structure of wiring board 10A) As shown in Figure 26, the wiring board 10A has a wiring structure 11A, one or more (two in this embodiment) cavities 40 formed in the wiring structure 11A, and one or more (two in this embodiment) electronic components 50 arranged in the cavities 40. The wiring board 10A is a wiring board with built-in electronic components 50.

[0093] (Wiring structure 11A structure) As shown in Figure 27, in the wiring structure 11A of this embodiment, the lower surface of the insulating layer 30, the mounting surface 20A of the wiring layer 20, the lower surface of the insulating layer 33 in the portion filled in the cavity 40, the lower surface of the insulating resin 55, and the mounting surface 52A of the first electrode 52 are formed flush with each other. Thus, in the wiring structure 11A, the mounting surface 20A of the wiring layer 20 (here, the lower surface) and the mounting surface 52A of the first electrode 52 (here, the lower surface) are formed on the same plane.

[0094] In this embodiment, the insulating layer 30 is formed to cover the upper surface of the wiring layer 20 and the entire side surface of the wiring layer 20. In other words, the entire wiring layer 20 in this embodiment is embedded in the insulating layer 30. The insulating layer 30 is formed to expose the entire mounting surface 20A of the wiring layer 20.

[0095] In this embodiment, the insulating resin 55 is formed to cover the entire side surface of the first electrode 52. In other words, the entire first electrode 52 in this embodiment is embedded in the insulating resin 55. The insulating resin 55 is formed to expose the entire mounting surface 52A of the first electrode 52.

[0096] The wiring structure 11A has a solder resist layer 36 laminated on the lower surface of the insulating layer 30. The solder resist layer 36 is formed on the lower surface of the insulating layer 30 so as to cover a part of the mounting surface 20A of the wiring layer 20 and a part of the mounting surface 52A of the first electrode 52. The solder resist layer 36 is the outermost insulating layer provided on the outermost layer (in this case, the bottom layer) of the wiring substrate 10A. The thickness from the mounting surface 20A of the wiring layer 20 to the lower surface of the solder resist layer 36 can be, for example, about 12 μm to 50 μm. The solder resist layer 36 is an insulating layer mainly composed of a photosensitive resin. As the material for the solder resist layer 36, for example, a photosensitive insulating resin mainly composed of a phenolic resin or a polyimide resin can be used.

[0097] The solder resist layer 36 has an opening 36X that exposes a portion of the mounting surface 20A of the wiring layer 20, and an opening 36Y that exposes a portion of the mounting surface 52A of the first electrode 52. The openings 36X and 36Y are formed in a tapered shape, for example, in Figure 27, where the diameter (opening width) decreases from the bottom (bottom surface of the solder resist layer 36) to the top. The openings 36X and 36Y are formed in a frustoconical shape, for example, where the opening diameter at the lower opening end is larger than the opening diameter at the upper opening end.

[0098] A surface treatment layer 60 is formed on the mounting surface 20A exposed from the opening 36X and on the mounting surface 52A exposed from the opening 36Y, if necessary. (Manufacturing method for wiring board 10A) Next, the manufacturing method of the wiring board 10A will be described. For the sake of clarity, the parts that will ultimately become components of the wiring board 10A will be labeled with their final component reference numerals.

[0099] First, in the process shown in Figure 28, a support 220 is prepared. The support 220 has a structure in which a metal foil 222 and a metal film 223 are sequentially laminated on both the upper and lower surfaces of a substrate 221. The substrate 221 is a prepreg made by impregnating a reinforcing material such as glass, aramid, or LCP fiber woven or nonwoven fabric with a thermosetting resin such as epoxy resin or polyimide resin. The metal foil 222 is formed to cover the entire upper or lower surface of the substrate 221, for example. The metal foil 222 is, for example, copper foil. The metal film 223 is formed to cover the entire upper or lower surface of the metal foil 222, for example. The metal film 223 is, for example, a nickel (Ni) plated film. Note that the material of the metal foil 222 is not limited to copper, and may be a metal other than copper. Furthermore, the material of the metal film 223 may be a metal other than nickel, as long as it is a conductive material that can be selectively etched away from the wiring layer 20 (see Figure 27) formed in a later process.

[0100] In this embodiment, the manufacturing method involves forming structures corresponding to a part of the wiring board 10A on both the upper and lower surfaces of the support 220. However, for the sake of simplicity, only the structure formed on the upper surface of the support 220 will be illustrated and described.

[0101] Next, in the process shown in Figure 29, a resist layer 210 having an opening pattern 210X is formed on the upper surface of the metal film 223 of the support 220 by performing the same process as in Figure 5.

[0102] Next, electroplating, specifically electrolytic Cu plating, is applied to the upper surface of the metal film 223 exposed through the opening pattern 210X of the resist layer 210. This forms a wiring layer 20 on the upper surface of the metal film 223 exposed through the opening pattern 210X. At this time, the mounting surface 20A (in this case, the lower surface) of the wiring layer 20 is formed to be in contact with the upper surface of the metal film 223.

[0103] Next, in the process shown in Figure 30, the resist layer 210 shown in Figure 29 is removed with an alkaline stripping solution by performing the same process as in Figure 7. Next, in the process shown in Figure 31, the same process as in Figures 8 to 10 is performed to sequentially laminate the insulating layer 30, the wiring layer 21, the insulating layer 31, the wiring layer 22, and the insulating layer 32 onto the upper surface of the metal film 223.

[0104] Next, in the process shown in Figure 32, a cavity 40 is formed that is recessed from the upper surface of the insulating layer 32 toward the support 220, by performing the same process as in Figure 12, such that a portion of the upper surface of the metal film 223 is exposed. The cavity 40 is formed so as to penetrate the insulating layers 30, 31, and 32 in the thickness direction.

[0105] Next, in the process shown in Figure 33, the same process as in Figure 13 is performed to fix the electronic component 50 to the upper surface of the metal film 223 exposed from the cavity 40 via an adhesive insulating resin 55 using a mounter. At this time, the mounting surface 52A of the first electrode 52 is in contact with the upper surface of the metal film 223. As a result, the mounting surface 52A of the first electrode 52 is placed on the same plane as the mounting surface 20A of the wiring layer 20.

[0106] Next, in the process shown in Figure 34, the same process as in Figure 8 is performed to cover the upper surface of the insulating layer 32 and to form an insulating layer 33 that fills the cavity 40.

[0107] Next, by performing the same steps as shown in Figures 8 to 10, the wiring layer 23, the insulating layer 34, and the wiring layer 24 are sequentially laminated on the upper surface of the insulating layer 33. Next, in the process shown in Figure 35, a first protective portion 231 is formed on the upper surface of the wiring layer 24 to cover the upper surface of the wiring layer 24, and a second protective portion 232 is formed on the upper surface of the insulating layer 34 to cover the upper surface of the first protective portion 231. The second protective portion 232 is formed to cover the upper surface of the insulating layer 34 that is located outside the first protective portion 231. The second protective portion 232 is formed to cover the entire side surface of the outermost wiring layer 24 in the planar direction, and also to cover the entire side surface of the first protective portion 231.

[0108] Next, the substrate 221 of the support 220 is removed. For example, the substrate 221 is mechanically peeled off from the metal foil 222. Next, the metal foil 222 is removed. For example, the metal foil 222 is selectively etched away from the metal film 223. Note that the wiring layer 24 is covered by the first protective part 231 and the second protective part 232, and is therefore not removed in this etching step.

[0109] Next, the metal film 223 is removed. For example, the metal film 223 is removed by etching. The metal film 223 is selectively etched off with respect to the wiring layer 20, for example. As a result, as shown in Figure 36, the lower surfaces of the insulating layers 30, 33, the mounting surface 20A of the wiring layer 20, the lower surface of the insulating resin 55, and the mounting surface 52A of the first electrode 52 are exposed to the outside. At this time, the lower surfaces of the insulating layers 30, 33, the mounting surface 20A of the wiring layer 20, the lower surface of the insulating resin 55, and the mounting surface 52A of the first electrode 52, which were in contact with the upper surface of the metal film 223 (see Figure 35), are formed in a shape that follows the upper surface of the metal film 223 (in this case, the flat surface). Therefore, the lower surfaces of the insulating layers 30, 33, the mounting surface 20A of the wiring layer 20, the lower surface of the insulating resin 55, and the mounting surface 52A of the first electrode 52 are formed flush with each other.

[0110] Subsequently, the first protective section 231 and the second protective section 232 shown in Figure 35 are removed. For example, the first protective section 231 and the second protective section 232 are mechanically peeled off from the insulating layer 34. Next, in the process shown in Figure 37, a solder resist layer 36 having openings 36X and 36Y is formed on the lower surface of the insulating layer 30, and a solder resist layer 35 having an opening 35X is formed on the upper surface of the insulating layer 34 by performing the same process as in Figure 18.

[0111] Next, in the process shown in Figure 38, a surface treatment layer 60 is formed on the mounting surfaces 20A and 52A exposed from the openings 36X and 36Y, and a surface treatment layer 61 is formed on the upper surface of the wiring layer 24 exposed from the opening 35X, by performing the same process as in Figure 22.

[0112] The wiring board 10A of this embodiment can be manufactured through the above manufacturing process. As shown in Figure 39, one or more (three in this embodiment) semiconductor chips 110 can be mounted on the wiring board 10A. Note that in Figure 39, the wiring board 10A shown in Figure 38 is shown rotated by 180°.

[0113] Each semiconductor chip 110 is flip-chip mounted on the wiring layer 20 and the first electrode 52 of the wiring board 10A. Each semiconductor chip 110 is electrically connected to the wiring layer 20 and the first electrode 52 via a bonding member 62 and a surface treatment layer 60. Each semiconductor chip 110 is mounted on the wiring board 10A so as to straddle the wiring layer 20 and the first electrode 52. In this case, the mounting surface 20A of the wiring layer 20 (top surface in Figure 39) and the mounting surface 52A of the first electrode 52 (top surface in Figure 39) are located on the same plane. This improves the mountability of the semiconductor chip 110 on the wiring layer 20 and the first electrode 52 of the wiring board 10A.

[0114] The joining member 62 is joined to a surface treatment layer 60 formed on the mounting surfaces 20A and 52A that are exposed from the openings 36X and 36Y. The joining member 62 is formed, for example, to fill the openings 36X and 36Y.

[0115] In this embodiment, opening 36X is an example of a first opening, and opening 36Y is an example of a second opening. (Effects of the second embodiment) According to the second embodiment described above, the same effects and advantages as those of (1-1) and (1-2) of the first embodiment can be achieved.

[0116] (Third embodiment) The third embodiment will be described below with reference to Figures 40 to 53. The following description will focus on the differences from the first embodiment. Components identical to those shown in Figures 1 to 39 will be denoted by the same reference numerals, and detailed explanations of each of these elements will be omitted.

[0117] (Structure of wiring board 10B) As shown in Figure 40, the wiring board 10B has a wiring structure 11B, one or more (two in this embodiment) cavities 40 formed in the wiring structure 11B, and one or more (two in this embodiment) electronic components 50 arranged in the cavities 40. The wiring board 10B is a wiring board with built-in electronic components 50.

[0118] (Wiring structure 11B structure) As shown in Figure 41, in the wiring structure 11B of this embodiment, the mounting surface 20A of the wiring layer 20 and the mounting surface 52A of the first electrode 52 are located in positions that are recessed upward from the lower surface of the insulating layer 30. In the wiring structure 11B, the mounting surfaces 20A and 52A are located in positions that are recessed upward from the lower surface of the insulating resin 55. In other words, the lower surface of the insulating layer 30 and the lower surface of the insulating resin 55 are located in positions that are downward from the mounting surfaces 20A and 52A. In the wiring structure 11B, the mounting surface 20A and the mounting surface 52A are located on the same plane.

[0119] In this embodiment, the insulating layer 30 is formed to cover the upper surface of the wiring layer 20 and the entire side surface of the wiring layer 20. An opening 30Y is formed on the lower surface of the insulating layer 30, which is recessed upward from the lower surface of the insulating layer 30 and exposes the mounting surface 20A of the wiring layer 20. The opening 30Y is formed to expose the entire mounting surface 20A of the wiring layer 20. The inner wall surface of the opening 30Y is formed, for example, to extend perpendicularly to the lower surface of the insulating layer 30.

[0120] In this embodiment, the insulating resin 55 is formed to cover the entire side surface of the first electrode 52. An opening 55X is formed on the lower surface of the insulating resin 55, which is recessed upward from the lower surface of the insulating resin 55 and exposes a part of the mounting surface 52A of the first electrode 52. The opening 55X is formed in a tapered shape, for example, in Figure 41, where the diameter (opening width) decreases from the lower side (lower surface side of the insulating resin 55) to the upper side. The opening 55X is formed in a frustoconical shape, for example, where the opening diameter at the lower opening end is larger than the opening diameter at the upper opening end.

[0121] The insulating layer 33 in the portion filled in the cavity 40 is formed to cover the entire side surface of the insulating resin 55. The lower surface of the insulating layer 33 in the portion filled in the cavity 40 is located below the mounting surface 20A of the wiring layer 20 and the mounting surface 52A of the first electrode 52.

[0122] In the wiring structure 11B, the lower surface of the insulating layer 30, the lower surface of the insulating layer 33 in the portion filled in the cavity 40, and the lower surface of the insulating resin 55 are formed flush with each other. (Manufacturing method for wiring board 10B) Next, the manufacturing method of the wiring board 10B will be described. For the sake of clarity, the parts that will ultimately become components of the wiring board 10B will be labeled with their final component reference numerals.

[0123] First, in the process shown in Figure 42, a support 200 is prepared. Subsequently, by performing the same process as shown in Figure 5, a resist layer 210 having an opening pattern 210X is formed on the upper surface of the metal film 203 of the support 200.

[0124] Next, an electroplating method, specifically electrolytic nickel plating, is applied to the upper surface of the metal film 203 exposed through the opening pattern 210X of the resist layer 210. This forms a metal layer 211 on the upper surface of the metal film 203 exposed through the opening pattern 210X. Subsequently, an electroplating method, specifically electrolytic copper plating, is applied to the metal layer 211, utilizing the metal film 203 as a plating power supply layer. This forms a wiring layer 20 on the metal layer 211. At this time, the mounting surface 20A (the lower surface in this case) of the wiring layer 20 is formed to be in contact with the upper surface of the metal layer 211.

[0125] Next, in the process shown in Figure 43, the resist layer 210 shown in Figure 42 is removed with an alkaline stripping solution by performing the same process as in Figure 7. Next, in the process shown in Figure 44, the same process as in Figures 8 to 10 is performed to sequentially laminate the insulating layer 30, the wiring layer 21, the insulating layer 31, the wiring layer 22, and the insulating layer 32 onto the upper surface of the metal film 203.

[0126] Next, in the process shown in Figure 45, a cavity 40 is formed that is recessed from the upper surface of the insulating layer 32 toward the support 200, by performing the same process as in Figure 12, such that a portion of the upper surface of the metal film 203 is exposed. The cavity 40 is formed so as to penetrate the insulating layers 30, 31, and 32 in the thickness direction.

[0127] Next, in the process shown in Figure 46, the same process as in Figure 13 is performed to fix the electronic component 50 to the upper surface of the metal film 203 exposed from the cavity 40 via an adhesive insulating resin 55 using a mounter. At this time, the insulating resin 55 is formed to cover the entire side surface of the first electrode 52 and the entire mounting surface 52A of the first electrode 52. In this process, the thickness of the insulating resin 55 from the mounting surface 52A of the first electrode 52 to the lower surface of the insulating resin 55 is adjusted so that the mounting surface 52A of the first electrode 52 is placed on the same plane as the mounting surface 20A of the wiring layer 20.

[0128] Next, in the process shown in Figure 47, the same process as in Figure 8 is performed to cover the upper surface of the insulating layer 32 and to form an insulating layer 33 that fills the cavity 40. The insulating layer 33 is formed to cover the entire side surface of the insulating resin 55.

[0129] Next, by performing the same steps as shown in Figures 8 to 10, the wiring layer 23, the insulating layer 34, and the wiring layer 24 are sequentially laminated on the upper surface of the insulating layer 33. Next, in the process shown in Figure 48, a solder resist layer 35 having an opening 35X is formed on the upper surface of the insulating layer 34 by performing the same process as in Figure 18.

[0130] Next, the outer periphery of the support 200 is cut using a slicer or the like. Then, the support 200 is removed by performing the same steps as shown in Figures 18 and 19. As a result, as shown in Figure 49, the lower surfaces of the insulating layers 30 and 33, the insulating resin 55, and the metal layer 211 are exposed to the outside. At this time, the lower surfaces of the insulating layers 30 and 33, the insulating resin 55, and the metal layer 211 are formed flush with each other.

[0131] Next, in the process shown in Figure 50, the metal layer 211 is removed. This creates an opening 30Y on the underside of the insulating layer 30 that exposes the entire mounting surface 20A of the wiring layer 20. At this time, the inner wall surface of the opening 30Y is formed in a shape that follows the side surface of the metal layer 211 (see Figure 49).

[0132] Next, in the process shown in Figure 51, an opening 55X is formed at a predetermined location in the insulating resin 55 so that a portion of the mounting surface 52A of the first electrode 52 is exposed. The opening 55X can be formed by a laser processing method, for example, using a CO2 laser or a UV-YAG laser.

[0133] Next, in the process shown in Figure 52, a surface treatment layer 60 is formed on the mounting surfaces 20A and 52A exposed from the openings 30Y and 55X, and a surface treatment layer 61 is formed on the upper surface of the wiring layer 24 exposed from the opening 35X, by performing the same process as in Figure 22.

[0134] The wiring board 10B of this embodiment can be manufactured through the above manufacturing process. As shown in Figure 53, one or more (three in this embodiment) semiconductor chips 110 can be mounted on the wiring board 10B. Note that in Figure 53, the wiring board 10B shown in Figure 52 is shown rotated by 180°.

[0135] Each semiconductor chip 110 is flip-chip mounted on the wiring layer 20 and the first electrode 52 of the wiring substrate 10B. Each semiconductor chip 110 is electrically connected to the wiring layer 20 and the first electrode 52 via a bonding member 62 and a surface treatment layer 60. Each semiconductor chip 110 is mounted on the wiring substrate 10B so as to straddle the wiring layer 20 and the first electrode 52. In this case, the mounting surface 20A of the wiring layer 20 (top surface in Figure 53) and the mounting surface 52A of the first electrode 52 (top surface in Figure 53) are formed on the same plane. This improves the mountability of the semiconductor chip 110 on the wiring layer 20 and the first electrode 52 of the wiring substrate 10B.

[0136] The joining member 62 is joined to a surface treatment layer 60 formed on the wiring layer 20 exposed from the opening 30Y. The joining member 62 is formed, for example, to fill the opening 30Y. The joining member 62 is joined to a surface treatment layer 60 formed on the first electrode 52 exposed from the opening 55X. The joining member 62 is formed, for example, to fill the opening 55X.

[0137] In this embodiment, opening 30Y is an example of a third opening, and opening 55X is an example of a fourth opening. (Effects of the third embodiment) According to the third embodiment described above, the same effects and advantages as those of (1-1) and (1-2) of the first embodiment can be achieved.

[0138] (Example of change) Each of the above embodiments can be implemented with the following modifications. Each of the above embodiments and the following modifications can be combined with each other to the extent that they do not contradict each other technically.

[0139] The structures of the wiring boards 10, 10A, and 10B in each of the above embodiments can be modified as appropriate. In the wiring boards 10, 10A, and 10B of the above embodiments, the number of wiring layers and insulating layers laminated on the upper surface of the insulating layer 33 for cavity filling is not particularly limited. For example, only one wiring layer 23 may be laminated on the upper surface of the insulating layer 33.

[0140] The solder resist layer 35 in each of the above embodiments may be omitted. In the wiring structures 11, 11A, and 11B of the above embodiments, the insulating layer for cavity formation is composed of three insulating layers 30, 31, and 32. However, the insulating layer for cavity formation may be composed of one insulating layer, two insulating layers, or four or more insulating layers.

[0141] The number of electronic components 50 incorporated into the wiring boards 10, 10A, and 10B of each of the above embodiments is not limited. For example, only one electronic component 50 may be incorporated into the wiring boards 10, 10A, and 10B. For example, three or more electronic components 50 may be incorporated into the wiring boards 10, 10A, and 10B.

[0142] In the wiring boards 10, 10A, and 10B of the above embodiments, one electronic component 50 is placed in each cavity 40, but this is not limited to this. For example, multiple electronic components 50 may be placed in each cavity 40.

[0143] In the above embodiment, the electronic component 50 having a through electrode 54 is embedded in the wiring boards 10, 10A, and 10B, but the embodiment is not limited to this. For example, an electronic component without a through electrode 54 may be embedded in the wiring boards 10, 10A, and 10B.

[0144] In the above embodiments, an electronic component 50 having two types of electrodes, namely a first electrode 52 and a second electrode 53, is incorporated into the wiring boards 10, 10A, and 10B, but the invention is not limited to this. For example, an electronic component having three or more types of electrodes may be incorporated into the wiring boards 10, 10A, and 10B. For example, an electronic component having only one type of electrode, namely a first electrode 52, may be incorporated into the wiring boards 10, 10A, and 10B.

[0145] The structure of the electronic components 50 built into the wiring boards 10, 10A, and 10B of each of the above embodiments can be modified as appropriate. For example, as shown in Figure 54, instead of electronic component 50, electronic component 50A may be embedded in the wiring board 10. Here, electronic component 50A is, for example, an organic interposer.

[0146] As shown in Figure 55, the electronic component 50A includes, for example, a first wiring structure 310 and a second wiring structure 320 laminated on the lower surface of the first wiring structure 310. The second wiring structure 320 is a fine wiring structure in which a wiring layer with a higher wiring density than the first wiring structure 310 is formed.

[0147] The first wiring structure 310 includes an electrode pad 311, an insulating layer 312, and a wiring layer 313. The second wiring structure 320 includes a wiring layer 321, an insulating layer 322, a wiring layer 323, an insulating layer 324, a wiring layer 325, an insulating layer 326, and an electrode pad 327. For example, copper or a copper alloy can be used as the material for the electrode pads 311, 327 and the wiring layers 313, 321, 323, and 325.

[0148] The electrode pad 311 is embedded in the insulating layer 312. The upper surface of the electrode pad 311 is formed flush with, for example, the upper surface of the insulating layer 312. The insulating layer 312 covers the lower and side surfaces of the electrode pad 311, while being formed to expose the lower surface of the electrode pad 311. The insulating layer 312 is an insulating layer mainly composed of a non-photosensitive thermosetting resin and has reinforcing members such as glass cloth. The insulating layer 312 has higher rigidity than the insulating layers 322, 324, and 326.

[0149] The insulating layers 322, 324, and 326 are, for example, insulating layers mainly composed of a photosensitive resin. As the material for insulating layers 322, 324, and 326, for example, a photosensitive insulating resin mainly composed of a phenolic resin or a polyimide resin can be used. The insulating layers 322, 324, and 326 may also contain fillers such as silica or alumina.

[0150] The wiring layer 313 is a via wiring embedded in the insulating layer 312. More specifically, the wiring layer 313 is a via wiring filled in a through-hole that penetrates the insulating layer 312 in the thickness direction and exposes a portion of the lower surface of the electrode pad 311. The wiring layer 313 is electrically connected to the electrode pad 311. The lower end surface of the wiring layer 313 is formed flush with, for example, the lower surface of the insulating layer 312.

[0151] The wiring layer 321 is laminated on the underside of the insulating layer 312 so as to connect with the lower end surface of the wiring layer 313. The wiring layer 321 and the wiring layer 313 are electrically connected but not integral.

[0152] The insulating layer 322 is formed on the lower surface of the insulating layer 312 so as to cover the wiring layer 321. The wiring layer 323 is laminated on the lower surface of the insulating layer 322. The wiring layer 323 is electrically connected to the wiring layer 321 via via wiring that penetrates the insulating layer 322 in the thickness direction. The insulating layer 324 is formed on the lower surface of the insulating layer 322 so as to cover the wiring layer 323. The wiring layer 325 is laminated on the lower surface of the insulating layer 324. The wiring layer 325 is electrically connected to the wiring layer 323 via via wiring that penetrates the insulating layer 324 in the thickness direction. The insulating layer 326 is formed on the lower surface of the insulating layer 324 so as to cover the wiring layer 325.

[0153] The electrode pad 327 is laminated on the lower surface of the insulating layer 326. The electrode pad 327 is electrically connected to the wiring layer 325 via via wiring that penetrates the insulating layer 326 in the thickness direction. The electrode pad 327 is formed to protrude downward from the lower surface of the insulating layer 326. The electrode pad 327 has a mounting surface 327A (here, the lower surface) on which electronic components such as semiconductor chips 110 (see Figure 3) are mounted. The mounting surface 327A of the electrode pad 327 is located on the same plane as the mounting surface 20A of the wiring layer 20.

[0154] A portion of the electrode pad 327, specifically the upper part of the electrode pad 327, is embedded in the insulating resin 55. In other words, the insulating resin 55 is formed to cover the side surface of the upper part of the electrode pad 327.

[0155] Furthermore, if necessary, a surface treatment layer 60 may be formed on the surface of the electrode pad 327 (mounting surface 327A and side surfaces, or mounting surface 327A only). In this modified example, the surface treatment layer 60 is formed to cover only the mounting surface 327A of the electrode pad 327.

[0156] In this modified example, the insulating layer 33 has through-holes VH3 formed at required locations, which penetrate the insulating layer 33 in the thickness direction and expose a portion of the upper surface of the electrode pad 311. The wiring layer 23 in this modified example has a wiring layer that is electrically connected to the electrode pad 311 via via wiring filled in the through-holes VH3, for example.

[0157] In this modification example, electronic component 50A is an example of a first electronic component, insulating layers 312, 322, 324, and 326 are examples of the main body, electrode pad 327 is an example of a first electrode, and electrode pad 311 is an example of a second electrode.

[0158] Even when the electronic component 50A described above is incorporated, the mounting surface 327A of the electrode pad 327 is provided on the same plane as the mounting surface 20A of the wiring layer 20, so the same effects as in the first embodiment can be achieved.

[0159] • In the wiring boards 10, 10A, and 10B of each of the above embodiments, the structure may be changed to one that incorporates only the electronic component 50A. The structure of the substrate 70 in each of the above embodiments can be modified as appropriate.

[0160] In the substrate 70 of each of the above embodiments, the number of wiring layers and insulating layers laminated on the upper surface of the core substrate 71 is not particularly limited. In the substrate 70 of each of the above embodiments, the number of wiring layers and insulating layers laminated on the lower surface of the core substrate 71 is not particularly limited.

[0161] The number of electronic components 76 to be embedded in the substrate 70 of each of the above embodiments is not limited. For example, only one electronic component 76 may be embedded in the substrate 70. For example, three or more electronic components 76 may be embedded in the substrate 70.

[0162] The number of semiconductor chips 110 mounted on the wiring boards 10, 10A, and 10B in the semiconductor device 1 of each of the above embodiments is not limited. In the above embodiments, structures corresponding to parts of the wiring boards 10, 10A, and 10B are formed on both the upper and lower surfaces of the support bodies 200 and 220, but the embodiment is not limited to this. For example, structures corresponding to parts of the wiring boards 10, 10A, and 10B may be formed on only one side of the support bodies 200 and 220. [Explanation of Symbols]

[0163] 1 Semiconductor device 10, 10A, 10B Wiring Board 20 Wiring layer (1st wiring layer) 20A mounting surface (first mounting surface) 23 Wiring layer (2nd wiring layer) 30. Insulating layer (first insulating layer) 30Y opening (3rd opening) 31,32 Insulating layer 33. Insulating layer (filled insulating layer) 36 Solder Resist Layers 36X opening (1st opening) 36Y opening (second opening) 40 Cavity 50, 50A Electronic Components (First Electronic Component) 51 Main body 52 1st electrode 52A Mounting surface (second mounting surface) 53 2nd electrode 55 Insulating resin 55X opening (4th opening) 110 Semiconductor chips (second electronic components) 200,220 Support 211,212 metal layer 311 Electrode pad (second electrode) 327 Electrode pad (first electrode) 327A mounting surface (second mounting surface)

Claims

1. A wiring board having the form of a coreless substrate, The first wiring layer and An insulating layer comprising N layers (where N is a natural number of 1 or more) including a first insulating layer formed to cover the first wiring layer, A cavity formed so as to penetrate the insulating layer of the N layer in the thickness direction, A first electronic component having a first electrode and disposed within the cavity, It has a filling insulating layer that fills the cavity and covers the first electronic component, The first wiring layer is provided in a position that does not overlap with the cavity in a plan view. The first wiring layer has a first mounting surface exposed from the first insulating layer, The first electrode has a second mounting surface exposed from the filling insulating layer, The second mounting surface is a wiring board provided on the same plane as the first mounting surface.

2. The first electronic component comprises a main body, a first electrode formed to protrude from a first surface of the main body in a first direction, and an insulating resin formed to cover the first surface of the main body. The insulating resin has a second surface facing the first direction, The first insulating layer has a third surface facing the first direction, The wiring board according to claim 1, wherein the second mounting surface is formed to be exposed from the second surface.

3. The first insulating layer is formed to cover a portion of the side surface of the first wiring layer, The insulating resin is formed to cover a portion of the side surface of the first electrode, The first wiring layer is formed to protrude in the first direction from the third surface, The first electrode is formed to protrude in the first direction from the second surface, The wiring board according to claim 2, wherein the first mounting surface and the second mounting surface are provided at positions that are more toward the first direction than the second surface.

4. The first insulating layer is formed to cover the entire side surface of the first wiring layer, The insulating resin is formed to cover the entire side surface of the first electrode. The wiring board according to claim 2, wherein the first mounting surface, the second mounting surface, the second surface, and the third surface are formed flush with each other.

5. The device further comprises solder resist layers laminated on the second and third surfaces, The wiring substrate according to claim 4, wherein the solder resist layer has a first opening that exposes a part of the first mounting surface and a second opening that exposes a part of the second mounting surface.

6. The first insulating layer is formed to cover the entire side surface of the first wiring layer, The insulating resin is formed to cover the entire side surface of the first electrode. The third surface is formed flush with the second surface, The wiring board according to claim 2, wherein the second and third surfaces are provided in positions that are directed more toward the first direction than the first mounting surface.

7. The first insulating layer has a third opening that exposes the entire surface of the first mounting surface, The insulating resin has a fourth opening that exposes a part of the second mounting surface, The inner wall surface of the third opening is formed to extend perpendicularly to the third surface, The wiring board according to claim 6, wherein the fourth opening is formed such that the opening width decreases as it moves from the second surface toward the second mounting surface.

8. The first electronic component has a second electrode provided on the opposite side of the first electrode, The wiring board according to claim 1, wherein the wiring board has a second wiring layer laminated on the filling insulating layer and electrically connected to the second electrode.

9. A wiring board according to any one of claims 1 to 8, The circuit board comprises a first wiring layer and a second electronic component mounted on the first electrode, The second electronic component is a semiconductor device mounted on the wiring board so as to span the first wiring layer and the first electrode.

10. The process of preparing the support, The steps include forming a first wiring layer on the support, A step of forming an N-layer (N is a natural number of 1 or more) insulating layer, which includes a first insulating layer laminated on the support so as to cover the first wiring layer, A step of forming a cavity in the insulating layer of the N layer that exposes a part of the support, A step of fixing a first electronic component having a first electrode onto the support exposed from the cavity, A step of filling the cavity and forming a filling insulating layer that covers the first electronic component, The process includes removing the support, The first wiring layer has a first mounting surface exposed from the first insulating layer, The first electrode has a second mounting surface exposed from the filling insulating layer, In the step of forming the first wiring layer, the first wiring layer is formed such that the first mounting surface is in contact with the support. A method for manufacturing a wiring board, wherein in the step of fixing the first electronic component, the first electronic component is fixed on the support such that the second mounting surface is on the same plane as the first mounting surface.

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