semiconductor devices

Abstract

This invention provides a semiconductor device that improves the performance of integrated circuits and reduces damage caused by the dicing process. [Solution] The semiconductor device includes a plurality of semiconductor dies and a bonding conductive wire 220. These semiconductor dies are located on both sides of a predetermined dicing region SL. The bonding conductive wire electrically connects these semiconductor dies, and in a top view, the bonding conductive wire includes a plurality of crack prevention corners CR located in the predetermined dicing region. The crack prevention corners of the bonding conductive wire can prevent cracks generated by the dicing process from extending along the bonding conductive wire into the semiconductor die, thereby improving product yield.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a conductive line having a crack prevention structure used for connecting a plurality of dies.

Background Art

[0002] Known integrated circuit manufacturing methods mainly use masks to define the size of each device member. Among them, device performance is often restricted by the two-dimensional chip size. Improving the performance of an integrated circuit (e.g., capacitance or computing speed) in a limited area can be achieved by reducing the feature size and / or vertically stacking multiple chips. However, this also causes problems such as a decrease in process yield and an increase in cost. As the amount of information processing increases, the requirements for the performance of integrated circuits also become higher. Generally, each chip in an integrated circuit often adopts a single die design. However, limited by various factors such as processes and product yields, it is difficult for a single die design to meet the increasingly high requirements for performance.

[0003] In order to improve the performance of an integrated circuit, at the wafer manufacturing stage, bonding metal wires are formed between a plurality of dies, and appropriate dicing is performed on the wafer to form a bonded chip including a plurality of electrically coupled dies. However, since the bonding metal wires are straight lines intersecting the dicing direction, cracks generated by the dicing process are likely to propagate into the die along the bonding metal wires, reducing the product yield.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention provides a semiconductor device capable of improving the performance of an integrated circuit and reducing damage caused by the dicing process.

Means for Solving the Problems

[0005] One embodiment of the present invention provides a semiconductor device comprising a plurality of semiconductor dies and bonding conductive wires. These semiconductor dies are located on both sides of a predetermined dicing region. The bonding conductive wires electrically connect these semiconductor dies, and in a top view, the bonding conductive wires include a plurality of crack-preventing corners located within the predetermined dicing region. [Effects of the Invention]

[0006] Based on the above, the crack-preventing corner of the bonding conductive wire of the present invention can prevent cracks generated by the dicing process from extending along the bonding conductive wire into the semiconductor die, thereby improving product yield. [Brief explanation of the drawing]

[0007] [Figure 1A] This is a schematic top view of a semiconductor device according to one embodiment of the present invention. [Figure 1B] This is a partially enlarged view of Figure 1A, representing a top view of a bonded conductive wire according to one embodiment of the present invention. [Figure 1C] This is a cross-sectional view along line A-A' in Figure 1B. [Figure 1D] This is a cross-sectional view along the line B-B' in Figure 1A. [Figure 1E] This is a partially enlarged view of Figure 1A, showing a top view of a jointed conductive wire in another embodiment of the present invention. [Figure 1F] This is a partially enlarged view of Figure 1A, showing a top view of a jointed conductive wire of yet another embodiment of the present invention. [Figure 1G] Figure 1D is a partially enlarged view, showing a cross-sectional view of a capacitor element according to one embodiment of the present invention. [Figure 2A] This is a schematic top view of a semiconductor device according to one embodiment of the present invention. [Figure 2B] This is a magnified view of a portion of Figure 2A, showing a top view of the diced junction conductive wires of a semiconductor device. [Figure 2C] This is a cross-sectional view along the line B-B' in Figure 2A. [Figure 3] This is a partial top view of a semiconductor device according to one embodiment of the present invention. [Figure 4A] This is a top view of a bonded conductive wire according to another embodiment of the present invention. [Figure 4B] Figure 4A is a top view of the bonded conductive wire after dicing. [Figure 5A] This is a top view of a jointed conductive wire according to yet another embodiment of the present invention. [Figure 5B] Figure 5A is a top view of the bonded conductive wire after dicing. [Figure 6A] This is a schematic top view of a wafer according to one embodiment of the present invention. [Figure 6B] This is a partially enlarged view of Figure 6A, showing a top view of the junction conductive wire located between the first semiconductor die and the second semiconductor die in the intermediate manufacturing process of a semiconductor device. [Figure 6C] This is a cross-sectional view along the line B-B' in Figure 6A. [Figure 7A] This is a schematic top view of a conductor device according to one embodiment of the present invention. [Figure 7B] Figure 7A is a partial cross-sectional view of a semiconductor device. [Modes for carrying out the invention]

[0008] Referring to Figures 1A to 1D, the semiconductor device of this embodiment is a wafer 10. The wafer 10 may include a plurality of semiconductor dies D and bonding conductive lines 220. These semiconductor dies D are located on both sides of a predetermined dicing region SL. The bonding conductive lines 220 electrically connect adjacent semiconductor dies D. Each semiconductor die D may include an array element 110 formed on a substrate 100 of the wafer 10, an internal connection structure 200, a sealing structure 210, and connection terminals 300. The substrate 100 may include a semiconductor substrate, a glass substrate, or a ceramic substrate, such as a silicon substrate, a silicon germanium substrate, silicon carbide, an aluminum nitride substrate, a sapphire substrate, or a combination thereof. Furthermore, the substrate 100 may include a silicon-on-insulator, but the present invention is not limited thereto.

[0009] One point to explain is that, for the sake of simplification, Figure 1A shows the electrical connection relationship between the bonding conductive wire 220 and the adjacent semiconductor die D as a straight line; however, the bonding conductive wire 220 of the present invention is not a straight line. As shown in Figure 1B, which is a partial enlargement of the dashed box DB1 area in Figure 1A, the bonding conductive wire 220 of the present invention includes multiple crack-preventing corners CR in a top view, thereby preventing cracks generated by the dicing process from extending along the bonding conductive wire 220 into the semiconductor die D, and consequently improving the yield of semiconductor devices. Furthermore, Figures 2A, 6A, and 7A are also illustrated for the same simplification reasons as above, so please understand that the bonding conductive wire 220 of the present invention is not a straight line but includes multiple crack-preventing corners CR.

[0010] The array element 110 includes a plurality of identical or similar elements, for example, a silicon capacitor array including a plurality of silicon capacitor elements, or a memory cell array including a plurality of memory cell elements, and the present invention does not limit the type of array element 110. In some embodiments, a buffer layer 102 may be included between the array element 110 and the substrate 100. A cover layer 120 may be provided on the array element 110.

[0011] In this embodiment, the array element 110 may be a silicon capacitor array, and the silicon capacitor array of a single semiconductor die D may be connected in series with the silicon capacitor array of another semiconductor die D via the bonding conductive line 220. Thereby, the breakdown voltage of the device can be increased. In another embodiment, the silicon capacitor array of a single semiconductor die D may be connected in parallel with the silicon capacitor array of another semiconductor die D via the bonding conductive line 220. Thereby, the total capacitance value of the semiconductor device can be increased. As shown in FIG. 1D, the array element 110 may include a first flat electrode 112, a capacitor element 113, and a second flat electrode 116. The capacitor element 113 is located between the first flat electrode 112 and the second flat electrode 116. It should be noted that, as described above, since the line B-B' in FIG. 1A is used to represent the electrical connection relationship with the adjacent semiconductor die D at the location corresponding to the bonding conductive line 220, the line B-B' should be understood as a cross-section based on the extending direction of the bonding conductive line 220 at the location corresponding to the bonding conductive line 220, and represents the bonding conductive line 220 extending from one semiconductor die D to another semiconductor die D in FIG. 1D. Also, based on the same reason, the locations corresponding to the bonding conductive line 220 in FIGS. 2C, 6C, and 7B that follow should also be understood as cross-sections based on the extending direction of the bonding conductive line 220.

[0012] FIG. 1G corresponds to the position of the dashed frame X in FIG. 1D. In the present embodiment, as shown in FIG. 1G, the capacitor element 113 may include a bottom electrode 1131, a dielectric layer 1132, and a top electrode 1133. The dielectric layer 1132 may be provided on the bottom electrode 1131. The capacitor element 113 may further include a stop layer 1134 provided on the first flat electrode 112, and the bottom of the bottom electrode 1131 may penetrate the stop layer 1134 and contact the first flat electrode 112. It should be noted that the capacitor element 113 in FIG. 1G is only an example, and the capacitor element 113 of the present invention can be fabricated according to various known processes and structures, and the present embodiment is not limited to the content shown in the figure. Also, the array element 110 of the present invention can be fabricated by adopting any known structure and process, and is not limited to a silicon capacitor array.

[0013] In the present embodiment, the bonding conductive line 220 may be provided on the cover layer 120, and the internal connection structure 200 may be provided above the bonding conductive line 220. The bonding conductive line 220 and the internal connection structure 200 may be located in the interlayer insulating layer 290 on the cover layer 120. In other words, the bonding conductive line 220 may be provided above the array element 110. The internal connection structure 200 may include stacked conductive layers 231, 232 and a pad layer 230, and the conductive layers 231, 232 and the pad layer 230 may be electrically connected via conductive vias. In the present embodiment, the conductive layer 231 is located between the conductive layer 232 and the pad layer 230. In some embodiments, the conductive layers 231, 232 include, for example, tungsten, aluminum, copper, an alloy of the above metals, or other suitable conductive materials. The internal connection structure 200 may be electrically connected to the array element 110 via the bonding conductive line 220, and is electrically connected to, for example, the first electrode 112 and the second electrode 116 of the array element 110. Thereby, the interconnection between the plurality of semiconductor dies D can be realized via the bonding conductive line 220, and thus the performance of the semiconductor device (for example, improvement in capacitance or improvement in electrical performance) can be improved.

[0014] The pad layer 230 is located at the top of the internal connection structure 200. In some embodiments, the pad layer 230 includes, for example, tungsten, aluminum, copper, an alloy of the above metals, or other suitable conductive material. In some embodiments, the pad layer 230 and the conductive layers 231, 232 located below it may include the same or different conductive materials.

[0015] The interlayer insulating layer 290 includes a plurality of openings 292, each of which exposes a pad layer 230. The connection terminal 300 may be located above the pad layer 230. In this embodiment, the connection terminal 300 may be embedded in the openings 292 and in contact with the pad layer 230, and may be electrically connected to the pad layer 230. In some embodiments, an under-bump metallization (UBM) layer may be further included between the connection terminal 300 and the pad layer 230, but the present invention is not limited thereto. In some embodiments, the connection terminal 300 may include microbumps, controlled collapse chip connection (C4) bumps, ball grid arrays (BGAs), or other types of connection terminals.

[0016] In some embodiments, the bonding conductive wire 220 connects semiconductor dies D arranged along the X direction, or connects semiconductor dies D arranged along the Y direction.

[0017] As shown in Figure 1C, the sealing structure 210 is located at the edge of each semiconductor die D, surrounding the array elements 110 and thereby protecting them. For example, the sealing structure 210 functions as a protective barrier, improving the mechanical strength of the semiconductor die D and preventing damage to the semiconductor die D from external forces during the manufacturing process or subsequent packaging and dicing. The sealing structure 210 also helps prevent moisture and other external contaminants from entering the array elements 110, thus avoiding any impact on the array elements 110.

[0018] Referring to Figures 1B, 1C, and 1D, the sealing structure 210 may include, but is not limited to, a first seal ring 211, an open ring 212, a second seal ring 213, a third seal ring 214, and a fourth seal ring 215, which are stacked together. In this embodiment, the bonding wire 220 passes through the opening 2121 of the open ring 212 and is electrically connected to the array element 110. In other words, the bonding wire 220 has a portion 2201 that overlaps with the vertical projections of the second seal ring 213, the third seal ring 214, and / or the fourth seal ring 215, but does not overlap with the open ring 212.

[0019] The first seal ring 211 may be located on the substrate 100. In some embodiments, the first seal ring 211 may be formed in the cover layer 120 and belong to the same conductive layer as the first electrode 112 or second electrode 116 of the array element 110. For example, the first seal ring 211 and the first electrode 112 (or second electrode 116) may be formed simultaneously by a metal layer deposition process and a patterning process. In some embodiments, the first seal ring 211 may be electrically connected to the substrate 100 below via a conductive via 103, but the present invention is not limited thereto.

[0020] The open ring 212 may be located above the first seal ring 211. In this embodiment, the open ring 212 may include a conductive layer and be electrically connected to the first seal ring 211 via a conductive via 103. In some embodiments, the bonding wire 220 may belong to the same conductive layer as the open ring 212. For example, the bonding wire 220 and the open ring 212 may be formed simultaneously by a metal layer deposition process and a patterning process, and the bonding wire 220 and the open ring 212 may be separated from each other.

[0021] The second seal ring 213 is located above the open ring 212 and may straddle the bonding conductive wire 220. In this embodiment, the second seal ring 213 may be located within the interlayer insulating layer 290. The second seal ring 213 may include a conductive layer and may be electrically connected to the open ring 212 via conductive vias 103. In some embodiments, the second seal ring 213 may belong to the same conductive layer as the conductive layer 232 of the internal connection structure 200. For example, the second seal ring 213 and the conductive layer 232 may be formed simultaneously by a metal layer deposition process and a patterning process.

[0022] The third seal ring 214 is located above the second seal ring 213 and may straddle the bonding conductive wire 220. The third seal ring 214 is electrically connected to the second seal ring 213 via conductive vias. In this embodiment, the third seal ring 214 may be located in the interlayer insulating layer 290. The third seal ring 214 may include a conductive layer and may be electrically connected to the second seal ring 213 via conductive vias 103. In some embodiments, the third seal ring 214 may belong to the same conductive layer as the conductive layer 231 of the internal connection structure 200. For example, the third seal ring 214 and the conductive layer 231 may be formed simultaneously by a metal layer deposition process and a patterning process.

[0023] The fourth seal ring 215 is located above the third seal ring 214 and may straddle the bonding conductive wire 220. In this embodiment, the fourth seal ring 215 may be located in the interlayer insulating layer 290. The fourth seal ring 215 may include a conductive layer and may be electrically connected to the third seal ring 214 via conductive vias 103. In some embodiments, the fourth seal ring 215 may belong to the same conductive layer as the pad layer 230 of the internal connection structure 200. For example, the fourth seal ring 215 and the pad layer 230 may be formed simultaneously by a metal layer deposition process and a patterning process.

[0024] In this embodiment, the predetermined dicing region SL is located between the sealing structures 210 of adjacent semiconductor dies D. In some embodiments, the thickness T2 of the interlayer insulating layer 290 at the location of the predetermined dicing region SL is less than or equal to the thickness T1 of the interlayer insulating layer 290 located inside the sealing structure 210, causing the top surface of the predetermined dicing region SL to be recessed relative to the top surface of the semiconductor die D (not shown in the figure). Furthermore, in this embodiment, by positioning the bonding conductive wire 220 in a relatively low layer of these metal layers (i.e., the metal layer between the array element 110 and the internal connection structure 200), the influence of the bonding conductive wire 220 on the surface flatness of the predetermined dicing region SL can be reduced, thus eliminating the need to perform an additional planarization process on the predetermined dicing region SL.

[0025] The bonded conductive wire 220 includes a plurality of crack-preventing corners CR located between the sealing structures 210 of two adjacent semiconductor dies D. In other words, the crack-preventing corners CR are located in a predetermined dicing region SL. More specifically, in this embodiment, the bonded conductive wire 220 may include a predetermined dicing portion 220C and crack-preventing portions 220D located on both sides of the predetermined dicing portion 220C. The direction of extension of the predetermined dicing portion 220C is different from the direction of extension of the predetermined dicing region SL in which it is located, and these crack-preventing corners CR are located in the crack-preventing portion 220D. In Figure 1B, the predetermined dicing region SL extends along a first direction E1 (also referred to as the dicing direction), and the crack-preventing portion 220D of the bonded conductive wire 210 includes a plurality of first line segments 220B parallel to the first direction E1 and a plurality of second line segments 220A perpendicular to the first direction E1. The crack-preventing corner CR is located at the boundary between the first line segment 220B and the second line segment 220A. In other words, the second line segment 220A may be connected to the first line segment 220B via the crack-preventing corner CR. In this embodiment, the crack-preventing corner CR may include a right angle. As shown in Figure 1B, the extension direction of the predetermined dicing portion 220C may be perpendicular to the first direction E1. In this embodiment, the extension direction of the portion of the connecting conductive wire 220 that penetrates the opening 2121 of the open ring 212 (i.e., the second line segment 220A) is the same as the extension direction of the predetermined dicing portion 220C.

[0026] In some embodiments, the wafer 10 may have bonding conductive wires 280 for connecting adjacent semiconductor dies D arranged diagonally.

[0027] As shown in Figure 1E, it represents a magnified view of a portion of the dashed frame DB2 in Figure 1A, and the joint conductive wire 280 of this embodiment includes a plurality of crack prevention corners CR in a top view. More specifically, the joint conductive wire 280 may include a predetermined dicing portion 280C and crack prevention portions 280D located on both sides of the predetermined dicing portion 280C. The extension direction of the predetermined dicing portion 280C is different from the extension direction of the predetermined dicing region SL in which it is located, and these crack prevention corners CR are located in the crack prevention portion 280D. Figures 1F and 1E have the same inventive concept, the difference being the number of crack prevention corners CR, and therefore the shape. Also, since the joint conductive wire 280 and the joint conductive wire 220 have the same inventive concept, the related technical details will not be explained repeatedly. The predetermined dicing portion 280C is the portion that overlaps with the dicing line SR in the dicing process.

[0028] In another embodiment of the present invention, a semiconductor device MD may be manufactured by performing a dicing process on a wafer 10. For example, a semiconductor device MD may be obtained by dicing the wafer 10 along the dashed frame shown in Figure 2A. The dicing process may be performed, for example, by a saw blade or by another suitable method. The semiconductor device MD includes a plurality of semiconductor dies D, and the number of semiconductor dies D in a single semiconductor device MD may be determined according to requirements. In this embodiment, the array element 110 may be a memory cell array including a plurality of memory cell elements. Each semiconductor die D may have any capacity size, for example, 2 GB, but is not limited thereto. Based on the present invention, the capacity of the semiconductor device MD may be flexibly adjusted by changing the dicing range. For example, the higher the required capacity, the more semiconductor dies D the semiconductor device MD may contain.

[0029] This method eliminates the need to change the design of the semiconductor die D according to different capacity requirements, thereby reducing the design cost of the semiconductor device MD. Furthermore, the present invention integrates multiple semiconductor dies D into a single semiconductor device MD by interconnecting them from one semiconductor die D to another using a bonding conductive wire 220, rather than combining multiple semiconductor dies D through a packaging method. In this way, the area of ​​the semiconductor device MD (also referred to as a chip) can be reduced.

[0030] Referring to Figures 2B and 2C, in the dicing process, the wafer 10 may be cut along the dicing line SR in a predetermined dicing region SL, leaving a cut mark SW at the edge of the semiconductor device MD. In this embodiment, the bonded conductive wire 220 in the predetermined dicing region SL located at the edge of the semiconductor device MD remains as a cut bonded conductive wire C220 after dicing. In other words, the semiconductor die D located at the edge of the semiconductor device MD includes the cut bonded conductive wire C220. The cut bonded conductive wire C220 penetrates the opening 2121 of the opening ring 212 of the sealing structure 210 (see Figure 1C) and extends to the edge of the semiconductor device MD (i.e., the cut mark SW).

[0031] Furthermore, the central region of the semiconductor device MD includes many predetermined dicing regions SL that are not cut, and these predetermined dicing regions SL include uncut bonding conductive wires 220, as shown in Figure 1B.

[0032] In this embodiment, the crack-preventing corner CR prevents cracks generated by the dicing process from extending along the bonding conductive wire 220 to the semiconductor die D, thereby avoiding damage to the array element 110 located inside the sealing structure 210. In this embodiment, both the uncut bonding conductive wire 220 (see Figure 1B) and the cut bonding conductive wire C220 (see Figure 2B) include the crack-preventing corner CR. Furthermore, in this embodiment, components identical or similar to those in the embodiments shown in Figures 1A to 1F are denoted by the same reference numerals, and these identical or similar components will not be described repeatedly.

[0033] In the embodiments described above, each semiconductor die D includes one sealing structure 210, but the present invention is not limited thereto. The number of sealing structures 210 may be adjusted as needed. As shown in Figure 3, a single semiconductor die D may include multiple sealing structures 210. These sealing structures 210 are arranged between the array element 110 and the edge of each semiconductor die D, such that one sealing structure 210 surrounds another sealing structure 210.

[0034] When a single semiconductor die D includes multiple encapsulation structures 210, the junction wires coupled to it penetrate the multiple encapsulation structures 210 of the semiconductor die D. As shown in Figure 3, the severed junction wire C220 penetrates the openings 2121 of the open rings 212 of the multiple encapsulation structures 210. It should be noted that, although not shown, unsevered junction wires also penetrate the openings 2121 of the open rings 212 of the multiple encapsulation structures 210. Furthermore, the severed junction wire C220 in Figure 3 is shown to illustrate its relative position to the encapsulation structures 210, and the complete structure of the severed junction wire C220 is not shown.

[0035] In the embodiments described above, each joint conductive wire 220 (see Figure 1B) has four crack-preventing corners CR located in a predetermined dicing region SL, but the present invention does not limit the number of crack-preventing corners CR. Preferably, each joint conductive wire 220 may include two or more crack-preventing corners CR located in a predetermined dicing region SL. For example, the number of crack-preventing corners CR may be a multiple of two. Examples based on other modifications of the present invention are given below.

[0036] Referring to Figures 4A and 4B, in this embodiment, the joint conductive wire 220 may include eight crack-preventing corners CR. Also, the cut joint conductive wire C220 may include four crack-preventing corners CR. Furthermore, in this embodiment, components identical or similar to those in the previously described embodiments are denoted by the same reference numerals, and these identical or similar components will not be described repeatedly.

[0037] Referring to Figures 5A and 5B, in this embodiment, the joint conductive wire 220 includes 12 crack-preventing corners CR. The cut joint conductive wire C220 also includes 6 crack-preventing corners CR. In this embodiment, components identical or similar to those in the previous embodiments are denoted by the same reference numerals, and these identical or similar components will not be described repeatedly.

[0038] In the embodiments described above, the connection terminal 300 (see Figure 2C) of the semiconductor die D is electrically connected to the pad layer 230, but the present invention is not limited thereto. Examples based on other modifications of the present invention are given below.

[0039] Referring to Figures 6A and 6B, in this embodiment, each semiconductor die in the wafer 10 may be tested before forming the connection terminals 300 (shown in Figure 7B). After testing, semiconductor dies in which no abnormalities were found are designated as first semiconductor die D, and semiconductor dies in which abnormalities were found (for example, problems such as open circuits, short circuits, or leakage currents) are designated as second semiconductor die D'. The structures of second semiconductor die D' and first semiconductor die D are identical, and the only difference between them is that second semiconductor die D' may have abnormal electrical characteristics or functions due to process deviations, contamination, or other factors. The detailed structure of second semiconductor die D' will not be described repeatedly here.

[0040] In this embodiment, after testing, the position of the second semiconductor die D' on the wafer 10 is obtained, and subsequently, a barrier structure 240 may be formed on the pad layer 230 of the internal connection structure 200 of the second semiconductor die D' using three-dimensional printing technology, lithography technology, or other suitable method. For example, the barrier structure 240 may be filled into an opening 292 of the interlayer insulating layer 290 of the second semiconductor die D', and the barrier structure 240 may be brought into contact with the pad layer 230.

[0041] Next, as shown in Figures 7A and 7B, connection terminals 300 are provided above each pad layer 230. Here, the connection terminal 300 of the first semiconductor die D is electrically connected to the pad layer 230, while the connection terminal 300 of the second semiconductor die D' is electrically insulated from the pad layer 230 because a barrier structure 240 is provided between the pad layer 230 and the connection terminal 300. In this embodiment, due to the presence of the barrier structure 240, the top surface of the connection terminal 300 of the first semiconductor die D is lower than the top surface of the connection terminal 300' of the second semiconductor die D'.

[0042] After forming the connection terminals 300, a dicing process may be performed on the wafer 10 to obtain a semiconductor device MD. In this embodiment, the semiconductor device MD may include a first semiconductor die D and a second semiconductor die D'. In a well-known manufacturing process for bonded chips, if any of the semiconductor dies is determined to be abnormal during the testing phase, the entire bonded chip is discarded. Alternatively, a complex dicing process is required to remove the specific abnormal semiconductor die. This leads to the waste of resources. In contrast, this embodiment provides a barrier structure 240, which not only reduces interference from the second semiconductor die D' but also allows the semiconductor device MD to contain an abnormal semiconductor die (i.e., the second semiconductor die D'). In this way, this embodiment does not require the specific removal of the second semiconductor die D' in the semiconductor device MD by performing a complex dicing process, thereby improving process yield, reducing resource waste, and ultimately lowering manufacturing costs.

[0043] According to the semiconductor device of the present invention, in the actual production process, regardless of how many semiconductor dies are needed for the integrated circuit to meet performance requirements, the same wafer, for example, a wafer containing 1000 semiconductor dies, can still be produced uniformly. Subsequently, based on the required performance, the wafer is cut in the dicing process into a semiconductor device having four semiconductor dies, a semiconductor device having two semiconductor dies, or a semiconductor device having only one semiconductor die. This makes it possible to manufacture integrated circuits with different performance characteristics using the same mask, reduces the frequency of lithography equipment updates, shortens development time, and lowers production costs. Furthermore, the crack-preventing corners of the bonding conductive wires of the present invention can prevent cracks generated during the dicing process from extending along the bonding conductive wires into the semiconductor dies, thereby improving product yield. For this reason, the semiconductor device of the present invention belongs to a type of green semiconductor technology. [Industrial applicability]

[0044] Embodiments of the present invention are applicable to semiconductor technology, for example, semiconductor wafers and / or semiconductor dies. [Explanation of Symbols]

[0045] 10: Wafer 100: Circuit board 102: Buffer Layer 110: Array element 112: 1st flat electrode 113: Capacitor element 1131: Bottom electrode 1132: Dielectric layer 1133:Top electrode 1134: Stop layer 116:Second flat electrode 120: Cover layer 200: Internal connection structure 210: Sealing structure 211: First seal ring 212: Open ring 213: Second seal ring 214: Third seal ring 215: Fourth seal ring 220: Conductive wire for bonding 220B: First line section 220A: Second line section 230: Pad layer 240: Barrier structure 280: Conductive wire for bonding 290: Interlayer insulating layer 292:Aperture 300, 300': Connection terminals 2121: Opening of the ring 2201: Part C220: Severed jointed conductive wire CR: Crack prevention corners D: Semiconductor die / First semiconductor die D': Second semiconductor die DB1, DB2, X: Dashed line frame E1: 1st direction MD: Semiconductor device SL: Designated dicing area SR: Dicing Line SW: Cutting marks

Claims

1. Multiple semiconductor dies located on both sides of a predetermined dicing region, A junction conductive wire that electrically connects the plurality of semiconductor dies and Includes, In a top view, the bonding conductive wire includes a plurality of crack-preventing corners located in the predetermined dicing region. Semiconductor devices.

2. The aforementioned conductive joint wire is A predetermined dicing portion and Crack prevention portions located on both sides of the predetermined dicing portion and Includes, The extension direction of the predetermined dicing portion differs from the extension direction of the predetermined dicing region, and the plurality of crack prevention corners are located in the crack prevention portion. The semiconductor device according to claim 1.

3. The predetermined dicing region extends along the first direction, and The crack-preventing portion of the aforementioned conductive wire is Each of the following first line segments extends parallel to the first direction: Each of the following second line segments extends perpendicularly to the first direction and is connected to one of the multiple first line segments via one of the multiple crack-preventing corners: including, The semiconductor device according to claim 2.

4. The extension direction of the predetermined dicing portion is perpendicular to the first direction. The semiconductor device according to claim 3.

5. The number of the aforementioned crack-preventing corners is two or more. The semiconductor device according to claim 1.

6. The number of the aforementioned crack-preventing corners is a multiple of two. The semiconductor device according to claim 1.

7. The aforementioned plurality of crack-preventing corners include right angles. The semiconductor device according to claim 1.

8. Each of the aforementioned plurality of semiconductor dies is Array elements and A sealing structure located at the edge of each of the plurality of semiconductor dies and surrounding the array element Includes, The aforementioned sealing structure is A first seal ring is provided in a stacked configuration, Open ring and The connection includes, and the conductive wire passes through the opening of the open ring and is electrically connected to the array element. The semiconductor device according to claim 1.

9. The array element is a silicon capacitor array, and one of the silicon capacitor arrays among the plurality of semiconductor dies is connected in series with another of the plurality of semiconductor dies via the junction conductive wire. The semiconductor device according to claim 8.

10. The array element is a silicon capacitor array, and one of the silicon capacitor arrays among the plurality of semiconductor dies is connected in parallel to another of the plurality of semiconductor dies via the junction conductive wire. The semiconductor device according to claim 8.

11. The aforementioned bonding conductive wire is provided above the array element, and Each of the aforementioned plurality of semiconductor dies is An internal connection structure provided above the bonding conductive wire and electrically connected to the array element via the bonding conductive wire, wherein the internal connection structure includes a conductive layer and a pad layer arranged in a laminate, Connection terminals provided above the pad layer and It further includes, The plurality of semiconductor dies include a first semiconductor die and a second semiconductor die, and the connection terminal of the first semiconductor die is electrically connected to the pad layer. The semiconductor device according to claim 8.

12. The second semiconductor die is A barrier structure provided between the pad layer and the connection terminal, which electrically insulates the connection terminal of the second semiconductor die from the pad layer. This also includes, The semiconductor device according to claim 11.

13. The sealing structure further includes a second seal ring, the opening ring is provided on the first seal ring, and the second seal ring is provided on the opening ring and straddles the connecting conductive wire. The semiconductor device according to claim 8.

14. The bonding conductive wire located at one of the edges of the semiconductor device in the plurality of semiconductor dies extends through the open ring to the edge of the semiconductor device. The semiconductor device according to claim 8.

15. Each of the plurality of semiconductor dies includes a plurality of the sealing structures, and the plurality of sealing structures are arranged between the array element and the edge of each of the plurality of semiconductor dies, with one of the plurality of sealing structures surrounding another of the plurality of sealing structures. The semiconductor device according to claim 8.

16. The direction in which the connecting conductive wire extends through the opening portion of the open ring is the same as the direction in which the predetermined dicing portion extends. The semiconductor device according to claim 8.

17. Including a plurality of the aforementioned connecting conductive wires, One of the plurality of bonding conductive wires connects the plurality of semiconductor dies arranged along the X direction, Another of the aforementioned multiple bonding conductive wires connects the multiple semiconductor dies arranged along the Y direction, One of the plurality of bonding conductive wires connects the plurality of semiconductor dies arranged along the diagonal direction. The semiconductor device according to claim 1.

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