Method for forming a semiconductor layer stack including at least a portion of a vertical channel transistor structure

Abstract

The present invention provides a method for forming a semiconductor layer stack that includes at least a portion of a vertical channel transistor structure. [Solution] A method for forming a semiconductor layer stack including at least a portion of a vertical channel transistor structure is disclosed. The disclosed method includes depositing one or more carbon-doped silicon layers between a doped layer and a channel layer to form one or more blocking layers to reduce the diffusion of dopants into the channel layer.

Description

[Technical Field]

[0001] This disclosure generally relates to the field of semiconductor processing methods, related structures, and the field of device and integrated circuit manufacturing. More specifically, this disclosure generally relates to methods for forming semiconductor layer stacks used in the fabrication of vertical channel transistor structures. [Background technology]

[0002] A vertical channel transistor (VCT) is a type of transistor in which current flows vertically through the device, rather than horizontally as in conventional planar transistors. The vertical design offers several advantages over planar devices, particularly in terms of miniaturization and performance. Furthermore, VCTs allow for shorter channel lengths, which can be crucial for scaling down device size.

[0003] One of the key features of VCTs is their high performance. Vertical channel transistors can handle high currents and high voltages more efficiently than certain planar transistors. For example, vertical channel field-effect transistors (V-FETs) exhibit improved on-resistance and frequency response, making V-FETs suitable for high-power applications. Furthermore, VCTs can be fabricated from a variety of semiconductor materials, including but not limited to silicon and compound semiconductor materials such as Si, SiGe, GaAs, and InP. The aforementioned materials can enhance the performance characteristics of the device, such as current handling capability and energy bandgap.

[0004] However, despite the advantages mentioned above, vertical channel transistors also face many challenges. Managing heat dissipation in VCTs can be difficult and may require advanced cooling solutions. Furthermore, fabricating VCTs can be more complex and costly compared to conventional planar transistors. Therefore, improvements to the fabrication process for vertical channel transistor structures are desirable.

[0005] Any discussions, including the discussions of problems and solutions described herein, are included in this disclosure solely for the purpose of providing background to the disclosure, and none of the discussions, in whole or in part, should be considered to be known at the time the invention was made, or to constitute prior art otherwise. [Overview of the project]

[0006] This summary introduces the selected concepts in a simplified form, which are described in more detail below. This summary is not necessarily intended to identify the main or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. [Means for solving the problem]

[0007] Various embodiments of this disclosure relate to methods for forming a semiconductor layer stack including at least a portion of a vertical channel transistor structure. The semiconductor layer stack includes a blocking layer comprising a carbon-doped silicon layer configured to reduce the migration of dopants into the channel layer.

[0008] An example of the present disclosure discloses a method for forming a semiconductor layer stack including at least a portion of a vertical channel transistor structure. The method includes placing a substrate in a reaction chamber, depositing a doped silicon layer on the substrate, depositing a channel layer on the substrate, and depositing a carbon-doped silicon layer between the doped silicon layer and the channel layer. In such a method, the carbon-doped silicon layer includes a blocking layer configured to reduce the migration of dopant species from the doped silicon layer into the channel layer.

[0009] In some embodiments, the carbon-doped silicon layer is deposited directly on top of the doped silicon layer.

[0010] In some embodiments, the channel layer is deposited directly on the carbon-doped silicon layer.

[0011] In some embodiments, an additional carbon-doped silicon layer is deposited directly on the channel layer.

[0012] In some embodiments, the carbon-doped silicon layer is deposited directly on the channel layer.

[0013] In some embodiments, an additional doped silicon layer is deposited directly on the carbon-doped silicon layer.

[0014] In some embodiments, the semiconductor layer stack is deposited by an isothermal deposition process at a deposition temperature selected from 500 °C to 850 °C.

[0015] In some embodiments, the doped silicon layer comprises an epitaxially doped silicon layer doped with at least one of phosphorus and arsenic.

[0016] In some embodiments, the carbon-doped silicon layer comprises an epitaxial carbon-doped silicon layer.

[0017] In some embodiments, the epitaxial carbon-doped silicon layer is doped at a carbon doping concentration of 1×10 17 cm -3 ~1×10 21 cm -3 and deposited.

[0018] In some embodiments, the epitaxial carbon-doped silicon layer is co-doped with a further dopant, and the concentration of the further dopant is 1×10 16 cm -3 ~1×10 21 cm -3 is.

[0019] According to an example of the present disclosure, a method of epitaxially depositing a semiconductor layer stack including at least a part of a vertical channel transistor structure, the method comprising placing a silicon substrate in a reaction chamber, epitaxially depositing a doped silicon layer on the silicon substrate, epitaxially depositing a carbon-doped silicon layer directly on the doped silicon layer, and epitaxially depositing a silicon channel layer directly on the carbon-doped silicon layer. In such a method, the semiconductor layer stack is deposited by an isothermal chemical vapor deposition process without breaking the vacuum in the reaction chamber.

[0020] In some embodiments, the method further comprises epitaxially depositing an additional carbon-doped silicon layer directly on the silicon channel layer.

[0021] In some embodiments, at least one of the carbon-doped silicon layer and the additional carbon-doped silicon layer is deposited at a carbon doping concentration of 1×10 17 cm -3 ~1×10 21 cm -3 .

[0022] In some embodiments, at least one of the carbon-doped silicon layer and the additional carbon-doped silicon layer is co-doped with a further dopant, and the further dopant has a concentration of 1×10 16 cm -3 ~1×10 21 cm -3 .

[0023] An example of the present disclosure provides a method for forming a semiconductor layer stack including at least a portion of a vertical channel transistor structure, comprising: placing a silicon substrate in a reaction chamber; and heating the silicon substrate to a deposition temperature selected between 500°C and 850°C. The method involves epitaxially depositing the semiconductor layer stack by an isothermal chemical vapor deposition process, comprising: introducing at least a first silicon precursor and dopant gas into a reaction chamber and epitaxially depositing a doped silicon layer onto a silicon substrate; introducing at least a second silicon precursor and carbon dopant gas into a reaction chamber and directly epitaxially depositing a carbon-doped silicon layer onto the doped silicon layer; and introducing at least a third silicon precursor into a reaction chamber and directly epitaxially depositing a silicon channel layer onto the carbon-doped silicon layer. In such a method, the carbon-doped silicon layer forms a blocking layer that reduces the migration of dopant species from the doped silicon layer to the silicon channel layer.

[0024] In some embodiments, the reaction chamber comprises a quartz assembly including an upper wall and a lower wall, wherein the upper wall extends longitudinally between the injection chamber flange and the exhaust chamber flange opposite in the longitudinal direction, and the lower wall is below and parallel to the upper wall.

[0025] In some embodiments, heating the silicon substrate includes radiant heating of the silicon substrate disposed inside the chamber of the reaction chamber by using at least one of an upper heater element array positioned above the upper wall of the reaction chamber and a lower heater element array positioned below the lower wall of the reaction chamber, and maintaining the isothermal chemical deposition process by monitoring and controlling the temperature of the silicon substrate and one of the semiconductor layer stacks thereon by using one or more temperature sensors and a controller that operably communicates with at least one of the upper heater element array and the lower heater element array.

[0026] In some embodiments, the carbon-doped silicon layer is 1 × 10 17 cm -3 ~1 × 10 21 cm -3 It is deposited with carbon doping concentrations of [value missing].

[0027] In some embodiments, the carbon-doped silicon layer is co-doped with a further dopant, the further dopant being 1 × 10 16 cm -3 ~1 × 10 21 cm -3 It has a concentration of [value].

[0028] For the purpose of summarizing the advantages of the present invention over the prior art, certain objectives and advantages of the present invention are described herein. Naturally, it will be understood that not all of these objectives or advantages are necessarily achieved according to any particular embodiment of the present invention. Therefore, those skilled in the art will recognize that the present invention may be embodied or practiced in a manner that achieves or optimizes one or a group of advantages as disclosed or suggested herein, without necessarily achieving other objectives or advantages as disclosed or suggested herein.

[0029] All of the embodiments described above are intended to be within the scope of the present invention disclosed herein. The above and other embodiments may be readily apparent to those skilled in the art from the following detailed description of certain embodiments by reference to the accompanying drawings, but the present invention is not limited to any particular embodiment disclosed. [Brief explanation of the drawing]

[0030] [Figure 1] This is a partial cross-sectional view of a vertical channel transistor structure according to one or more embodiments of the present disclosure. [Figure 2] This is a flowchart illustrating a method for forming a semiconductor layer stack including at least a portion of a vertical channel transistor structure according to one or more embodiments of the present disclosure. [Figure 3] This is a schematic cross-sectional view of a semiconductor processing system and associated reaction chamber that may be used for forming a semiconductor layer stack according to one or more embodiments of the present disclosure. [Figure 4] This is a cross-sectional view of a vertical channel transistor structure including a semiconductor layer stack according to one or more embodiments of the present disclosure. [Figure 5] This is a cross-sectional view of a vertical channel transistor structure including a semiconductor layer stack according to one or more embodiments of the present disclosure. [Figure 6] This is a cross-sectional view of a vertical channel transistor structure including a semiconductor layer stack according to one or more embodiments of the present disclosure. [Modes for carrying out the invention]

[0031] To facilitate the identification of any particular component or operation, the most significant digit of the reference number refers to the figure number in which that element is first introduced.

[0032] A more complete understanding of the embodiments of this disclosure can be obtained by referring to the modes for carrying out the invention and the claims, as considered in relation to the following illustrative drawings.

[0033] It will be understood that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to actual size. For example, the dimensions of some of the elements in the figures may be exaggerated relative to others to help improve understanding of the illustrated embodiments of this disclosure.

[0034] The descriptions of exemplary embodiments of the methods and configurations provided below are illustrative and for illustrative purposes only. The following descriptions are not intended to limit the scope of this disclosure or the claims. Furthermore, the enumeration of numerous embodiments having the exemplary configurations or steps is not intended to exclude other embodiments having additional configurations or steps, or other embodiments incorporating different combinations of the configurations or steps described.

[0035] In this specification, the term “substrate” may refer to any substrate material used to form a device, circuit, or film, or on which a device, circuit, or film can be formed, by a method according to one embodiment of the present disclosure. The substrate may comprise a bulk material such as silicon (e.g., single-crystal silicon), another Group IV material such as germanium, or another semiconductor material such as a Group II-VI or Group III-V semiconductor material, and may comprise one or more layers on or beneath the bulk material. Furthermore, the substrate may comprise various features such as recesses, protrusions, and similar portions formed in or on at least a portion of the layers of the substrate. For example, the substrate may comprise a bulk semiconductor material and an insulating or dielectric material layer on at least a portion of the bulk semiconductor material. Furthermore, the term “substrate” may refer to any substrate material that can be used, or any substrate material on which a device, circuit, or film can be formed. The “substrate” may be continuous or discontinuous, rigid or flexible, solid or porous. The “substrate” may be in any form, such as a powder, a plate, or a workpiece. The substrate in plate form may include wafers of various shapes and sizes. The substrate may be made from materials such as silicon, silicon germanium, silicon oxide, gallium arsenide, gallium nitride, and silicon carbide. The continuous substrate may extend beyond the boundary of the process chamber where the deposition process takes place, or it may move through the process chamber so that the process continues until it reaches the end of the substrate. The continuous substrate may be supplied from a continuous substrate supply system that enables the manufacture and output of the continuous substrate in any suitable form. Non-limiting examples of the continuous substrate may include sheets, nonwoven films, rolls, foils, webs, flexible materials, continuous filaments, or bundles of fibers (i.e., ceramic fibers or polymer fibers). The continuous substrate may also include a carrier or sheet to which discontinuous substrates are attached. For example, the substrate may include semiconductor materials.The semiconductor material may include one or more of the source, drain, or channel regions of the device, or may be used to form them. The substrate may further include an interlayer dielectric (e.g., silicon dioxide) and / or high-dielectric-constant material layer overlaid on the semiconductor material. In this text, a high-dielectric-constant material (or high-k dielectric material) is a material having a dielectric constant greater than that of silicon dioxide.

[0036] Where used in this disclosure, the terms “film” and / or “layer” are mutually interchangeable and may mean any continuous or discontinuous structure and material, such as a material deposited by the methods disclosed herein. For example, layers may be two-dimensional materials, three-dimensional materials, nanoparticles, partial or complete molecular layers, or partial or complete atomic layers, or clusters of atoms and / or molecules. A layer may consist partially or completely of multiple atoms dispersed on the surface of a substrate and / or embedded in the substrate and / or embedded in a device manufactured on the substrate. A film may comprise a material or layer having pinholes and / or isolated islands. A layer may be at least partially continuous. A layer may be patterned, for example, subdivided, and may consist of multiple semiconductor devices.

[0037] As used herein, the term “gas” may include materials that are gases at room temperature and pressure (NTP), vaporized solids, and / or vaporized liquids, and may, depending on the context, consist of a single gas or a mixture of gases. Gases other than process gases, i.e., gases introduced without passing through gas distribution assemblies, other gas distribution devices, or similar, may be used, for example, to seal reaction spaces and may include sealing gases. Precursors and reactants may be gases. Exemplary sealing gases include noble gases, nitrogen, and similar substances. In some cases, the term “precursor” may refer to compounds involved in a chemical reaction that produces another compound, particularly compounds that constitute the membrane matrix or the main skeleton of a membrane. Furthermore, the term “reactant” may be used interchangeably with the term “precursor.”

[0038] As used herein, the term “epitaxial layer” may refer to a substantially single crystalline layer directly above a substantially single crystalline substrate or layer that is located beneath it.

[0039] As used herein, the term "chemical vapor deposition" may refer to any process by which a substrate is exposed to one or more volatile precursors (and optionally additional process gases) to cause a reaction and / or decomposition on the substrate surface to produce a desired deposition.

[0040] It should be noted that while many exemplary materials are given through embodiments of this disclosure, the chemical formulas given for each exemplary material should not be interpreted as restrictive, and the non-restrictive exemplary materials given should not be limited by any exemplary stoichiometry.

[0041] In this specification, the terms “on top of” or “covering over” may be used to describe relative spatial relationships. Another element, membrane, or layer may be directly on top of the layer being referred to, or another layer (intermediate layer) or element may be interposed between them, or a layer may be positioned on top of the layer being referred to but not completely covering its surface. Thus, unless the term “directly” is used otherwise, the terms “on top of” or “~on top of” are interpreted as relative concepts. Similarly, the terms “below,” “below,” or “below / below” are interpreted as relative concepts.

[0042] In this disclosure, any two numbers of a variable can constitute a viable range of the variable, and any range shown may include or exclude the endpoints. In addition, any value of a variable shown (whether shown with “approximately” or not) may refer to the exact value, an approximate value, or its equivalent. Also, in some embodiments, it may refer to the mean, median, representative value, principal value, etc. Furthermore, in this disclosure, the terms “include,” “composed of,” and “have” may independently refer to “typically or generally comprise,” “compose,” “essentially consist of,” or “consist of.” In this disclosure, the meaning of any defined term does not necessarily exclude the ordinary and conventional meanings in some embodiments. In some cases, the percentages shown herein may be relative or absolute percentages.

[0043] It should be noted that while many exemplary materials are given through embodiments of this disclosure, the chemical formulas given for each exemplary material should not be interpreted as restrictive, and the non-restrictive exemplary materials given should not be limited by any exemplary stoichiometry.

[0044] Various embodiments of this disclosure relate to methods for forming semiconductor layer stacks used in the fabrication of vertical channel transistor structures.

[0045] A vertical channel transistor can include numerous layers deposited by various deposition techniques. As a non-limiting example, Figure 1 is a partial cross-sectional view of a vertical channel transistor structure 100, including a substrate 102 and a semiconductor layer stack 104 disposed on the substrate 102. The semiconductor layer stack 104 comprises a source layer 106 and a drain layer 110 sandwiching a channel layer 108. The source layer 106 and drain layer 110 are generally highly doped layers. Highly doped source / drain layers are commonly used for many reasons, including but not limited to improved carrier injection, reduced contact resistance, improved on-state performance, and minimization of short-channel effects. Note that in some examples, the source layer 106 and drain layer 110 in the semiconductor layer stack 104 are interchangeable, such that the drain layer 110 is below the channel layer 108 and the source layer 106 is above the channel layer 108.

[0046] The channel layer 108, which is directly disposed between the highly doped source layer 106 and drain layer 110, is often either lightly doped or undoped. As a non-limiting example, an undoped (e.g., or intrinsically doped) channel layer may be advantageous in certain applications because it may exhibit reduced scattering and improved carrier mobility, which can be beneficial to device speed and efficiency. Unfortunately, dopant migration from the highly doped source / layer to the channel layer may occur during the deposition of the channel layer 108 on the source layer 106 and / or the deposition of the drain layer 110 on the channel layer 108. Such dopant migration can adversely affect the device performance of a vertical channel transistor structure. For example, such dopant migration may result in a threshold voltage shift, exacerbate short-channel effects, lead to higher leakage current, degrade device performance, and increase device variability.

[0047] Therefore, various embodiments of the present disclosure utilize one or more carbon-doped silicon layers between a highly doped layer and a channel layer. In various embodiments, a single carbon-doped silicon layer, or a pair of carbon-doped silicon layers, are deposited between a highly doped layer and a channel layer in a vertical channel transistor structure. In such embodiments, the carbon-doped silicon layer(s) form a blocking layer(s) between the highly doped layer and the channel layer to prevent or substantially reduce the migration of dopant species from the doped layer into the channel layer.

[0048] Figure 2 is a flowchart of an exemplary method 200 for forming a semiconductor layer stack including at least a portion of a vertical channel transistor structure according to an embodiment of the present disclosure. Briefly, the method flow 200 includes the steps of: placing a substrate in a reaction chamber (step 202); depositing a doped silicon layer on the substrate (step 204); depositing a channel layer on the substrate (step 208); depositing a carbon-doped silicon layer between the doped silicon layer and the channel layer (steps 206 and / or 210); and depositing an additional doped silicon layer (step 212). In various examples, both step 204 for depositing the doped silicon layer and step 212 for depositing the additional doped silicon layer may include the deposit of a highly doped source / drain layer.

[0049] As described in detail below, the carbon-doped silicon layer(s) form one or more blocking layers (also referred to herein as blocking layers) configured to reduce the migration of dopant species from the doped silicon layer into the channel layer (i.e., by selection of deposition parameters, composition, thickness, and the like). Various embodiments, as described below, include depositing a single carbon-doped silicon layer before or after the deposition of the channel layer. Various additional embodiments include depositing a pair of carbon-doped silicon layers. In such embodiments, the carbon-doped silicon layer can be deposited before the channel layer is deposited, and an additional carbon-doped silicon layer can be deposited after the channel layer is deposited.

[0050] Referring again to Figure 2, flow 200 includes placing the substrate in the reaction chamber (step 202). In various embodiments, step 202 includes heating the substrate to a deposition temperature suitable for forming the semiconductor layer stack of the present disclosure. The reaction chamber and associated semiconductor processing system suitable for forming the semiconductor layer stack may include one configured to carry out a chemical vapor deposition (CVD) process. In some embodiments, the reaction chamber and associated semiconductor processing system are constructed and configured to carry out an epitaxial chemical vapor deposition process. In certain examples, the reaction chamber and associated semiconductor processing system are constructed and configured to carry out an isothermal chemical vapor deposition process and / or an isothermal epitaxial chemical vapor deposition process. As used herein, the term “isothermal” may refer to a deposition process (e.g., CVD) in which the semiconductor layer stack is deposited on a substrate under conditions that maintain a constant deposition temperature throughout the entire process of depositing the various layers of the semiconductor layer stack. In such an “isothermal” deposition process, the deposition temperature (e.g., the substrate temperature during deposition) may vary by less than 5%, less than 3%, less than 1%, or less than 0.5% from a selected setpoint deposition temperature. Furthermore, the reaction chamber and associated semiconductor processing system are constructed and configured to enable the deposition of an entire semiconductor layer stack by an isothermal chemical deposition process without disrupting the vacuum within the reaction chamber. For example, multiple layers of a semiconductor layer stack constituting part of a vertical channel transistor structure can be deposited by a single deposition process without the need to remove the substrate and the layers on it from one reaction chamber to another.

[0051] In various embodiments, the substrate on which the semiconductor layer stack of the Disclosure is formed (e.g., by a deposition process) may include a bulk crystalline substrate, such as a bulk silicon substrate. In some embodiments, the substrate of the Disclosure may include one or more surface layers. In such examples, the surface layers may form part of a vertical channel transistor structure. The substrate may include, for example, a high carrier mobility surface layer used to enhance device performance, such as a silicon germanium (SiGe) surface layer. In some examples, the surface layers on the substrate, in combination with a semiconductor layer stack deposited on the surface layer by the method disclosed herein, together form constituent layers of a vertical channel transistor structure. In addition, the substrate may include, for example, one or more partially fabricated device structures, such as logic elements and / or memory elements. In certain embodiments, the substrate may further include, but not limited to, one or more dielectric materials, including silicon oxides, silicon nitrides, and high dielectric constant dielectric layers such as hafnium oxide, hafnium zirconium oxide, etc.

[0052] Figure 3 is a cross-sectional view of a semiconductor processing system 302 (including a reaction chamber 304) that may be used to form a semiconductor layer stack including a carbon-doped blocking layer of the present disclosure. As shown in Figure 3, a process gas is supplied to the reaction chamber 304 from a gas supply assembly 306, and any excess process gas and any reaction byproducts are exhausted from the reaction chamber 304 by an exhaust assembly 308.

[0053] The gas source assembly 306 is constructed and positioned to supply process gas (e.g., gas-phase process gas) to the reaction chamber 304. The process gas may be a single gas or a mixture of gases, including but not limited to precursor gas, dopant gas, etchant gas, and inert gas (e.g., purge gas, carrier gas). The gas source assembly 306 may include various systems, subsystems, and components (not shown) for generating and controlling the flow of process gas from the source contained therein to the process gas supply line 312. The process gas supply line 312 fluidly connects the gas source assembly 306 to the reaction chamber 304 via an injection flange 314.

[0054] The gas supply source assembly 306 includes a precursor supply source 316 which may include several precursor supply sources. The precursor supply source 316 includes a silicon supply source containing one or more silicon precursors. The process gas supplied by the gas supply source assembly 306 is introduced into the chamber interior 318 (as indicated, for example, by the process gas flow 320) through an injection flange 314 which includes a plurality of injection ports 322.

[0055] In various embodiments, the silicon precursor contains one silicon atom per molecule, such as silane (SiH4) and / or monochlorosilane (ClH3Si). Alternatively (or additionally), the silicon precursor may, in certain examples, include higher-order silicon precursors having two or more silicon atoms per molecule, or three or more silicon atoms. The higher-order silicon precursor may include non-halogenated higher-order silicon precursors such as trisilane and / or tetrasilane. The higher-order silicon precursor may include halogenated higher-order silicon precursors such as chlorodisilane, dichlorosilane, trichlorosilane, and tetrachlorosilane. In some embodiments, the silicon precursor contains silane and / or halosilane. In some embodiments, the silicon precursor may include silicon hydride precursors. In such embodiments, the silicon hydride precursors may include silane (SiH4), disilane (Si2H6), trisilane (Si3H8), and tetrasilane (Si4H 10 ) may be selected from one or more of the following. In further embodiments, the silicon precursor may include a silicon halide precursor. In such examples, the silicon halide precursor may include a silicon chloride precursor selected from one or more of monochlorosilane (MCS), dichlorosilane (DCS), trichlorosilane (TCS), hexachlorodisilane (HCDS), octachlorotrisilane (OCTS), and silicon tetrachloride (STC). In further embodiments, the silicon precursor may include a silicon iodide precursor. In such examples, the silicon halide precursor may include a silicon iodide precursor selected from one or more of monoiodosilane, diiodosilane, triiodosilane, and tetraiodosilane.

[0056] The precursor source 316 subsystem of the gas source assembly 306 may include one or more germanium sources for supplying a germanium precursor to the reaction chamber 304. The germanium precursor may be selected from germane and / or germanium halides. For example, the germanium precursor may include germanes such as germane (GeH4), digermann (Ge2H6), trigermann (Ge3H8), or germylsilane (GeH6Si). In further examples, the germanium precursor may include germanium halides such as GeCl4, GeCl2, and GeCl2H2.

[0057] In addition to the precursor source 316, the gas source assembly 306 may include an etchant source 326 and a carrier source 328. The etchant source 326 may include a halide-containing compound. In one embodiment, the halide-containing compound flows independently of the precursor, for example, to provide a purge and / or to remove condensates from within the reaction chamber 304. In another embodiment, the halide-containing compound may flow together with one or more other process gases. Examples of suitable halides include chlorine (Cl), e.g., chlorine (Cl2) gas and hydrochloric acid (HCl), as well as fluorine (F), e.g., fluorine (F2) gas and hydrofluoric acid (HF). The carrier source 328 may be configured to provide an inert carrier gas and / or a purge gas to the reaction chamber 304. Suitable purge / carrier gases include inert gases such as hydrogen (H2), nitrogen (N2), argon (Ar), or helium (He), and mixtures thereof.

[0058] The gas supply source assembly 306 may further include a dopant supply source 324 which includes one or more dopant gas supply sources. The dopant supply source 324 may include a variety of dopant gases suitable for doping silicon layers, including but not limited to phosphorus (P), boron (B), carbon (C), and / or arsenic (As). In various embodiments, the dopant gas may include one or more silicon p-type dopant gases, such as borane, diborane (B2H6), deuterium-diborane (B2D6), and boron halides such as BBr3, BH2Cl, and BCl2H. In various embodiments, the dopant gas may include one or more silicon n-type dopant gases, such as phosphine (PH3) and arsine (AsH3). In various embodiments, the dopant gas may include one or more carbon dopant gases introduced into the reaction chamber to enable the deposition of the carbon-doped silicon layer (i.e., block layer) of the present disclosure. In some embodiments, the carbon dopant gas may include alkanes or alkenes such as methane (CH4), ethylene (C2H4), acetylene (C2H2), and propylene (C3H6). In some embodiments, the carbon dopant gas may include, for example, methylsilane (CH3SiH3), neopentasilane (Si5H 12 ), can include organosilicon compounds such as trimethylsilane (C3H9Si) and tetramethylsilane (Si(CH3)4). In some embodiments, the carbon dopant gas can include organohalides such as carbon tetrachloride (CCl4), trichloromethylsilane (CH3SiCl3), dichloromethane (CH2Cl2), and tetrachloroethylene (C2Cl4).

[0059] Referring again to the semiconductor processing system 302 in Figure 3, the reaction chamber 304 may include a cross-flow cold-wall epitaxial reaction chamber. In various embodiments, the reaction chamber 304 includes a chamber body 330 and a substrate support 332. As shown in Figure 3, the substrate 352 can be heated by using at least one of the upper heater element array 334 and the lower heater element array 336. While specific arrangements are shown and described herein, it should be understood and acknowledged that the semiconductor processing system 302 and associated reaction chamber 304 may include other elements and / or exclude elements shown and described herein, and may still remain within the scope of this disclosure.

[0060] As shown in Figure 3, the chamber body 330 comprises an upper wall 338, a lower wall 340, and side walls (not shown). The upper wall 338 and the lower wall 340 extend longitudinally between the injection end 342 and the exhaust end 344 on the opposite longitudinal side, defining at least partially the chamber interior 318 and the chamber exterior 346. The lower wall 340 is below and parallel to the upper wall 338. In certain examples, the chamber body 330 can be formed from a ceramic material such as sapphire or quartz. The chamber body 330 may include a plurality of external ribs 348. The plurality of external ribs 348 extend laterally around the chamber exterior 346 and may be longitudinally spaced between the injection end 342 and the exhaust end 344 of the chamber body 330. Also, according to certain examples, the chamber body 330 may not include ribs.

[0061] In various embodiments, the semiconductor processing system 302 includes an injection flange 314 coupled to the injection end 342 of the chamber body 330. The injection flange 314 includes a front surface coupled to the injection end 342 of the chamber body 330. The injection flange 314 includes a substrate channel 350 through which a substrate (e.g., substrate 352) can be fed in and out of the chamber outside 346. The injection flange 314 includes a plurality of injection ports (as shown by the exemplary injection port 322 in Figure 3). The injection flange 314 may further include a gas distribution assembly (not shown) which includes a plurality of flow controllers that can be configured to control the flow of process gas from the gas source assembly 306 to the plurality of injection ports 322 and through them to the chamber inside 318.

[0062] As shown in Figure 3, the substrate support 332 is disposed within the chamber interior 318. The substrate support 332 may be positioned between the injection end 342 and the exhaust end 344 of the chamber body 330. The substrate support 332 includes a shaft member 354 that is disposed within the chamber body 330 and configured to rotate around a pivot axis within the chamber interior 318. The substrate support 332 can be formed from an opaque material such as silicon carbide or bulk graphite material.

[0063] In various embodiments, the upper heater element array 334 may be configured to heat the substrate 352 and / or the epitaxial layer 356 (e.g., a semiconductor layer stack) during deposition on the substrate 352 by radiating heat into the chamber interior 318. The upper heater element array 334 may include a plurality of upper linear lamps supported above the chamber body 330 (e.g., above the upper wall 338) and optically coupled to the substrate support 332 by the material forming the chamber body 330, such as quartz. The lower heater element array 336 may be similar to the upper heater element array 334 and may be configured to heat the substrate 352 and / or the epitaxial layer 356 during deposition on the substrate 352. The lower heater element array 336 may include a plurality of lower linear lamps supported below the chamber body 330 (e.g., below the lower wall 340) and optically coupled to the substrate support 332 by the material forming the chamber body 330. In various embodiments, the upper heater element array 334 and / or the lower heater element array 336 may be used to epitaxially deposit the epitaxial layer 356 onto the substrate 352.

[0064] In various embodiments, the semiconductor processing system 302 uses one or more temperature sensors to monitor the temperature of the substrate inside the chamber 318 (and any epitaxial layer 356 thereon). As shown in Figure 3, multiple temperature sensors 366 can be used to measure the temperature at different points across the substrate. In certain examples, the temperature sensors 366 may include pyrometers (e.g., single pyrometer, double pyrometer, or triple pyrometer). The temperature sensors 366 are operably connected to a controller 310, which is then operably connected to an upper heater element array 334 and / or a lower heater element array 336. The controller 310 can compensate for any fluctuations in the substrate temperature (i.e., the deposition temperature) by communicating with the temperature sensors 366 and adjusting the power to the upper heater element array 334 and / or the lower heater element array 336 accordingly, thereby maintaining isothermal deposition process conditions. Therefore, the formation of the semiconductor layer stack of the present disclosure may include maintaining an isothermal chemical deposition process by monitoring and controlling the temperature of a silicon substrate and one of the semiconductor layer stacks thereon by using one or more temperature sensors and a controller that operably communicates with at least one of the upper heater element array and the lower heater element array.

[0065] The semiconductor processing system 302 also includes an exhaust assembly 308. The exhaust assembly 308 can be configured to exhaust from the reaction chamber 304 and may include one or more vacuum pumps 358 and a removal system 360. The vacuum pump 358 may be fluid-coupled to the reaction chamber 304 and configured to control the pressure inside the chamber 318. The removal system 360 may be fluid-coupled to the vacuum pump 358 and configured to handle the flow of residual precursors and / or reaction products that have flowed out of the reaction chamber 304. In some embodiments, the exhaust assembly 308 may be configured to maintain environmental conditions inside the chamber 318 suitable for the deposition operation.

[0066] The controller 310 includes a processor and memory, in which instructions are recorded. When an instruction is read by the processor, the controller 310 causes the processor to perform a process for depositing epitaxial layers 356, such as semiconductor layer stacks suitable for fabricating vertical channel transistor structures on a substrate 352, as will be described in detail below.

[0067] Referring again to Figure 2, step 202 of the method flow 200 includes heating the substrate to a suitable deposition temperature. In various embodiments, the substrate is heated to a selected deposition temperature (e.g., substrate temperature) below 850°C, below 800°C, below 750°C, below 700°C, below 650°C, below 600°C, below 550°C, or below 500°C. In some embodiments, the substrate is heated to a selected deposition temperature of 500°C to 850°C, or 550°C to 750°C, or 600°C to 700°C. In some embodiments, the substrate is heated to a selected deposition temperature above 500°C and below 850°C.

[0068] As described above, the deposition process of the present disclosure may include an isothermal deposition process. In such embodiments, the deposition temperature is maintained at a constant or substantially constant temperature during the deposition of layers constituting a semiconductor layer stack (including a blocking layer) that includes at least a portion of a vertical channel transistor structure. In certain examples, the deposition temperature is maintained at a constant temperature selected from 500°C to 850°C, or 550°C to 750°C, or 600°C to 700°C. In some embodiments, the deposition temperature is maintained at a constant temperature (i.e., isothermal) by using a temperature sensor 366, an upper heater element array 334 and / or a lower heater element array 336, and a controller 310, as described above. In such examples, the deposition temperature is maintained at a selected temperature of 500°C to 850°C, or 550°C to 750°C, or 600°C to 700°C during the deposition of the semiconductor layer stack, with a variation from the selected deposition temperature of less than 5%, less than 3%, less than 1%, or less than 0.5%.

[0069] In addition to controlling the temperature of the substrate, the pressure inside the reaction chamber is also adjustable. For example, in some embodiments of this disclosure, the pressure inside the reaction chamber during the deposition of various layers of a semiconductor layer stack constituting part of a vertical channel transistor structure is less than 760 Torre, less than 350 Torre, less than 250 Torre, less than 50 Torre, less than 25 Torre, less than 10 Torre, or even less than 5 Torre. In some embodiments, the pressure inside the reaction chamber is between 5 Torre and 760 Torre, or between 10 Torre and 250 Torre, or between 25 Torre and 200 Torre.

[0070] Referring again to Figure 2, the flow of the method 200 includes depositing a doped silicon layer onto a substrate (step 204). In some embodiments, the doped silicon layer includes a highly doped source / drain layer.

[0071] In the examples of this disclosure, the doped silicon layer may be either a doped p-type or n-type. In such examples, the doped silicon layer can be epitaxially deposited on a substrate by introducing at least a first silicon precursor and a dopant gas into a reaction chamber. The first silicon precursor may include one or more of the silicon precursors described herein, and the dopant gas may include one or more of the dopant gases described above. The dopant gas may be selected depending on the desired conductivity of the epitaxially deposited doped silicon layer. In non-limiting examples, the doped silicon layer may include, for example, an n-type layer doped with phosphorus or arsenic. In such examples, the doped silicon layer can be deposited by introducing at least a first silicon precursor and phosphine (PH3) into a reaction chamber to form a phosphorus-doped silicon layer (Si:P). In further non-limiting examples, the doped silicon layer may include, for example, a p-type layer doped with boron. In such examples, the doped silicon layer can be deposited by introducing at least a first silicon precursor and diborane (B2H6) into the reaction chamber to form a boron-doped silicon layer (Si:B).

[0072] In some embodiments, the doped silicon layer is 1 × 10 16 ~1 × 10 21 cm -3 It can be epitaxially deposited at dopant concentrations. Furthermore, the doped silicon layer can be epitaxially deposited on the substrate with an average layer thickness of 1 nanometer (nm) to 1000 nm.

[0073] In some embodiments, a single carbon-doped silicon layer is deposited to form a blocking layer configured to prevent the migration of dopants into the channel layer of the semiconductor layer stack. In such embodiments, the single carbon-doped silicon layer may be deposited either before or after the deposition of the channel layer.

[0074] In some embodiments, a single carbon-doped silicon layer is deposited before depositing the channel layer. The carbon-doped silicon layer is deposited directly on the doped silicon layer (e.g., source / drain layer), thereby forming a blocking layer that can reduce the migration of dopant species from the doped silicon layer into the subsequently deposited channel layer. The carbon-doped silicon layer may be positioned between the doped silicon layer and the channel layer.

[0075] Therefore, referring again to Figure 2, the method flow 200 may include placing the substrate in the reaction chamber (step 202), depositing a doped silicon layer on the substrate (step 204), depositing a carbon-doped silicon layer directly on the doped silicon layer (step 206), depositing a channel layer directly on the carbon-doped silicon layer (step 208), and depositing an additional doped silicon layer on the channel layer (step 212). In such exemplary embodiments, step 210, which involves depositing a carbon-doped silicon layer on the channel layer, is omitted.

[0076] Figure 4 shows a portion of a vertical channel transistor structure 400 including a semiconductor layer stack 404 deposited by the method described above. The semiconductor layer stack 404 includes a single blocking layer (i.e., a carbon-doped silicon layer 408) disposed between the doped silicon layer 406 and the channel layer 410. As shown in Figure 4, a portion of the vertical channel transistor structure 400 includes a substrate 402 and a semiconductor layer stack 404 disposed on the substrate 402. In such an embodiment, the semiconductor layer stack 404 includes a doped silicon layer 406 disposed on the substrate 402, a carbon-doped silicon layer 408 disposed on the doped silicon layer 406, a channel layer 410 disposed on the carbon-doped silicon layer 408, and an additional doped silicon layer 412 disposed on the channel layer 410.

[0077] In some embodiments, a single carbon-doped silicon layer is deposited after the channel layer. In such embodiments, the carbon-doped silicon layer may be deposited directly on the channel layer, thereby forming a blocking layer that can reduce the migration of dopant species from additional doped silicon layers (e.g., source / drain layers) subsequently deposited on the channel layer. In such embodiments, the carbon-doped silicon layer is positioned between the channel layer and the additional doped silicon layer.

[0078] Therefore, referring again to Figure 2, the method flow 200 may include placing the substrate in the reaction chamber (step 202), depositing a doped silicon layer on the substrate (step 204), depositing a channel layer directly onto the doped silicon layer (step 208), depositing a carbon-doped silicon layer directly onto the channel layer (step 210), and depositing an additional doped silicon layer onto the channel layer (step 212). In such exemplary embodiments, step 206, which involves depositing a carbon-doped silicon layer onto the doped silicon layer, is omitted.

[0079] Figure 5 shows a portion of a vertical channel transistor structure 500 including a semiconductor layer stack 504 deposited by the method described above. The semiconductor layer stack 504 includes a single blocking layer (i.e., a carbon-doped silicon layer 510) disposed between the channel layer 508 and an additional doped silicon layer 512. As shown in Figure 5, a portion of the vertical channel transistor structure 500 includes a substrate 502 and a semiconductor layer stack 504 disposed on the substrate 502. In such an embodiment, the semiconductor layer stack 504 includes a doped silicon layer 506 disposed on the substrate 502, a channel layer 508 disposed on the doped silicon layer 506, a carbon-doped silicon layer 510 disposed on the channel layer 508, and an additional doped silicon layer 512 disposed on the carbon-doped silicon layer 510.

[0080] In some embodiments, a pair of carbon-doped silicon layers are deposited to form a blocking layer configured to prevent or reduce the migration of dopants from both the doped silicon layer (e.g., a first source / drain layer) and the additional doped silicon layer (e.g., a second source / drain layer) into the channel layer of the semiconductor layer stack. In such embodiments, the pair of carbon-doped silicon layers are deposited before and after the deposition of the channel layer.

[0081] Therefore, referring again to Figure 2, the method flow 200 may include placing a substrate in a reaction chamber (step 202), depositing a doped silicon layer on the substrate (step 204), depositing a carbon-doped silicon layer directly on the doped silicon layer (step 206), depositing a channel layer directly on the carbon-doped silicon layer (step 208), depositing a carbon-doped silicon layer (also referred to herein as an additional carbon-doped silicon layer) directly on the channel layer (step 210), and depositing an additional doped silicon layer on the carbon-doped silicon layer (step 212).

[0082] Figure 6 shows a portion of a vertical channel transistor structure 600 including a semiconductor layer stack 604 deposited by the method described above. It includes a pair of blocking layers (i.e., a carbon-doped silicon layer 608 and an additional carbon-doped silicon layer 612) disposed on either side of the channel layer 610 between the doped silicon layer 606 and an additional doped silicon layer 614. As shown in Figure 6, a portion of the vertical channel transistor structure 600 includes a substrate 602 and a semiconductor layer stack 604 disposed on the substrate 602. In such an embodiment, the semiconductor layer stack 604 includes a doped silicon layer 606 disposed on the substrate 602, a carbon-doped silicon layer 608 disposed on the doped silicon layer 606, a channel layer 610 disposed on the carbon-doped silicon layer 608, an additional carbon-doped silicon layer 612 disposed on the channel layer 610, and an additional doped silicon layer 614 disposed on the additional carbon-doped silicon layer 612.

[0083] According to an example of the present disclosure, the carbon-doped silicon layer and additional carbon-doped silicon layers deposited by step 206 and / or step 210 of method flow 200 can be epitaxially deposited on a substrate by introducing at least a second silicon precursor and a carbon dopant gas into a reaction chamber to epitaxially deposit the carbon-doped silicon layer. The second silicon precursor may include one or more of the silicon precursors described herein, and the carbon dopant gas may include one or more of the carbon dopant gases described above. In non-limiting examples, the carbon-doped silicon layer may be, for example, methylsilane (CH3SiH3), neopentasilane (Si5H3), etc. 12 ), can be deposited by introducing at least a second silicon precursor and a carbon dopant gas, including organosilicon compounds such as trimethylsilane (C3H9Si) and tetramethylsilane (Si(CH3)4).

[0084] In various embodiments, the carbon-doped silicon layer(s) may be 1 × 10 17 cm -3 ~1 × 1021 cm -3 It can be epitaxially deposited at carbon doping concentrations.

[0085] In various embodiments, carbon-doped silicon layers may be epitaxially deposited using both a carbon dopant and a further dopant. In such embodiments, carbon-doped silicon layers may be co-doped with both a carbon dopant and a further dopant. The further dopant in the carbon-doped silicon layer may include one or more of the aforementioned dopants, such as phosphorus (P), boron (B), and arsenic (As). As a non-limiting example, a co-doped carbon-doped silicon layer can be deposited by introducing at least a second silicon precursor, a carbon dopant gas, and a further dopant gas, the further dopant gas being selected from one or more of the aforementioned dopant gases (e.g., phosphine, arsine, diborane, etc.). In one embodiment, the carbon-doped silicon layer is co-doped with a further dopant, and the concentration of the further dopant is 1 × 10⁻⁶. 16 cm -3 ~1 × 10 21 cm -3 That is the case.

[0086] In various embodiments, carbon-doped silicon layers (multiple layers) (e.g., either doped or co-doped) can be epitaxially deposited on a substrate to an average layer thickness of 0.1 nm to 30 nm.

[0087] Referring again to the method flow 200 in Figure 2, the step of depositing the channel layer may include epitaxially depositing the channel layer (step 208). In such an example, the channel layer may be epitaxially deposited on the substrate by introducing at least a third silicon precursor into the reaction chamber and epitaxially depositing the silicon channel layer. The third silicon precursor may include one or more of the silicon precursors described herein. In non-limiting examples, the channel layer may include an undoped silicon channel layer or an intrinsically doped silicon channel layer. In some embodiments, the channel layer includes a silicon channel layer epitaxially deposited on the substrate to an average layer thickness of 1 nm to 1000 nm, or 50 nm to 500 nm, or 100 nm to 300 nm.

[0088] In an example of this disclosure, an additional doped silicon layer may be epitaxially deposited on a substrate as described above with respect to the doped silicon layer. In a non-limiting example, the additional doped silicon layer may include an n-type silicon layer doped with at least one of phosphorus and arsenic. In such an example, the additional doped silicon layer can be deposited by introducing at least a first silicon precursor and phosphine (PH3) into a reaction chamber to form a phosphorus-doped silicon layer (Si:P) as described above. In a further non-limiting example, the additional doped silicon layer may include a boron-doped p-type silicon layer. In such an example, the additional doped silicon layer can be deposited by introducing at least a first silicon precursor and diborane (B2H6) into a reaction chamber to form a boron-doped silicon layer (Si:B). The additional doped silicon layer may be 1 × 10⁻⁶ 16 ~1 × 10 21 cm -3 Epitaxial deposition is possible at dopant concentrations. Furthermore, additional doped silicon layers can be epitaxially deposited on the substrate with an average layer thickness of 1 nm to 1000 nm.

[0089] For the purpose of summarizing the advantages of the present invention and the advantages achieved over the prior art, certain objectives and advantages of the present invention are described above herein. Naturally, it can be understood that not all of these objectives or advantages are necessarily achieved according to any particular embodiment of the present invention. Thus, a person skilled in the art will recognize that the present invention may be embodied or practiced in a manner that achieves or optimizes one or a group of advantages as taught or suggested herein, without necessarily achieving other objectives or advantages as taught or suggested herein.

[0090] All of the embodiments described above are intended to be within the scope of the present invention disclosed herein. While the above and other embodiments may be readily apparent to those skilled in the art from the detailed description of specific embodiments with reference to the accompanying drawings, the present invention is not limited to any specific embodiment disclosed.

Claims

1. A method for forming a semiconductor layer stack including at least a portion of a vertical channel transistor structure, Placing the substrate inside the reaction chamber, Depositing a doped silicon layer onto the substrate, Depositing the channel layer onto the substrate, This includes depositing a carbon-doped silicon layer between the doped silicon layer and the channel layer, A method wherein the carbon-doped silicon layer includes a blocking layer configured to reduce the migration of dopant species from the doped silicon layer into the channel layer.

2. The method according to claim 1, wherein the carbon-doped silicon layer is deposited directly on the doped silicon layer.

3. The method according to claim 2, wherein the channel layer is deposited directly on the carbon-doped silicon layer.

4. The method according to claim 3, wherein an additional carbon-doped silicon layer is deposited directly on the channel layer.

5. The method according to claim 1, wherein the carbon-doped silicon layer is deposited directly on the channel layer.

6. The method according to claim 5, wherein an additional doped silicon layer is deposited directly on the carbon-doped silicon layer.

7. The method according to claim 1, wherein the semiconductor layer stack is deposited by an isothermal deposition process at a deposition temperature selected between 500°C and 850°C.

8. The method according to claim 1, wherein the doped silicon layer comprises an epitaxially doped silicon layer doped with at least one of phosphorus and arsenic.

9. The method according to claim 1, wherein the carbon-doped silicon layer includes an epitaxial carbon-doped silicon layer.

10. The epitaxial carbon-doped silicon layer is 1 × 10 １７ cm －３ ~1 x 10 ２１ cm －３ The method according to claim 9, wherein the deposit is made at a carbon doping concentration.

11. The epitaxial carbon-doped silicon layer is co-doped with a further dopant, and the concentration of the further dopant is 1 × 10⁻¹⁶ １６ cm －３ ~1 x 10 ２１ cm －３ The method according to claim 10.

12. A method for epitaxially depositing a semiconductor layer stack including at least a portion of a vertical channel transistor structure, Placing the silicon substrate inside the reaction chamber, The doped silicon layer is epitaxially deposited on the silicon substrate, Direct epitaxial deposition of a carbon-doped silicon layer onto the aforementioned doped silicon layer, This includes directly epitaxially depositing a silicon channel layer onto the carbon-doped silicon layer, A method wherein the semiconductor layer stack is deposited by an isothermal chemical deposition process without disrupting the vacuum in the reaction chamber.

13. The method according to claim 12, further comprising directly epitaxially depositing an additional carbon-doped silicon layer onto the silicon channel layer.

14. At least one of the carbon-doped silicon layer and the additional carbon-doped silicon layer is deposited at a carbon doping concentration of 1×10 １７ cm －３ to 1×10 ２１ cm －３ The method according to claim 13, wherein the method is carried out.

15. At least one of the carbon-doped silicon layer and the additional carbon-doped silicon layer is co-doped with a further dopant, wherein the further dopant is 1 × 10 １６ cm －３ ~1 x 10 ２１ cm －３ The method according to claim 14, having the concentration of [a certain value].

16. A method for forming a semiconductor layer stack including at least a portion of a vertical channel transistor structure, Placing the silicon substrate inside the reaction chamber, The silicon substrate is heated to a deposition temperature selected between 500°C and 850°C, The semiconductor layer stack is epitaxially deposited by an isothermal chemical deposition process, The process involves introducing at least a first silicon precursor and a dopant gas into the reaction chamber and epitaxially depositing a doped silicon layer onto the silicon substrate, The method involves introducing at least a second silicon precursor and a carbon dopant gas into the reaction chamber, and directly epitaxially depositing a carbon-doped silicon layer onto the doped silicon layer, The method includes introducing at least a third silicon precursor into the reaction chamber and directly epitaxially depositing a silicon channel layer onto the carbon-doped silicon layer, A method wherein the carbon-doped silicon layer forms a blocking layer that reduces the migration of dopant species from the doped silicon layer into the silicon channel layer.

17. The method according to claim 16, wherein the reaction chamber comprises a quartz assembly including an upper wall and a lower wall, the upper wall extending longitudinally between an injection chamber flange and an exhaust chamber flange opposite in the longitudinal direction, and the lower wall being below and parallel to the upper wall.

18. Heating the aforementioned silicon substrate is By using at least one of the upper heater element array positioned above the upper wall of the reaction chamber and the lower heater element array positioned below the lower wall of the reaction chamber, the silicon substrate disposed inside the chamber of the reaction chamber is radiantly heated. The method according to claim 17, comprising maintaining the isothermal deposition process by monitoring and controlling the temperature of the silicon substrate and at least one of the semiconductor layer stacks thereon using one or more temperature sensors and a controller that operably communicates with at least one of the upper heater element array and the lower heater element array.

19. The carbon-doped silicon layer is 1 × 10 １７ cm －３ ~1 x 10 ２１ cm －３ The method according to claim 18, wherein the deposit is made at a carbon doping concentration.

20. The carbon-doped silicon layer is co-doped with a further dopant, the further dopant being 1 × 10 １６ cm －３ ~1 x 10 ２１ cm －３ The method according to claim 19, having the concentration of [a certain value].

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