Field-effect transistor and method for manufacturing the same

Abstract

The objective is to provide a field-effect transistor that can shorten the gate length without forming spike grooves. [Solution] The device comprises an active layer 2 containing GaAs formed on a semi-insulating substrate 1, a recess 8 formed in the active layer 2 between a source electrode 3 and a drain electrode 4, an insulating film 5a formed in the active layer 2 extending toward the recess 8, an insulating film 5b formed in the active layer 2 extending to the upper part of the recess 8 on the electrode 4 side, and a gate electrode 14 having a recessed portion 13 of platinum arsenide layer that sinks from the recess bottom surface 20 toward the substrate 1 side. The gate electrode 14 comprises a sequentially formed titanium layer 9, platinum layer 10, and gold layer 12. The titanium layer 9 is formed on the recess bottom surface 20 and the insulating film 5b. The platinum layer 10 is formed on the opposite surfaces 45a, 45b and the side surfaces 46a, 46b on the electrode 3 side of the titanium layer 9. The recessed portion 13 is connected to the platinum layer 10.

Description

Technical Field

[0001] The present disclosure relates to a field effect transistor and a method for manufacturing the same.

Background Art

[0002] With the increase in the high frequency of field effect transistors, the gate length has been shortened. As an example of a field effect transistor with a very short gate length, a spike gate type FET (Field Effect Transistor) is disclosed in Patent Document 1. The spike gate type FET shown in FIG. 11 of Patent Document 1 includes a gate electrode having a convex portion protruding in a spike shape on an insulating semiconductor layer on the surface side of a channel layer, and controls the current between a source electrode and a drain electrode by the convex portion of the gate electrode. The spike gate type FET has a spike gate structure in which the gate electrode structure has a convex portion. The channel layer is an active layer in which a channel is formed. The gate length of the spike gate type FET corresponds to the length of the convex portion in the direction in which the current flows between the source electrode and the drain electrode, that is, the current direction. The spike gate type FET adjusts the gate length by a spike groove that forms the convex portion of the gate electrode in the channel layer, that is, the active layer. The gate electrode of the spike gate type FET has, together with the convex portion, a source side overlap portion that covers the channel layer from the convex portion to the source electrode side and a drain side overlap portion that covers the channel layer from the convex portion to the drain electrode side.

[0003] The manufacturing process of the spike gate type FET shown in FIG. 11 of Patent Document 1 is shown in FIG. 12 of Patent Document 1. In order to form the spike groove of the spike gate type FET, a thin resist pattern is formed on the channel layer, and then a silicon oxide film is laminated, and a first groove is formed from a thin opening of the silicon oxide film formed by the lift-off method. Further, by etching the channel layer having the first groove, a recess and a spike groove are formed in the channel layer. The spike groove corresponds to the tip side of the first groove. The method of forming this spike groove will be referred to as the first spike groove forming method.

[0004] Furthermore, Figure 1 of Patent Document 1 discloses a method for forming spike grooves in a spike gate type FET using direct drawing technology of FIB (Focused Ion Beam). This method for forming spike grooves will be referred to as the second spike groove formation method. In the second spike groove formation method, a narrow damage layer with a width of about 0.1 μm is formed in the channel layer, and recesses and spike grooves are formed in the channel layer by etching the channel layer having the damage layer. The spike grooves are formed by utilizing the difference in etching rates between the damage layer and the channel layer other than the damage layer. The width of the spike groove, i.e., the length in the direction perpendicular to the depth direction, corresponds to the width of the damage layer formed by FIB. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 10-209178 [Overview of the project] [Problems that the invention aims to solve]

[0006] Although the spike-gate type FET described in Patent Document 1 can achieve high performance by shortening the gate length, it uses a first spike groove formation method and a second spike groove formation method, making the process of determining the gate length, i.e., the process of forming the spike groove, complex. For this reason, spike-gate structures are not generally adopted in field-effect transistors.

[0007] The present disclosure aims to provide a field-effect transistor that can shorten the gate length without forming spike grooves. [Means for solving the problem]

[0008] The field-effect transistor according to this disclosure comprises an active layer containing GaAs formed on a semi-insulating substrate; a source electrode and a drain electrode formed on the opposite side of the active layer, which is the side of the active layer opposite to the semi-insulating substrate; a recess formed between the source electrode and the drain electrode on the opposite side of the active layer; a source-side insulating film formed on the opposite side of the active layer, covering the source electrode and extending toward the recess; a drain-side insulating film formed on the opposite side of the active layer, covering the drain electrode and extending to the upper part of the recess on the drain electrode side; and a gate electrode formed on the bottom surface of the recess and having a recessed portion that sinks in toward the semi-insulating substrate side from the bottom surface of the recess. The gate electrode comprises a titanium layer, a platinum layer, and a gold layer. The titanium layer has a drain-side overlap portion that extends from the recessed portion toward the drain electrode side and is formed on the bottom surface of the recess, and is formed riding on the drain-side insulating film. The platinum layer is formed on the opposite side of the titanium layer, which is the side of the titanium layer opposite to the semi-insulating substrate, and on the side surface of the titanium layer on the source electrode side. The gold layer is formed on the side of the platinum layer opposite the semi-insulating substrate and on the side of the platinum layer on the source electrode side. The recessed portion is a platinum arsenide layer connected to the platinum layer. [Effects of the Invention]

[0009] According to the field-effect transistor of this disclosure, the gate electrode has a recessed portion of the platinum arsenide layer that sinks from the bottom surface of the recess towards the semi-insulating substrate, so the gate length can be shortened without forming a spike groove. [Brief explanation of the drawing]

[0010] [Figure 1] This is a cross-sectional view showing a field-effect transistor according to Embodiment 1. [Figure 2] This figure shows the cross-sectional shape of the titanium layer in the gate electrode of Figure 1. [Figure 3] This figure shows the cross-sectional shape of the platinum layer in the gate electrode of Figure 1. [Figure 4] This figure shows the cross-sectional shape of the recessed portion of the gate electrode in Figure 1. [Figure 5] It is a cross-sectional view showing a method for manufacturing the field-effect transistor of FIG. 1. [Figure 6] It is a cross-sectional view showing a method for manufacturing the field-effect transistor of FIG. 1. [Figure 7] It is a cross-sectional view showing a method for manufacturing the field-effect transistor of FIG. 1. [Figure 8] It is a cross-sectional view showing a method for manufacturing the field-effect transistor of FIG. 1. [Figure 9] It is a cross-sectional view showing a method for manufacturing the field-effect transistor of FIG. 1. [Figure 10] It is a cross-sectional view showing a method for manufacturing the field-effect transistor of FIG. 1. [Figure 11] It is a cross-sectional view showing a method for manufacturing the field-effect transistor of FIG. 1. [Figure 12] It is a cross-sectional view showing a method for manufacturing the field-effect transistor of FIG. 1. [Figure 13] It is a cross-sectional view showing a method for manufacturing the field-effect transistor of FIG. 1. [Figure 14] It is a cross-sectional view showing a method for manufacturing the field-effect transistor of FIG. 1. [Figure 15] It is a cross-sectional view showing the active layer of FIG. 1. [Figure 16] It is a cross-sectional view showing the gate electrode and the active layer of the comparative example. [Figure 17] It is a cross-sectional view showing the gate electrode and the active layer according to Embodiment 1. [Figure 18] It is a diagram for explaining the gate-source capacitance in the field-effect transistor of FIG. 16. [Figure 19] It is a diagram for explaining the gate-source capacitance in the field-effect transistor of FIG. 17.

Embodiments for Carrying Out the Invention

[0011] Embodiment 1. FIG. 1 is a cross-sectional view showing a field-effect transistor according to Embodiment 1. FIG. 2 is a view showing a cross-sectional shape of a titanium layer in the gate electrode of FIG. 1, and FIG. 3 is a view showing a cross-sectional shape of a platinum layer in the gate electrode of FIG. 1. FIG. 4 is a view showing a cross-sectional shape of a recess portion in the gate electrode of FIG. 1. FIGS. 5 to 14 are cross-sectional views showing a method of manufacturing the field-effect transistor of FIG. 1, and FIG. 15 is a cross-sectional view showing the active layer of FIG. 1. FIG. 16 is a cross-sectional view showing a gate electrode and an active layer of a comparative example, and FIG. 17 is a cross-sectional view showing a gate electrode and an active layer according to Embodiment 1. FIG. 18 is a view for explaining the gate-source capacitance in the field-effect transistor of FIG. 16, and FIG. 19 is a view for explaining the gate-source capacitance in the field-effect transistor of FIG. 17. The field-effect transistor 100 of Embodiment 1 includes a semi-insulating substrate 1, an active layer 2 having a HEMT (High Electron Mobility Transistor) structure including GaAs formed on the semi-insulating substrate 1, a source electrode 3 and a drain electrode 4 formed on the active layer 2, a recess 8 formed between the source electrode 3 and the drain electrode 4 in the active layer 2, a gate electrode 14 formed in the recess 8, and an insulating film 5 for insulating the source electrode 3, the drain electrode 4, and the gate electrode 14. A direction perpendicular to the semi-insulating substrate 1 is defined as the Z direction, a direction from the source electrode 3 to the drain electrode 4 perpendicular to the Z direction is defined as the X direction, and a direction perpendicular to the Z direction and the X direction is defined as the Y direction. A surface of the active layer 2 on the side of the semi-insulating substrate 1 is defined as a facing surface facing the semi-insulating substrate 1, and a surface of the active layer 2 on the side opposite to the semi-insulating substrate 1 is defined as an opposite surface. Also, in each layer of the object, that is, the source electrode 3, the drain electrode 4, the insulating film 5, and the gate electrode 14, a surface facing the semi-insulating substrate 1 is defined as a facing surface, and a surface of the object on the side opposite to the semi-insulating substrate 1 is defined as an opposite surface. When describing including the side surface of the object in the facing surface, the facing surface and the side surface are defined as the facing side surface, and when describing including the side surface of the object in the opposite surface, the opposite surface and the side surface are defined as the opposite side surface.

[0012] Recess 8 is formed between the source electrode 3 and the drain electrode 4 on the opposite side of the active layer 2, i.e., the opposite side of the active layer, and has a recess bottom surface 20, a recess end 19a on the source electrode 3 side, and a recess end 19b on the drain electrode 4 side (see Figure 10). Note that the recess bottom surface 20 is also the opposite side of the active layer. The gate electrode 14 has a recessed portion 13 formed by sinking in toward the semi-insulating substrate 1 from the recess bottom surface 20, i.e., the opposite side of the active layer, i.e., the opposite side of the active layer, and a drain-side overlap portion 25 that extends from the recessed portion 13 toward the drain electrode 4 and is formed on the recess bottom surface 20, and comprises a titanium layer 9 formed on the insulating film 5b on the drain side, a platinum layer 10 formed on the opposite side of the titanium layer 9, and a gold layer 12 formed on the opposite side of the platinum layer 10. The platinum layer 10 is connected to the recessed portion 13. In Figure 1, the opposite side of the titanium layer 9 on which the platinum layer 10 is formed is the positive Z-direction and negative X-direction surfaces of the titanium layer 9, i.e., the opposite titanium layer (opposite surfaces 45a, 45b) and the titanium layer side on the source electrode 3 side (source side surfaces 46a, 46b). In Figure 1, the opposite side of the platinum layer 10 on which the gold layer 12 is formed is the positive Z-direction and negative X-direction surfaces of the platinum layer 10, i.e., the opposite platinum layer (opposite surfaces 56a, 56b) and the platinum layer side on the source electrode 3 side (source side surface 57b). The cross-sectional shapes of the titanium layer 9 and the platinum layer 10 will be described later. The semi-insulating substrate 1 is a GaAs semiconductor substrate. The active layer 2 comprises, for example, a GaAs buffer layer 31, an electron transport layer 32, an electron supply layer 33, and an n-type GaAs (nGaAs) layer 34 sequentially formed on the semi-insulating substrate 1. The electron transport layer 32 is an undoped InGaAs (i-InGaAs) layer, and the electron supply layer 33 is an n-type AlGaAs (i-InGaAs) layer with a high n-type impurity concentration. + -It is an AlGaAs layer.

[0013] The recessed portion 13 is a platinum arsenide layer, or PtAs2 layer, formed when the platinum (Pt) of the platinum layer 10 sinks into the n-type GaAs layer 34 of the active layer 2 due to the heat treatment in the recessed portion formation process described later. The bottom surface 20 of the recess 8 is formed in the n-type GaAs layer 34 of the active layer 2. That is, the depth of the recess 8, i.e., the depth in the Z direction, is smaller than the thickness of the n-type GaAs layer 34.

[0014] The insulating film 5 has an insulating film opening 17 that separates it into insulating film 5a on the source electrode 3 side and insulating film 5b on the drain electrode 4 side (see Figure 8). Note that insulating film 5a and insulating film 5b may also be connected in the Y direction. The insulating film is generally denoted as 5, and 5a and 5b are used to distinguish between them. When appropriate, insulating film 5a will be referred to as source-side insulating film 5a, and insulating film 5b as drain-side insulating film 5b. The end of insulating film 5a on the drain electrode 4 side is insulating film end 18a, and the end of insulating film 5b on the source electrode 3 side is insulating film end 18b. Insulating film end 18a is also the end of the insulating film opening 17 on the source electrode 3 side, and insulating film end 18b is also the end of the insulating film opening 17 on the drain electrode 4 side. The end of recess 8 on the source electrode 3 side is recess end 19a, and the end of recess 8 on the drain electrode 4 side is recess end 19b (see Figure 10).

[0015] The insulating film 5a is formed to cover the source electrode 3 and extend toward the recess 8 to cover a portion of the opposite surface of the active layer 2. The insulating film end 18a of the insulating film 5a is positioned between the source electrode 3 and the recess end 19a of the recess 8. That is, the insulating film end 18a of the insulating film 5a is positioned closer to the source electrode 3 than the recess end 19a, which is the end of the recess 8 on the source electrode 3 side. The insulating film 5b is formed to cover the drain electrode 4 and extend toward the recess 8 to cover the surface, i.e., the opposite surface of the active layer 2 and a portion of the upper part of the recess 8, away from the recess bottom surface 20 of the recess 8. That is, the insulating film 5b is formed on the opposite surface of the active layer 2, covering the drain electrode 4 and extending to the upper part of the recess 8 on the drain electrode 4 side. The insulating film end 18b of the insulating film 5b is positioned between the recess end 19a and the recess end 19b. The tip of the insulating film 5b on the source electrode 3 side is floating away from the active layer 2. In other words, the insulating film 5b is formed to encompass the drain electrode 4 side of the recess 8 without contacting the recess bottom surface 20 side of the recess end 19b of the recess 8 or the recess bottom surface 20 of the recess 8. The tip of the insulating film 5b on the source electrode 3 side is the tip of the drain-side insulating film 5b on the source electrode 3 side, and can therefore also be called the tip of the drain-side insulating film. Figure 1 shows an example in which the insulating film 5b is not connected to all sides of the recess end 19b of the recess 8. The cavity 30 shown in Figure 1 is a space surrounded by the recess bottom surface 20 and the side of the recess end 19b of the recess 8, the opposing surface of the insulating film 5b, and the drain-side surface 47a of the titanium layer 9.

[0016] The cross-sectional shape of the titanium layer 9 of the gate electrode 14 is described below. The titanium layer 9 has a first titanium stage 41 on the semi-insulating substrate 1 side, a second titanium stage 42 positioned further away from the semi-insulating substrate 1 than the first titanium stage 41, and a titanium connection portion 43 connecting the first titanium stage 41 and the second titanium stage 42. The surface of the first titanium stage 41 on the semi-insulating substrate 1 side is the opposing surface 44a, and the surface of the second titanium stage 42 on the semi-insulating substrate 1 side is the opposing surface 44b. The surface of the first titanium stage 41 opposite to the semi-insulating substrate 1 is the opposite surface 45a, and the surface of the second titanium stage 42 opposite to the semi-insulating substrate 1 is the opposite surface 45b. The dashed line 48a is a line extending from the opposite surface 45a in the positive X direction and also indicates the boundary between the first titanium stage 41 and the titanium connection portion 43. The dashed line 48b is a line extending from the opposing surface 44b in the negative X direction and also indicates the boundary between the second titanium stage 42 and the titanium connection portion 43. The negative X-side of the titanium layer 9, i.e., the side facing the source electrode 3, is the source side 46a and the source side 46b. The source side 46a is the negative X-side of the titanium first stage 41, i.e., the side facing the source electrode 3. The source side 46b is the negative X-side of the titanium second stage 42 and the titanium connection part 43, i.e., the side facing the source electrode 3. The positive X-side of the titanium layer 9, i.e., the side facing the drain electrode 4, is the drain side 47a and the drain side 47b. The drain side 47a is the positive X-side of the titanium first stage 41 and the titanium connection part 43, i.e., the side facing the drain electrode 4. The drain side 47b is the positive X-side of the titanium second stage 42, i.e., the side facing the drain electrode 4.

[0017] The titanium layer 9 of the gate electrode 14 is formed such that the source electrode 3 side is connected to the opposite side of the active layer 2, i.e., the bottom surface 20 of the recess 8, and the drain electrode 4 side rides on the insulating film 5b. More specifically, the titanium layer 9 of the gate electrode 14 has the opposing surface 44a of the first titanium stage 41 located on the source electrode 3 side connected to the opposite side of the active layer 2, i.e., the bottom surface 20 of the recess 8, the opposing surface 44b of the second titanium stage 42 located on the drain electrode 4 side connected to the opposite side of the insulating film 5b, i.e., the opposite surface of the insulating film, and the drain-side surface 47a is connected to the insulating film end 18b of the insulating film 5b.

[0018] The cross-sectional shape of the platinum layer 10 of the gate electrode 14 will now be described. The platinum layer 10 has a first platinum stage 51 connected to the first titanium stage 41, a second platinum stage 52 positioned further away from the semi-insulating substrate 1 than the first platinum stage 51, a platinum connecting portion 53 connecting the first platinum stage 51 and the second platinum stage 52, and a platinum extended portion 54 extending from the first platinum stage 51 toward the semi-insulating substrate 1. The surface of the first platinum stage 51 toward the semi-insulating substrate 1 is the opposing surface 55b, the surface of the second platinum stage 52 toward the semi-insulating substrate 1 is the opposing surface 55c, and the surface of the platinum extended portion 54 toward the semi-insulating substrate 1 is the opposing surface 55a. The surface of the first platinum stage 51 opposite to the semi-insulating substrate 1 is the opposite surface 56a, and the surface of the second platinum stage 52 opposite to the semi-insulating substrate 1 is the opposite surface 56b. The dashed line 59a is a line extending from the opposing surface 55b to the negative X direction, and also indicates the boundary between the first platinum stage 51 and the platinum extension portion 54. The dashed line 59b is a line extending from the opposite surface 56a to the positive X direction, and also indicates the boundary between the first platinum stage 51 and the platinum connection portion 53. The dashed line 59c is a line extending from the opposing surface 55c to the negative X direction, and also indicates the boundary between the second platinum stage 52 and the platinum connection portion 53. The negative X-side of the platinum layer 10, i.e., the side facing the source electrode 3, is the source side surface 57a and the source side surface 57b. The source side surface 57a is the negative X-side of the first platinum stage 51 and the platinum extension portion 54, i.e., the side facing the source electrode 3. The source side surface 57b is the negative X-side of the second platinum stage 52 and the platinum connection portion 53, i.e., the side facing the source electrode 3. The sides of the platinum layer 10 on the positive X-direction side, i.e., the drain electrode 4 side, are drain side 58a, drain side 58b, and drain side 58c. Drain side 58a is the side of the platinum stretched portion 54 on the positive X-direction side, i.e., the drain electrode 4 side. Drain side 58b is the side of the platinum first stage 51 and the platinum connecting portion 53 on the positive X-direction side, i.e., the drain electrode 4 side. Drain side 58c is the side of the platinum second stage 52 on the positive X-direction side, i.e., the drain electrode 4 side.

[0019] A platinum layer 10 is formed on the opposite side of the titanium layer 9, that is, on the side opposite to the side connected to the active layer 2 and the insulating film 5b. More specifically, the platinum layer 10 is formed on the source side surface 46a, the opposite side 45a, the source side surface 46b, and the opposite side 45b of the titanium layer 9. The drain side surface 58a, the opposing surface 55b, the drain side surface 58b, and the opposing surface 55c of the platinum layer 10 are connected to the source side surface 46a, the opposite side 45a, the source side surface 46b, and the opposite side 45b of the titanium layer 9. The second platinum stage is connected to the second titanium stage 42. The opposing surface 55a of the platinum layer 10, that is, the opposing surface 55a of the platinum stretched portion 54, is connected to the recessed portion 13.

[0020] The gold layer 12 is formed on the opposite side of the platinum layer 10. More specifically, the gold layer 12 is formed on the opposite side 56a, the source side 57b, and the opposite side 56b of the platinum layer 10. Figure 1 shows an example where the gold layer 12 does not cover the source side 57a or the drain side 58c. However, the gold layer 12 may cover the opposite side 56a of the source side 57a, and may also cover the opposite side 55b of the source side 57a if it is separated from the sinking portion 13. Furthermore, the gold layer 12 may also cover the drain side 58c.

[0021] The gate length Lg1 of the field-effect transistor 100 in Embodiment 1 is the length in the X direction of the recessed portion 13 of the gate electrode 14, and is 0.02 μm to 0.1 μm. The overlap length Lg2 on the drain electrode 4 side of the field-effect transistor 100 in Embodiment 1 is the length in the X direction of the titanium layer 9 connected to the active layer 2, and is approximately 0.1 μm. The cross-sectional shape of the recessed portion 13 can be approximated as an inverted trapezoid. The lower base of the inverted trapezoidal recessed portion 13 is connected to the opposing surface 55a of the platinum layer 10, and the upper base of the trapezoid is the boundary with the active layer 2. Note that in Figures 18 and 19, the cross-sectional shape of the recessed portion 13 is shown as a quadrilateral for ease of explanation. The thickness of the recessed portion 13, i.e., the recessed length dg in the Z direction, is approximately twice the thickness of the platinum layer 10. The thickness of the platinum layer 10 is the thickness of the first platinum layer 51 or the second platinum layer, that is, the thickness from the opposing surface 55b to the opposite surface 56a of the platinum layer 10 or from the opposing surface 55c to the opposite surface 56b of the platinum layer 10.

[0022] In the field-effect transistor 100 of Embodiment 1, the recessed portion 13 that determines the gate length Lg1 is a platinum arsenide (PtAs2) layer, so the gate length can be shortened by heat treatment without forming spike grooves like the spike-gate type FET of Patent Document 1. In the field-effect transistor 100 of Embodiment 1, the recessed portion 13 can be formed by heat treatment in the recessed portion formation process, so unlike the spike-gate type FET of Patent Document 1, a complex process for forming spike grooves is unnecessary, and the manufacturing method is simpler than that of the spike-gate type FET of Patent Document 1.

[0023] Next, the manufacturing method of the field-effect transistor 100 of Embodiment 1 will be described. As shown in Figure 5, an active layer 2 containing GaAs is formed on a semi-insulating substrate 1 (active layer formation step). Subsequently, the materials for the source electrode 3 and drain electrode 4 are formed on the active layer 2, and then etching is performed using a patterned resist mask to form the source electrode 3 and drain electrode 4 (source-drain electrode formation step). The active layer 2 has a HEMT structure, and when forming the active layer 2 shown in Figure 15, the semiconductor materials constituting the active layer 2 are sequentially formed on the semi-insulating substrate 1. That is, a buffer layer 31, an electron transport layer 32, an electron supply layer 33, and an n-type GaAs layer 34 are sequentially formed on the semi-insulating substrate 1.

[0024] After the source-drain electrode formation process, as shown in Figure 6, an insulating film 5, such as SiN with a thickness of 50 nm to 200 nm, is formed on the source electrode 3, drain electrode 4, and exposed active layer 2 (insulating film formation process). After the insulating film formation process, as shown in Figure 7, a first resist 6 with a patterned opening 61, 0.5 μm to 1.5 μm in thickness, is formed (first resist formation process). Subsequently, the insulating film 5 is removed by etching or the like to form an insulating film opening 17 that exposes the opposite side of the active layer 2 (insulating film opening formation process). Then, as shown in Figure 8, the first resist 6 is removed by oxygen asher or the like to form a base structure with the active layer 2 exposed. The base structure shown in Figure 8 comprises a semi-insulating substrate 1, an active layer 2, a source electrode 3, a drain electrode 4, and an insulating film 5 that covers part of the source electrode 3, drain electrode 4, and active layer 2. A recess 8 is formed in the region of the active layer 2 exposed by the insulating film opening 17.

[0025] As shown in Figure 9, a second resist 7 with a thickness of 0.5 μm to 1.0 μm, patterned with an opening 62, is formed on the base structure (second resist formation step). The second resist 7 has an opening 62 with an inverse taper shape, where the distance between the opening side surface 63a and the opening side surface 63b increases towards the semi-insulating substrate 1 side. In other words, the second resist formation step is a step of forming a resist that exposes a part of the surface opposite the active layer exposed by the insulating film opening 17 and the leading edge of the insulating film on the drain side of the insulating film 5b, and has an inverse taper shape resist opening (opening 62) where the opening length in the direction from the source electrode 3 to the drain electrode 4 increases towards the semi-insulating substrate 1 side. The side edge P1 of the opening side surface 63a on the source electrode 3 side of the opening 62 is the end of the opening side surface 63a on the semi-insulating substrate 1 side, and the position of the side edge P1 is the contact position with the base structure. The side edge P2 of the opening side 63b on the drain electrode 4 side of the opening 62 is the edge of the opening side 63b on the semi-insulating substrate 1 side, and the position of the side edge P2 is the contact position with the base structure. The side edge P1 of the opening side 63a is in contact with the active layer 2, and the side edge P2 of the opening side 63b is in contact with the insulating film 5 on the drain electrode 4 side. The contact position between the opening side 63a and the active layer 2, i.e., the position of the side edge P1, is located approximately 0.1 μm towards the drain electrode 4 side, i.e., the positive X direction side, from the insulating film edge 18a of the insulating film 5 on the source electrode 3 side. The contact position between the opening side 63b and the insulating film 5, i.e., the position of the side edge P2, is located between the insulating film edge 18b of the insulating film 5 on the drain electrode 4 side and the dashed line 49. The dashed line 49 indicates the position of the source electrode 3 side edge of the step created by the insulating film 5 riding up onto the drain electrode 4. The opening 62 is formed such that the insulating film edge 18a of the insulating film 5 on the source electrode 3 side is covered by the second resist 7, and the insulating film edge 18b of the insulating film 5 on the drain electrode 4 side is exposed. In other words, the opening 62 is formed to expose the drain electrode 4 side of the active layer 2 exposed by the insulating film opening 17, and the source electrode 3 side of the insulating film 5 on the drain electrode 4 side. Figure 9 shows an example where the position of the insulating film edge 18b of the insulating film 5 on the drain electrode 4 side is approximately in the center of the opening 62.

[0026] The second resist 7 having an inversely tapered opening 62 is an image reversal resist. The process for forming the inversely tapered opening can be the image reversal method described in Japanese Patent Application Publication No. 2-3067. An image reversal resist is a resist that can form an inversely tapered opening while maintaining the good resolution of a positive resist. The second resist 7 on the source electrode 3 side having the opening side surface 63a is the source-side resist, and the second resist 7 on the drain electrode 4 side having the opening side surface 63b is the drain-side resist.

[0027] As shown in Figure 10, the active layer 2 exposed by the opening 62 is etched to a depth of 50 nm to 200 nm by wet etching using tartaric acid, citric acid, etc., to form a groove, or recess 8 (recess formation step). A groove formed by wet etching is generally called a recess. Recess 8 has a recess bottom surface 20, a recess end 19a on the source electrode 3 side, and a recess end 19b on the drain electrode 4 side. Due to recess 8, the resist corner 65 on the semi-insulating substrate 1 side of the second resist 7 on the source electrode 3 side, including the side edge P1 of the opening side surface 63a, is lifted away from the active layer 2. The surface of the resist corner 65 on the semi-insulating substrate 1 side is the exposed bottom surface 64. In other words, the recess formation process involves exposing the opening 62 side of the resist-facing surface of the source-side resist that faces the semi-insulating substrate 1, and the opening 62 side of the drain-side insulating film-facing surface of the drain-side insulating film tip of the insulating film 5b that faces the semi-insulating substrate 1, while simultaneously etching the active layer 2 with an etching solution to form a recess 8.

[0028] Subsequently, a gate electrode 14 is formed using a second resist 7 having an inversely tapered opening 62 (gate electrode formation step). The gate electrode formation step includes a titanium layer formation step to form a titanium layer 9, a platinum layer formation step to form a platinum layer 10, a gold layer formation step to form a gold layer 12, and a recessed portion formation step to form a recessed portion 13. Each step of the gate electrode formation step will be described below.

[0029] As shown in Figure 11, for example, a titanium layer 9 of 10 nm to 150 nm thickness is formed using a vacuum deposition apparatus (titanium layer formation process). The dashed line 21a is a line parallel to the Z direction that passes through the upper end of the opening side surface 63a of the second resist 7, which is the end opposite to the semi-insulating substrate 1, and the dashed line 21b is a line parallel to the Z direction that passes through the upper end of the opening side surface 63b of the second resist 7, which is the end opposite to the semi-insulating substrate 1. The dashed line 21a indicates the boundary on the source electrode 3 side, i.e., the propagation boundary, when the metal particles propagate through the opening 62 towards the semi-insulating substrate 1 side, i.e., the negative Z direction side. The dashed line 21b indicates the boundary on the drain electrode 4 side, i.e., the propagation boundary, when the metal particles propagate through the opening 62 towards the semi-insulating substrate 1 side. The titanium layer 9 formed on the active layer 2 and the insulating film 5 has the source electrode 3 side end at the position of the dashed line 21a and the drain electrode 4 side end at the position of the dashed line 21b. In other words, the titanium layer formation process is a process of forming a titanium layer 9 from the opening 62 of the second resist 7 to the recess bottom surface 20 of the recess 8 and the tip of the drain-side insulating film. In addition, during the titanium layer formation process, a titanium layer 9 is also formed on the opposite sides of the source-side resist and the drain-side resist.

[0030] The cross-sectional shape of the titanium layer 9 formed on the active layer 2 and the insulating film 5 is as shown in Figure 2. Since the titanium layer 9 covers the active layer 2 and the insulating film 5, a cavity 30 is formed on the drain electrode 4 side of the recess 8. The source-side surface 46a of the first titanium stage 41 of the titanium layer 9 is close to the progressing boundary shown by the dashed line 21a, so it is not perpendicular to the semi-insulating substrate 1 but is formed at an angle toward the drain electrode 4 side. The drain-side surface 47b of the second titanium stage 42 of the titanium layer 9 is close to the progressing boundary shown by the dashed line 21b, so it is not perpendicular to the semi-insulating substrate 1 but is formed at an angle toward the source electrode 3 side. The source-side surface 46b of the titanium layer 9 is formed at an angle toward the drain electrode 4 side because the titanium layer 9 rides up over the tip of the insulating film 5b on the source electrode 3 side. Figure 11 shows an example where the titanium layer 9 covering the second resist 7 on the source electrode 3 side is formed with the side facing the opening 62 inclined toward the source electrode 3 side from the dashed line 21a, and the titanium layer 9 covering the second resist 7 on the drain electrode 4 side is formed with the side facing the opening 62 inclined toward the drain electrode 4 side from the dashed line 21b.

[0031] As shown in Figure 12, for example, a platinum layer 10 of 10 nm to 100 nm thickness is formed using a vacuum deposition apparatus (platinum layer formation process). At this time, the second resist 7 on the source electrode 3 side, which has a resist corner 65 that is floating away from the active layer 2 due to thermal stress, shifts towards the source electrode 3 side by a resist change length dW. Accordingly, the position of the dashed line 21a changes to the position of the dashed line 22. The dashed line 22 indicates the boundary on the source electrode 3 side, i.e., the propagation boundary, when platinum particles propagate towards the semi-insulating substrate 1 side through the opening 62. The resist change length dW is 0.05 μm or less. Due to the shift of the second resist 7 on the source electrode 3 side toward the source electrode 3 side, the platinum layer 10 formed on the titanium layer 9 has its end on the source electrode 3 side at the position of the dashed line 22 and its end on the drain electrode 4 side at the position of the dashed line 21b. Therefore, due to the shift of the second resist 7 on the source electrode 3 side toward the source electrode 3 side, the platinum layer 10 is also laminated on the active layer 2 and formed on the active layer 2. In other words, the platinum layer formation process is a process of forming a platinum layer 10 on the side of the titanium layer 9 opposite to the semi-insulating substrate 1, the side of the titanium layer on the source electrode 3 side, and the bottom surface 20 of the recess 8. In addition, during the platinum layer formation process, a platinum layer 10 is also formed on the opposite side of the titanium layer 9 on the source resist and the drain resist.

[0032] The cross-sectional shape of the platinum layer 10 formed on the titanium layer 9 is as shown in Figure 3. On the source electrode 3 side, the propagation boundary where platinum particles advance toward the semi-insulating substrate 1 side, i.e., the negative Z direction, is at the position of the dashed line 22, so the platinum layer 10 covers the source side surface 46a of the titanium layer 9, forming the platinum stretched portion 54. The platinum layer side surfaces (source side surfaces 57a, 57b) on the source electrode 3 side of the platinum layer 10 are inclined toward the drain electrode 4 side, similar to the titanium layer side surfaces (source side surfaces 46a, 46b), because the platinum layer 10 covers the titanium layer side surfaces (source side surfaces 46a, 46b). On the drain electrode 4 side, the second resist 7 on the drain electrode 4 side is in close contact with the insulating film 5, so the position of the dashed line 21b is unchanged or changes by 0.01 μm or less. Figure 12 shows an example in which the platinum layer 10 is not formed on the drain-side surface 47b of the second titanium layer 9, and the platinum layer 10 is not formed on the opening-side surface 62 of the titanium layer 9 covering the second resist 7.

[0033] As shown in Figure 13, for example, a gold layer 12 of 200 nm to 500 nm is formed using a vacuum deposition apparatus (gold layer formation process). The gold layer formation process is a process of forming the gold layer 12 on the side of the platinum layer opposite to the semi-insulating substrate 1 and on the side of the platinum layer on the source electrode 3 side of the platinum layer 10. In addition, during the gold layer formation process, the gold layer 12 is also formed on the opposite side of the platinum layer 10 on the source side resist and the drain side resist. As explained in Figure 1, Figure 13 shows an example in which the source side surface 57a and the drain side surface 58c are not covered.

[0034] As shown in Figure 14, the titanium layer 9, platinum layer 10, and gold layer 12 on the second resist 7 are removed together with the second resist 7 by lift-off (metal lift-off process). The metal lift-off process is a process in which the titanium layer 9, platinum layer 10, and gold layer 12 that were sequentially formed on the second resist 7 by the titanium layer formation process, platinum layer formation process, and gold layer formation process are removed together with the second resist 7.

[0035] After the metal lift-off process, the platinum layer 10 connected to the active layer 2 sinks into the active layer 2 by heat treatment at, for example, about 360°C, forming a recessed portion 13 of the platinum arsenide layer, i.e., the PtAs2 layer (recessed portion formation process). The field-effect transistor 100 shown in Figure 1 is manufactured by performing the recessed portion formation process. As mentioned above, the thickness of the recessed portion 13, i.e., the recessed length dg in the Z direction, is about twice the thickness of the platinum layer 10, which is 10 nm to 100 nm, so it is, for example, about 20 nm to 200 nm. The recessed portion formation process is a process in which, after the metal lift-off process, the platinum layer 10 connected to the active layer 2 at the recess bottom surface 20 sinks into the active layer 2 by heat treatment, forming a recessed portion 13 of the platinum arsenide layer. Furthermore, in the platinum layer formation process, the platinum layer 10 is formed at a temperature at which thermal stress is applied to the second resist 7, causing the opening 62 side, which is floating from the active layer 2 due to the recess 8 in the source resist, to move towards the source electrode 3 side compared to the titanium layer formation process.

[0036] The field-effect transistor manufacturing method of Embodiment 1 can realize a short-gate field-effect transistor 100 with a gate length Lg1 of 0.02 μm to 0.1 μm, and can realize a field-effect transistor 100 with an overlap structure only on the drain electrode 4 side. The recessed portion 13 that determines the gate length Lg1 is formed when the platinum-stretched portion 54 of the platinum layer 10 formed in the platinum layer formation process is recessed into the active layer 2 by the heat treatment in the recessed portion formation process. Therefore, the field-effect transistor manufacturing method of Embodiment 1 can realize an ultrashort-gate field-effect transistor 100 with a gate length Lg1 of 0.02 μm to 0.05 μm without forming spike grooves. In the field-effect transistor manufacturing method of Embodiment 1, the width in the X direction and the thickness in the Z direction of the platinum stretched portion 54 of the platinum layer 10 connected to the active layer 2 are controlled by the thickness in the Z direction of the titanium layer 9 and the thickness in the Z direction of the platinum layer 10. As a result, a recessed portion 13 is formed in which the recessed length dg is approximately twice the thickness in the Z direction of the platinum layer 10. Therefore, it is less susceptible to the influence of the surface of the active layer 2, i.e., the opposite surface of the active layer 2, and the gate length Lg1 can be determined with high precision.

[0037] Unlike the spike gate type FET of Patent Document 1, which has a source-side overlap portion 24 on the source electrode side, the field-effect transistor 100 of Embodiment 1 does not have a source-side overlap portion 24 on the source electrode 3 side. Therefore, the gate-source capacitance Cgs can be suppressed more effectively than the spike gate type FET of Patent Document 1, and the operation speed can be increased and the frequency can be increased compared to the spike gate type FET of Patent Document 1.

[0038] The source-side overlap portion 24 on the source electrode 3 side, the drain-side overlap portion 25 on the drain electrode 4 side, and the gate-source capacitance Cgs will be explained using Figures 16 to 19. Figure 16 is a schematic diagram showing the spike gate structure of the spike gate type FET of Patent Document 1 as a comparative example, and Figure 17 is a schematic diagram showing the spike gate structure of the field-effect transistor 100 of Embodiment 1. The gate electrode 15 of the comparative example is formed in the active layer 2 and has a convex portion 16, a source-side overlap portion 24, and a drain-side overlap portion 25. The drain-side overlap portion 25 has the function of a GFP (gate field plate). When a voltage is applied to the gate electrode 15, there is almost no potential on the source electrode 3 side of the gate electrode 15, and the drain applied voltage (e.g., 10V) is applied to the drain electrode 4 side. In the drain-side overlap portion 25, the electric field is concentrated at the electric field concentration portion 23 which corresponds to the corner of the gate electrode 15 on the drain electrode 4 side. For this reason, the spike gate structure of the comparative example can suppress drain conductance. Since there is almost no potential applied to the source electrode 3 side of the gate electrode 15, the source-side overlap portion 24 does not have an electric field concentration portion 23 like the drain-side overlap portion 25. Therefore, there is no effect such as conductance suppression. On the contrary, the gate-source capacitance Cgs increases due to the source-side overlap portion 24, worsening the cutoff frequency ft, which is an important parameter when increasing the frequency of a field-effect transistor. The cutoff frequency ft will be discussed later.

[0039] Unlike the gate electrode 15 of the comparative example shown in Figure 16, the gate electrode 14 of the field-effect transistor 100 in Embodiment 1 does not have a source-side overlap portion 24, but instead has a recessed portion 13 and a drain-side overlap portion 25. The effect of the drain-side overlap portion 25 in the gate electrode 14 is the same as the effect of the drain-side overlap portion 25 in the gate electrode 15. In the drain-side overlap portion 25, the electric field is concentrated at the electric field concentration portion 23, which corresponds to the corner of the gate electrode 14 on the drain electrode 4 side. Therefore, the spike gate structure of the field-effect transistor 100 in Embodiment 1 can suppress drain conductance. Furthermore, unlike the spike gate structure of the comparative example, the spike gate structure of the field-effect transistor 100 in Embodiment 1 can reduce the gate-source capacitance Cgs by eliminating the source-side overlap portion 24. Thus, the spike gate structure of the field-effect transistor 100 in Embodiment 1 can suppress drain conductance while suppressing the increase in gate-source capacitance Cgs.

[0040] Next, the gate-source capacitance Cgs and cutoff frequency ft in the spike gate structure of the comparative example and the spike gate structure of the field-effect transistor 100 of Embodiment 1 will be described. In the spike gate structure of the comparative example shown in Figure 18, the gate length of the convex portion 16 is Lg1, and the overlap lengths of the source-side overlap portion 24 and the drain-side overlap portion 25 are Lg2. The depletion layer regions in the convex portion 16, the drain-side overlap portion 25, and the source-side overlap portion 24 are depletion layer regions 26a, 26b, and 26c, respectively. The length of depletion layer region 26a in the Z direction is depletion layer length d1, and the lengths of depletion layer regions 26b and 26c in the Z direction are depletion layer length d2. The gate-source capacitance Cgs is the sum of the capacitances of each depletion layer region 26a, 26b, and 26c in the convex portion 16, the drain-side overlap portion 25, and the source-side overlap portion 24. Since the capacities of each depletion layer region 26a, 26b, and 26c are proportional to the gate length / depletion layer length or overlap length / depletion layer length, the gate-source capacity Cgs in the comparative spike gate structure has the relationship given by equation (1). Cgs∝Lg1 / d1+2×(Lg2 / d2) ···(1)

[0041] The cutoff frequency ft can be expressed using the transconductance gm of the field-effect transistor as shown in equation (2). The transconductance gm of a field-effect transistor is obtained by dividing the change in drain current |ΔId| by the change in gate voltage (gate-source voltage) |ΔV| when a constant drain-source voltage is applied. The cutoff frequency ft is also the frequency at which the current gain |ΔId| / |ΔIg| becomes 1, where |ΔIg| is the change in gate current. ft = gm / (2π × Cgs) ... (2)

[0042] In the spike gate structure of the field-effect transistor 100 of Embodiment 1 shown in Figure 19, the gate length of the recessed portion 13 is Lg1, and the overlap length of the drain-side overlap portion 25 is Lg2. The depletion layer regions in the recessed portion 13 and the drain-side overlap portion 25 are depletion layer regions 26a and 26b, respectively. The length of the depletion layer region 26a in the Z direction is depletion layer length d1, and the length of the depletion layer region 26b in the Z direction is depletion layer length d2. The gate-source capacitance Cgs is the sum of the capacitances of the respective depletion layer regions 26a and 26b in the recessed portion 13 and the drain-side overlap portion 25. The gate-source capacitance Cgs in the spike gate structure of the field-effect transistor 100 of Embodiment 1 has the relationship given by equation (3). Cgs∝Lg1 / d1+Lg2 / d2 ···(3)

[0043] As mentioned above, the cutoff frequency ft is also the frequency at which the current gain |ΔId| / |ΔIg| becomes 1. The higher the cutoff frequency ft, the higher the frequency to which the field-effect transistor can amplify, and the faster the field-effect transistor can operate. To improve the cutoff frequency ft, reducing Cgs is important from equation (2), and suppressing the overlap length Lg2 of the source-side overlap portion 24 is important from equations (1) and (3). Since the field-effect transistor 100 of Embodiment 1 does not have a source-side overlap portion 24, it can have a higher cutoff frequency ft than the spike-gate type FET of Patent Document 1, and can operate at higher speeds and frequencies than the spike-gate type FET of Patent Document 1.

[0044] As described above, the field-effect transistor 100 of Embodiment 1 comprises an active layer 2 containing GaAs formed on a semi-insulating substrate 1, a source electrode 3 and a drain electrode 4 formed on the opposite side of the active layer 2, which is the side of the active layer 2 opposite to the semi-insulating substrate 1, a recess 8 formed between the source electrode 3 and the drain electrode 4 on the opposite side of the active layer, a source-side insulating film 5a formed on the opposite side of the active layer that covers the source electrode 3 and extends toward the recess 8, a drain-side insulating film 5b formed on the opposite side of the active layer that covers the drain electrode 4 and extends to the upper part of the recess 8 toward the drain electrode 4, and a gate electrode 14 formed on the recess bottom surface 20 of the recess 8 and having a recessed portion 13 that sinks in toward the semi-insulating substrate 1 from the recess bottom surface 20. The gate electrode 14 comprises a titanium layer 9, a platinum layer 10, and a gold layer 12. The titanium layer 9 extends from the recessed portion 13 toward the drain electrode 4 and has a drain-side overlap portion 25 formed on the recess bottom surface 20, and is formed riding on the drain-side insulating film 5b. The platinum layer 10 is formed on the titanium layer opposite the semi-insulating substrate 1 (opposite surfaces 45a, 45b) and on the titanium layer side toward the source electrode 3 (source-side surfaces 46a, 46b). The gold layer 12 is formed on the platinum layer opposite the semi-insulating substrate 10 (opposite surfaces 56a, 56b) and on the platinum layer side toward the source electrode 3 (source-side surface 57b). The recessed portion 13 is a platinum arsenide layer connected to the platinum layer 10. In the field-effect transistor 100 of Embodiment 1, this configuration has a recessed portion 13 of the platinum arsenide layer where the gate electrode 14 sinks from the recess bottom surface 20 towards the semi-insulating substrate 1, so the gate length Lg1 can be shortened without forming a spike groove.

[0045] Furthermore, the manufacturing method of the field-effect transistor of Embodiment 1 is a method for manufacturing a field-effect transistor 100 comprising a source electrode 3, a drain electrode 4, and a gate electrode 14 having a recessed portion 13 that is recessed into the active layer 2, which is formed on an active layer 2 containing GaAs formed on a semi-insulating substrate 1. The manufacturing method of the field-effect transistor of Embodiment 1 includes an active layer formation step, a source-drain electrode formation step, an insulating film formation step, an insulating film aperture formation step, a resist formation step, a recess formation step, a titanium layer formation step, a platinum layer formation step, a gold layer formation step, a metal reoff step, and a recessed portion formation step. In the active layer formation step, an active layer 2 containing GaAs is formed on the semi-insulating substrate 1. In the source-drain electrode formation step, the source electrode 3 and the drain electrode 4 are formed on the surface opposite to the active layer, which is the surface of the active layer 2 opposite to the semi-insulating substrate 1. In the insulating film formation step, an insulating film 5 is formed on the source electrode 3, the drain electrode 4, and the surface opposite to the active layer. In the insulating film opening formation process, an insulating film opening 17 is formed in the insulating film 5, exposing the surface opposite the active layer. In the resist formation process, the insulating film 5 on the source electrode 3 side is designated as the source-side insulating film (insulating film 5a), the insulating film 5 on the drain electrode 4 side is designated as the drain-side insulating film (insulating film 5b), the source electrode 3 side of the drain-side insulating film (insulating film 5b) is designated as the drain-side insulating film tip, and a resist (second resist 7) ​​is formed having a resist opening (opening 62) with an inverse taper shape, where a part of the surface opposite the active layer exposed by the insulating film opening 17 and the drain-side insulating film tip are exposed, and the opening length in the direction from the source electrode 3 to the drain electrode 4 increases as it approaches the semi-insulating substrate 1. In the recess formation process, the resist (second resist 7) ​​on the source electrode 3 side is designated as the source-side resist, and the resist opening (opening 62) side of the resist-facing surface of the source-side resist, which is the surface facing the semi-insulating substrate 1, and the resist opening (opening 62) side of the drain-side insulating film-facing surface, which is the surface facing the semi-insulating substrate 1, are exposed, and the active layer 2 is etched with an etching solution to form a recess 8. In the titanium layer formation process, a titanium layer 9 is formed from the resist opening (opening 62) to the recess bottom surface 20 of the recess 8 and the tip of the insulating film on the drain side.In the platinum layer formation process, a platinum layer 10 is formed on the titanium layer opposite side (opposite sides 45a, 45b) of the titanium layer 9, which is the side opposite to the semi-insulating substrate 1, and on the titanium layer side on the source electrode 3 side (source side 46a, 46b), and on the recess bottom surface 20 of the recess 8. In the gold layer formation process, a gold layer 12 is formed on the platinum layer opposite side (opposite sides 56a, 56b) of the platinum layer 10, which is the side opposite to the semi-insulating substrate 1, and on the platinum layer side on the source electrode 3 side (source side 57b). In the metal re-off process, the titanium layer 9, platinum layer 10, and gold layer 12, which were sequentially formed on the resist (second resist 7) ​​in the titanium layer formation process, platinum layer formation process, and gold layer formation process, are removed together with the resist (second resist 7). In the sinking portion formation process, after the metal reoffoff process, the platinum layer 10 connected to the active layer 2 at the recess bottom surface 20 sinks into the active layer 2 by heat treatment, forming a sinking portion 13 of the platinum arsenide layer. In the platinum layer formation process, the platinum layer 10 is formed at a temperature at which thermal stress is applied to the resist (second resist 7) ​​that causes the resist opening (opening 62), which is floating from the active layer 2 due to the recess 8 in the source side resist, to move towards the source electrode 3 side compared to the titanium layer formation process. With this configuration, the manufacturing method of the field-effect transistor of Embodiment 1 has a sinking portion 13 of the platinum arsenide layer into which the gate electrode 14 is sunk into the active layer 2, so the gate length Lg1 of the field-effect transistor 100 can be shortened without forming a spike groove.

[0046] While this disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in the embodiments are not limited to the application of any particular embodiment, but can be applied individually or in various combinations to the embodiments. Accordingly, countless variations not illustrated are conceivable within the scope of the technology disclosed in this specification. For example, these may include modifying, adding, or omitting at least one component, or even extracting at least one component and combining it with a component from another embodiment.

[0047] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims.

[0048] The various aspects of this disclosure are summarized below as an appendix.

[0049] (Note 1) An active layer containing GaAs formed on a semi-insulating substrate, Source electrodes and drain electrodes formed on the side of the active layer opposite to the semi-insulating substrate, A recess formed between the source electrode and the drain electrode on the opposite side of the active layer, A source-side insulating film is formed on the opposite side of the active layer, covering the source electrode and extending toward the recess side, A drain-side insulating film is formed on the surface opposite the active layer, covering the drain electrode and extending to the upper part of the recess on the drain electrode side, The device comprises a gate electrode formed on the bottom surface of the recess and having a recessed portion that sinks in from the bottom surface of the recess toward the semi-insulating substrate, The aforementioned terminal is, It has a drain-side overlap portion that extends from the recessed portion toward the drain electrode side and is formed on the bottom surface of the recess, and a titanium layer that is formed riding up onto the drain-side insulating film, A platinum layer formed on the titanium layer opposite to the semi-insulating substrate, which is the opposite side of the titanium layer, and on the side of the titanium layer on the source electrode side, The platinum layer comprises a gold layer formed on the side of the platinum layer opposite to the semi-insulating substrate and on the side of the platinum layer on the source electrode side. The aforementioned subducting portion is a platinum arsenide layer connected to the platinum layer. Field-effect transistor. (Note 2) The aforementioned titanium layer is The first titanium stage connected to the bottom surface of the recess, A second titanium stage is positioned further away from the semi-insulating substrate than the first titanium stage and is connected to the opposite side of the insulating film, which is the side of the drain-side insulating film opposite to the semi-insulating substrate. It has a titanium connecting portion that connects the first titanium stage and the second titanium stage. The field-effect transistor described in Appendix 1. (Note 3) The field-effect transistor as described in Appendix 1, wherein the titanium layer side on the source electrode side of the titanium layer is inclined toward the drain electrode side. (Note 4) The field-effect transistor as described in Appendix 2, wherein the titanium layer side on the source electrode side of the titanium layer is inclined toward the drain electrode side. (Note 5) The platinum layer is connected to the first platinum stage of the first titanium stage, The platinum second stage is positioned further away from the semi-insulating substrate than the platinum first stage and is connected to the titanium second stage, A platinum connecting section connecting the first platinum stage and the second platinum stage, The first platinum stage has a platinum-extended portion that extends from the source electrode side to the semi-insulating substrate side, The platinum stretched portion is connected to the sinking portion. The field-effect transistor described in Appendix 2. (Note 6) The platinum layer is connected to the first platinum stage of the first titanium stage, The platinum second stage is positioned further away from the semi-insulating substrate than the platinum first stage and is connected to the titanium second stage, A platinum connecting section connecting the first platinum stage and the second platinum stage, The first platinum stage has a platinum-extended portion that extends from the source electrode side to the semi-insulating substrate side, The platinum stretched portion is connected to the sinking portion. Field-effect transistor as described in Appendix 4. (Note 7) The field-effect transistor according to any one of appendices 1 to 6, wherein the platinum layer side on the source electrode side of the platinum layer is inclined toward the drain electrode side. (Note 8) The drain electrode side end of the source-side insulating film is positioned closer to the source electrode than the source electrode side end of the recess. A field-effect transistor as described in any one of the notes 1 through 7. (Note 9) The active layer has a HEMT structure. A field-effect transistor as described in any one of the appendices 1 through 8. (Note 10) A method for manufacturing a field-effect transistor comprising a source electrode, a drain electrode, and a gate electrode having a recessed portion that is recessed into the active layer formed on a semi-insulating substrate and containing GaAs, A step of forming an active layer containing GaAs formed on the semi-insulating substrate, A source-drain electrode formation step in which the source electrode and the drain electrode are formed on the surface of the active layer opposite to the semi-insulating substrate, which is the surface of the active layer opposite to the active layer, An insulating film forming step is performed to form an insulating film on the source electrode, the drain electrode, and the surface opposite the active layer, An insulating film opening formation step is to form an insulating film opening in the insulating film that exposes the surface opposite to the active layer, The insulating film on the source electrode side is designated as the source-side insulating film, the insulating film on the drain electrode side is designated as the drain-side insulating film, and the source electrode side of the drain-side insulating film is designated as the tip of the drain-side insulating film. A resist forming step of forming a resist having a reverse tapered resist opening that exposes a part of the surface opposite the active layer exposed by the insulating film opening and the leading edge of the drain-side insulating film, and in which the opening length in the direction from the source electrode to the drain electrode increases as it moves toward the semi-insulating substrate side, The resist on the source electrode side is referred to as the source side resist. A recess formation step involves exposing the resist opening side of the resist-facing surface of the source-side resist that faces the semi-insulating substrate, and the resist opening side of the drain-side insulating film-facing surface of the drain-side insulating film-facing surface that faces the semi-insulating substrate at the tip of the drain-side insulating film, and etching the active layer with an etching solution to form a recess, A titanium layer formation step in which a titanium layer is formed from the resist opening to the recess bottom surface and the drain-side insulating film tip, A platinum layer formation step in which a platinum layer is formed on the titanium layer opposite to the semi-insulating substrate, the titanium layer opposite side, the titanium layer side on the source electrode side, and the bottom surface of the recess. A gold layer formation step is to form a gold layer on the side of the platinum layer opposite to the semi-insulating substrate, which is the side of the platinum layer opposite to the source electrode, and on the side of the platinum layer on the source electrode side. A metal re-off step is performed to remove the titanium layer, platinum layer, and gold layer that have been sequentially formed on the resist by the titanium layer formation step, the platinum layer formation step, and the gold layer formation step, together with the resist. The process includes, after the metal reoff-off process, a sinking portion formation process in which the platinum layer connected to the active layer at the bottom surface of the recess sinks into the active layer by heat treatment to form a sinking portion of the platinum arsenide layer. In the platinum layer formation process, The platinum layer is formed at a temperature at which thermal stress is applied to the resist, causing the resist opening side, which is floating from the active layer due to the recess in the source resist, to move towards the source electrode side compared to the titanium layer formation process. A method for manufacturing a field-effect transistor. [Explanation of Symbols]

[0050] 1...Semi-insulating substrate, 2...Active layer, 3...Source electrode, 4...Drain electrode, 5...Insulating film, 5a...Insulating film (source side insulating film), 5b...Insulating film (drain side insulating film), 7...Second resist, 8...Recess, 9...Titanium layer, 10...Platinum layer, 12...Gold layer, 13...Recessed portion, 14...Gate electrode, 17...Insulating film opening, 18a, 18b...Insulating film edge, 19a, 19b...Recess edge, 20...Recess bottom, 25...Drain Side overlap section, 41...Titanium first stage, 42...Titanium second stage, 43...Titanium connection section, 45a, 45b...Opposite side (opposite side of titanium layer), 46a, 46b...Source side, 51...Platinum first stage, 52...Platinum second stage, 53...Platinum connection section, 54...Platinum stretched section, 56a, 56b...Opposite side (opposite side of platinum layer), 57a, 57b...Source side, 62...Opening (resist opening), 100...Field-effect transistor

Claims

1. An active layer containing GaAs formed on a semi-insulating substrate, Source electrodes and drain electrodes formed on the side of the active layer opposite to the semi-insulating substrate, A recess formed between the source electrode and the drain electrode on the opposite side of the active layer, A source-side insulating film is formed on the opposite side of the active layer, covering the source electrode and extending toward the recess side, A drain-side insulating film is formed on the surface opposite the active layer, covering the drain electrode and extending to the upper part of the recess on the drain electrode side, The device comprises a gate electrode formed on the bottom surface of the recess and having a recessed portion that sinks in from the bottom surface of the recess toward the semi-insulating substrate, The aforementioned terminal is, It has a drain-side overlap portion that extends from the recessed portion toward the drain electrode side and is formed on the bottom surface of the recess, and a titanium layer that is formed riding up onto the drain-side insulating film, A platinum layer formed on the titanium layer opposite to the semi-insulating substrate, which is the opposite side of the titanium layer, and on the side of the titanium layer on the source electrode side, The platinum layer comprises a gold layer formed on the side of the platinum layer opposite to the semi-insulating substrate and on the side of the platinum layer on the source electrode side. The aforementioned subducting portion is a platinum arsenide layer connected to the platinum layer. Field-effect transistor.

2. The aforementioned titanium layer is The first titanium stage connected to the bottom surface of the recess, A second titanium stage is positioned further away from the semi-insulating substrate than the first titanium stage and is connected to the opposite side of the insulating film, which is the side of the drain-side insulating film opposite to the semi-insulating substrate. It has a titanium connecting portion that connects the first titanium stage and the second titanium stage. The field-effect transistor according to claim 1.

3. The field-effect transistor according to claim 1, wherein the titanium layer side on the source electrode side of the titanium layer is inclined toward the drain electrode side.

4. The field-effect transistor according to claim 2, wherein the titanium layer side on the source electrode side of the titanium layer is inclined toward the drain electrode side.

5. The platinum layer is connected to the first platinum stage of the first titanium stage, The platinum second stage is positioned further away from the semi-insulating substrate than the platinum first stage and is connected to the titanium second stage, A platinum connecting section connecting the first platinum stage and the second platinum stage, The first platinum stage has a platinum-extended portion that extends from the source electrode side to the semi-insulating substrate side, The platinum stretched portion is connected to the sinking portion. The field-effect transistor according to claim 2.

6. The platinum layer is connected to the first platinum stage of the first titanium stage, The platinum second stage is positioned further away from the semi-insulating substrate than the platinum first stage and is connected to the titanium second stage, A platinum connecting section connecting the first platinum stage and the second platinum stage, The first platinum stage has a platinum-extended portion that extends from the source electrode side to the semi-insulating substrate side, The platinum stretched portion is connected to the sinking portion. The field-effect transistor according to claim 4.

7. The field-effect transistor according to any one of claims 1 to 6, wherein the platinum layer side on the source electrode side of the platinum layer is inclined toward the drain electrode side.

8. The drain electrode side end of the source-side insulating film is positioned closer to the source electrode than the source electrode side end of the recess. A field-effect transistor according to any one of claims 1 to 6.

9. The active layer has a HEMT structure. A field-effect transistor according to any one of claims 1 to 6.

10. A method for manufacturing a field-effect transistor comprising a source electrode, a drain electrode, and a gate electrode having a recessed portion that is recessed into the active layer formed on a semi-insulating substrate and containing GaAs, The process includes forming an active layer containing GaAs on the semi-insulating substrate, A source-drain electrode formation step in which the source electrode and the drain electrode are formed on the surface of the active layer opposite to the semi-insulating substrate, which is the surface of the active layer opposite to the active layer, An insulating film forming step is performed to form an insulating film on the source electrode, the drain electrode, and the surface opposite the active layer, An insulating film opening formation step is to form an insulating film opening in the insulating film that exposes the surface opposite to the active layer, The insulating film on the source electrode side is designated as the source-side insulating film, the insulating film on the drain electrode side is designated as the drain-side insulating film, and the source electrode side of the drain-side insulating film is designated as the tip of the drain-side insulating film. A resist forming step of forming a resist having a reverse tapered resist opening that exposes a part of the surface opposite the active layer exposed by the insulating film opening and the leading edge of the drain-side insulating film, and in which the opening length in the direction from the source electrode to the drain electrode increases as it moves toward the semi-insulating substrate side, The resist on the source electrode side is referred to as the source side resist. A recess formation step involves exposing the resist opening side of the resist-facing surface of the source-side resist that faces the semi-insulating substrate, and the resist opening side of the drain-side insulating film-facing surface of the drain-side insulating film-facing surface that faces the semi-insulating substrate at the tip of the drain-side insulating film, and etching the active layer with an etching solution to form a recess, A titanium layer formation step in which a titanium layer is formed from the resist opening to the recess bottom surface and the drain-side insulating film tip, A platinum layer formation step in which a platinum layer is formed on the titanium layer opposite to the semi-insulating substrate, the titanium layer opposite side, the titanium layer side on the source electrode side, and the bottom surface of the recess. A gold layer formation step is to form a gold layer on the side of the platinum layer opposite to the semi-insulating substrate, which is the side of the platinum layer opposite to the source electrode, and on the side of the platinum layer on the source electrode side. A metal re-off step is performed to remove the titanium layer, platinum layer, and gold layer that have been sequentially formed on the resist by the titanium layer formation step, the platinum layer formation step, and the gold layer formation step, together with the resist. The process includes, after the metal reoff-off process, a sinking portion formation process in which the platinum layer connected to the active layer at the bottom surface of the recess sinks into the active layer by heat treatment to form a sinking portion of the platinum arsenide layer. In the platinum layer formation process, The platinum layer is formed at a temperature at which thermal stress is applied to the resist, causing the resist opening side, which is floating from the active layer due to the recess in the source resist, to move towards the source electrode side compared to the titanium layer formation process. A method for manufacturing a field-effect transistor.

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