Test equipment

Abstract

The present invention provides a testing apparatus that can simultaneously suppress damage to the surface electrodes of semiconductor devices caused by contact with the surface electrodes and reduce the electrical contact resistance of the surface electrodes. [Solution] The test apparatus 100 comprises a stage 10, a pressurizing mechanism 20, a metal foil 30, and an intermediary foil 32. The stage 10 is capable of supporting a semiconductor element 50, which includes a surface electrode 55 and a back electrode 57 opposite to the surface electrode 55, for testing. The pressurizing mechanism 20 can press the semiconductor element 50 placed on the stage 10 from the opposite side of the stage 10. The metal foil 30 is sandwiched between the stage 10 and the pressurizing mechanism 20. The intermediary foil 32 is sandwiched between the stage 10 and the pressurizing mechanism 20 and is positioned on the stage 10 side of the metal foil 30. The metal foil 30 has an uneven surface. The metal foil 30 includes protrusions as part of the uneven surface.

Description

Technical Field

[0001] The present disclosure relates to a test apparatus.

Background Art

[0002] Japanese Patent Application Laid-Open No. 2009-128190 (Patent Document 1) proposes a test apparatus for a semiconductor element. The semiconductor element has a surface electrode including a main electrode and a control electrode, and a back electrode on the opposite side.

[0003] The test apparatus of Patent Document 1 includes a conductive sheet, a pressurizing mechanism, and an elastic body layer. The pressurizing mechanism applies a load to the conductive sheet through the elastic body layer. As a result, the conductive sheet makes surface contact with the main electrode of the semiconductor element. At this time, the conductive sheet and the main electrode are energized in a state where the electrical contact resistance of the conductive sheet is reduced. Thereby, the semiconductor element is tested.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0008] According to the test apparatus of this disclosure, the arrangement of the intermediary foil can suppress damage to the surface electrodes of the semiconductor element. Furthermore, the uneven shape of the metal foil further reduces the electrical contact resistance between the intermediary foil and the semiconductor element. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic cross-sectional view showing the configuration of the test apparatus according to the first example of Embodiment 1. [Figure 2] This is a schematic cross-sectional view showing the configuration of a test apparatus according to a second example of Embodiment 1. [Figure 3] This is a plan view showing a first example of the metal foil in Figure 1 viewed from above in the Z direction. [Figure 4] This is a schematic cross-sectional view of the area along the line IV-IV in Figure 3. [Figure 5] This is a plan view showing a second example of the metal foil in Figure 1 viewed from above in the Z direction. [Figure 6] This is a schematic cross-sectional view of the interlayer foil in Figure 1, similar to Figure 4. [Figure 7] Figures 1 and 2 are plan views of the semiconductor device. [Figure 8] This is a schematic cross-sectional view of the portion along the line VIII-VIII in Figure 7. [Figure 9] This is a flowchart illustrating the test method using the test apparatus of Embodiment 1. [Figure 10]It is a schematic cross-sectional view showing the state in the pressure application start process in the test method. [Figure 11] It is a schematic enlarged view showing the state in which the convex portion of the metal foil faces downward and contacts the intermediate material foil. [Figure 12] It is a schematic enlarged view showing the state in which the convex portion of the metal foil faces upward and contacts the pressure plate. [Figure 13] It is a schematic cross-sectional view showing the configuration of the test apparatus according to Embodiment 2. [Figure 14] It is a schematic plan view showing the state in which the stage of Embodiment 2, the semiconductor element thereon, and the metal foil thereon are overlaid. [Figure 15] It is a schematic cross-sectional view showing the configuration of the test apparatus according to the first example of Embodiment 3. [Figure 16] It is a schematic plan view showing the state in which the stage of the first example of Embodiment 3, the semiconductor element thereon, and the two-layer metal foil thereon are overlaid. [Figure 17] It is a schematic cross-sectional view of a portion along line XVII-XVII of FIG. 16. [Figure 18] It is a schematic cross-sectional view showing the configuration of the test apparatus according to the second example of Embodiment 3.

Embodiments of the Invention

[0010] Embodiment 1. Hereinafter, this embodiment will be described with reference to the drawings. For the sake of convenience of explanation, the X direction, the Y direction, and the Z direction are introduced.

[0011] FIG. 1 is a schematic cross-sectional view showing the configuration of the test apparatus according to the first example of Embodiment 1. As shown in FIG. 1, the test apparatus 100 of this embodiment tests the semiconductor element 50. The test apparatus 100 mainly includes a stage 10, a pressure mechanism​​​Stage 10 is positioned below the test apparatus 100 in the Z direction. Stage 10 is capable of supporting a semiconductor element 50. The semiconductor element 50, placed on stage 10 and tested, includes a front electrode 55 and a back electrode 57. The front electrode 55 is formed on one of the main surfaces of the semiconductor substrate constituting the semiconductor element 50. Here, the one main surface is the upper main surface in the Z direction in Figure 1. The back electrode 57 is positioned on the semiconductor element 50 opposite to the front electrode 55. That is, the back electrode 57 is formed on the lower main surface in the Z direction of the semiconductor substrate constituting the semiconductor element 50 in Figure 1. In Figure 1, only the positions where the front electrode 55 and back electrode 57 are positioned are shown.

[0013] The pressurizing mechanism 20 can press the semiconductor element 50 placed on the stage 10 from the opposite side of the stage 10. Placing the semiconductor element 50 on the stage 10 includes both cases: when it is placed directly so as to be in contact with the surface of the stage 10, and when it is placed indirectly with another component (underlay foil 33) in between. The opposite side of the stage 10 means the upper side in the Z direction as viewed from the semiconductor element 50. This is because the stage 10 is located below the semiconductor element 50 in the Z direction. The pressurizing mechanism 20 is located at the top in the Z direction in the test apparatus 100 of Figure 1.

[0014] The pressurizing mechanism 20 is movable along the Z direction, i.e., the vertical direction. By moving downward in the Z direction, the pressurizing mechanism 20 can press against the surface electrode 55 and the back electrode 57. In other words, by moving downward in the Z direction, the pressurizing mechanism 20 can apply pressure to the surface electrode 55 and the back electrode 57. The semiconductor element 50 is positioned on the stage 10. Here, positioning the semiconductor element 50 on the stage 10 includes both cases where the semiconductor element 50 is directly placed so as to be in contact with the surface of the stage 10, and cases where the semiconductor element 50 is indirectly placed with another member (underlay foil 33) in between. In the former case, the semiconductor element 50 is positioned on the stage 10 so as to be in contact with the stage 10, with the back electrode 57 in contact with the stage 10.

[0015] The metal foil 30 is sandwiched between the stage 10 and the pressurizing mechanism 20 in the Z direction. The metal foil 30 is made of a metallic material. The metal foil 30 has an uneven surface. Specifically, the metal foil 30 has a convex shape as part of the uneven surface on its upper main surface in the Z direction. The convex shape protrudes upward in the Z direction from the upper main surface in the Z direction. Multiple convex shapes are periodically arranged on the metal foil 30. The metal foil 30 also has a concave shape on its lower main surface in the Z direction. The concave shape is recessed upward in the Z direction from the lower main surface in the Z direction. Multiple concave shapes are periodically arranged on the metal foil 30. The concave shape may have the same shape and size as the convex shape in a cross-section along the Z direction. The concave shape may also be positioned to overlap with the convex shape in a plan view from the Z direction. In this way, in the cross-sectional view of Figure 1, the thickness of the metal foil 30 in the Z direction is approximately equal in both the portions having concave and convex parts and the flat portions between adjacent convex parts.

[0016] The intermediary foil 32 is sandwiched between the stage 10 and the pressurizing mechanism 20 in the Z direction. The intermediary foil 32 is installed on the stage 10 side of the metal foil 30. In other words, the intermediary foil 32 is positioned below the metal foil 30 in the Z direction. Specifically, the intermediary foil 32 is positioned so that at least a portion of it is in contact with the main surface on the underside of the metal foil 30. However, the intermediary foil 32 does not have to have an uneven shape like the metal foil 30. For example, the intermediary foil 32 may have a flat shape almost entirely. The flat shape of the intermediary foil 32 is similar to the flat portions between the multiple protrusions on the metal foil 30.

[0017] As described above, the metal foil 30 is placed on the interlining foil 32 such that its protrusions face the pressurizing mechanism 20. In other words, the multiple protrusions of the metal foil 30 have their protruding portions facing upward in the Z direction. In Figure 1, the size of the metal foil 30 in plan view is smaller than that of the interlining foil 32. However, this is not limited to this. The sizes of the metal foil 30 and the interlining foil 32 in plan view may be equal. Alternatively, the metal foil 30 may be larger than the interlining foil 32 in plan view.

[0018] In addition to the above, the test apparatus 100 of this embodiment includes the following components. The test apparatus 100 includes a current supply unit 40. The current supply unit 40 is electrically connected to the stage 10 and the pressurizing mechanism 20. More specifically, the current supply unit 40 has electrodes 40a and 40b. In Figure 1, electrode 40a is provided on the stage 10 side and electrode 40b is provided on the pressurizing mechanism 20 side. Electrode 40a is electrically connected to the stage 10. Electrode 40b is electrically connected to the pressurizing mechanism 20. Electrodes 40a and 40b are electrodes with opposite polarities. The current supply unit 40 has a power supply circuit that can apply a DC voltage between electrodes 40a and 40b. Therefore, the current supply unit 40 can apply a voltage and supply current between the stage 10 and the pressurizing mechanism 20. The current supply unit 40 can apply a DC voltage between the stage 10 and the pressurizing mechanism 20.

[0019] A base foil 33 may be further provided as a component of the test apparatus 100. The base foil 33 has, for example, a flat shape almost entirely. The flat shape of the base foil 33 is similar to the flat portion between multiple protrusions in the metal foil 30. The base foil 33 may be placed on the top surface 10d of the stage 10. That is, the base foil 33 may be installed so as to be sandwiched between the semiconductor element 50 and the stage 10. In this case, the base foil 33 is positioned so as to be in contact with the semiconductor element 50 and the top surface 10d. The back electrode 57 formed on the lower main surface of the semiconductor element 50 in the Z direction is in contact with the base foil 33.

[0020] The pressure plate 70 is a component that is pressurized by the pressurizing mechanism 20. The pressure plate 70 is positioned directly below the pressurizing mechanism 20 in the Z direction and in contact with the pressurizing mechanism 20. As a result, when the pressurizing mechanism 20 moves downward in the Z direction, the pressure plate 70 is pressed downward and comes into contact with the component directly below it. In this state, the pressure plate 70 is pressurized downward in the Z direction by the pressurizing mechanism 20.

[0021] The supply unit 80 stores some of the above-mentioned components. Specifically, the supply unit 80 can store metal foil 30, intermediary foil 32, underlay foil 33, semiconductor element 50, and pressure plate 70. When the test apparatus 100 is not in use, the supply unit 80 may store reusable components from the above-mentioned components.

[0022] The waste receiving section 82 stores some of the above-mentioned components. Specifically, the waste receiving section 82 can store metal foil 30, intermediary foil 32, underlay foil 33, semiconductor element 50, and pressure plate 70. After use of the test apparatus 100, the waste receiving section 82 stores any of the above-mentioned components that cannot be reused.

[0023] The transport robot 81 transports each component from the supply unit 80 to the desired position when the test apparatus 100 is in use. The transport robot 81 transports each component so that, for example, each component is positioned as shown in Figure 1. Alternatively, the transport robot 81 transports each component to the supply unit 80 or the waste receiving unit 82 after the test apparatus 100 has been used.

[0024] Figure 2 is a schematic cross-sectional view showing the configuration of a test apparatus according to a second example of Embodiment 1. As shown in Figure 2, the test apparatus 100 of the second example of this embodiment has basically the same configuration as the test apparatus 100 of the first example in Figure 1. For this reason, in Figure 2, the same components as in Figure 1 are denoted by the same reference numerals as in Figure 1, and their descriptions are not repeated unless particularly necessary. This is also true for the descriptions of each figure thereafter. In Figure 2, the underlay foil 33 is not placed on the top surface 10d. Therefore, the semiconductor element 50 is placed on the stage 10. Specifically, the lower main surface of the semiconductor element 50 in the Z direction is in contact with the top surface 10d of the stage 10. Thus, the underlay foil 33 does not need to be placed.

[0025] Next, we will describe each component in detail. Stage 10 includes a first surface 10a and a second surface 10b. The first surface 10a is the lowest surface of Stage 10 in the Z direction. The second surface 10b is positioned above the first surface 10a, spaced apart in the Z direction. The second surface 10b is part of the top surface of Stage 10 in the Z direction. The second surface 10b is located at the edge of the top surface of Stage 10 in the Z direction. Stage 10 has a generally flat shape with a thickness along the Z direction. Here, a flat shape means a shape in which the dimension in the Z direction is, for example, 1 / 10 or less of the dimensions in the X and Y directions.

[0026] However, the stage 10 includes a projection 10c. The projection 10c is a region that extends upward from the second surface 10b in the Z direction. The projection 10c is located in the central part of the stage 10, excluding the edges, when viewed from above in the Z direction.

[0027] The surface of the projection 10c that is furthest upward in the Z direction from the first surface 10a and the second surface 10b is the top surface 10d. In other words, the top surface 10d is the uppermost surface of the stage 10. The arithmetic mean roughness (Ra) of the top surface 10d is, for example, 5 μm or less. Preferably, the arithmetic mean roughness of the top surface 10d is 2 μm or less. Arithmetic mean roughness is a surface property parameter specified in JIS (Japan Industrial Standard) B0601:2013.

[0028] Although not shown, a slit may be formed on the first surface 10a. Air may be flowed through the slit using a fan or the like (not shown). The stage 10 may have a cooling mechanism. More specifically, a flow path may be formed inside the stage 10. A coolant such as water may be flowed through the flow path inside the stage 10 using a circulation device. When the temperature of the semiconductor element 50 during the test is 80°C or lower, it is preferable that the stage 10 includes an air cooling mechanism. When the temperature of the semiconductor element 50 during the test is above 80°C, it is preferable that the stage 10 includes a liquid cooling mechanism.

[0029] A positioning plate 11 is attached to the stage 10. The positioning plate 11 has a first surface 11a and a second surface 11b. The first surface 11a is the lowest surface of the positioning plate 11 in the Z direction. The second surface 11b is positioned above the first surface 11a, with a gap in the Z direction between them. The second surface 11b is the highest surface of the positioning plate 11 in the Z direction. The first surface 11a faces the second surface 10b. The first surface 11a and the second surface 10b may be in contact. The second surface 11b is positioned above the top surface 10d in the Z direction. That is, there is a step between the second surface 11b and the top surface 10d.

[0030] A through-hole 11c is formed in the positioning plate 11. The through-hole 11c has a square or rectangular shape when viewed from a plan view from the Z direction. The through-hole 11c is formed in the center of the positioning plate 11 when viewed from a plan view. Therefore, the positioning plate 11 has a rectangular annular shape when viewed from a plan view from the Z direction. The through-hole 11c penetrates the entire length of the positioning plate 11 in the Z direction. The projection 10c of the stage 10 is fitted into the through-hole 11c. The positioning plate 11 positions at least a portion of the semiconductor element 50 within the through-hole 11c. Specifically, for example, the lower part of the semiconductor element 50 is positioned within the through-hole 11c. This positions the semiconductor element 50. When viewed from a plan view from the Z direction, the area of ​​the top surface 10d is preferably 1.0 to 1.2 times the area of ​​the semiconductor element 50.

[0031] The pressurizing mechanism 20 is positioned directly above the pressurizing plate 70 in the Z direction. The pressurizing mechanism 20 extends along the Z direction. The central axis of the pressurizing mechanism 20 extends along the Z direction. In Figures 1 and 2, only the lowest part of the pressurizing mechanism 20 is shown. In Figures 1 and 2, the pressurizing mechanism 20 is not shown except for the lowest part. The pressurizing mechanism 20 may be cylindrical in shape, for example. Alternatively, as shown in Figures 1 and 2, the pressurizing mechanism 20 may have a shape in which the lowest surface in the Z direction protrudes downward. From a different perspective, the shape of the lowest surface of the pressurizing mechanism 20 may be a curved surface that is convex toward the pressurizing plate 70. This reduces the contact area between the pressurizing mechanism 20 and the pressurizing plate 70 at its lowest point, allowing a large pressure to be applied toward the pressurizing plate 70.

[0032] The pressurizing mechanism 20 is movable along the Z-direction, for example by a hydraulic jack. The hydraulic jack is not shown in Figures 1 and 2. By moving along the Z-direction, the pressurizing mechanism 20 applies pressure to the metal foil 30 and the surface electrode 55 from the lowest surface (first surface 70a) of the pressurizing plate 70.

[0033] Figure 3 is a plan view showing a first example of the metal foil of Figure 1 viewed from above in the Z direction. Figure 4 is a schematic cross-sectional view of the portion along the line IV-IV in Figure 3. As shown in Figures 3 and 4, the metal foil 30 has a first surface 30a and a second surface 30b. The first surface 30a is the bottom surface of the metal foil 30 in the Z direction. The second surface 30b is positioned above the first surface 30a, spaced apart in the Z direction. The second surface 30b is the top surface of the metal foil 30 in the Z direction. The overall thickness of the metal foil 30 in the Z direction is T.

[0034] On the first surface 30a, multiple recesses 30c are formed at a pitch p, which is a fixed period. On the second surface 30b, multiple protrusions 30v are formed at a pitch p, which is a fixed period. The pitch p is the distance along the XY plane between the uppermost points of a pair of adjacent protrusions 30v in the direction along the XY plane. The recesses 30c and protrusions 30v have approximately the same shape and size in the cross-sectional view of Figure 4. For example, the cross-sectional shape of the recesses 30c and protrusions 30v is semicircular. However, if possible, the cross-section of the recesses 30c and protrusions 30v may be triangular. In the metal foil 30, multiple recesses 30c and protrusions 30v as uneven surfaces are formed by surface processing. Let t be the height at which the protrusions 30v protrude upward in the Z direction from the second surface 30b. Let d be the width of the protrusions 30v along the second surface 30b in the XY direction. If the convex portion 30v has a semicircular cross-sectional shape, the entire convex portion 30v will be, for example, hemispherical. In this case, d will be the diameter of the hemisphere. Also, the depth to which the recess 30c is recessed upward in the Z direction from the first surface 30a is approximately equal to t. The diameter of the hemisphere of the recess 30c is approximately equal to d. Therefore, the recess 30c and the convex portion 30v will almost overlap when viewed from the Z direction in a plan view.

[0035] The overall thickness T of the metal foil 30 is, for example, 10 μm or more and 500 μm or less. Thickness T is the distance in the Z direction between the first surface 30a and the second surface 30b. However, the lower limit of thickness T may be 50 μm or 100 μm. The upper limit of thickness T may be 400 μm or 300 μm. The pitch p of the multiple protrusions 30v is, for example, 50 μm or more and 300 μm or less. However, the lower limit of pitch p may be 100 μm. The upper limit of pitch p may be 200 μm.

[0036] The height t of the protrusion 30v in the Z direction is, for example, 5 μm or more and 20 μm or less. The height t is the dimension along the Z direction from the point where the protrusion 30v intersects with the second surface 30b, i.e., the lowest point, to the uppermost point furthest from the second surface 30b in the Z direction. However, the lower limit of the height t may be 10 μm. The upper limit of the height t may be 15 μm. The width d of the protrusion 30v along the XY plane is, for example, 20 μm or more and 200 μm or less. The width d is the maximum dimension of the protrusion 30v along the X or Y direction at the point where the protrusion 30v intersects with the second surface 30b, i.e., the lowest point. However, the lower limit of the width d may be 40 μm. The upper limit of the width d may be 180 μm.

[0037] In the first example of the metal foil 30 shown in Figure 3, the multiple protrusions 30v are arranged to form a so-called square grid. That is, in a plan view from the Z direction in Figure 3, a square is obtained by connecting the multiple protrusions 30v so that they become vertices. The multiple protrusions 30v may be arranged in this manner. Here, Figure 5 is a plan view showing a second example of the metal foil of Figure 1 viewed from above in the Z direction. In the second example of the metal foil 30 shown in Figure 5, the multiple protrusions 30v are arranged to form a so-called triangular grid. That is, in a plan view from the Z direction in Figure 5, a triangle is obtained by connecting the multiple protrusions 30v so that they become vertices. The multiple protrusions 30v may be arranged in this manner. Furthermore, the multiple protrusions 30v may be arranged in other ways. For example, the multiple protrusions 30v may be arranged to form a so-called rhombic grid.

[0038] In Figures 3 and 5, protrusions 30v are formed at equal intervals on the second surface 30b. This configuration is also acceptable. However, the protrusions 30v may be formed such that they are denser in the central part of the second surface 30b in a plan view than at the edges. In other words, the pitch between adjacent protrusions 30v is shorter in the central part of the second surface 30b than at the edges, and the number of protrusions 30v per unit area may be greater. In this case, in Figures 1 and 2, it is preferable to install the semiconductor element 50 so that the region with dense protrusions 30v in the central part overlaps with the semiconductor element 50. Note that when the density of protrusions 30v differs locally on the second surface 30b as described above, high-precision alignment may be required when installing the metal foil 30.

[0039] The interlining foil 32 may be entirely flat in shape. Figure 6 is a schematic cross-sectional view of the interlining foil in Figure 1, similar to that in Figure 4. In other words, Figure 6 shows the interlining foil 32 in a cross-sectional view similar to that of the metal foil 30 in Figure 4. As shown in Figure 6, the interlining foil 32 includes a main portion 32c and a plated portion 32d. The main portion 32c constitutes the main part of the interlining foil 32. Therefore, the main portion 32c is located in the center of the interlining foil 32 in Figure 6 and constitutes the majority of the interlining foil 32. The plated portion 32d is applied to the surface of the main portion 32c. The plated portion 32d is the part of the main portion 32c whose surface is plated.

[0040] The overall thickness of the interlining foil 32, including the main portion 32c and the plated portion 32d, in the Z direction during installation is, for example, 10 μm or more and 500 μm or less. However, the lower limit of the thickness of the interlining foil 32 may be 50 μm or 80 μm. The upper limit of the thickness of the interlining foil 32 may be 100 μm or 150 μm. Alternatively, although it falls partially outside the above numerical range, the thickness of the interlining foil 32 may be between 5 μm and 50 μm.

[0041] The base foil 33 may be entirely flat. The thickness of the base foil 33 in the Z direction when installed is, for example, 5 μm or more and 150 μm or less. However, the lower limit of the thickness of the intermediary foil 32 may be 10 μm or 80 μm. Also, the upper limit of the thickness of the intermediary foil 32 may be 100 μm or 50 μm.

[0042] The pressure plate 70 may be entirely flat. The pressure plate 70 has a first surface 70a and a second surface 70b. The first surface 70a is the lowest surface of the pressure plate 70 in the Z direction. The second surface 70b is positioned above the first surface 70a, spaced apart in the Z direction. The second surface 70b is the highest surface of the pressure plate 70 in the Z direction. The arithmetic mean roughness of the first surface 70a is, for example, 5 μm or less. However, it is more preferable that the arithmetic mean roughness of the first surface 70a be 2 μm or less.

[0043] The stage 10, positioning plate 11, semiconductor element 50, metal foil 30, pressure plate 70, and pressure mechanism 20 may be fixed in place so that their relative positions in the direction along the XY plane do not move.

[0044] Next, we will explain the materials used for each component. Stage 10 is conductive. The constituent material of Stage 10 has high thermal conductivity and high electrical conductivity. Stage 10 is formed from, for example, either a metallic material or a carbon material. If Stage 10 is made of a metallic material, Stage 10 is formed to have either copper or aluminum as its main component.

[0045] The materials used to construct the pressurizing mechanism 20 are highly conductive and highly rigid. The pressurizing mechanism 20 is formed primarily from either stainless steel or carbon material.

[0046] The metal foil 30 is made of a metal material that has high electrical conductivity and is as soft as aluminum. The metal foil 30 is formed so that its main component is selected from the group consisting of aluminum, nickel, and copper. The same applies to the protrusions 30v.

[0047] The main portion 32c of the interlayer foil 32 is made of a metallic material with high electrical conductivity and a softness similar to that of aluminum. The main portion 32c is formed so that it is mainly composed of one of the group selected from aluminum, nickel, and copper. The plated portion 32d applied to the surface of the main portion 32c is made of a metallic material. The plated portion 32d is mainly composed of either nickel or gold.

[0048] The underlay foil 33 is made of a metal material that has high electrical conductivity and is as soft as aluminum. The underlay foil 33 is formed so that its main component is selected from the group consisting of copper, aluminum, and silver.

[0049] The constituent material of the pressure plate 70 has high conductivity. The pressure plate 70 is formed from either a metallic material or a carbon material. If the pressure plate 70 is made of a metallic material, it is formed so that aluminum, copper, or stainless steel is the main component. Stainless steel here refers to a type of steel that includes the symbol SUS (Steel Use Stainless) in the steel grade symbols specified in JIS (Japanese Industrial Standards), for example. If the main component of the pressure plate 70 is copper, the surface of the main copper part of the pressure plate 70 may be covered with a coating film. The coating film is formed from a precious metal. The coating film is not shown in Figure 1, etc. By covering the surface of the main part with a coating film, oxidation of the surface of the pressure plate 70 is suppressed.

[0050] Figure 7 is a plan view of the semiconductor device shown in Figures 1 and 2. Figure 8 is a schematic cross-sectional view of the portion along line VIII-VIII in Figure 7. As shown in Figures 7 and 8, the semiconductor device 50 includes a semiconductor substrate 51, a gate insulating film 52, a gate 53, an interlayer insulating film 54, a surface electrode 55, a gate electrode 56, a back electrode 57, and an insulating film 58. The semiconductor device 50 includes, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, the semiconductor device 50 is not limited to this. The semiconductor device 50 may be, for example, a Schottky barrier diode or a pn junction diode instead of a MOSFET.

[0051] The semiconductor substrate 51 is a component that forms the main part of the semiconductor element 50. The constituent material of the semiconductor substrate 51 is, for example, silicon. However, the constituent material of the semiconductor substrate 51 may be a wide-bandgap semiconductor material. If the semiconductor substrate 51 is a wide-bandgap semiconductor material, the semiconductor substrate 51 is, for example, silicon carbide. The semiconductor substrate 51 has a first surface 51a and a second surface 51b. The first surface 51a is the bottom surface of the semiconductor substrate 51 in the Z direction. The second surface 51b is positioned above the first surface 51a, with a gap in the Z direction. The second surface 51b is the top surface of the semiconductor substrate 51 in the Z direction.

[0052] The semiconductor substrate 51 has a source region 51c, a drain region 51d, a well region 51e, and a drift region 51f. The source region 51c is formed on the second surface 51b. The drain region 51d is formed on the first surface 51a. Multiple source regions 51c are formed in a portion of the second surface 51b, spaced apart from each other. The source region 51c is of the first conductivity type. The drain region 51d is formed over almost the entire first surface 51a. The drain region 51d is of the first conductivity type. The well region 51e is formed on the second surface 51b so as to surround, for example, two source regions 51c that are spaced apart from each other. The well region 51e is of the second conductivity type. The second conductivity type is the opposite conductivity type to the first conductivity type. For example, if the first conductivity type is n-type, then the second conductivity type is p-type. The drift region 51f is located above the drain region 51d in the Z direction.

[0053] The drift region 51f is a region of the semiconductor substrate 51 where none of the source region 51c, drain region 51d, or well region 51e were formed. In other words, the drift region 51f corresponds to the conductivity type and dopant concentration of the original semiconductor substrate 51. Here, the drift region 51f is of the first conductivity type. The drift region 51f is formed surrounding the well region 51e. The well region 51e and the drift region 51f have different conductivity types and are in contact with each other. For this reason, the well region 51e and the drift region 51f form a parasitic diode 51g. The dopant concentration in the drift region 51f is lower than that of the source region 51c and the drain region 51d.

[0054] The gate insulating film 52 is formed by thermal oxidation of the semiconductor substrate 51 from the second surface 51b. Therefore, the uppermost part of the gate insulating film 52 is the second surface 51b. The second surface 51b is positioned above the part of the gate insulating film 52 in the Z direction compared to the part of the semiconductor substrate 51 that is not the gate insulating film 52. The gate insulating film 52 is positioned above the uppermost part of the drift region 51f located between two adjacent source regions 51c. The constituent material of the gate insulating film 52 is, for example, silicon oxide.

[0055] The well region 51e includes the channel region 51n. The channel region 51n is a region within the well region 51e that does not overlap planarly with the source region 51c but overlaps with the gate insulating film 52. In other words, the channel region 51n is formed on the second surface 51b within the well region 51e and is sandwiched between the source region 51c and the drift region 51f. The gate 53 is formed, for example, from polycrystalline silicon containing a dopant. The gate 53 is positioned directly above the gate insulating film 52 so as to straddle the channel region 51n.

[0056] The interlayer insulating film 54 is positioned on the second surface 51b of the gate insulating film 52 so as to cover the gate 53 and the gate insulating film 52. The constituent material of the interlayer insulating film 54 is, for example, silicon oxide. A contact hole 54a is formed in the interlayer insulating film 54. No constituent material of the interlayer insulating film 54 is placed in the contact hole 54a. Therefore, a portion of the source region 51c and the well region 51e are exposed in the contact hole 54a.

[0057] The surface electrode 55 is positioned on the second surface 51b so as to cover the interlayer insulating film 54. The surface electrode 55 is positioned directly above the interlayer insulating film 54 and within the contact hole 54a. In other words, the surface electrode 55 is embedded within the contact hole 54a. Therefore, the surface electrode 55 is electrically connected to the source region 51c and the well region 51e. The constituent material of the surface electrode 55 is, for example, aluminum.

[0058] The back electrode 57 is positioned in contact with the first surface 51a. The back electrode 57 is electrically connected to the drain region 51d. The back electrode 57 is formed, for example, by laminating thin films of nickel and gold on the second surface 51b.

[0059] The gate electrode 56 and insulating film 58, described below, are shown in Figure 7. The gate electrode 56 and insulating film 58, which are not shown in Figure 8, are as follows: The interlayer insulating film 54 has other contact holes in addition to the contact hole 54a in Figure 8. The other contact holes are connected to the gate 53. The gate electrode 56 is embedded in one of the other contact holes. Therefore, the gate electrode 56 is electrically connected to the gate 53. In a plan view from the Z direction, the surface electrode 55 and the gate electrode 56 are spaced apart from each other. That is, there is a gap between the outermost part of the surface electrode 55 and the innermost part of the gate electrode 56 in Figure 7. The constituent material of the gate electrode 56 is, for example, aluminum. In this way, the gate electrode 56 is arranged on the interlayer insulating film 54.

[0060] The gate electrode 56 is generally annular in shape, surrounding the surface electrode 55 in a plan view from the Z direction. The surface electrode 55 and the gate electrode 56 may also have a rectangular planar shape. The gate electrode 56 extends partially inward in a plan view, that is, towards the area where the surface electrode 55 is located. This area is referred to as region 56a.

[0061] The insulating film 58 is positioned outside the surface electrode 55 and the gate electrode 56 surrounding it. Therefore, the insulating film 58 surrounds the surface electrode 55 and the gate electrode 56. This is shown in Figure 7. The insulating film 58 is positioned on the interlayer insulating film 54. The constituent material of the insulating film 58 is, for example, polyimide. The insulating film 58 suppresses the generation of unintended high electric fields within the semiconductor device 50. In Figures 1 and 2, the insulating film 58 of Figure 7 is shown on the substrate of the semiconductor device 50. The thickness of the insulating film 58 in the Z direction in Figures 1 and 2 is exaggerated to be thicker than it actually is.

[0062] Next, a test method using the test apparatus 100 will be described. Figure 9 is a flowchart illustrating the test method using the test apparatus of Embodiment 1. As shown in Figure 9, the test method using the test apparatus 100 has steps (S1) to (S5). Step (S1) is the component transport step. Step (S2) is the pressurization start step. Step (S3) is the energization test step. Step (S4) is the pressurization end step. Step (S5) is the component retrieval step.

[0063] In the component transport process (S1), each component stored in the supply unit 80 is placed on the stage 10 and the part directly above it having the pressurizing mechanism 20. Specifically, firstly, the semiconductor element 50 is placed on the stage 10. If there is a backing foil 33 as shown in Figure 1, prior to the above, the backing foil 33 stored in the supply unit 80 is removed from the supply unit 80. The removed backing foil 33 is transported by the transport robot 81 and placed on the top surface 10d of the stage 10. Subsequently, the semiconductor element 50 stored in the supply unit 80 is removed from the supply unit 80. The removed semiconductor element 50 is transported by the transport robot 81 and placed on the backing foil 33. At this time, the back electrode 57 comes into contact with the backing foil 33. As a result, the semiconductor element 50 and the stage 10 are electrically connected via the backing foil 33.

[0064] As shown in Figure 2, if there is no backing foil 33, the semiconductor element 50 taken out from the supply unit 80 is transported by the transport robot 81 and placed on the top surface 10d of the stage 10. At this time, the back electrode 57 comes into contact with the top surface 10d of the stage 10. This electrically connects the semiconductor element 50 and the stage 10.

[0065] In the component transport process (S1), secondly, the intermediary foil 32 stored in the supply unit 80 is taken out of the supply unit 80. The taken-out intermediary foil 32 is transported by the transport robot 81 and placed on the semiconductor element 50. In the component transport process (S1), thirdly, the metal foil 30 stored in the supply unit 80 is taken out of the supply unit 80. The taken-out metal foil 30 is transported by the transport robot 81 and placed on the intermediary foil 32. At this time, the metal foil 30 protrudes so that the convex portion 30v faces upward in the Z direction. In other words, the metal foil 30 is positioned so that the second surface 30b faces upward in the Z direction and the first surface 30a faces downward in the Z direction. In the component transport process (S1), fourthly, the pressure plate 70 stored in the supply unit 80 is taken out of the supply unit 80. The taken-out pressure plate 70 is transported by the transport robot 81 and placed on the metal foil 30. At this time, the first surface 70a faces the second surface 30b of the metal foil 30. The first surface 70a and the second surface 30b come into contact. This electrically connects the pressure plate 70 and the metal foil 30. The pressure plate 70 is installed directly below the pressure mechanism 20.

[0066] After the component transport process (S1) is performed, the pressurization start process (S2) is performed. Figure 10 is a schematic cross-sectional view showing the state of the pressurization start process in the test method. As shown in Figure 10, in the pressurization start process (S2), firstly, the pressurization mechanism 20 moves toward the pressurization plate 70. That is, the pressurization mechanism 20 moves downward in the Z direction. As a result, the lowest surface of the pressurization mechanism 20 comes into contact with the second surface 70b of the pressurization plate 70. This electrically connects the pressurization mechanism 20 and the pressurization plate 70.

[0067] In the pressurization start step (S2), secondly, after the pressurization mechanism 20 contacts the pressurization plate 70 as described above, the pressurization mechanism 20 further presses the pressurization plate 70 toward the semiconductor element 50. In other words, the pressurization mechanism 20 further presses the pressurization plate 70 toward the downward direction in the Z direction. As a result, a downward pressure in the Z direction is applied from the pressurization mechanism 20 to the metal foil 30 and the interlining foil 32 via the pressurization plate 70. As a result, the metal foil 30 and the interlining foil 32 deform, as shown in Figure 10. Specifically, both the metal foil 30 and the interlining foil 32 deform to conform to the surface shape of the upper side in the Z direction of the semiconductor element 50.

[0068] In Figure 10, the upper surface of the semiconductor element 50 in the Z direction protrudes upward at one and the other end in the X direction by the thickness of the insulating film 58 provided on the semiconductor substrate. Therefore, due to the pressure of the pressurizing mechanism 20, the intermediary foil 32 is also positioned higher in the Z direction than other parts at both ends in the X direction where it overlaps planarly with the insulating film 58. As a result of this configuration, the intermediary foil 32 is bent in the region adjacent to the X-direction end of the insulating film 58. Specifically, the X-direction end of the insulating film 58 is the end facing the central part of the semiconductor element 50. Due to this bending, in the cross-sectional view of Figure 10, the uppermost and lowermost surfaces of the intermediary foil 32 extend in a direction that is inclined with respect to both the X and Z directions.

[0069] Consequently, the metal foil 30 in contact with the uppermost surface of the interlining foil 32, particularly its lowest surface, takes on a shape similar to the uppermost and lowest surfaces of the interlining foil 32. That is, the portion of the metal foil 30's lowest surface located on the bent region of the interlining foil 32 bends so as to extend in a direction that is inclined with respect to both the X and Z directions. As a result, the lowest part of the recess 30c is at the same Z-direction position as the flat surface of the first surface 30a other than the recess 30c. This forms a flat first surface 30a connecting the lowest parts of the multiple recesses 30c. On the other hand, the uppermost surface of the metal foil 30 deforms so that the uppermost part of the convex portion 30v of the second surface 30b becomes flat. As a result, the uppermost surface of the convex portion 30v and the second surface 30b of the metal foil 30 at both ends in the X direction directly above the insulating film 58 come into contact with the first surface 70a of the pressure plate 70. The uppermost surface of the metal foil 30 is recessed in the portion sandwiched between the pair of convex portions 30v. However, outside of the recessed area, the second surface 30b of the metal foil 30, including the convex portion 30v, is flat.

[0070] As described above, in the pressurization start step (S2), the intermediary foil 32 and the surface electrode 55 come into contact. At this time, the intermediary foil 32 does not need to come into contact with the gate electrode 56.

[0071] The downward pressure applied from the pressurizing mechanism 20 to the pressurizing plate 70, metal foil 30, etc., is as follows. The lower limit of this pressure is not particularly limited. However, it is preferable that the lower limit of this pressure be 2.94 MPa or higher. 2.94 MPa is 30 kgf / cm². 2 This corresponds to the above. This improves the adhesion between the pressure plate 70, the metal foil 30, the intermediary foil 32, and the semiconductor element 50. The upper limit of the pressure is not particularly limited. However, it is preferable that the upper limit of the pressure be 4.9 MPa or less. 4.9 MPa is 50 kgf / cm². 2 This corresponds to the above. This makes it possible to suppress the application of excessive pressure to the semiconductor element 50.

[0072] After the pressurization start process (S2) is performed, the current test process (S3) is carried out. In the current test process (S3), the current supply unit 40 applies a voltage between the stage 10 and the pressurization mechanism 20. In this way, current flows between the interlayer foil 32 and the surface electrode 55. This tests the electrical characteristics of the semiconductor element 50.

[0073] The current flowing between the interlayer foil 32 and the surface electrode 55 during the energization test process (S3) is as follows. The lower limit of this current is not particularly limited. However, the lower limit of this current is 100 A / cm². 2 The value may be greater than or equal to this. This allows for a shorter current flow time. In other words, the test time can be shortened. The upper limit of the current is not particularly limited. However, the upper limit of the current is 1000 A / cm². 2 The following is also acceptable. This suppresses the destruction of the semiconductor element 50 due to electric current stress.

[0074] When an electric current flows, each component positioned on the lower side in the Z direction of the pressurizing mechanism 20 generates heat. Specifically, the pressurizing plate 70, the metal foil 30, the intermediary foil 32, the semiconductor element 50, the underlay foil 33, and the stage 10 generate heat. The heat causes the metal foil 30 and the intermediary foil 32 to soften. As a result, the metal foil 30 and the intermediary foil 32 deform further than the state shown in Figure 10. That is, the uppermost and lowermost surfaces of the metal foil 30 and the intermediary foil 32 bend to an even larger angle than the state shown in Figure 10. This causes the metal foil 30 and the intermediary foil 32 to adhere more closely to the surface electrode 55. The semiconductor element 50 may be cooled by the stage 10.

[0075] After the energization test process (S3) is performed, the pressurization termination process (S4) is carried out. In the pressurization termination process (S4), the pressurization mechanism 20 moves away from the pressurization plate 70 along the Z direction. In other words, the pressurization mechanism 20 moves upward in the Z direction. As a result, the pressurization mechanism 20 separates from the pressurization plate 70. The pressurization by the pressurization mechanism 20 on the pressurization plate 70, metal foil 30, intermediary foil 32, and semiconductor element 50 is terminated.

[0076] After the pressurization completion process (S4) is performed, the component retrieval process (S5) is carried out. In the component retrieval process (S5), the transport robot 81 transports each component in the opposite direction to the component transport process (S1). That is, each component is transported from the stage 10 to the supply unit 80 or the waste receiving unit 82. At this time, the metal foil 30 is kept away from the intermediary foil 32 and does not come into contact with it. At this time, the intermediary foil 32 is kept away from the surface electrode 55 and does not come into contact with it.

[0077] The test apparatus 100 according to this embodiment comprises a stage 10, a pressurizing mechanism 20, a metal foil 30, and an intermediary foil 32. The stage 10 is capable of supporting a semiconductor element 50, including a surface electrode 55 and a back electrode 57 opposite to the surface electrode 55, for testing. The pressurizing mechanism 20 can press the semiconductor element 50 placed on the stage 10 from the opposite side of the stage 10. The metal foil 30 is sandwiched between the stage 10 and the pressurizing mechanism 20. The intermediary foil 32 is sandwiched between the stage 10 and the pressurizing mechanism 20 and is positioned on the stage 10 side of the metal foil 30 (the side with the semiconductor element 50 placed on the stage 10). The metal foil 30 has an uneven shape (recesses 30c and protrusions 30v). The protrusions 30v are part of the uneven shape.

[0078] The intermediary foil 32 is sandwiched between the metal foil 30 on the stage 10 side. In other words, the intermediary foil 32 is sandwiched on the lower side of the metal foil 30 in the Z direction, on the semiconductor element 50 side. As a result, the uneven shape or protrusions 30v of the metal foil 30 do not directly contact the semiconductor element 50 or the surface electrode 55. Therefore, the occurrence of scratches on the surface of the surface electrode 55 due to the pressurization by the pressurization mechanism 20 can be suppressed.

[0079] The metal foil 30 has an uneven surface. As a result, as shown in Figure 10, the intermediary foil 32 and the metal foil 30 deform in accordance with the surface shape of the semiconductor element 50 at the portion adjacent to the innermost edge of the insulating film 58 in a plan view. That is, the intermediary foil 32 and the metal foil 30 deform so that they are positioned higher than other parts in the portion where the semiconductor element 50 protrudes upward due to the presence of the insulating film 58. The pressure from the pressurizing mechanism 20 causes the metal foil 30, which has an uneven surface, to plastically deform and bend to conform to the shape of the semiconductor element 50 including the insulating film 58. As a result, the adhesion of the intermediary foil 32 to the surface electrode 55 in the current test process (S3) is improved. That is, as the metal foil 30 and the intermediary foil 32 deform, high adhesion between them and the surface electrode 55 is ensured. Consequently, the contact area between the surface electrode 55 and the intermediary foil 32 increases, and the electrical contact resistance during current application decreases. If the metal foil 30 does not have any protrusions 30v, the contact area between the intermediary foil 32 and the semiconductor element 50 will decrease compared to the embodiment in which the protrusions 30v are present. Therefore, if the protrusions 30v are absent, the contact resistance between the semiconductor element 50 and the foil member directly above it will increase compared to when the protrusions 30v are present.

[0080] As described above, according to this embodiment, both effects can be obtained simultaneously: suppression of damage to the surface electrode 55 due to contact with the semiconductor element 50, and reduction of the electrical contact resistance of the surface electrode 55.

[0081] In the above-described test apparatus 100, the pressurizing mechanism 20 can press the semiconductor element 50 against the surface electrode 55 and the back electrode 57 while the semiconductor element 50 is placed on the stage 10. The above-described test apparatus 100 further includes a current supply unit 40 that can supply current by applying a voltage between the stage 10 and the pressurizing mechanism 20. Due to the pressurizing mechanism 20, the intermediary foil 32 and the surface electrode 55 are in close contact, and current flows between the intermediary foil 32 and the surface electrode 55. As a result, the current supply unit 40 can evaluate the electrical characteristics of the semiconductor element 50 with high accuracy.

[0082] In the above-described test apparatus 100, the metal foil 30 can be installed on the intermediary foil 32 such that the protrusion 30v faces the pressurizing mechanism 20. In other words, the metal foil 30 can be installed on the intermediary foil 32 such that the protrusion 30v faces upward, opposite to the semiconductor element 50 in the Z direction. As a result, the protrusion 30v does not face the semiconductor element 50, and thus the occurrence of scratches on the semiconductor element 50 can be suppressed.

[0083] Figure 11 is a schematic enlarged view showing a configuration in which the convex portion of the metal foil faces downward and contacts the interlining foil. Figure 12 is a schematic enlarged view showing a configuration in which the convex portion of the metal foil faces upward and contacts the pressure plate. In Figure 11, unlike in Figure 1, the metal foil 30 is positioned with the first surface 30a on the upper side in the Z direction and the second surface 30b on the lower side in the Z direction. Therefore, the concave portion 30c is positioned directly above the convex portion 30v. The first surface 30a faces and contacts the first surface 70a. The second surface 30b faces the second surface 32b, which is the uppermost surface of the interlining foil 32 in the Z direction. At this time, the surface of the convex portion 30v formed on the second surface 30b contacts the second surface 32b at the contact surface 30t1. The contact surface 30t1 is at least a part of the surface forming the convex portion 30v, for example, a hemisphere. The convex portion 30v and the second surface 32b are in surface contact, not point contact. This is because the metal foil 30 undergoes plastic deformation.

[0084] In Figure 12, the metal foil 30 is positioned with the first surface 30a on the lower side in the Z direction and the second surface 30b on the upper side in the Z direction, similar to Figure 1. The second surface 30b faces and contacts the first surface 70a. The first surface 30a faces and contacts the second surface 32b. At this time, the flat portion of the first surface 30a between adjacent recesses 30c contacts the second surface 32b. Therefore, the first surface 30a contacts the second surface 32b at the contact surface 30t2.

[0085] Firstly, if the protrusion 30v faces downwards as shown in Figure 11, the shape of the protrusion 30v is transferred to the surface of the semiconductor element 50 via the interlayer foil 32 when current is applied. This may damage the semiconductor element 50. In contrast, if the protrusion 30v faces upwards as shown in Figure 12, the transfer of the shape of the protrusion 30v to the semiconductor element 50 can be suppressed. By installing the protrusion 30v facing upwards, that is, away from the semiconductor element 50, and then applying current, a large current can be passed without damaging the surface of the semiconductor element 50.

[0086] Secondly, as shown in Figure 12, the protrusion 30v is positioned on the upper side, towards the pressure plate 70. In this way, the contact area between the metal foil 30 and the intermediary foil 32 when the pressure plate 70 presses is larger than when the protrusion 30v is positioned on the lower side, towards the intermediary foil 32, as shown in Figure 11. This is because the contact surface 30t2 in Figure 12 is larger than the contact surface 30t1 in Figure 11. Therefore, the adhesion between the metal foil 30 and the intermediary foil 32 is improved in Figure 12 compared to Figure 11. Consequently, the electrical contact resistance between the metal foil 30 and the intermediary foil 32 when energized is reduced in Figure 12 compared to Figure 11.

[0087] In the above-described test apparatus 100, the interlining foil 32 includes a main portion 32c whose main component is either aluminum, nickel, or copper, and a plated portion 32d applied to the surface of the main portion 32c. The plated portion 32d is mainly composed of either nickel or gold. If the interlining foil 32 does not have a plated portion 32d, a native oxide film is formed on the surface of the main portion 32c of the interlining foil 32. This native oxide film may damage the semiconductor element 50. By providing the plated portion 32d on the interlining foil 32, the formation of a native oxide film on the surface of the interlining foil 32 can be prevented. As a result, damage to the semiconductor element 50 can be suppressed.

[0088] In the above-described test apparatus 100, the metal foil 30 is mainly composed of aluminum, nickel, or copper. The thickness of the metal foil 30 is 10 μm or more and 500 μm or less. The pitch p of the multiple protrusions 30v, which are part of the uneven shape formed on the metal foil 30, is 50 μm or more and 300 μm or less. The height of the multiple protrusions 30v of the metal foil 30 is 5 μm or more and 20 μm or less. The width of the multiple protrusions 30v of the metal foil 30 is 20 μm or more and 200 μm or less. By setting the pitch p as described above, the current path in the energization test process (S3) can be secured and the electrical resistance between the metal foil 30 and the surface electrode 55 can be reduced. Furthermore, by setting the pitch p as described above, damage to the surface electrode 55 can be suppressed. By setting the height of the protrusions 30v as described above, tearing of the metal foil 30 can be suppressed while ensuring the ability of the metal foil 30 to deform when pressed.

[0089] In the above-described test apparatus 100, the multiple protrusions 30v of the metal foil 30 are arranged periodically. Therefore, the metal foil 30 having the multiple protrusions 30v undergoes plastic deformation and bends due to the pressure applied by the pressurizing mechanism 20. Consequently, the adhesion of the intermediary foil 32 to the surface electrode 55 in the current-conducting test process (S3) is improved. In other words, as the metal foil 30 and intermediary foil 32 deform, high adhesion between them and the surface electrode 55 is ensured. Consequently, the electrical contact resistance during current application is reduced.

[0090] In the above-described test apparatus 100, the multiple protrusions 30v of the metal foil 30 are arranged to form either a square grid or an orthorhombic grid. Regardless of which arrangement of the protrusions 30v is used, the periodic arrangement of the protrusions 30v improves the adhesion of the intermediary foil 32 to the surface electrode 55 during the current-conducting test process (S3), as described above. That is, as the metal foil 30 and intermediary foil 32 deform, high adhesion between them and the surface electrode 55 is ensured. Consequently, the electrical contact resistance during current application is reduced.

[0091] Embodiment 2. Figure 13 is a schematic cross-sectional view showing the configuration of the test apparatus according to Embodiment 2. As shown in Figure 13, the test apparatus 100 of this embodiment has basically the same configuration as the test apparatus 100 of Embodiment 1 shown in Figure 1. For this reason, components that are the same and perform the same function are given the same reference numerals as in Figure 1, and their descriptions are not repeated unless particularly necessary. Although the supply unit 80, transport robot 81, and waste receiving unit 82 are not shown in Figure 13, these components are also provided in this embodiment. As shown in Figure 13, in this embodiment, metal foil 31 is provided in place of metal foil 30 in Figure 1. The material, shape, and size of metal foil 31 are the same as those of metal foil 30.

[0092] Figure 14 is a schematic plan view showing the stage of Embodiment 2, the semiconductor element on it, and the metal foil on top of it superimposed. Figure 14 shows the positional relationship of each superimposed component. For this reason, components that are not visible and are placed on the lower side of the superimposed components are also shown. As shown in Figure 14, a plurality of protrusions 31v are formed on the second surface 31b, which is the uppermost surface of the metal foil 31 in the Z direction. The shape and size of the protrusions 31v are the same as those of the protrusions 30v in Embodiment 1. However, there is a difference between the metal foil 30 and the metal foil 31 at the position on the second surface 31b where the protrusions 31v are formed. Specifically, the protrusions 31v are formed at a higher density in the region that overlaps with the region 56a where the gate electrode 56 extends inward in a plan view, compared to the region outside of the region that overlaps with region 56a. Thus, in this embodiment, the formation density of the protrusions 31v is adjusted to change from region to region according to the characteristics of the electrodes and other components that constitute the semiconductor element 50 that should overlap it planarly. The convex portion 31v, which has a higher density than other regions in region 56a, causes electrical conductivity between the metal foil 31 and the region 56a directly beneath it.

[0093] In other words, the metal foil 31 has regions in which the protrusions 31v are densely formed so as to match the planar shape of the surface electrode 55 and gate electrode 56 of the semiconductor element 50. In this respect, this embodiment is structurally different from Embodiment 1 in which the protrusions 31v are formed uniformly regardless of the configuration of the semiconductor element 50.

[0094] The test apparatus 100 of this embodiment is characterized by the protrusions 31v of the metal foil 31 as described above. The area ratio of the gate electrode 56 included in the semiconductor element 50 is smaller than the area ratio of the surface electrode 55. For this reason, as shown in Figure 14, the protrusions 31v of the metal foil 31 that should overlap the semiconductor element 50 are surface-processed to match the surface shape of the semiconductor element 50. As a result, the number of protrusions 31v that overlap the gate electrode 56, which has a small area, increases. Therefore, compared to Embodiment 1, in which the protrusions are formed haphazardly, the adhesion between the gate electrode 56 and the metal foil 31 and the intermediary foil 32 can be improved. Improved adhesion reduces the electrical contact resistance between the gate electrode 56 and the metal foil 31.

[0095] Embodiment 3. Figure 15 is a schematic cross-sectional view showing the configuration of a test apparatus according to the first example of Embodiment 3. As shown in Figure 15, the test apparatus 100 of this embodiment has basically the same configuration as the test apparatus 100 of Embodiment 1 shown in Figure 1. For this reason, components that are the same and perform the same function are given the same reference numerals as in Figure 1, and their descriptions are not repeated unless particularly necessary. Although the supply unit 80, transport robot 81, and waste receiving unit 82 are not shown in Figure 15, these components are also provided in this embodiment. As shown in Figure 15, in this embodiment, multiple metal foils 30 are laminated together.

[0096] Specifically, as shown in Figure 15, the metal foil 30 has two layers: a lower metal foil 30L and an upper metal foil 30U. The material, shape, and size of the lower metal foil 30L and the upper metal foil 30U are the same as those of the metal foil 30 in Embodiment 1, for example. However, the metal foil 30 may be laminated in three or more layers. The upper metal foil 30U is in contact with the upper side of the lower metal foil 30L in the Z direction. The lower metal foil 30L is placed on the intermediary foil 32. The pressure plate 70 is placed on the upper metal foil 30U.

[0097] Both the lower metal foil 30L and the upper metal foil 30U have multiple protrusions. These protrusions are formed at intervals, similar to the protrusions in Embodiments 1 and 2.

[0098] Figure 16 is a schematic plan view showing the stage of the first example of Embodiment 3, the semiconductor element on it, and the two layers of metal foil on top of it superimposed. Figure 17 is a schematic cross-sectional view of the portion along the line XVII-XVII in Figure 16. Figure 16 shows the positional relationship of each superimposed component. For this reason, components that are not visible and are placed on the lower side of the superimposed components are also shown. As shown in Figures 16 and 17, the protrusions of the lower metal foil 30L are referred to as lower protrusions 30vL. The protrusions of the upper metal foil 30U are referred to as upper protrusions 30vU. As shown in Figures 15 and 17, the upper protrusions 30vU are positioned so as to overlap with the flat portion between adjacent lower protrusions 30vL of the lower metal foil 30L. The upper protrusions 30vU and the lower protrusions 30vL are positioned with the same period in the direction along the XY plane. Therefore, the upper protrusions 30vU and the lower protrusions 30vL are arranged similarly throughout the entire structure. In other words, throughout the entire structure, the upper protrusions 30vU are positioned to overlap with the flat areas between adjacent lower protrusions 30vL of the lower metal foil 30L.

[0099] Figure 18 is a schematic cross-sectional view showing the configuration of the test apparatus according to the second example of Embodiment 3. As shown in Figure 18, the upper protrusion 30vU of the upper metal foil 30U faces away from the pressurizing mechanism 20. That is, the upper protrusion 30vU faces the semiconductor element 50 side, which is the lower side. In this respect, the second example in Figure 18 differs from the first example in Figures 15 to 17. However, in Figure 18 as in Figures 15 to 17, the upper protrusion 30vU is positioned so as to overlap with the flat portion between adjacent lower protrusions 30vL of the lower metal foil 30L. The flat portion between the lower protrusions 30vL is also called the "pitch portion". The downward-facing upper protrusion 30vU contacts the pitch portion of the lower metal foil 30L by biting into it. The configuration shown in Figure 18 is also acceptable. Even with the configuration shown in Figure 18, no damage occurs to the surface electrode 55. As shown in Figure 18, it is possible to achieve an increase in contact area, improved adhesion, and a reduction in electrical resistance during current flow.

[0100] As shown in Figure 18, if there are two layers of metal foil 30, the upper protrusion 30vU of the upper metal foil 30U may face downwards. Among the multiple layers of metal foil 30, it is sufficient that the protrusion of the bottom layer of metal foil 30 faces upwards. In this case, no damage will occur to the surface electrode 55. Among the multiple layers of metal foil 30, the protrusion of the bottom layer of metal foil 30 may face upwards or downwards.

[0101] The test apparatus 100 of this embodiment has multiple metal foils 30 stacked together as described above. In Figures 15 to 17, the protrusions of each of the two layers of metal foil 30 are arranged in a staggered pattern so as to be in alternating positions when viewed from the Z direction in plan view. In this way, for example, the upper protrusions 30vU cover the flat portion between adjacent lower protrusions 30vL of the lower metal foil 30L. Also, the lower protrusions 30vL are positioned to overlap the flat portion between adjacent upper protrusions 30vU of the upper metal foil 30U. In this state, pressure is applied from above in the Z direction by the pressurizing mechanism 20. As a result, when current is applied, the contact area between the metal foils 30 and the intermediary foil 32 and the semiconductor element 50 increases. This is because contact occurs directly below the protrusions 30v. In other words, because the upper protrusions 30vU and the lower protrusions 30vL are positioned at different positions in plan view, the total number of protrusions 30 appears to increase. Therefore, the number of contact points increases. Therefore, the contact area increases, and the adhesion between the metal foil 30 and the intermediary foil 32 and the semiconductor element 50 can be improved. The same applies to Figure 18.

[0102] When two or more layers of metal foil 30 are laminated, the pitch, number, and shape of the protrusions of each laminated metal foil 30 may be changed as appropriate. For example, the pitch, number, and shape of the protrusions of one of the multiple layers of metal foil may be partially or entirely different from the other parts. Alternatively, the pitch, number, and shape of all the protrusions of each of the multiple laminated metal foils 30 may be the same.

[0103] The features described in the embodiments above may be applied in appropriate combinations to the extent that they do not contradict the technical standards.

[0104] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The basic scope of this disclosure is indicated by the claims rather than the foregoing description, and all modifications within the meaning and scope equivalent to the claims are intended.

[0105] The various aspects of this disclosure are summarized below as an appendix. (Note 1) A stage on which a semiconductor device including a surface electrode and a back electrode opposite to the surface electrode can be placed for testing, A pressurizing mechanism capable of pressing the semiconductor element placed on the stage from the opposite side of the stage, A metal foil sandwiched between the stage and the pressurizing mechanism, The system comprises an intermediary foil sandwiched between the stage and the pressurizing mechanism, and installed on the stage side of the metal foil, The metal foil has an uneven surface formed on it, and the test apparatus includes a protrusion as part of the uneven surface.

[0106] (Note 2) The pressurizing mechanism is capable of pressing the semiconductor element against the surface electrode and the back electrode while the semiconductor element is positioned on the stage. The test apparatus as described in Appendix 1, further comprising a current supply unit capable of applying voltage and supplying current between the stage and the pressurizing mechanism.

[0107] (Note 3) The test apparatus according to Appendix 1 or 2, wherein the metal foil can be installed on the intermediary foil such that the protrusions face the pressurizing mechanism side.

[0108] (Note 4) The aforementioned intermediary foil includes a main part which is mainly composed of aluminum, nickel, and copper, and a plated part which is applied to the surface of the main part. The plated portion is mainly composed of either nickel or gold. The thickness of the intermediary foil is 10 μm or more and 500 μm or less, as described in any one of the appendices 1 to 3.

[0109] (Note 5) The aforementioned metal foil mainly consists of aluminum, nickel, and copper. The thickness of the metal foil is 10 μm or more and 500 μm or less. The pitch of the multiple protrusions formed on the metal foil is 50 μm or more and 300 μm or less. The height of the multiple protrusions on the metal foil is 5 μm or more and 20 μm or less. The test apparatus according to any one of the appendices 1 to 4, wherein the width of the multiple protrusions on the metal foil is 20 μm or more and 200 μm or less.

[0110] (Note 6) The test apparatus as described in Appendix 5, wherein the plurality of protrusions on the metal foil are arranged periodically.

[0111] (Note 7) The test apparatus according to Appendix 5 or 6, wherein the plurality of protrusions of the metal foil are arranged to form either a square grid or an orthorhombic grid.

[0112] (Note 8) A test apparatus according to any one of the appendices 1 to 7, wherein multiple metal foils are laminated together. [Explanation of Symbols]

[0113] 10 Stage, 10a, 11a, 30a, 51a, 70a First surface, 10b, 11b, 30b, 32b, 70b Second surface, 10c Protrusion, 10d Top surface, 11 Positioning plate, 11c Through hole, 20 Pressurization mechanism, 30, 31 Metal foil, 30c Recess, 30L Lower metal foil, 30t1, 30t2 Contact surface, 30U Upper metal foil, 30v Protrusion, 30vL Lower protrusion, 30vU Upper protrusion, 32 Intermediate foil, 32c Main part, 32d Plated part, 33 Underlay foil, 40 Current supply part, 40a, 40b Electrodes, 50 Semiconductor element, 51 Semiconductor substrate, 51c Source area, 51d Drain area, 51e Well area, 51f Drift area, 51g Parasitic diode, 51n channel region, 52 gate insulating film, 53 gate, 54 interlayer insulating film, 54a contact hole, 55 surface electrode, 56 gate electrode, 56a region, 57 back electrode, 58 insulating film, 70 pressure plate, 80 supply unit, 81 transport robot, 82 waste receiving unit, 100 test apparatus.

Claims

1. A stage on which a semiconductor device including a surface electrode and a back electrode opposite to the surface electrode can be placed for testing, A pressurizing mechanism capable of pressing the semiconductor element placed on the stage from the opposite side of the stage, A metal foil sandwiched between the stage and the pressurizing mechanism, The system comprises an intermediary foil sandwiched between the stage and the pressurizing mechanism, and installed on the stage side of the metal foil, The metal foil has an uneven surface formed on it, and the test apparatus includes a protrusion as part of the uneven surface.

2. The pressurizing mechanism is capable of pressing the semiconductor element against the surface electrode and the back electrode while the semiconductor element is positioned on the stage. The test apparatus according to claim 1, further comprising a current supply unit capable of applying voltage and supplying current between the stage and the pressurizing mechanism.

3. The test apparatus according to claim 1 or 2, wherein the metal foil can be installed on the intermediary foil such that the protrusions face the pressurizing mechanism side.

4. The aforementioned intermediary foil includes a main part which is mainly composed of aluminum, nickel, and copper, and a plated part which is applied to the surface of the main part. The plated portion is mainly composed of either nickel or gold. The test apparatus according to claim 1 or 2, wherein the thickness of the intermediary foil is 10 μm or more and 500 μm or less.

5. The aforementioned metal foil mainly consists of aluminum, nickel, and copper. The thickness of the metal foil is 10 μm or more and 500 μm or less. The pitch of the multiple protrusions formed on the metal foil is 50 μm or more and 300 μm or less. The height of the multiple protrusions on the metal foil is 5 μm or more and 20 μm or less. The test apparatus according to claim 1 or 2, wherein the width of the plurality of protrusions on the metal foil is 20 μm or more and 200 μm or less.

6. The test apparatus according to claim 5, wherein the plurality of protrusions on the metal foil are arranged periodically.

7. The test apparatus according to claim 5, wherein the plurality of protrusions of the metal foil are arranged to form either a square grid or an orthorhombic grid.

8. The test apparatus according to claim 1 or 2, wherein a plurality of the aforementioned metal foils are laminated.

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