Semiconductor substrates and methods for manufacturing the same, and semiconductor devices.

Abstract

To provide a semiconductor substrate having a high-quality III-V semiconductor layer. [Solution] The semiconductor substrate comprises a substrate, a plurality of nanowires extending from the substrate and made of a III-V semiconductor different from the material of the substrate, a first semiconductor layer made of a III-V semiconductor provided so as to surround the nanowires in the width direction, and a second semiconductor layer made of a III-V semiconductor provided on the first semiconductor layer and covering the substrate.

Description

[Technical Field]

[0001] This invention relates to a semiconductor substrate, a method for manufacturing the same, and a semiconductor device. [Background technology]

[0002] The following techniques are known for growing III-V semiconductor layers with different lattice constants on a substrate: A technique for forming a III-V semiconductor layer on an off-cut silicon substrate is known. A technique for forming a III-V semiconductor buffer layer on a silicon substrate at a low temperature and then forming a III-V semiconductor layer on the buffer layer at a high temperature is known. A technique for forming a superlattice buffer layer on a silicon substrate and then forming a III-V semiconductor layer on the buffer layer is known. A technique for forming a dielectric film with pinholes on a silicon substrate and then forming a III-V semiconductor layer on the dielectric film is known. In addition, a technique for forming InAs nanowires on a silicon substrate is known (for example, Non-Patent Document 1). [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] R. Nakagawa et al. J. Appl. Phys. 134 (2023) 154302 [Overview of the project] [Problems that the invention aims to solve]

[0004] With previously known techniques, lattice distortion caused crystal defects and transitions, making it difficult to grow high-quality III-V semiconductor layers.

[0005] This disclosure aims to provide a semiconductor substrate having a high-quality III-V semiconductor layer, a method for manufacturing the same, and a semiconductor device. [Means for solving the problem]

[0006] Embodiments of the present disclosure are semiconductor substrates comprising: a substrate; a plurality of nanowires extending from the substrate and made of a III-V semiconductor different from the material of the substrate; a first semiconductor layer made of a III-V semiconductor provided so as to surround the nanowires in the width direction; and a second semiconductor layer made of a III-V semiconductor provided on the first semiconductor layer and covering the substrate.

[0007] Embodiments of the present disclosure are methods for manufacturing a semiconductor substrate, comprising the steps of: forming a substrate; forming a plurality of nanowires extending from the substrate and made of a III-V semiconductor different from the material of the substrate; forming a first semiconductor layer made of a III-V semiconductor so as to surround the nanowires in the width direction; and forming a second semiconductor layer made of a III-V semiconductor on the first semiconductor layer so as to cover the substrate. [Effects of the Invention]

[0008] According to this disclosure, it is possible to provide a semiconductor substrate having a high-quality III-V semiconductor layer, a method for manufacturing the same, and a semiconductor device. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a cross-sectional view of a semiconductor substrate according to the first embodiment. [Figure 2] Figures 2(A) to 2(D) are cross-sectional views showing a method for manufacturing a semiconductor substrate according to the first embodiment. [Figure 3] Figure 3 is a cross-sectional transmission electron microscope image showing a pinhole in the example. [Figure 4] Figures 4(A) and 4(B) are scanning electron microscope images showing the nanowires in the examples. [Figure 5] Figure 5 is a histogram of the nanowire diameters in the examples. [Figure 6] Figures 6(A) to 6(C) are optical microscope images of the surface of the semiconductor layer 18 in the embodiment, and Figures 6(D) to 6(F) are scanning electron microscope images of the surface of the semiconductor layer 18. [Figure 7] Figs. 7(A) and 7(B) are RHEED images in the examples. [Figure 8] Fig. 8 is a diagram showing the photoluminescence spectrum of the semiconductor substrate in the examples. [Figure 9] Figs. 9(A) to 9(C) are diagrams showing the X-ray diffraction intensity in the examples. [Figure 10] Figs. 10(A) to 10(C) are diagrams showing the X-ray diffraction intensity in the examples. [Figure 11] Fig. 11 is a cross-sectional view of the semiconductor device according to the second embodiment.

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following embodiments are examples for embodying the technical idea of the invention, and do not limit the present invention to the described configurations and numerical values. In the drawings, components having the same function may be denoted by the same reference numerals, and redundant descriptions may be omitted. Partial substitution or combination between different embodiments and configuration examples is possible. The sizes, positional relationships, etc. of each member shown in each drawing may be exaggerated for easy understanding of the invention.

[0011] (First Embodiment) Fig. 1 is a cross-sectional view of the semiconductor substrate according to the first embodiment. The thickness direction of the substrate 10 is the Z direction, and the plane direction of the substrate 10, which is perpendicular to each other, is the X direction and the Y direction. As shown in Fig. 1, the semiconductor substrate 100 of the first embodiment includes a substrate 10, a dielectric film 12, a nanowire 14, and semiconductor layers 16 and 18.

[0012] The dielectric film 12 is provided on the upper surface (+Z plane) of the substrate 10. The dielectric film 12 has a plurality of pinholes 11 that penetrate through the dielectric film 12. The plurality of nanowires 14 are in contact with the upper surface of the substrate 10 within the pinholes 11 and extend from the substrate 10. The plurality of semiconductor layers 16 (first semiconductor layer) are provided so as to surround each of the plurality of nanowires 14 in the width direction. The semiconductor layer 18 (second semiconductor layer) is provided on the semiconductor layer 16 and covers the substrate 10.

[0013] The substrate 10 is, for example, a single-crystal silicon substrate with the (111) plane as its main plane. The main plane of the substrate 10 may also be the (100) plane. The substrate 10 may also be a semiconductor substrate, such as a III-V semiconductor substrate. Alternatively, the substrate 10 may be an insulating substrate. It is preferable that the substrate 10 be a single-crystal substrate in order to epitaxially grow the nanowires 14.

[0014] The dielectric film 12 is, for example, a silicon oxide film. The dielectric film 12 may also be a silicon nitride film or an aluminum oxide film. The thickness of the dielectric film 12 is, for example, 1 nm to 3 nm. The diameter D11 of the pinholes 11 is, for example, 10 nm to 100 nm. The density of the pinholes 11 is, for example, 1 × 10⁻⁶ 9 cm -2 The above 1 x 10 11 cm -2 The following applies:

[0015] The nanowire 14 is made of a III-V semiconductor different from the material of the substrate 10. The nanowire 14 is made of, for example, an arsenic compound semiconductor. Examples of arsenic compound semiconductors include InAs, GaAs, AlAs, or mixed crystals thereof. The nanowire 14 has a hexagonal crystal structure, such as a wurtzite crystal structure. The diameter D14 of the nanowire 14 is approximately equal to the diameter D11 of the pinhole 11, for example, 100 nm or less. The length of the nanowire 14 is, for example, between 30 nm and 300 nm. The density of the nanowire 14 is approximately equal to the density of the pinhole 11, for example, 1 × 10⁻⁶ 9 cm -2 The above 1 x 10 11 cm -2The following applies: The extension direction of the nanowire 14 is the Z direction. The extension direction of the nanowire 14 may be inclined from the Z direction.

[0016] The semiconductor layer 16 is made of a III-V semiconductor. The material of the semiconductor layer 16 may be the same as the material of the nanowire 14, or it may be different. The semiconductor layer 16 is made of, for example, a mixed crystal of an arsenic compound semiconductor and an antimony compound semiconductor. Examples of antimony compound semiconductors include InSb, GaSb, AlSb, or mixed crystals thereof. When the semiconductor layer 16 is made of InAsSb, the composition ratio of Sb is, for example, 0.04 to 0.35 in atomic ratio. The semiconductor layer 16 has, for example, a zincblende crystal structure. The width W16 of the semiconductor layer 16 in the width direction of the nanowire 14 is, for example, 20 nm to 200 nm.

[0017] The semiconductor layer 18 is made of a III-V semiconductor. The material of the semiconductor layer 16 may be the same as the material of the nanowire 14, or it may be different. The material of the semiconductor layer 18 may be the same as the material of the semiconductor layer 16, or it may be different. The semiconductor layer 18 is made of, for example, an arsenic compound semiconductor, or a mixed crystal of an arsenic compound semiconductor and an antimony compound semiconductor. The semiconductor layer 18 has, for example, a zincblende type crystal structure. The thickness of the semiconductor layer 18 is, for example, 100 nm or more. A semiconductor layer made of a different material from the semiconductor layer 18 may be provided on the semiconductor layer 18.

[0018] (Manufacturing method of the first embodiment) Figures 2(A) to 2(D) are cross-sectional views showing a method for manufacturing a semiconductor substrate according to the first embodiment. As shown in Figure 2(A), a substrate 10 is prepared. A dielectric film 12 is formed on the substrate 10. If the substrate 10 is, for example, a silicon substrate, a silicon oxide film can be formed as the dielectric film 12 by oxidizing the main surface of the silicon substrate. From the viewpoint of forming a thin dielectric film 12, the dielectric film 12 is formed by natural oxidation of the silicon substrate or by thermal oxidation at 250°C to 400°C. The atmosphere during thermal oxidation is, for example, air.

[0019] Next, as shown in Figure 2(B), pinholes 11 are formed in the dielectric film 12. If the dielectric film 12 is a silicon oxide film, the pinholes are formed by depositing Ga droplets on the dielectric film 12 at a temperature of, for example, 500°C to 550°C, and then performing a heat treatment at, for example, 600°C to 700°C. The pinholes 11 may also be formed using methods other than Ga droplets.

[0020] Next, as shown in Figure 2(C), nanowires 14 are grown extending from the pinholes 11. The nanowires 14 are formed, for example, using the MBE (Molecular Beam Epitaxy) method. The substrate temperature when forming the nanowires 14 is, for example, between 400°C and 500°C.

[0021] Next, as shown in Figure 2(D), a semiconductor layer 16 is grown in the width direction of the nanowire 14. The semiconductor layer 16 is formed, for example, using the MBE method. The substrate temperature when forming the semiconductor layer 16 is, for example, between 400°C and 500°C.

[0022] Next, as shown in Figure 1, a semiconductor layer 18 is grown on the semiconductor layer 16 so as to cover the substrate 10. The semiconductor layer 18 is formed, for example, using the MBE method. The substrate temperature when forming the semiconductor layer 18 is, for example, 400°C to 650°C. When forming the semiconductor layer 18, voids or the like may be formed in the area between the semiconductor layers 16. The semiconductor substrate 100 according to the first embodiment is then manufactured.

[0023] (Examples) The semiconductor substrate was fabricated as follows. In Figure 2(A), a (111) single-crystal silicon substrate was prepared as substrate 10. A silicon oxide film was formed on substrate 10 as a dielectric film 12. The dielectric film 12 was formed by heat-treating substrate 10, whose surface had been cleaned with a mixed solution of HCl and HF, in air at 300°C for 10 minutes.

[0024] In FIG. 2(B), the substrate 10 on which the dielectric film 12 was formed was thermally cleaned at 650° C. in a vacuum. With the substrate temperature set at 530° C., Ga droplets were deposited on the dielectric film 12. The substrate 10 on which Ga was deposited was set at 650° C. in a vacuum, and Ga was reacted with the silicon oxide film. As a result, pinholes 11 were formed in the dielectric film 12.

[0025] FIG. 3 is a cross-sectional transmission electron microscope image showing pinholes in the example. In FIG. 3, the thin SiOx portion is the dielectric film 12. Although the pinholes 11 in the dielectric film 12 cannot be clearly confirmed, a black depression is observed at the tip of the arrow with "pinhole" on the substrate 10. This black depression is a portion where a part of the bottom surface of the pinhole 11 was etched by Ga droplets. That is, pinholes 11 are formed in the dielectric film 12 above the black recess. The diameter of the pinhole 11 is about 20 nm.

[0026] Next, in FIG. 2(C), a nanowire 14 made of InAs was formed using the MBE method. With the substrate 10 at 450° C., In molecular beams and As4 molecular beams were supplied to the surface of the dielectric film 12 for 15 minutes. As a result, a nanowire 14 made of InAs extending from the pinhole 11 was formed.

[0027] FIGS. 4(A) and 4(B) are scanning electron microscope images showing the nanowires in the example. FIG. 4(B) is an approximately 4-fold magnification of FIG. 4(A). As shown in FIGS. 4(A) and 4(B), a plurality of linear nanowires 14 are formed. When growing the nanowire 14, RHEED (Reflection High-Energy Electron Beam Diffraction) observation may be performed by irradiating an electron beam. However, in FIGS. 4(A) and 4(B), the electron beam is not irradiated. When the density of the nanowires 14 is low, polycrystals containing In and As grow on the dielectric film 12 between the nanowires 14. Therefore, it is preferable that the density of the nanowires 14 is high. The density of the nanowires 14 is 1.5×10 10 cm -2 is.

[0028] Figure 5 is a histogram of the nanowire diameters in the example. As shown in Figure 5, the average diameter of the nanowires 14 is 20 nm and the standard deviation is 1.8 nm. Thus, by growing the nanowires 14 without irradiation with an electron beam, nanowires 14 with a uniform diameter were formed.

[0029] Next, in Figure 2(D), a semiconductor layer 16 made of InAsSb was formed in the width direction of the nanowire 14 using the MBE method. The semiconductor layer 16 was grown on the substrate 10 at 450°C for 20 minutes.

[0030] Next, in Figure 1, a semiconductor layer 18 made of InAs was formed on the semiconductor layer 16 using the MBE method. The semiconductor layer 18 was grown on the substrate 10 at 450°C.

[0031] Figures 6(A) to 6(C) are optical microscope images of the surface of the semiconductor layer 18 in the example, and Figures 6(D) to 6(F) are scanning electron microscope images of the surface of the semiconductor layer 18. Figures 6(A) and 6(D) are samples of the semiconductor layer 18 with a growth time of 90 minutes. Figures 6(B) and 6(E) are samples of the semiconductor layer 18 with a growth time of 150 minutes. Figures 6(C) and 6(F) are samples of the semiconductor layer 18 with a growth time of 210 minutes.

[0032] As shown in Figures 6(A) and 6(D), when the growth time of the semiconductor layer 18 is 90 minutes, a gap-like shape can be observed on the surface of the semiconductor layer 18, and a structure with a size of approximately 0.5 μm can be observed. This suggests that the semiconductor layer 18 is not sufficiently embedded between the semiconductor layers 16.

[0033] As shown in Figures 6(B) and 6(E), when the growth time of the semiconductor layer 18 is 150 minutes, gap-like shapes on the surface of the semiconductor layer 18 decrease. The size of the structure becomes larger than that shown in Figure 6(D).

[0034] As shown in Figures 6(C) and 6(F), when the growth time of the semiconductor layer 18 is 210 minutes, almost no gap-like shapes can be observed on the surface of the semiconductor layer 18. The size of the structure is 1 μm or larger.

[0035] As described above, when the growth time of the semiconductor layer 18 is short, gaps are observed on the surface of the semiconductor layer 18, but as the growth time is increased, the gaps decrease. When the growth time of the semiconductor layer 18 is set to 210 minutes, the gaps are filled and hardly any gaps are observed. In Figures 6(C) and 6(F), the semiconductor layer 18 is grown thick, so hardly any gaps are observed.

[0036] Figures 7(A) and 7(B) are RHEED images in the examples. Figure 7(A) is a RHEED image after deposition of nanowire 14. Figure 7(B) is a RHEED image after growth of semiconductor layer 18 for 150 minutes.

[0037] The REHEED pattern shown in Figure 7(A) is a wurtzite crystal structure, indicating that the nanowire 14 has a wurtzite crystal structure. The REHEED pattern shown in Figure 7(B) is a zincblende crystal structure, indicating that the semiconductor layers 16 and 18 have a zincblende crystal structure.

[0038] Figure 8 shows the photoluminescence spectrum of a semiconductor substrate in an example. The measured sample was one in which the semiconductor layer 18 was grown for 150 minutes. As shown in Figure 8, a peak is observed at approximately 0.38 eV. This peak is thought to be emission from the heterointerface between the nanowire 14 made of InAs and the semiconductor layer 16 made of InAsSb. The very high height of the peak indicates good crystallinity.

[0039] Figures 9(A) to 9(C) show the X-ray diffraction intensities in the examples. The horizontal axis represents the diffraction angle 2θ, and the vertical axis represents the logarithmic scale of the intensity normalized by the Si(111) peak. Figures 9(A) to 9(D) show samples of semiconductor layer 18 with growth times of 90 minutes, 150 minutes, and 210 minutes, respectively. A peak at 2θ = 28.44° is due to the (111) plane of silicon. A peak at 2θ = 25.42° is due to the (111) plane of InAs having a zincblende crystal structure. A peak at 2θ = 24.99° is due to InAs having a zincblende crystal structure. 1-x S x This is the peak due to the (111) plane at (x=0.25).

[0040] As shown in Figures 9(A) to 9(C), a very sharp peak on the (111) plane of InAs is observed. Thus, InAs with a high-quality crystalline zincblende-type crystal structure has been grown. The weak peak observed around 24.99° is thought to be the peak of InAsSb. Since the InAsSb in semiconductor layer 16 is distorted, the x of InAsSb is not necessarily 0.25. The x is thought to be around 0 to 0.25.

[0041] Figures 10(A) to 10(C) show the X-ray diffraction intensities in the examples. The horizontal axis represents the diffraction angle 2θ, and the vertical axis represents the intensity normalized by the InAs peak. Figures 10(A) to 10(D) show samples with semiconductor layer 18 growth times of 90 minutes, 150 minutes, and 210 minutes, respectively.

[0042] As shown in Figure 10(A), the full width at half maximum (FWHM) of the InAs peak is 0.11° when the growth time is 90 minutes. As shown in Figure 10(B), the FWHM of the InAs peak is 0.08° when the growth time is 150 minutes. As shown in Figure 10(C), the FWHM of the InAs peak is 0.05° when the growth time is 210 minutes. Thus, it can be seen that as the growth time of the semiconductor layer 18 increases, the FWHM narrows and the crystallinity improves.

[0043] As described above, in the embodiment, InAs having good crystallinity was formed as the semiconductor layer 18.

[0044] Based on the results of the examples, we will discuss the first embodiment. As shown in the process in Figure 2(C), multiple nanowires 14 are formed extending from the substrate 10 and made of a III-V semiconductor different from the material of the substrate 10. Even if the lattice constants of the substrate 10 and the nanowires 14 are different, the amount of lattice strain near the interface due to lattice mismatch can be reduced because the area in contact with the substrate 10 of the nanowires 14 is small. In addition, as the nanowire 14 moves toward the tip, the lattice within the nanowire 14 is more easily relaxed, which can reduce transitions and crystal defects.

[0045] As shown in the process in Figure 2(D), a semiconductor layer 16 (first semiconductor layer) made of a III-V semiconductor is formed so as to surround the nanowire 14 in the width direction. Since the nanowire 14 grown as a single crystal has a aligned growth direction and crystal orientation, the crystal structure of the semiconductor layer 16 grown in the width direction of the nanowire 14 is also aligned.

[0046] As shown in the process in Figure 1, a semiconductor layer 18 (second semiconductor layer) made of a III-V semiconductor covering the substrate 10 is formed on the semiconductor layer 16. Because the crystals of the semiconductor layer 16 grown as a single crystal are aligned, the single-crystal semiconductor layer 18 grown from the semiconductor layer 16 are linked to each other and become one unit. At this time, the semiconductor layer 18 can be easily lattice-matched, reducing lattice distortion, and reducing transitions and lattice defects.

[0047] In order to relax the lattice in the nanowire 14, it is preferable that the contact area between the nanowire 14 and the substrate 10 be small. From this viewpoint, the average diameter D14 of the nanowire 14 is preferably 100 nm or less, more preferably 60 nm or less, and even more preferably 40 nm or less. The average diameter D14 of the nanowire 14 is, for example, 10 nm or more, and 30 nm or more. If the density of the nanowire 14 is low, the semiconductor layers 16 and 18 grown in the width direction from the nanowire 14 will not connect to each other. From this viewpoint, the density of the nanowire 14 is 1 × 10⁻⁶ 9 cm -2 The above is preferable, 5 × 10 9 cm -2 The above is more preferable, 1 × 10 10 cm-2 The above is even more preferable. The density of the nanowire 14 is 1 × 10⁻⁶. 11 cm -2 The following applies:

[0048] As shown in Figure 7(A), multiple nanowires 14 having a wurtzite crystal structure are formed on the substrate 10. As shown in Figure 7(B), by forming semiconductor layers 16 and 18 having a zincblende crystal structure, the semiconductor layers 16 and 18 can be grown in the width direction of the nanowires 14.

[0049] As such a material, a single-crystal silicon substrate with the (111) plane as the main plane is used as the substrate 10. Note that having the (111) plane as the main plane means that the main plane is allowed to be tilted by about 5° from the (111) plane. When nanowires 14 made of arsenic compound semiconductor are grown on the (111) single-crystal silicon substrate, the nanowires 14 will have a wurtzite crystal structure. When a semiconductor with a lattice constant larger than that of the nanowires 14 is grown as the semiconductor layer 16, it is thought that a zincblende crystal structure is likely to be formed. A semiconductor with a large lattice constant is a mixed crystal of arsenic compound semiconductor and antimony compound semiconductor.

[0050] When the nanowire 14 is made of InAs, using InAsSb for the semiconductor layer 16 results in a lattice constant of the semiconductor layer 16 being slightly larger than that of the nanowire 14. When the nanowire 14 is made of GaAs, using GaAsSb for the semiconductor layer 16 results in a lattice constant of the semiconductor layer 16 being slightly larger than that of the nanowire 14. The composition ratio of Sb to As and Sb is, for example, greater than 0 atomic percent and 4 atomic percent or more. Too much Sb makes lattice matching with the nanowire 14 difficult. From this viewpoint, the composition ratio of Sb to As and Sb is, for example, 35 atomic percent or less and 25 atomic percent or less.

[0051] The substrate 10 may have a main surface other than the (111) plane. If the substrate 10 has the (111) plane as its main surface, the nanowire 14 is stretched in the Z direction. If the substrate 10 has a main surface other than the (111) plane (for example, if the (100) plane is its main surface), the nanowire 14 may be stretched in a direction that is inclined toward the Z direction.

[0052] In the sample where the semiconductor layer 18 was grown for 150 minutes, the thickness of the semiconductor layer 18 was 200 nm to 300 nm, and in the sample where the semiconductor layer 18 was grown for 210 minutes, the thickness of the semiconductor layer 18 was 400 nm to 500 nm. In the sample where the semiconductor layer 18 was grown for 150 minutes, the gaps were eliminated as shown in Figure 6(E), and the crystallinity was good as shown in Figure 10(B). For this reason, a semiconductor layer 18 thickness of 200 nm or more is preferable. Furthermore, in the sample where the semiconductor layer 18 was grown for 210 minutes, the gaps were further eliminated as shown in Figure 6(F), and the crystallinity was even better as shown in Figure 10(C). For this reason, a semiconductor layer 18 thickness of 400 nm or more is more preferable. That is the case.

[0053] (Second Embodiment) Figure 11 is a cross-sectional view of a semiconductor device according to the second embodiment. As shown in Figure 11, the semiconductor device 102 of the second embodiment comprises a substrate 10, a semiconductor layer 18, and semiconductor elements 20 and 22. The substrate 10 and semiconductor layer 18 are the same as those of the first embodiment. The dielectric film 12, nanowire 14, and semiconductor layer 16 are not shown. The semiconductor element 20 (first semiconductor element) is provided on the substrate 10. The semiconductor element 22 (second semiconductor element) is provided on the semiconductor layer 18.

[0054] The semiconductor element 20 is an electronic component, such as a transistor like a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor element 22 is an optical component, such as a light-emitting element or a light-receiving element. The light-emitting element is, for example, a laser diode or LED (Light Emitting Diode). The light-receiving element is, for example, a photodiode.

[0055] Electronic components such as transistors are formed in and on a silicon substrate. On the other hand, optical components are formed in and on a III-V semiconductor layer. In the first embodiment, the crystallinity of the semiconductor layer 18 can be improved. As a result, a semiconductor element 22 with good characteristics can be formed on the same substrate 10 as the semiconductor element 20. This makes it possible to provide a semiconductor laser on the same substrate as, for example, a CPU (Central Processing Unit) that has transistors.

[0056] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. [Explanation of Symbols]

[0057] 10 circuit boards 11 Pinholes 12 Dielectric film 14 nanowires 16, 18 Semiconductor layer 20, 22 Semiconductor elements

Claims

1. circuit board and A plurality of nanowires extending from the substrate and made of a III-V semiconductor different from the material of the substrate, A first semiconductor layer made of a group III-V semiconductor is provided so as to surround the nanowire in the width direction, A second semiconductor layer is provided on the first semiconductor layer, covering the substrate, and is made of a group III-V semiconductor. A semiconductor substrate comprising the above features.

2. The semiconductor substrate according to claim 1, wherein the plurality of nanowires are arsenic compound semiconductors, and the first semiconductor layer is a mixed crystal of an arsenic compound semiconductor and an antimony compound semiconductor.

3. The semiconductor substrate according to claim 2, wherein the substrate is a single-crystal silicon substrate.

4. The semiconductor substrate according to claim 3, wherein the plurality of nanowires are InAs, and the first semiconductor layer is InAsSb.

5. The semiconductor substrate according to any one of claims 1 to 4, wherein the plurality of nanowires have a wurtzite-type crystal structure, and the first semiconductor layer and the second semiconductor layer have a zincblende-type crystal structure.

6. The semiconductor substrate according to any one of claims 1 to 4, wherein the diameter of the plurality of nanowires is 100 nm or less.

7. The density of the aforementioned plurality of nanowires is 1 × 10 ９ cm －２ The semiconductor substrate according to any one of claims 1 to 4.

8. A dielectric film having a plurality of pinholes is provided on the aforementioned substrate, The semiconductor substrate according to any one of claims 1 to 4, wherein the plurality of nanowires are in contact with the surface of the substrate within the plurality of pinholes.

9. A semiconductor substrate according to any one of claims 1 to 4, A first semiconductor element provided on the substrate, A second semiconductor element provided on the second semiconductor layer, A semiconductor device equipped with a semiconductor device.

10. circuit board and A step of forming a plurality of nanowires extending from the substrate and made of a III-V semiconductor different from the material of the substrate, A step of forming a first semiconductor layer made of a group III-V semiconductor so as to surround the nanowire in the width direction, A step of forming a second semiconductor layer made of a group III-V semiconductor on the first semiconductor layer so as to cover the substrate, A method for manufacturing a semiconductor substrate, comprising:

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