Manufacturing method for semiconductor devices

Abstract

The present invention provides a method for manufacturing a semiconductor device that can improve the performance and reliability of the device elements. [Solution] The method for manufacturing a semiconductor device according to the present invention comprises the steps of: providing a lower channel pattern, an intermediate insulating pattern, and an upper channel pattern sequentially stacked vertically on a substrate; forming a lower source / drain pattern connected to the lower channel pattern; forming an upper source / drain pattern connected to the upper channel pattern; forming a gate structure surrounding the lower channel pattern and the upper channel pattern; forming an upper source / drain pattern and contact holes extending into the lower source / drain pattern; forming a contact film in the contact holes; and performing an annealing process on the contact film to form front source / drain contacts.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a MBCFET (registered trademark) (Multi-Bridge Channel Field Effect Transistor).

Background Art

[0002] As one of the scaling technologies for increasing the density of semiconductor devices, a multi-gate transistor has been proposed in which a multi-channel active pattern (or silicon body) in the form of a fin or nanowire is formed on a substrate, and a gate is formed on the surface of the multi-channel active pattern. Since such a multi-gate transistor utilizes a three-dimensional channel, scaling can be easily performed. In addition, the current control ability can be improved without increasing the gate length of the multi-gate transistor. In addition, the SCE (short channel effect) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed.

[0003] In addition, in order to realize more elements in the same area, research has been conducted on a semiconductor device using a stacked multi-gate transistor in which an upper multi-gate transistor is stacked on a lower multi-gate transistor, and improvement thereof has become an issue every day.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the problems in the above-mentioned conventional semiconductor device manufacturing methods, and the object of the present invention is to provide a semiconductor device manufacturing method that can improve the performance and reliability of the element. [Means for solving the problem]

[0005] To achieve the above objective, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: providing a lower channel pattern, an intermediate insulating pattern, and an upper channel pattern sequentially stacked vertically on a substrate; forming a lower source / drain pattern connected to the lower channel pattern; forming an upper source / drain pattern connected to the upper channel pattern; forming a gate structure surrounding the lower channel pattern and the upper channel pattern; forming contact holes extending into the upper source / drain pattern and the lower source / drain pattern; forming a contact film in the contact holes; and performing an annealing process on the contact film to form a front source / drain contact.

[0006] Furthermore, a method for manufacturing a semiconductor device according to the present invention, made to achieve the above objective, is characterized by comprising the steps of: providing a lower channel pattern, an intermediate insulating pattern, and an upper channel pattern sequentially stacked vertically on a substrate; forming a lower source / drain pattern containing a p-type dopant on the side surface of the lower channel pattern; forming a lower front interlayer insulating film on the lower source / drain pattern; forming an upper source / drain pattern containing an n-type dopant on the side surface of the upper channel pattern, wherein the lower front interlayer insulating film is positioned between the lower source / drain pattern and the upper source / drain pattern; forming an upper front interlayer insulating film on the upper source / drain pattern; forming a gate structure surrounding the lower channel pattern and the upper channel pattern; forming a contact hole that penetrates the upper front interlayer insulating film and exposes the upper source / drain pattern, wherein the bottom surface of the contact hole is positioned below the uppermost surface of the upper channel pattern; forming a contact film in the contact hole; and performing an annealing process on the contact film to form a front source / drain contact.

[0007] Furthermore, a method for manufacturing a semiconductor device according to the present invention, made to achieve the above objective, comprises the steps of: providing a lower stacked structure including a first lower semiconductor layer and a second lower semiconductor layer alternately stacked vertically on a substrate; forming an intermediate insulating pattern on the lower stacked structure; forming an upper stacked structure including a first upper semiconductor layer and a second upper semiconductor layer alternately stacked vertically on the intermediate insulating pattern; forming a plurality of first recesses penetrating the lower stacked structure, the intermediate insulating pattern, and the upper stacked structure; and forming a lower source / drain pattern, a lower front interlayer insulating film, and an upper source / drain pattern sequentially stacked vertically within each of the plurality of first recesses, wherein the lower source / drain pattern includes a first lower source / drain pattern and a second lower source / drain pattern in mutually different first recesses among the plurality of first recesses, and the upper source / drain The pattern includes a first upper source / drain pattern on the first lower source / drain pattern and a second upper source / drain pattern on the second lower source / drain pattern, and is characterized by comprising the steps of: removing the first lower semiconductor layer and the first upper semiconductor layer to form a gate trench; forming a gate structure provided in the gate trench; forming a first contact hole that exposes the first upper source / drain pattern and the first lower source / drain pattern; forming a second contact hole that exposes the second upper source / drain pattern; forming a contact film in the first contact hole and the second contact hole; and performing an annealing process on at least a portion of the contact film to form a first front source / drain contact in the first contact hole and a second front source / drain contact in the second contact hole. [Effects of the Invention]

[0008] According to the semiconductor device manufacturing method of the present invention, the contact film formed in the upper source / drain pattern and the contact holes extending within the lower source / drain pattern is subjected to an annealing process to remove seams, thereby improving contact resistance, reducing stress applied to the channel, and improving channel performance. [Brief explanation of the drawing]

[0009] [Figure 1] This is an exemplary layout diagram illustrating a semiconductor device according to an embodiment of the present invention. [Figure 2] This is a cross-sectional view taken along the line A-A' in Figure 1. [Figure 3] This is a cross-sectional view taken along the line B-B' in Figure 1. [Figure 4] This is a cross-sectional view taken along the line C-C' in Figure 1. [Figure 5] This is a cross-sectional view showing the schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 6] This is a cross-sectional view showing the schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 7] This is a cross-sectional view showing the schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 8] This is a cross-sectional view showing the schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 9] This figure illustrates a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] This figure illustrates a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] This figure illustrates a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] This figure illustrates a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] This figure illustrates a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14]It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 19] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 20] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 21] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 22] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 23] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 24] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 25] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 26] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 27] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 28] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 29] It is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 30] It is an exemplary layout diagram for explaining a semiconductor device according to an embodiment of the present invention. [Figure 31] This is a cross-sectional view taken along the line D-D' in Figure 30. [Figure 32] This is a cross-sectional view taken along the line E-E' in Figure 30. [Modes for carrying out the invention]

[0010] Next, specific examples of embodiments for carrying out the semiconductor device manufacturing method according to the present invention will be described with reference to the drawings.

[0011] The embodiments will be described in further detail with reference to the accompanying drawings, which show exemplary embodiments. The embodiments described herein are provided as examples only, and the present invention is not limited thereto and can be carried out in various other forms. Each embodiment described below is not excluded from other embodiments described herein or not described herein that are consistent with the present invention, or other embodiments associated with one or more features of other embodiments. In this specification, when an element or layer is described as being "on top of," "connected to," or "joined to" another element or layer, it means that the element or layer may be directly "on top of," "connected to," or "joined" to another element or layer, or an intermediate element or intermediate layer may be interposed. In contrast, if an element is described as being "directly on top of," "directly connected to," or "directly joined to" another element or layer, then there are no intermediate elements or layers. When expressions such as "at least one" are placed before an enumeration of elements, the modification applies to the entire enumeration, not to any individual element listed. For example, "at least one of a, b, and c" means a only, b only, c only, a and b, a and c, b and c, or all of a, b, and c. In this specification, ordinal numbers such as "1st," "2nd," etc., are used to describe various components regardless of their importance or order, and are not intended to limit those components, but rather to distinguish them from other components.

[0012] The drawings relating to a semiconductor device according to embodiments of the present invention show, as an example, a transistor including nanowires or nanosheets, MBCFET® (Multi-Bridge Channel Field Effect Transistor), but are not limited thereto. A semiconductor device according to an embodiment of the present invention may include a fin-type transistor (FinFET), a tunneling transistor (tunneling FET), or a vertical transistor (Vertical FET) having a channel region with a fin-shaped pattern. It goes without saying that the semiconductor device according to the embodiment of the present invention may include a planar transistor. Furthermore, the technical concept of the present invention can be applied to transistors based on two-dimensional materials (2D material-based FETs) and their heterostructures. Furthermore, the semiconductor device according to the embodiment of the present invention may include a bipolar junction transistor, a lateral double diffusion transistor (LDMOS), and the like.

[0013] A semiconductor device according to an embodiment of the present invention will be described with reference to Figures 1 to 4. Figure 1 is an exemplary layout diagram illustrating a semiconductor device according to an embodiment of the present invention; Figure 2 is a cross-sectional view taken along the line A-A' in Figure 1; Figure 3 is a cross-sectional view taken along the line B-B' in Figure 1; and Figure 4 is a cross-sectional view taken along the line C-C' in Figure 1.

[0014] Referring to Figures 1 to 4, the semiconductor device according to an embodiment of the present invention includes a lower channel pattern BNS, an upper channel pattern UNS, a gate structure GS, lower source / drain patterns (150B1, 150B2), upper source / drain patterns (150U1, 150U2), an intermediate insulation pattern 115, a first front source / drain contact 170, a second front source / drain contact 180, a second back source / drain contact 80, and a back wiring line 50. In the following, the third direction DR3 is orthogonal to the first direction DR1 and the second direction DR2. The second direction DR2 is orthogonal to the first direction DR1. The first direction DR1 is referred to as the first horizontal direction, the second direction DR2 as the second horizontal direction, and the third direction DR3 as the vertical direction. The top, bottom, upper surface, lower surface, and bottom surface are defined relative to the third direction DR3.

[0015] The back interlayer insulating film 290 includes an upper surface and a bottom surface facing the third direction DR3. The back surface interlayer insulating film 290 may include, for example, at least one of silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and low dielectric constant material. The dielectric constant of low dielectric constant materials is smaller than the dielectric constant of silicon oxide, which is "3.9". The back surface interlayer insulating film 290 is shown as a single layer, but this is for explanatory purposes only and is not limited to this.

[0016] The insulating pattern 290P is positioned on the upper surface of the back interlayer insulating film 290. The insulating pattern 290P protrudes in a third direction DR3 from the upper surface of the back interlayer insulating film 290. The insulating pattern 290P is extended in the first direction DR1. The insulating pattern 290P may contain the same material as the back interlayer insulating film 290.

[0017] The field insulating film 105 is positioned on the upper surface of the back interlayer insulating film 290. The field insulating film 105 surrounds the sidewall of the insulating pattern 290P. For example, the upper surface of the insulating pattern 290P is formed higher than the upper surface of the field insulating film 105. In other words, at least a portion of the insulating pattern 290P protrudes in the third direction DR3 from the upper surface of the field insulating film 105. Another example is that the upper surface of the insulating pattern 290P may be formed substantially coplanar with the upper surface of the field insulating film 105. The field insulating film 105 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof. For example, the field insulating film 105 may contain the same material as the back interlayer insulating film 290 and the insulating pattern 290P, and there may be no distinction of an interface between the field insulating film 105 and the back interlayer insulating film 290, there may be no distinction of an interface between the field insulating film 105 and the insulating pattern 290P, and there may be no distinction of an interface between the back interlayer insulating film 290 and the insulating pattern 290P.

[0018] The lower channel pattern BNS is placed on the back interlayer insulating film 290. For example, the lower channel pattern BNS is positioned on the upper surface of the back interlayer insulating film 290. Multiple lower channel patterns BNS are separated in the third direction DR3. Multiple lower channel patterns BNS separated in the third direction DR3 are separated in the first direction DR1. The diagram shows, but is not limited to, a configuration in which two lower channel patterns BNS are arranged on the upper surface of the back interlayer insulating film 290. In one embodiment, one or more lower channel patterns BNS may be arranged on the upper surface of the back interlayer insulating film 290.

[0019] The upper channel pattern UNS is positioned on the upper surface of the back interlayer insulating film 290. The upper channel pattern UNS is placed on top of the lower channel pattern BNS. The lower channel pattern BNS is positioned between the back interlayer insulating film 290 and the upper channel pattern UNS. The upper channel pattern UNS is separated from the lower channel pattern BNS and the third direction DR3. Multiple upper channel patterns UNS are separated in the third direction DR3. Multiple upper channel patterns UNS separated in the third direction DR3 are separated in the first direction DR1. The diagram shows, but is not limited to, an arrangement where two upper channel patterns UNS are positioned on the upper surface of the back interlayer insulating film 290. In one embodiment, one or more upper channel patterns UNS may be arranged on the upper surface of the back interlayer insulating film 290. Furthermore, the number of upper channel patterns UNS is shown to be the same as the number of lower channel patterns BNS, but this is not limited to this case.

[0020] The lower channel pattern BNS and the upper channel pattern UNS each have the form of a nanosheet or nanowire. The lower channel pattern BNS and the upper channel pattern UNS may each contain elemental semiconductor materials such as silicon or germanium. Furthermore, the lower channel pattern BNS and the upper channel pattern UNS may each contain a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. Group IV-IV compound semiconductors may be, for example, binary compounds, ternary compounds, or compounds doped with Group IV elements, each containing at least two of the following elements: carbon (C), silicon (Si), germanium (Ge), and tin (Sn). III-V compound semiconductors can be, for example, binary, ternary, or quaternary compounds formed by bonding at least one of the group III elements, aluminum (Al), gallium (Ga), and indium (In), with one of the group V elements, phosphorus (P), arsenic (As), and antimony (Sb). For example, the lower channel pattern BNS may contain the same substance as the upper channel pattern UNS. As another example, the lower channel pattern BNS may include the upper channel pattern UNS and other substances.

[0021] The intermediate insulation pattern 115 is positioned between the lower channel pattern BNS and the upper channel pattern UNS. The intermediate insulation pattern 115 is separated from the lower channel pattern BNS and the third direction DR3. The intermediate insulation pattern 115 is separated from the upper channel pattern UNS and the third direction DR3. The intermediate insulation pattern 115 contains an insulating material. For example, the intermediate insulating pattern 115 may include at least one of silicon nitride, silicon oxynitride, silicon boron carbonitride, silicon carbonitride, silicon oxide, silicon oxynitride, and combinations thereof.

[0022] Multiple gate structures GS are arranged on the back interlayer insulating film 290. For example, each gate structure GS is placed on the upper surface of the back interlayer insulating film 290. The gate structure GS is extended in the second direction DR2. The gate structure GS is positioned separated in the first direction DR1. The gate structures GS are adjacent to each other in the first direction DR1. The gate structure GS encloses the lower channel pattern BNS and the upper channel pattern UNS. For example, in a cross-sectional view obtained by cutting the gate structure GS in the second direction DR2, the gate structure GS surrounds the lower channel pattern BNS and the upper channel pattern UNS. The gate structure GS surrounds the intermediate insulation pattern 115. For example, the gate structure GS is in contact with the insulating pattern 290P. The gate structure GS is in contact with the upper surface of the insulating pattern 290P. The gate structure GS includes a gate electrode 120 and a gate insulating film 130.

[0023] The gate electrode 120 is placed on the back interlayer insulating film 290. The gate electrode 120 is extended in the second direction DR2. The gate electrode 120 surrounds the lower channel pattern BNS, the upper channel pattern UNS, and the intermediate insulating pattern 115. In other words, the lower channel pattern BNS, the upper channel pattern UNS, and the intermediate insulating pattern 115 penetrate the gate electrode 120. The gate electrode 120 is positioned between the adjacent lower channel pattern BNS and the adjacent upper channel pattern UNS. The gate electrode 120 is positioned between the lower channel pattern BNS and the insulating pattern 290P, between the lower channel pattern BNS and the intermediate insulating pattern 115, and between the upper channel pattern UNS and the intermediate insulating pattern 115. The gate electrode 120 surrounding the lower channel pattern BNS and the upper channel pattern UNS is shown as a single layer film, but is not limited to this. For example, the gate electrode 120 surrounding the lower channel pattern BNS is distinguished from the gate electrode 120 surrounding the upper channel pattern UNS.

[0024] The gate electrode 120 may include at least one of the following: metal, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide, and conductive metal oxynitride. The gate electrode 120 is made of, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), and tungsten (W). This may include, but is not limited to, at least one of the following: aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (NiPt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. Conductive metal oxides and conductive metal oxynitrides may include, but are not limited to, oxidized forms of the above-mentioned substances.

[0025] The gate insulating film 130 is placed between the gate electrode 120 and the insulating pattern 290P. The gate insulating film 130 is placed between the gate electrode 120 and the field insulating film 105. The gate insulating film 130 extends along the upper surface of the field insulating film 105, and along the upper and side surfaces of the insulating pattern 290P that protrudes from the field insulating film 105 in a third direction DR3. The gate insulating film 130 is in contact with the field insulating film 105 and the insulating pattern 290P. The gate insulating film 130 is placed between the lower channel pattern BNS and the gate electrode 120, between the upper channel pattern UNS and the gate electrode 120, and between the intermediate insulating pattern 115 and the gate electrode 120. The gate insulating film 130 is positioned around the lower channel pattern BNS, around the upper channel pattern UNS, and around the intermediate insulating pattern 115. The gate electrode 120 is placed on the gate insulating film 130.

[0026] The gate insulating film 130 may contain at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material with a dielectric constant greater than that of silicon oxide. High dielectric constant materials may include, for example, one or more of the following: boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. The gate insulating film 130 is shown as a single layer, but is not limited to this.

[0027] One embodiment of the semiconductor device includes a Negative Capacitance (NC) FET that utilizes a negative capacitor. For example, the gate insulating film 130 includes a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties. Ferroelectric material films have negative capacitance, while paraelectric material films have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance will be less than the capacitance of each individual capacitor. On the other hand, if at least one of the capacitances of two or more capacitors connected in series is negative, the total capacitance is positive and greater than the absolute values ​​of each individual capacitance. When a ferroelectric material film with negative capacitance and a paraelectric material film with positive capacitance are connected in series, the overall capacitance value of the series-connected ferroelectric and paraelectric material films increases. By utilizing the increase in overall capacitance, transistors containing ferroelectric material films have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0028] Ferroelectric material films possess ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide is a substance in which hafnium oxide is doped with zirconium (Zr). Another example is hafnium zirconium oxide, a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0029] The ferroelectric material film further contains doped dopants. For example, a dopant may contain at least one of the following: aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant contained in a ferroelectric material film varies depending on which ferroelectric material it contains.

[0030] When the ferroelectric material film contains hafnium oxide, the dopants contained in the ferroelectric material film may include at least one of the following: gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y). When the dopant is aluminum (Al), the ferroelectric material film contains 3-8 at% (atomic %) of aluminum. Here, the dopant ratio is the ratio of aluminum to the total of hafnium and aluminum. When the dopant is silicon (Si), the ferroelectric material film contains 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film contains 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film contains 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film contains 50-80 at% zirconium.

[0031] A paraelectric material film possesses the properties of a paraelectric material. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide contained in the paraelectric material film may include, but is not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

[0032] Ferroelectric material films and paraelectric material films may contain the same material. A ferroelectric material film possesses ferroelectric properties, but a paraelectric material film does not necessarily have to possess ferroelectric properties. For example, if both the ferroelectric material film and the paraelectric material film contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material film will differ from the crystal structure of the hafnium oxide contained in the paraelectric material film. A ferroelectric material film has a thickness that gives it ferroelectric properties. The thickness of the ferroelectric material film is, for example, 0.5 to 10 nm, but is not limited to this. Since the critical thickness at which each ferroelectric material exhibits ferroelectric properties can differ, the thickness of the ferroelectric material film varies depending on the ferroelectric material. As an example, the gate insulating film 130 may include a single ferroelectric material film. As another example, the gate insulating film 130 may include multiple ferroelectric material films spaced apart from each other. The gate insulating film 130 may have a multilayer film structure in which multiple ferroelectric material films and multiple paraelectric material films are alternately stacked.

[0033] The gate spacer 140 is placed on the upper surface of the back interlayer insulating film 290. The gate spacer 140 is positioned on the side wall of the gate electrode 120. The gate spacer 140 is not placed between the back interlayer insulating film 290 and the lower channel pattern BNS, nor between the lower channel pattern BNS adjacent to the third direction DR3. The gate spacer 140 is not placed between the intermediate insulating pattern 115 and the upper channel pattern UNS, nor between the upper channel pattern UNS adjacent to the third direction DR3. The gate spacer 140 is not placed between the intermediate insulating pattern 115 and the lower channel pattern BNS. The gate spacer 140 may include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbonite, silicon boron nitride, silicon oxyboronite, silicon oxycarbide, and combinations thereof. The gate spacers 140 are shown as single-layer films, but are not limited to this.

[0034] The gate capping pattern 145 is positioned on the upper surface of the gate electrode 120. The upper surface of the gate capping pattern 145 is coplanar with the upper surface of the upper interlayer insulating film 190U. In one embodiment, the gate capping pattern 145 is positioned between the gate spacers 140. The gate capping pattern 145 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. The gate capping pattern 145 contains a material having an etching selectivity ratio with respect to the upper interlayer insulating film 190U.

[0035] A semiconductor device according to one embodiment further includes a gate contact electrically connected to the gate electrode 120. For example, the gate contact extends in a third direction DR3 and penetrates the gate capping pattern 145 on the upper surface of the gate electrode 120. The gate contact makes contact with the upper surface of the gate electrode 120. Another example is a gate contact that extends in a third direction DR3 and penetrates the gate insulating film 130 on the underside of the gate electrode 120. The gate contact makes contact with the lower surface of the gate electrode 120. The gate contact may include, for example, at least one of metals, conductive metal nitrides, conductive metal carbides, conductive metal oxides, conductive metal carbonitrides, and two-dimensional materials.

[0036] The lower source / drain patterns (150B1, 150B2) are located on the back interlayer insulating film 290. The lower source / drain patterns (150B1, 150B2) are located on at least one side of the gate electrode 120. For example, the lower source / drain patterns (150B1, 150B2) are located on both sides of the gate electrode 120. The lower source / drain patterns (150B1, 150B2) are connected to the lower channel pattern BNS. The lower source / drain patterns (150B1, 150B2) are in contact with the lower channel pattern BNS. The uppermost surface of the lower source / drain patterns (150B1, 150B2) is formed higher than the uppermost surface of the lower channel pattern BNS. The gate insulating film 130 is positioned between the gate electrode 120 and the lower source / drain patterns (150B1, 150B2).

[0037] The upper source / drain patterns (150U1, 150U2) are positioned on top of the lower source / drain patterns (150B1, 150B2). The upper source / drain patterns (150U1, 150U2) are separated from the lower source / drain patterns (150B1, 150B2) in the third direction DR3. The upper source / drain patterns (150U1, 150U2) are located on at least one side of the gate electrode 120. For example, the upper source / drain patterns (150U1, 150U2) are positioned on both sides of the gate electrode 120. The upper source / drain patterns (150U1, 150U2) are connected to the upper channel pattern UNS. The upper source / drain patterns (150U1, 150U2) are in contact with the upper channel pattern UNS. The uppermost surface of the upper source / drain patterns (150U1, 150U2) is formed higher than the uppermost surface of the upper channel pattern UNS. The gate insulating film 130 is positioned between the gate electrode 120 and the upper source / drain patterns (150U1, 150U2). In Figure 4, the lower source / drain patterns (150B1, 150B2) are shown as having a shape similar to a hexagon, but are not limited to this. In one embodiment, the outer shape of the lower source / drain patterns (150B1, 150B2) may be similar to a pentagon or a quadrilateral.

[0038] The lower source / drain patterns (150B1, 150B2) and the upper source / drain patterns (150U1, 150U2) each contain semiconductor material. For example, the lower source / drain patterns (150B1, 150B2) and the upper source / drain patterns (150U1, 150U2) may each contain elemental semiconductor materials such as silicon or germanium. Furthermore, the lower source / drain patterns (150B1, 150B2) and the upper source / drain patterns (150U1, 150U2) may each contain, for example, a binary compound, a ternary compound, or a compound doped with a Group IV element, each containing at least two of the following elements: carbon (C), silicon (Si), germanium (Ge), and tin (Sn).

[0039] The lower source / drain patterns (150B1, 150B2) are included in the source / drain of transistors that use the lower channel pattern BNS as the channel region. The upper source / drain patterns (150U1, 150U2) are included in the source / drain of the transistor that uses the upper channel pattern UNS as the channel region. The lower channel pattern BNS and the upper channel pattern UNS are contained within transistors of different conductivity types. The lower source / drain patterns (150B1, 150B2) contain a dopant of a first conductivity type, and the upper source / drain patterns (150U1, 150U2) contain a dopant of a second conductivity type different from the first conductivity type. The lower channel pattern BNS is used as the channel region for PMOS, and the upper channel pattern UNS is used as the channel region for NMOS. The lower source / drain patterns (150B1, 150B2) contain a p-type dopant, and the upper source / drain patterns (150U1, 150U2) contain an n-type dopant. The p-type dopant may, but is not limited to, include at least one of boron (B) and gallium (Ga). n-type dopants may include, but are not limited to, at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0040] In one embodiment, the lower source / drain patterns (150B1, 150B2) each include a first lower epitaxial film 150Ba and a second lower epitaxial film 150Bb, and the upper source / drain patterns (150U1, 150U2) each include a first upper epitaxial film 150Ua and a second upper epitaxial film 150Ub. For example, the first lower epitaxial film 150Ba extends along the upper surface of the insulating pattern 290P, the side surface of the lower channel pattern BNS, and the side surface of the gate structure GS. The second lower epitaxial film 150Bb is laminated on the first lower epitaxial film 150Ba. The first lower epitaxial film 150Ba is provided as a seed layer for growing the second lower epitaxial film 150Bb. The dopant concentration in the second lower epitaxial membrane 150Bb is greater than the dopant concentration in the first lower epitaxial membrane 150Ba. The first upper epitaxial film 150Ua extends along the upper surface of the intermediate insulating pattern 115, the side surface of the upper channel pattern UNS, and the side surface of the gate structure GS. The second upper epitaxial film 150Ub is laminated on the first upper epitaxial film 150Ua. The first upper epitaxial film 150Ua is provided as a seed layer for growing the second upper epitaxial film 150Ub. The dopant concentration in the second upper epitaxial membrane 150Ub is greater than the dopant concentration in the first upper epitaxial membrane 150Ua. In the drawings, the lower source / drain patterns (150B1, 150B2) and the upper source / drain patterns (150U1, 150U2) are shown as being multilayered, but are not limited to this.

[0041] The lower front interlayer insulating film 190B is positioned on the upper surface of the back interlayer insulating film 290. The lower front interlayer insulating film 190B covers the lower source / drain pattern (150B1, 150B2). The upper source / drain patterns (150U1, 150U2) are positioned on the lower front interlayer insulating film 190B. The lower front interlayer insulating film 190B is positioned between the lower source / drain patterns (150B1, 150B2) and the upper source / drain patterns (150U1, 150U2). The lower source / drain etching stop film 185B extends along the profile of the lower source / drain pattern (150B1, 150B2). The lower source / drain etching stop film 185B is positioned between the field insulating film 105 and the first lower front interlayer insulating film 190B. The lower source / drain etching stop film 185B extends along the profile of the upper surface of the field insulating film 105. In one embodiment, the lower source / drain etching stop film 185B is not positioned between the lower source / drain patterns (150B1, 150B2) and the lower front interlayer insulating film 190B.

[0042] The upper front interlayer insulating film 190U is placed on the lower front interlayer insulating film 190B. The upper front interlayer insulating film 190U covers the upper source / drain patterns (150U1, 150U2). The upper source / drain etching stop film 185U is positioned between the upper front interlayer insulating film 190U and the upper source / drain patterns (150U1, 150U2). The upper source / drain etching stop film 185U extends along at least a portion of the profile of the upper source / drain pattern (150U1, 150U2). In one embodiment, in the cross-sectional view of Figure 4, the upper front interlayer insulating film 190U and the lower front interlayer insulating film 190B are not separated by the upper source / drain etching stop film 185U.

[0043] The lower front interlayer insulating film 190B and the upper front interlayer insulating film 190U may each contain at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The lower source / drain etching stop film 185B and the upper source / drain etching stop film 185U may each include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbonite, silicon boron nitride, silicon oxyboronite, silicon carbonitride, silicon oxycarbide, and combinations thereof.

[0044] The front source / drain contacts (170, 180) are positioned on the upper source / drain patterns (150U1, 150U2). The front source / drain contacts (170, 180) include a first front source / drain contact 170 connected to the upper source / drain pattern 150U1 and the lower source / drain pattern 150B1, and a second front source / drain contact 180 connected to the upper source / drain pattern 150U2 and the lower source / drain pattern 150B2. The average grain size of the first front source / drain contact 170 is greater than the average grain size of the second front source / drain contact 180.

[0045] For example, the lower source / drain patterns (150B1, 150B2) include a first lower source / drain pattern 150B1 and a second lower source / drain pattern 150B2 that are different from each other; the upper source / drain patterns (150U1, 150U2) include a first upper source / drain pattern 150U1 on the first lower source / drain pattern 150B1 and a second source / drain pattern 150U2 on the second lower source / drain pattern 150B2; and the front source / drain contacts (170, 180) include a first front source / drain contact 170 connected to the first upper source / drain pattern 150U1 and the first lower source / drain pattern 150B1, and a second front source / drain contact 180 connected to the second upper source / drain pattern 150U2.

[0046] The first front source / drain contact 170 is positioned on the upper surface of the back interlayer insulating film 290. The first front source / drain contact 170 is extended to the third direction DR3. The first front source / drain contact 170 extends into the first upper source / drain pattern 150U1, the lower front interlayer insulating film 190B, and the first lower source / drain pattern 150B1. The first front source / drain contact 170 is located within the upper front interlayer insulating film 190U, the first upper source / drain pattern 150U1, the lower front interlayer insulating film 190B, and the first lower source / drain pattern 150B1. A portion of the first front source / drain contact 170 is located within the first lower source / drain pattern 150B1. The first front source / drain contact 170 is superimposed on the upper channel pattern UNS in the first direction DR1.

[0047] The first front source / drain contact 170 is electrically connected to the first upper source / drain pattern 150U1 and the first lower source / drain pattern 150B1. The first upper source / drain pattern 150U1 and the first lower source / drain pattern 150B1 are electrically connected by the first front source / drain contact 170. The first upper contact silicide film 155U is positioned between the first front source / drain contact 170 and the first upper source / drain pattern 150U1. The first upper contact silicide film 155U is in contact with the first front source / drain contact 170. The first lower contact silicide film 155B is positioned between the first front source / drain contact 170 and the first lower source / drain pattern 150B1. The first lower contact silicide film 155B is in contact with the first front source / drain contact 170.

[0048] The second front source / drain contact 180 is positioned on the upper surface of the back interlayer insulating film 290. The second front source / drain contact 180 is directed towards the third direction DR3. The second front source / drain contact 180 is extended into the second upper source / drain pattern 150U2. The second front source / drain contact 180 is located within the upper front interlayer insulating film 190U and the second upper source / drain pattern 150U2. A portion of the first front source / drain contact 170 is located within the second upper source / drain pattern 150U2. The second front source / drain contact 180 is electrically connected to the second upper source / drain pattern 150U2. At least a portion of the second front source / drain contact 180 overlaps the upper channel pattern UNS and the first direction DR1.

[0049] The second upper contact silicide film 156U is positioned between the second front source / drain contact 180 and the second upper source / drain pattern 150U2. The second upper contact silicide film 156U is in contact with the second front source / drain contact 180. The first and second front source / drain contacts (170, 180) are shown as having a single conductive film structure, but are not limited to this. In one embodiment, the first and second front source / drain contacts (170, 180) may each have a multi-layer conductive film structure including a front contact barrier film and a front contact filling film.

[0050] The first and second front source / drain contacts (170, 180) may each include at least one of, for example, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material. The first upper contact silicide film 155U and the second upper contact silicide film 156U each contain a metal silicide material. In one embodiment, the first and second front source / drain contacts (170, 180) do not contain any seams or voids inside each other.

[0051] The front insulating film 191 is positioned on the upper front interlayer insulating film 190U, the gate structure GS, the first front source / drain contact 170, and the second front source / drain contact 180. The front insulating film 191 may include, for example, at least one of silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and low dielectric constant material.

[0052] The front wiring structure 195 is placed within the front insulating film 191. The front wiring structure 195 includes front via plugs 196 and front wiring lines 197. The front wiring structure 195 is electrically connected to the first and second front source / drain contacts (170, 180). The first front source / drain contact 170 is positioned between the front wiring structure 195 and the first lower source / drain pattern 150B1. The first front source / drain contact 170 electrically connects the first lower source / drain pattern 150B1 and the first upper source / drain pattern 150U1 to the front wiring structure 195. The second front source / drain contact 180 is positioned between the front wiring structure 195 and the second upper source / drain pattern 150U2. The second front source / drain contact 180 electrically connects the front wiring structure 195 and the second upper source / drain pattern 150U2. The first and second front source / drain contacts (170, 180) are electrically connected to different front wiring lines 197.

[0053] The front via plug 196 and the front wiring line 197 may each include at least one of, for example, metal, conductive metal nitride, conductive metal carbide, conductive metal oxide, conductive metal carbonitride, and two-dimensional material. The front via plug 196 and front wiring line 197 are shown as single conductive film structures, but are not limited to these. In one embodiment, for example, at least one of the front via plug 196 and the front wiring line 197 has a multi-layer conductive film structure including a barrier film and a filling film. As another example, the front wiring structure 195 may have an integral structure in which there is no distinction of an interface between the front via plugs 196 and the front wiring lines 197.

[0054] In one embodiment, the sacrificial pattern 150PH is located below the first lower source / drain pattern 150B1. The first lower source / drain pattern 150B1 is positioned on the sacrificial pattern 150PH. The sacrificial pattern 150PH is placed within the insulating pattern 290P. Sacrificial pattern 150PH contains semiconductor material.

[0055] The second back-side source / drain contact 80 is located between the second lower source / drain pattern 150B2 and the back-side wiring line 50. The second back-side source / drain contact 80 is superimposed on the second lower source / drain pattern 150B2 and the third direction DR3. The second back-side source / drain contact 80 is extended in the third direction DR3. The second back-side source / drain contact 80 is electrically connected to the second lower source / drain pattern 150B2. The second rear source / drain contact 80 electrically connects the second lower source / drain pattern 150B2 to the rear wiring line 50. The second rear source / drain contact 80 is electrically connected to the rear wiring line 50. The second lower source / drain pattern 150B2, which is not connected to the first front source / drain contact 170, is electrically connected to the rear wiring line 50. The second back surface source / drain contact 80 is located within the back surface interlayer insulating film 290 and the second lower source / drain pattern 150B2. A portion of the second back-side source / drain contact 80 is located within the second lower source / drain pattern 150B2.

[0056] The second lower contact silicide film 156B is positioned between the second back surface source / drain contact 80 and the second lower source / drain pattern 150B2. The second lower contact silicide film 156B is in contact with the second back surface source / drain contact 80. The second back surface source / drain contact 80 is shown as having a single conductive film structure, but is not limited to this. In one embodiment, the second back-surface source / drain contact 80 may have a multi-conductive film structure. The second back surface source / drain contact 80 may include, for example, at least one of metals, conductive metal nitrides, conductive metal carbides, conductive metal oxides, conductive metal carbonitrides, and two-dimensional materials. The second lower contact silicide film 156B contains a metal silicide material.

[0057] The first back surface insulating film 291, the second back surface insulating film 292, and the third back surface insulating film 293 are arranged on the back surface interlayer insulating film 290. The first back-surface insulating film 291, the second back-surface insulating film 292, and the third back-surface insulating film 293 are sequentially arranged on the bottom surface of the back-surface interlayer insulating film 290. The first back-surface insulating film 291, the second back-surface insulating film 292, and the third back-surface insulating film 293 may each contain at least one of the following materials: silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and low dielectric constant material. The first back surface insulating film 291, the second back surface insulating film 292, and the third back surface insulating film 293 are shown as single layers, but are not limited to this.

[0058] The back surface connection contact 60 is located within the first back surface insulating film 291. The back-side connection contact 60 is electrically connected to the second back-side source / drain contact 80. The second back-side source / drain contact 80 is positioned between the back-side connection contact 60 and the second lower source / drain pattern 150B2. The back-side connection via 55 is located within the second back-side insulating film 292. The rear-side connection via 55 is electrically connected to the rear-side connection contact 60. The back-side connection contact 60 is positioned between the back-side connection via 55 and the second back-side source / drain contact 80. Rear-side connection via 55 is electrically connected to the second lower source / drain pattern 150B2. The back-side connection vias 55 and back-side connection contacts 60 are shown as having a single conductive film structure, but are not limited to this. In one embodiment, at least one of the back-side connection vias 55 and the back-side connection contacts 60 may have a multi-layer conductive film structure. The back-side connection vias 55 and back-side connection contacts 60 may each include at least one of, for example, metal, conductive metal nitride, conductive metal carbide, conductive metal oxide, conductive metal carbonitride, and two-dimensional material.

[0059] The back surface wiring line 50 is located within the third back surface insulating film 293. For example, the rear wiring line 50 is extended in the first direction DR1. For example, the back-side wiring line 50 is a power line that supplies power to the semiconductor device. As another example, the back-side wiring line 50 could be a signal line that supplies operating signals for the semiconductor device. The rear wiring line 50 includes a first surface (50_S1) and a second surface (50_S2) facing the third direction DR3. The lower channel pattern BNS, the upper channel pattern UNS, and the gate electrode 120 are arranged on the second side (50_S2) of the back surface wiring line 50. The second backside source / drain contact 80 is connected to the second side (50_S2) of the backside wiring line 50. The back-side wiring line 50 is shown as having a single conductive film structure, but is not limited to this. In one embodiment, the back wiring line 50 may have a multi-layer conductive film structure including a wiring barrier film and a wiring filling film. In such cases, the wiring filling film fills the wiring filling film trench defined by the wiring barrier film.

[0060] The back surface wiring line 50 may include, for example, at least one of metal, conductive metal nitride, conductive metal carbide, conductive metal oxide, conductive metal carbonitride, and two-dimensional material. A two-dimensional material (2D material) may include a two-dimensional allotrope or a two-dimensional compound, and may include, but is not limited to, at least one of graphene, boron nitride (BN), molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, or tantalum sulfide. In other words, since the two-dimensional materials described above are merely listed, the two-dimensional materials that may be included in the semiconductor device of the present invention are not limited to those described above.

[0061] In one embodiment, the rear wiring line 50 is extended in the second direction DR2. In such cases, the shapes of the cross-sectional views obtained by cutting along lines A-A', B-B', and C-C' in Figure 1 may differ. In one embodiment, the rear wiring line 50 includes a line portion and a via portion. The line portion of the rear wiring line 50 is extended in the first direction DR1. The via portion of the rear wiring line 50 protrudes from the line portion of the rear wiring line 50 in the third direction DR3. The via portion of the rear wiring line 50 protrudes toward the second rear source / drain contact 80. In one embodiment, at least one of the back-side connection contacts 60 and back-side connection vias 55 is not located between the second back-side source / drain contact 80 and the back-side wiring line 50.

[0062] Figures 5 to 8 are cross-sectional views showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. For reference, Figures 5 to 8 are cross-sectional views taken along the line A-A' in Figure 1. For the sake of clarity, this explanation will focus on the differences from what was explained using Figures 1 to 4.

[0063] Referring to Figures 5 and 6, in a semiconductor device according to an embodiment of the present invention, the first front source / drain contact 170 includes at least one first seam 170S internally. The first seam 170S has a first size W1 in the third direction DR3. For example, the first front source / drain contact 170 includes a plurality of first seams 170S internally, spaced apart in a third direction DR3. Another example is the first front source / drain contact 170, which includes a first seam 170S inside.

[0064] Referring to Figure 5, in one embodiment, the second front source / drain contact 180 does not have a seam inside. Referring to Figure 6, in one embodiment, the second front source / drain contact 180 includes at least one second seam 180S internally. The second seam 180S has a second size W2 in the third direction DR3. Referring to Figure 7, in one embodiment of the semiconductor device, the sacrificial pattern (150PH in Figure 2) is omitted. The first lower source / drain pattern 150B1 is located on the insulating pattern 290P.

[0065] Referring to Figure 8, the semiconductor device according to an embodiment of the present invention further includes a first back-side source / drain contact 70. The first rear-side source / drain contact 70 is positioned between the first lower source / drain pattern 150B1 and the rear-side wiring line 50. The first back-side source / drain contact 70 is superimposed on the first lower source / drain pattern 150B1 and the third direction DR3. The first back-side source / drain contact 70 is extended in the third direction DR3. The first back-side source / drain contact 70 is electrically connected to the first lower source / drain pattern 150B1. The first rear source / drain contact 70 is not electrically connected to the rear wiring line 50. The first lower source / drain pattern 150B1, which is connected to the first front source / drain contact 170, is not electrically connected to the rear wiring line 50. The second lower contact silicide film 156B is positioned between the first back surface source / drain contact 70 and the first lower source / drain pattern 150B1. The second lower contact silicide film 156B is in contact with the first back surface source / drain contact 70.

[0066] Figures 9 to 27 are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. For the sake of clarity, this explanation will focus on the differences from what was explained using Figures 1 to 4. For reference, Figure 24 is an enlarged view of the X region in Figure 23, and Figure 26 is an enlarged view of the X1 region in Figure 25.

[0067] Referring to Figures 9 and 10, a lower laminated structure 10, an intermediate insulating pattern 115, and an upper laminated structure 20 are formed on the substrate 100. The lower laminated structure 10, the intermediate insulating pattern 115, and the upper laminated structure 20 are sequentially laminated on the substrate 100 along the third direction DR3. The lower laminated structure 10, the intermediate insulating pattern 115, and the upper laminated structure 20 are extended in the first direction DR1. The lower laminated structure 10 includes a first lower semiconductor layer 11 and a second lower semiconductor layer 12 that are alternately stacked on the substrate 100 along the third direction DR3. The upper stacked structure 20 includes a first upper semiconductor layer 21 and a second upper semiconductor layer 22 that are alternately stacked along the third direction DR3. An intermediate insulating pattern 115 is formed between the lower laminated structure 10 and the upper laminated structure 20.

[0068] The substrate 100 is made of bulk silicon or SOI (silicon-on-insulator). In contrast, the substrate 100 may be a silicon substrate, or may contain, but is not limited to, other materials such as silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead tellurium compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The first lower semiconductor layer 11 and the first upper semiconductor layer 21 contain a material having an etching selectivity ratio with respect to the second lower semiconductor layer 12 and the second upper semiconductor layer 22. For example, the second lower semiconductor layer 12 and the second upper semiconductor layer 22 each contain silicon, and the first lower semiconductor layer 11 and the first upper semiconductor layer 21 each contain silicon germanium. In one embodiment, a fin pattern 110 is formed between the substrate 100 and the lower laminated structure 10. The fin pattern 110 is extended in the first direction DR1. In one embodiment, a field insulating film 105 is formed that covers at least a portion of the side surface of the fin pattern 110.

[0069] Referring to Figures 11 to 13, a dummy gate insulating film 31, a dummy gate electrode 32, and a dummy capping pattern 33 are formed on the upper stacked structure 20. The dummy gate electrode 32 extends in the second direction DR2 and is separated in the first direction DR1. The dummy gate insulating film 31 is formed between the dummy gate electrode 32 and the upper stacked structure 20. The dummy capping pattern 33 is formed on the dummy gate electrode 32.

[0070] For example, an insulating film is formed along the upper surface of the field insulating film 105, the side walls of the fin pattern 110 protruding from the field insulating film 105, the side walls of the lower laminated structure 10, the side walls of the intermediate insulating pattern 115, and the side walls and upper surface of the upper laminated structure 20. A conductive film is formed on the insulating film, and a dummy capping pattern 33 is formed on the upper laminated structure 20 and the conductive film on the field insulating film 105, extending in the second direction DR2. Using the dummy capping pattern 33 as a mask, the insulating film and conductive film are patterned to form the dummy gate insulating film 31 and the dummy gate electrode 32. The dummy gate insulating film 31 includes, for example, silicon oxide, but is not limited to this. The dummy gate electrode 32 may include, for example, polysilicon, but is not limited to this. The dummy capping pattern 33 includes, for example, silicon nitride, but is not limited to this.

[0071] Referring to Figures 14 and 15, a dummy capping pattern 33 is formed on the side wall of the dummy gate electrode 32 and on the upper laminated structure 20. The spare gate spacer 140P extends along the sidewall of the dummy gate insulating film 31, the sidewall of the dummy gate electrode 32, and the sidewall of the dummy capping pattern 33. Next, using the dummy gate electrode 32, dummy capping pattern 33, and spare gate spacer 140P as masks, a plurality of first recesses R1 are formed within the upper laminated structure (reference numeral 20 in Figures 11-13), the intermediate insulating pattern 115, and the lower laminated structure (reference numeral 10 in Figures 11-13). The first recess R1 is formed between adjacent dummy gate electrodes 32. The first recess R1 separates the second lower semiconductor layer 12, forming the lower channel pattern BNS, and the second upper semiconductor layer 22 separates, forming the upper channel pattern UNS. Next, a second recess R2 is formed below the first recess R1. The second recess R2 is formed within the fin pattern 110 (for example, by extending inward). For example, in the first direction DR1, the size of the second recess R2 is smaller than the size of the first recess R1, but this is not limited to this.

[0072] Referring to Figures 16 and 17, a sacrificial pattern 150PH is formed in the second recess (labeled R2 in Figures 14 and 15), and a lower source / drain pattern (150B1, 150B2), a lower source / drain etching stop film 185B, a lower front interlayer insulating film 190B, and an upper source / drain pattern (150U1, 150U2) are formed in the first recess (R1 in Figure 14). An upper source / drain etching stop film 185U and an upper front interlayer insulating film 190U are formed on the upper source / drain patterns (150U1, 150U2). The lower source / drain patterns (150B1, 150B2) include a first lower source / drain pattern 150B1 and a second lower source / drain pattern 150B2, which are formed within different first recesses (R1 in Figure 14). The upper source / drain patterns (150U1, 150U2) include the first upper source / drain pattern 150U1 on the first lower source / drain pattern 150B1 and the second lower source / drain pattern 150B2 on the second lower source / drain pattern 150B2.

[0073] The sacrificial pattern 150PH is formed by an epitaxial growth process. The sacrificial pattern 150PH is grown, for example, from substrate 100 using a bottom-up method. The lower source / drain patterns (150B1, 150B2) are formed on the sacrificial pattern 150PH. The lower source / drain patterns (150B1, 150B2) are formed on the sidewalls of the lower channel pattern BNS and the sidewalls of the first lower semiconductor layer 11. The lower source / drain patterns (150B1, 150B2) are in contact with the lower channel pattern BNS. For example, the lower source / drain patterns (150B1, 150B2) are formed by an epitaxial growth process using at least one of the lower sacrificial pattern 150PH and the lower channel pattern BNS exposed by the first recess (R1 in Figure 14) as a seed layer. In one embodiment, the second recess R2 and the sacrificial pattern 150PH may not be formed.

[0074] The lower source / drain patterns (150B1, 150B2) contain p-type dopants. For example, in the process of forming the lower source / drain patterns (150B1, 150B2), the p-type dopant is injected in situ. Another example involves forming the lower source / drain patterns (150B1, 150B2) and then injecting a p-type dopant into them. The lower source / drain etching stop film 185B is formed along the upper surface and lower source / drain pattern (150B1, 150B2) of the field insulating film 105. The lower front interlayer insulating film 190B is formed on the lower source / drain etching stop film 185B. The upper surface of the lower interlayer insulating film 190B is substantially coplanar with the upper surface of the intermediate insulating pattern 115, but is not limited to this.

[0075] The upper source / drain patterns (150U1, 150U2) are formed on the lower front interlayer insulating film 190B. The lower front interlayer insulating film 190B is positioned between the upper source / drain patterns (150U1, 150U2) and the lower source / drain patterns (150B1, 150B2). The upper source / drain patterns (150U1, 150U2) are formed on the sidewalls of the upper channel pattern UNS and the sidewalls of the first upper semiconductor layer 21. The upper source / drain patterns (150U1, 150U2) are in contact with the upper channel pattern UNS. For example, the upper source / drain patterns (150U1, 150U2) are formed by an epitaxial growth process using the upper channel pattern UNS, exposed by the first recess (indicated R1 in Figure 14), as a seed layer.

[0076] The upper source / drain patterns (150U1, 150U2) contain n-type dopants. For example, in the process of forming the upper source / drain patterns (150U1, 150U2), an n-type dopant is injected in situ. Another example involves forming an upper source / drain pattern (150U1, 150U2) and then injecting an n-type dopant into the upper source / drain pattern (150U1, 150U2). The upper source / drain etching stop film 185U is formed along the upper surface of the upper source / drain patterns (150U1, 150U2) and the lower front interlayer insulating film 190B. The upper front interlayer insulating film 190U is formed on the upper source / drain etching stop film 185U. Next, a portion of the upper source / drain etching stop film 185U, a portion of the upper front interlayer insulating film 190U, and the dummy gate capping pattern (reference numeral 33 in Figure 14) are removed to expose the upper surface of the dummy gate electrode 32. The gate spacer 140 is formed while the upper surface of the dummy gate electrode 32 is exposed. The upper surface of the upper interlayer insulating film 190U is substantially coplanar with the upper surface of the dummy gate electrode 32, but is not limited to this.

[0077] Referring to Figures 18 and 19, the dummy gate insulating film (reference numeral 31 in Figure 16), the dummy gate electrode (reference numeral 32 in Figure 16), the first lower semiconductor layer (reference numeral 11 in Figure 16), and the first upper semiconductor layer (reference numeral 21 in Figure 16) are removed to form a gate trench GT.

[0078] Referring to Figures 20 and 21, the gate insulating film 130 and the gate electrode 120 are sequentially formed in the gate trench (indicated as GT in Figure 18). This forms a gate structure GS that surrounds the lower channel pattern BNS and the upper channel pattern UNS. Next, a gate capping pattern 145 is formed to cover the upper surface of the gate electrode 120.

[0079] Referring to Figure 22, a first contact hole 170H and a second contact hole 180H are formed. The first contact hole 170H and the second contact hole 180H expose different upper source / drain patterns (150U1, 150U2), respectively. The bottom surfaces of the first contact hole 170H and the second contact hole 180H are positioned below the top surface of the upper channel pattern UNS. The first contact hole 170H is extended in the third direction DR3. The first contact hole 170H extends into the upper interlayer insulating film 190U, the first upper source / drain pattern 150U1, the lower interlayer insulating film 190B, the lower source / drain etching stop film 185B, and the first lower source / drain pattern 150B1. The bottom surface of the first contact hole 170H is located within the first lower source / drain pattern 150B1. The first contact hole 170H penetrates the upper interlayer insulating film 190U, the upper source / drain etching stop film 185U, the first upper source / drain pattern 150U1, the lower interlayer insulating film 190B, the lower source / drain etching stop film 185B, and a portion of the first lower source / drain pattern 150B1. The first upper source / drain pattern 150U1 and the first lower source / drain pattern 150B1 are exposed through the first contact hole 170H.

[0080] The second contact hole 180H is extended in the third direction DR3. The second contact hole 180H extends into the upper interlayer insulating film 190U and the second upper source / drain pattern 150U2. The bottom surface of the second contact hole 180H is located within the second upper source / drain pattern 150U2. The second contact hole 180H penetrates the upper interlayer insulating film 190U, the upper source / drain etching stop film 185U, and a portion of the second upper source / drain pattern 150U2. The second upper source / drain pattern 150U2 is exposed through the second contact hole 180H.

[0081] Referring to Figures 23 and 24, a contact film 175 is formed in the first contact hole 170H and the second contact hole 180H. The contact film 175 covers the upper surface of the gate capping pattern 145. The contact film 175 is conformally formed along the first contact hole 170H and the second contact hole 180H. The contact film 175 fills at least a portion of the first contact hole 170H and the second contact hole 180H, respectively. The contact film 175 extends along the upper surface of the gate capping pattern 145. The contact film 175 contains a metallic substance that is conformally deposited. The contact film 175 may contain, for example, molybdenum, tungsten, and the like.

[0082] The contact film 175 within the first contact hole 170H contains at least one first seam 171S internally. The first seam 171S is formed by the process of forming the contact film 175. The first seam 171S has a third size W3 in the third direction DR3. The contact film 175 within the first contact hole 170H contains a plurality of first crystal grains G1. A first upper contact silicide film 155U is formed between the contact film 175 and the first upper source / drain pattern 150U1, a first lower contact silicide film 155B is formed between the contact film 175 and the first lower source / drain pattern 150B1, and a second upper contact silicide film 156U is formed between the contact film 175 and the second upper source / drain pattern 150U2.

[0083] Referring to Figures 25 and 26, an annealing process is performed on the contact film 175 within the first contact hole 170H. In one embodiment, the annealing process includes a hydrogen radical annealing process, such as a plasma annealing process in a hydrogen atmosphere. The hydrogen radical annealing process is carried out under conditions that provide a temperature of 400°C to 450°C, a time of 5 minutes to 30 minutes, and a power of 4.5kV to 7.5kV. The annealing process may also include low-temperature soak annealing, flash lamp annealing, laser annealing, spike annealing, and / or rapid thermal annealing.

[0084] In one embodiment, the first seam (reference numeral 171S in Figures 23 and 24) of the contact film 175 in the first contact hole 170H is removed by an annealing process. Furthermore, the annealing process causes the first crystal grain (indicated as G1 in Figure 24) of the contact film 175 within the first contact hole 170H to grow, forming the second crystal grain G2. The first crystal grain (G1 in Figure 24) merges to form the second crystal grain G2. The average size of the second crystal grain of the contact film 175 in the first contact hole 170H in Figure 26 is greater than the average size of the first crystal grain of the contact film 175 in the first contact hole 170H in Figure 24. For example, the average size of the first crystal grains represents the average of the maximum sizes of each first crystal grain G1 in Figure 24, and the average size of the second crystal grains represents the average of the maximum sizes of each second crystal grain G2 in Figure 26. The first crystal grain G1 in Figure 24 and the second crystal grain G2 in Figure 26 can be analyzed, for example, by transmission electron microscopy (TEM) or PED (Precession electron diffraction) analysis.

[0085] Referring to Figure 27, a planarization process is performed on the contact film (175 in Figures 25 and 26) to form the first front source / drain contact 170 and the second front source / drain contact 180. The first front source / drain contact 170 fills the first contact hole 170H, and the second front source / drain contact 180 fills the second contact hole 180H. The contact film 175 filling the first contact hole 170H in Figures 25 and 26 is defined as the first front source / drain contact 170 in Figure 27, and the contact film 175 filling the second contact hole 180H in Figures 25 and 26 is defined as the second front source / drain contact 180 in Figure 27. Therefore, in one embodiment, the first front source / drain contact 170 does not contain internal seams due to the annealing process described with reference to Figures 25 and 26.

[0086] The average size of the second crystal grain of the first front source / drain contact 170 is the same as the average size of the second crystal grain of the contact film 175 in the first contact hole 170H in Figure 26. In other words, the average size of the second crystal grain of the first front source / drain contact 170 is greater than the average size of the first crystal grain of the contact film 175 in the first contact hole 170H in Figure 24. In one embodiment, the average size of the second crystal grains of the first front source / drain contact 170 may be larger than the average size of the crystal grains of the second front source / drain contact 180.

[0087] Referring to Figures 2 to 4, a front insulating film 191 and a front wiring structure 195 are formed on the gate capping pattern 145, the first front source / drain contact 170, and the second front source / drain contact 180, respectively. The front wiring structure 195 is connected to the first and second front source / drain contacts (170, 180). Remove the substrate (reference numeral 100 in Figure 27) and the fin pattern (reference numeral 110 in Figure 27). This exposes the gate structure GS, the lower source / drain patterns (150B1, 150B2), and the sacrificial pattern 150PH. An insulating pattern 290P and a back surface interlayer insulating film 290 are formed on the gate structure GS, the lower source / drain patterns (150B1, 150B2), and the sacrificial pattern 150PH. A first back surface source / drain contact 70 is formed within the back surface interlayer insulating film 290 and the insulating pattern 290P.

[0088] The etching process exposes the sacrificial pattern (labeled 150PH in Figure 27) at the bottom of the second lower source / drain pattern 150B2. Remove the exposed second sacrificial pattern (labeled 150PH in Figure 27) to expose the second lower source / drain pattern 150B2. Next, a second back surface source / drain contact 80 is formed, which is connected to the second lower source / drain pattern 150B2. A first back surface insulating film 291 and a back surface connection contact 60 are formed on the back surface interlayer insulating film 290 and within the first back surface insulating film 291. The back-side connection contact 60 is connected to the second back-side source / drain contact 80. A second back insulating film 292 and a back connecting via 55 are formed on the first back insulating film 291 and the back connecting contact 60, respectively. The rear-side connection via 55 is connected to the rear-side connection contact 60. Next, a third back-surface insulating film 293 and a back-surface wiring line 50 are formed on the second back-surface insulating film 292 and the back-surface connecting via 55. The rear wiring line 50 is connected to the second rear source / drain contact 80.

[0089] Referring to Figures 9 to 27, if a seam is present inside the first front source / drain contact 170, the seam increases the resistance of the first front source / drain contact 170. Furthermore, the stress applied to the first front source / drain contact 170 and the adjacent upper channel pattern UNS is reduced, thereby decreasing the channel performance of the upper channel pattern UNS used as the channel region of the NMOS. However, the method for manufacturing a semiconductor device according to an embodiment of the present invention includes an annealing step performed on the contact film 175 in the first contact hole 170H, for example, a hydrogen radical annealing step. The annealing process removes the first seam 171S, forming a first front source / drain contact 170 containing a relatively larger second crystal grain G2. Therefore, the resistance of the first front source / drain contact 170 can be improved and / or reduced, tensile stress can be applied to the upper channel pattern UNS, and the channel performance of the upper channel pattern UNS used as the channel region of the NMOS can be improved and / or enhanced. This makes it possible to provide semiconductor devices with improved and / or enhanced performance.

[0090] Figure 28 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. For the sake of clarity, this explanation will focus on the differences from the explanation given using Figures 1 to 27. For reference, Figure 28 is an enlarged view of the X1 region in Figure 25.

[0091] Referring to Figures 25 and 28, an annealing process is performed on the contact film 175 within the first contact hole 170H. In one embodiment, the annealing process reduces the size of the first seam (reference numeral 171S in Figures 23 and 24) of the contact film 175 within the first contact hole 170H, and at least one first seam 170S is formed. The first size W1 of the first seam 170S in the third direction DR3 is smaller than the third size (W3 in Figure 23) of the first seam (reference numeral 171S in Figures 23 and 24) in the third direction DR3. If multiple first seams 170S are formed, the first seams 170S are separated, for example, in a third direction DR3. Furthermore, when multiple first seams 170S are formed, the first size W1 of each first seam 170S in the third direction DR3 is smaller than the third size (W3 in Figure 23) of the first seam (reference numeral 171S in Figures 23 and 24) in the third direction DR3.

[0092] Next, referring to Figure 5, a planarization process is performed on the contact film (175 in Figures 25 and 26) to form the first front source / drain contact 170 and the second front source / drain contact 180. The contact film 175 filling the first contact hole 170H in Figures 25 and 28 is defined as the first front source / drain contact 170 in Figure 5, and the contact film 175 filling the second contact hole 180H in Figure 25 is defined as the second front source / drain contact 180 in Figure 5. Therefore, in one embodiment, the first front source / drain contact 170 includes at least one first seam 170S internally.

[0093] The average size of the second crystal grain of the first front source / drain contact 170 is the same as the average size of the second crystal grain of the contact film 175 in the first contact hole 170H in Figure 28. In other words, the average size of the second crystal grain of the first front source / drain contact 170 is greater than the average size of the first crystal grain of the contact film 175 in the first contact hole 170H in Figure 24. Next, as explained using Figures 2 to 4 above, a front insulating film 191 and a front wiring structure 195 are formed, the substrate (reference numeral 100 in Figure 25) and fin pattern (reference numeral 110 in Figure 25) are removed, and an insulating pattern 290P, a back interlayer insulating film 290, a second back source / drain contact 80, a first back insulating film 291, a back connection contact 60, a second back insulating film 292, a back connection via 55, a third back insulating film 293, and a back wiring line 50 are formed.

[0094] Figure 29 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. For the sake of explanation, this explanation will focus on the differences from what was explained using Figures 1 to 28. For reference, Figure 29 shows the manufacturing process that proceeds from Figure 22 onward.

[0095] Referring to Figure 29, a contact film 175 is formed in the first contact hole 170H and the second contact hole 180H. The contact film 175 conformally extends along the upper surface of the first contact hole 170H, the second contact hole 180H, and the gate capping pattern 145. In one embodiment, the contact film 175 within the second contact hole 180H includes at least one second seam 172S internally. The second seam 172S is formed during the process of forming the contact film 175. The second seam 172S has a third direction DR3 and a fourth size W4.

[0096] Next, referring to Figure 6, in one embodiment, an annealing process is performed on the contact film (reference numeral 175 in Figure 29) in the first contact hole (reference numeral 170H in Figure 29) and the contact film (reference numeral 175 in Figure 29) in the second contact hole (reference numeral 180H in Figure 29). Next, a planarization process is performed on the contact film (175 in Figure 29) to form the first front source / drain contact 170 and the second front source / drain contact 180. The contact film 175 filling the first contact hole H1 in Figure 29 is defined as the first front source / drain contact 170 in Figure 6, and the contact film 175 filling the second contact hole 170H in Figure 29 is defined as the second front source / drain contact 180 in Figure 6.

[0097] The above annealing process reduces the size of the second seam (reference numeral 172S in Figure 29) of the contact film (reference numeral 175 in Figure 29) within the second contact hole (reference numeral 180H in Figure 29), and at least one second seam 180S is formed. The second size W2 of the second seam 180S in the third direction DR3 is smaller than the fourth size (indicated as W4 in Figure 29) of the second seam (indicated as 172S in Figure 29) in the third direction DR3. If multiple second seams 180S are formed, the second seams 180S are separated, for example, in a third direction DR3. Furthermore, when multiple second seams 180S are formed, the second size W2 of each second seam 180S in the third direction DR3 is smaller than the fourth size (W4 in Figure 29) of the second seam (172S in Figure 29) in the third direction DR3.

[0098] Furthermore, the annealing process described above causes the first crystal grains of the contact film (reference numeral 175 in Figure 29) within the second contact hole (reference numeral 180H in Figure 29) to grow, forming the second crystal grains. The average size of the second crystal grain of the second front source / drain contact 180 in Figure 6 is greater than the average size of the first crystal grain of the contact film 175 in the second contact hole 180H in Figure 29. For example, the average size of the first crystal grains refers to the average of the maximum sizes of each first crystal grain in the contact film 175 within the second contact hole 180H in Figure 29, and the average size of the second crystal grains refers to the average of the maximum sizes of each second crystal grain in the second front source / drain contact 180 in Figure 6. Next, as explained using Figures 2 to 4 above, a front insulating film 191 and a front wiring structure 195 are formed, the substrate (reference numeral 100 in Figure 29) and fin pattern (reference numeral 110 in Figure 29) are removed, and an insulating pattern 290P, a back interlayer insulating film 290, a second back source / drain contact 80, a first back insulating film 291, a back connection contact 60, a second back insulating film 292, a back connection via 55, a third back insulating film 293, and a back wiring line 50 are formed.

[0099] Figure 30 is an exemplary layout diagram illustrating a semiconductor device according to an embodiment of the present invention, Figure 31 is a cross-sectional view taken along the line D-D' in Figure 30, and Figure 32 is a cross-sectional view taken along the line E-E' in Figure 30. For the sake of clarity, this explanation will focus on the differences from what was explained using Figures 1 to 8.

[0100] Referring to Figures 30 to 32, the semiconductor device according to an embodiment of the present invention includes a first region I and a second region II. The first region I and the second region II may be adjacent to each other, or they may be separated from each other. Domain 1 I and Domain 2 II may be domains that perform the same function, or they may be domains that perform different functions. In one embodiment, the first front source / drain contact 170 located in the first region I does not contain a seam internally, and the first front source / drain contact 170 located in the second region II includes at least one first seam 170S internally. In the first region I, the stress applied to the upper channel pattern UNS adjacent to the first front source / drain contact 170 is different from the stress applied to the upper channel pattern UNS adjacent to the first front source / drain contact 170 in the second region II.

[0101] For example, in the first region I, the stress applied to the upper channel pattern UNS adjacent to the first front source / drain contact 170 is greater than the stress applied to the upper channel pattern UNS adjacent to the first front source / drain contact 170 in the second region II. In the first region I, the upper channel pattern UNS adjacent to the first front source / drain contact 170 and in the second region II, the upper channel pattern UNS adjacent to the first front source / drain contact 170 differ from each other in at least one of the grid plane spacing (d-spacing) (i.e., pitch) and deformation rate. The grid plane spacing and deformation rate are analyzed using GPA (Geometric Phase Analysis). The average size of the crystal grains of the first front source / drain contact 170 located in the first region I and the first front source / drain contact 170 located in the second region II may be the same or different from each other.

[0102] In one embodiment, the first front source / drain contact 170 located in the first region I and the first front source / drain contact 170 located in the second region II do not contain any seams inside. In one embodiment, the first front source / drain contact 170 located in the first region I and the first front source / drain contact 170 located in the second region II each include at least one first seam 170S internally. In this case, the arrangement, number, size, etc., of the first seams 170S included in the first front source / drain contact 170 located in the first region I and the first front source / drain contact 170 located in the second region II may be the same or different.

[0103] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of Symbols]

[0104] 50 Rear wiring lines 55 Rear-side connection vias 60 Rear-side connection contacts 80 Second backside source / drain contact 115 Intermediate Insulation Pattern 120 gates 130 Gate Insulator 140 Gate Spacer 145 Gate capping patterns 150B1, 150B2 (1st, 2nd) Lower Source / Drain Pattern 150U1, 150U2 (1st, 2nd) Upper Source / Drain Pattern 150Ba First lower epitaxial membrane 150Bb Second lower epitaxial membrane 150PH Sacrifice Pattern 150Ua First upper epitaxial film 150Ub Second upper epitaxial membrane 155B First lower contact silicide film 155U First upper contact silicide film 156B Second lower contact silicide film 156U Second upper contact silicide film 170, 180 (1st, 2nd) Front Source / Drain Contacts 170H, 180H (1st and 2nd) contact holes 175 Contact film 180 Second front source / drain contact 185B Lower source / drain etching stop film 185U Upper source / drain etching stop film 190B Lower front interlayer insulating film 190U Upper front interlayer insulating film 191 Front Insulator 195 Front wiring structure 196 Front via plugs 197 Front wiring line 290 Interlayer insulating film on the back surface 290P Insulation Pattern 291 First back surface insulating film 292 Second back-side insulating film BNS Lower Channel Pattern GS Gate Structure UNS Upper Channel Pattern

Claims

1. The steps include providing a lower channel pattern, an intermediate insulating pattern, and an upper channel pattern sequentially stacked vertically on a substrate, The steps include forming a lower source / drain pattern connected to the lower channel pattern, The steps include forming an upper source / drain pattern connected to the upper channel pattern, The steps include forming a gate structure that surrounds the lower channel pattern and the upper channel pattern, The steps include forming the upper source / drain pattern and the contact holes extending within the lower source / drain pattern, The steps include forming a contact film in the contact hole, A method for manufacturing a semiconductor device, comprising the step of performing an annealing process on the contact film to form a front source / drain contact.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that the upper source / drain pattern and the lower source / drain pattern include dopants of different conductivity types.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that the annealing step includes a hydrogen radical annealing step.

4. The contact film includes a seam, The annealing process includes a step of removing the seam, The method for manufacturing a semiconductor device according to claim 1, characterized in that the front source / drain contact does not include the seam.

5. The contact film includes a first seam, The aforementioned front source / drain contact includes a second seam, The method for manufacturing a semiconductor device according to claim 1, characterized in that the size of the second seam in the vertical direction is smaller than the size of the first seam in the vertical direction.

6. The contact film includes a first seam, The aforementioned front source / drain contact includes a plurality of second seams, The method for manufacturing a semiconductor device according to claim 1, characterized in that the vertical size of each of the plurality of second seams is smaller than the vertical size of the first seam.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that the average size of the crystal grains of the contact film is smaller than the average size of the crystal grains of the front source / drain contact.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that the contact film is conformally formed along the contact hole.

9. The process further includes the step of forming a sacrificial pattern within the substrate, The method for manufacturing a semiconductor device according to claim 1, characterized in that the lower source / drain pattern is formed on the sacrificial pattern.

10. The step of removing the substrate to expose the lower channel pattern and the lower source / drain pattern, The steps include forming a back surface interlayer insulating film on the exposed lower channel pattern and the exposed lower source / drain pattern, The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming a backside source / drain contact that penetrates the backside interlayer insulating film and is connected to the lower source / drain pattern.

11. The process further comprises the step of forming a back surface insulating film and back surface wiring lines within the back surface insulating film on the back surface interlayer insulating film, The method for manufacturing a semiconductor device according to claim 10, characterized in that the back surface wiring lines are not electrically connected to the back surface source / drain contacts.

12. The steps include providing a lower channel pattern, an intermediate insulating pattern, and an upper channel pattern sequentially stacked vertically on a substrate, The steps include forming a lower source / drain pattern containing a p-type dopant on the side surface of the lower channel pattern, The steps include forming a lower front interlayer insulating film on the lower source / drain pattern, The steps include forming an upper source / drain pattern containing an n-type dopant on the side surface of the upper channel pattern, Here, the lower front interlayer insulating film is positioned between the lower source / drain pattern and the upper source / drain pattern. The steps include forming an upper front interlayer insulating film on the upper source / drain pattern, The steps include forming a gate structure that surrounds the lower channel pattern and the upper channel pattern, The steps include forming a contact hole that penetrates the upper front interlayer insulating film and exposes the upper source / drain pattern, Here, the bottom surface of the contact hole is positioned below the top surface of the upper channel pattern. The steps include forming a contact film within the contact hole, A method for manufacturing a semiconductor device, characterized by comprising the step of performing an annealing process on the contact film to form a front source / drain contact.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that the annealing step includes a hydrogen radical annealing step.

14. The contact hole further penetrates the upper source / drain pattern and the lower front interlayer insulating film, The method for manufacturing a semiconductor device according to claim 12, characterized in that the lower source / drain pattern is exposed through the contact hole.

15. The contact film includes a seam, The method for manufacturing a semiconductor device according to claim 12, characterized in that the front source / drain contact does not include the seam.

16. The contact film includes a first seam, The aforementioned front source / drain contact includes a second seam, The method for manufacturing a semiconductor device according to claim 12, characterized in that the size of the second seam in the vertical direction is smaller than the size of the first seam in the vertical direction.

17. The method for manufacturing a semiconductor device according to claim 12, characterized in that the average size of the crystal grains of the contact film is smaller than the average size of the crystal grains of the front source / drain contact.

18. The step of providing a lower stacked structure including a first lower semiconductor layer and a second lower semiconductor layer that are alternately stacked vertically on a substrate, The steps include forming an intermediate insulating pattern on the lower laminated structure, The steps include forming an upper laminated structure on the intermediate insulating pattern, which includes a first upper semiconductor layer and a second upper semiconductor layer that are alternately stacked in the vertical direction, The steps include forming a plurality of first recesses that penetrate the lower laminated structure, the intermediate insulating pattern, and the upper laminated structure, The steps include forming a vertically stacked lower source / drain pattern, a lower front interlayer insulating film, and an upper source / drain pattern within each of the plurality of first recesses, Here, the lower source / drain pattern includes a first lower source / drain pattern and a second lower source / drain pattern in different first recesses among the plurality of first recesses, The upper source / drain pattern includes a first upper source / drain pattern on the first lower source / drain pattern and a second upper source / drain pattern on the second lower source / drain pattern. The steps include removing the first lower semiconductor layer and the first upper semiconductor layer to form a gate trench, The steps include forming a gate structure provided within the gate trench, The steps include forming a first contact hole that exposes the first upper source / drain pattern and the first lower source / drain pattern, The steps include forming a second contact hole that exposes the second upper source / drain pattern, The steps include forming a contact film in the first contact hole and the second contact hole, A method for manufacturing a semiconductor device, comprising the steps of performing an annealing process on at least a portion of the contact film to form a first front source / drain contact in the first contact hole and forming a second front source / drain contact in the second contact hole.

19. The contact film includes a seam, The method for manufacturing a semiconductor device according to claim 18, characterized in that the first front source / drain contact and the second front source / drain contact do not include the seam.

20. The contact film includes a first seam, The first front source / drain contact includes a second seam, The method for manufacturing a semiconductor device according to claim 18, characterized in that the second front source / drain contact does not contain a seam.

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