Semiconductor equipment

Abstract

This suppresses current imbalances in multiple semiconductor chips connected in parallel. [Solution] The wiring board 12b is provided with an output portion 12b1 on the short side 11b, and a vertical connection portion 12b4 and a horizontal connection portion 12b3 on the short side 11b that are electrically connected to the output electrodes of semiconductor chips 30a to 30c. In this case, a slit 12b5 is formed in the vertical connection portion 12b4 along the long side 11a from the end on the output portion 12b1 side. As a result, the current output from the semiconductor chip 30a located closest to the terminal junction region 12a6 passes through the vertical connection portion 12b4 and the horizontal connection portion 12b3 before reaching the output portion 12b1 of the wiring board 12b. The difference between this current path and the current path of the current output from the semiconductor chip 30c located furthest from the terminal junction region 12a6 to reach the output portion 12b1 of the wiring board 12b is reduced.

Description

Technical Field

[0004] , , , , , ,

[0003] , , ,

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] The semiconductor device includes a power device and is used as a power conversion device. The power device described in this specification is a switching element. The switching element is, for example, an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device includes a plurality of semiconductor chips including the power device and an insulating circuit board. The insulating circuit board includes an insulating plate and a wiring board formed on the front surface of the insulating plate to which the semiconductor chips are joined. A plurality of semiconductor chips are connected in parallel on the wiring board. Also, the output electrodes of such a plurality of semiconductor chips and another wiring board are electrically connected by wires. A part of such semiconductor chips, the insulating circuit board, the wires, and the external connection terminals is housed in a case and the case is filled with a sealing member (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When multiple semiconductor chips are connected in parallel on a circuit board, current flows through the circuit board along the direction of the arrangement of the semiconductor chips. This current flows sequentially into the input electrodes on the back of each semiconductor chip, and is output from the output electrodes on the front of the semiconductor chip. The output current then flows to another circuit board via wires. In this case, the length of the current path differs for each of the multiple semiconductor chips, and this difference in length results in differences in impedance. As a result, current imbalance occurs among the multiple semiconductor chips. When such current imbalance occurs, the losses in each current path become uneven, hindering the long lifespan of the semiconductor device.

[0005] This invention has been made in view of the above points, and aims to provide a semiconductor device in which current imbalance of multiple semiconductor chips connected in parallel is suppressed. [Means for solving the problem]

[0006] According to one aspect of the present invention, the present invention includes a first arm portion and a second arm portion provided adjacent to the first arm portion, wherein the first arm portion includes a plurality of first semiconductor chips, each having input electrodes on its back surface and output electrodes on its front surface, and a first input wiring board that is rectangular in shape and has a first side, a second side, a third side, and a fourth side in that order and extends parallel to the first side, and a first output wiring board that is disposed on at least one of the first side side and the third side side of the first input wiring board and extends parallel to the first side, and the first input wiring The board comprises a first input region electrically connected to an input terminal and located on the fourth side, and a first chip bonding region located on the second side where the plurality of first semiconductor chips are bonded, and the first output wiring board comprises a first output region electrically connected to a first output terminal on the fourth side, extending along the first or third side toward the second side to a position corresponding to the plurality of first semiconductor chips, and comprising a first connection wiring region on the second side which is electrically connected to the output electrodes of the plurality of first semiconductor chips, and the second The arm portion comprises a second insulating circuit board including a plurality of second semiconductor chips, each having input electrodes on its back surface and output electrodes on its front surface; a second output wiring board that is rectangular in shape and has a fifth, sixth, seventh, and eighth side in that order, extending parallel to the fifth side; and a second input wiring board that is arranged on the fifth and eighth side sides of the second output wiring board and extends parallel to the fifth side. The second input wiring board has a second input region on the sixth side that is electrically connected to the first output region, and the plurality of second semiconductors arranged on the second output wiring board side. A semiconductor device is provided, comprising: a second chip bonding region to which chips are bonded; the second output wiring board having a second output region electrically connected to a second output terminal on the sixth side; and a second connection wiring region electrically connected to the output electrodes of the plurality of second semiconductor chips on the second input wiring board side; the second arm portion having a sixth side facing the fourth side of the first arm portion and adjacent to the first arm portion, and the first input region, the first output region and the second output region being located on the boundary line between the fourth side and the sixth side. [Effects of the Invention]

[0007] According to the disclosed technology, it is possible to suppress current imbalances in multiple semiconductor chips connected in parallel, thereby extending the lifespan of semiconductor devices and suppressing a decrease in the reliability of semiconductor devices. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view of the semiconductor device according to the embodiment. [Figure 2] This is a plan view of the semiconductor unit (upper arm portion) included in the semiconductor device of the embodiment. [Figure 3] This is a cross-sectional view of a semiconductor unit (upper arm portion) included in the semiconductor device of the embodiment. [Figure 4] This is a plan view of the semiconductor unit (lower arm portion) included in the semiconductor device of the embodiment. [Figure 5] This is a cross-sectional view of a semiconductor unit (lower arm portion) included in the semiconductor device of the embodiment. [Figure 6] This is a circuit diagram of a semiconductor unit included in the semiconductor device of the embodiment. [Figure 7] This is a plan view illustrating the current flow in the semiconductor unit (upper arm portion) included in the semiconductor device of the embodiment. [Figure 8] This is a plan view illustrating the current flow in the semiconductor unit (upper arm portion) included in the example semiconductor device. [Figure 9] This is a plan view illustrating the current flow in the semiconductor unit (lower arm portion) included in the semiconductor device of the embodiment. [Figure 10] This is a plan view of the semiconductor unit (upper arm portion) included in the semiconductor device of the embodiment (modification example 1). [Figure 11] This is a plan view of the semiconductor unit (upper arm portion) included in the semiconductor device of the embodiment (modified example 2). [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the drawings. In the following description, "front surface" and "top surface" refer to the XY plane facing upwards (+Z direction) in the semiconductor device shown in the figure. Similarly, "up" refers to the upward direction (+Z direction) in the semiconductor device 1 of Figure 1. "Back surface" and "bottom surface" refer to the XY plane facing downwards (-Z direction) in the semiconductor device 1 of Figure 1. Similarly, "down" refers to the downward direction (-Z direction) in the semiconductor device 1 of Figure 1. The same directionality will be used in other drawings as needed. "Front surface," "top surface," "up," "back surface," "bottom surface," "down," and "side" are merely convenient expressions to specify relative positional relationships and do not limit the technical concept of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. Also, in the following description, "main component" refers to a case where it contains 80 vol% or more.

[0010] The semiconductor device of the embodiment will be described using Figure 1. Figure 1 is a plan view of the semiconductor device of the embodiment. The semiconductor device 1 includes a housing 4, semiconductor units 2a, 2b, 3a, and 3b housed in the housing 4, and a heat dissipation base plate 15. Note that only the external shapes of the semiconductor units 2a, 2b, 3a, and 3b are shown. Details of the semiconductor units 2a, 2b, 3a, and 3b will be described later. Furthermore, the heat dissipation base plate 15 can be seen in Figures 3 and 5, which will be described later.

[0011] The enclosure 4 includes an outer frame 5 and control terminals 6a and 6b. The outer frame 5 is enclosed in order by its long side 5a, short side 5b, long side 5c, and short side 5d. The outer frame 5 also includes corners 5e to 5h. Corner 5e is composed of the long side 5a and short side 5b. Corner 5f is composed of the short side 5b and long side 5c. Corner 5g is composed of the long side 5c and short side 5d. Corner 5h is composed of the short side 5d and long side 5a. Such an outer frame 5 includes unit storage areas 5i to 5l. The unit storage areas 5i to 5l are arranged in two rows and two columns. The unit storage areas 5i to 5l should have a shape and area that accommodates semiconductor units 2a, 2b, 3a, and 3b, respectively. The thickness of this outer frame 5 (long side 5a, short side 5b, long side 5c, short side 5d) is greater than the thickness of the semiconductor units 2a, 2b, 3a, and 3b, which will be described later.

[0012] Furthermore, the unit housing regions 5i to 5l that house the semiconductor units 2a, 2b, 3a, and 3b are sealed with a sealing member 9 (see Figures 3 and 5). In this case, the upper ends of the external connection terminals 8a to 8c, which will be described later and connected at the terminal bonding regions 12a6, 12b6, 12c6, and 22a8, extend from the sealing member 9 in the +Z direction. The sealing member 9 contains a thermosetting resin and a filler contained in the thermosetting resin. Examples of thermosetting resins include epoxy resin, phenolic resin, and maleimide resin. Examples of fillers include glass, silicon dioxide, aluminum oxide, boron nitride, or aluminum nitride. An example of such a sealing member 9 includes an epoxy resin and a filler. At least one of the fillers described above is used as the filler.

[0013] The control terminals 6a and 6b are respectively provided on the short side edges 5b and 5d. When a control signal is applied from the outside, the control terminal 6a inputs a control signal to the semiconductor units 2a and 2b stored in the unit storage areas 5i and 5j. When a control signal is applied from the outside, the control terminal 6b inputs a control signal to the semiconductor units 3a and 3b stored in the unit storage areas 5k and 5l. Further, the housing 4 may include fastening holes at the corners 5e to 5h. The semiconductor device 1 is arranged in a predetermined area, and a screw inserted through the fastening hole is fastened to the area. Thereby, the semiconductor device 1 is attached to the area.

[0014] Such a housing 4 is formed by injection molding a housing 4 including the control terminals 6a and 6b using a resin. Examples of such a resin include polyphenylene sulfide, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0015] The semiconductor units 2a and 2b respectively constitute upper arm portions, and the semiconductor units 3a and 3b respectively constitute lower arm portions. Also, the semiconductor units 2a and 3a are arranged in the ±Y direction. The semiconductor units 2a and 3a are electrically connected by connection wires 7a and 7b to constitute one phase of the power conversion device. Similarly, the semiconductor units 2b and 3b are arranged in the ±Y direction. The semiconductor units 2b and 3b are electrically connected by connection wires 7a and 7b to constitute one phase of the power conversion device.

[0016] The semiconductor units 2a have terminal bonding regions 12a6, 12b6, 12c6 provided on the short side 5d side. The semiconductor units 3a have a terminal bonding region 22a8 provided on the short side 5b side. Therefore, in the semiconductor units 2a, 3a, the terminal bonding regions 12a6, 12b6, 12c6, 22a8 are provided on the boundary line side (close to the boundary line) between the semiconductor unit 2a and the semiconductor unit 3a. Also, the semiconductor units 2b have terminal bonding regions 12a6, 12b6, 12c6 provided on the short side 5d side. The semiconductor units 3b have a terminal bonding region 22a8 provided on the short side 5b side. Therefore, in the semiconductor units 2b, 3b, the terminal bonding regions 12a6, 12b6, 12c6, 22a8 are provided on the boundary line side (by the boundary line) between the semiconductor unit 2b and the semiconductor unit 3b. That is, the terminal bonding regions 12a6, 12b6, 12c6, 22a8 are provided at the central portions in the ±Y direction of the semiconductor units 2a, 3a and the semiconductor units 2b, 3b. This facilitates the connection of external terminals to the terminal bonding regions 12a6, 12b6, 12c6, 22a8 and the wiring.

[0017] Such semiconductor units 2a, 3a and semiconductor units 2b, 3b are arranged on the heat dissipation base plate 15 via the bonding members 16 and the bonding members 26. At this time, the semiconductor units 2a, 2b, 3a, 3b are arranged in two rows and two columns respectively. Further, a housing 4 is attached to the heat dissipation base plate 15 by an adhesive member. The semiconductor units 2a, 2b, 3a, 3b are respectively housed in the unit housing regions 5i to 5l of the housing 4. The heat dissipation base plate 15 may have the same shape and area as the outer shape of the housing 4 in plan view. Such a heat dissipation base plate 15 is composed mainly of a material having excellent thermal conductivity. Such a material is constituted by, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these.

[0018] Next, the upper arm portion included in the semiconductor device 1 will be described using Figures 2 and 3. Figure 2 is a plan view of the semiconductor unit (upper arm portion) included in the semiconductor device of the embodiment. Figure 3 is a cross-sectional view of the semiconductor unit (upper arm portion) included in the semiconductor device of the embodiment. Here, semiconductor unit 2a, which constitutes the upper arm portion, will be used as an example. Semiconductor unit 2b has a similar configuration. Semiconductor units 2a and 2b will be collectively referred to as semiconductor unit 2. Note that the center line C in Figure 2 is parallel to the long sides 11a and 11c and passes through the centers of the short sides 11b and 11d.

[0019] The semiconductor unit 2 includes an insulating circuit board 10 and a plurality of semiconductor chips 30a to 30f. The insulating circuit board 10 has an insulating plate 11, a plurality of wiring boards 12a to 12d formed on the front surface of the insulating plate 11, and a metal plate 13 formed on the back surface of the insulating plate 11. The outer shapes of the plurality of wiring boards 12a to 12d and the metal plate 13 are smaller than the outer shape of the insulating plate 11 in a plan view and are formed inside the insulating plate 11. Note that the shape and number of the plurality of wiring boards 12a to 12d are examples only.

[0020] The insulating plate 11 has a rectangular shape when viewed from above. The corners of the insulating plate 11 may also be chamfered. For example, they may be C-chamfered or R-chamfered. The insulating plate 11 is surrounded on all four sides by its outer perimeter, which consists of long sides 11a, short sides 11b, long sides 11c, and short sides 11d. The insulating plate 11 also includes a corner 11e formed by the long side 11a and short side 11b, and a corner 11f formed by the short side 11b and long side 11c. Furthermore, the insulating plate 11 includes a corner 11g formed by the long side 11c and short side 11d, and a corner 11h formed by the short side 11d and long side 11a.

[0021] The insulating plate 11 is made of a ceramic material with good thermal conductivity. The ceramic material is made of, for example, a material mainly composed of aluminum oxide, aluminum nitride, or silicon nitride. The thickness of the insulating plate 11 is 0.2 mm or more and 2.0 mm or less.

[0022] The wiring boards 12a to 12d are mainly composed of a metal with excellent conductivity. Examples of the metal include copper or copper alloys. The wiring boards 12a to 12d may be plated. Examples of the plating material include nickel, nickel-phosphorus alloy, nickel-boron alloy, silver, and silver alloy. Plating the wiring boards 12a to 12d improves their corrosion resistance and bonding properties. The thickness of the wiring boards 12a to 12d is, for example, 0.1 mm or more and 1.0 mm or less.

[0023] The wiring board 12a (first input wiring board) has a roughly T-shape in plan view. The wiring board 12a is formed approximately in the center of the front surface of the insulating board 11. Such a wiring board 12a includes an input portion 12a1, a chip bonding portion 12a2, and protruding portions 12a3 and 12a4.

[0024] The input portion 12a1 (first input area) is rectangular in shape when viewed from above. The input portion 12a1 is formed in the center of the short side 11d of the insulating plate 11, close to the short side 11d. A terminal connection area 12a6 is provided in the input portion 12a1. An external connection terminal 8a (input terminal), which is a P terminal, is connected to the terminal connection area 12a6.

[0025] The chip bonding portion 12a2 (chip bonding area) is rectangular in shape when viewed from above. The chip bonding portion 12a2 is integrally formed with the input portion 12a1, is parallel to the long sides 11a and 11c, and extends toward the short side 11b. There is a gap between the end of the chip bonding portion 12a2 (in the +Y direction) and the short side 11b. The width of the chip bonding portion 12a2 (in the ±X direction) is wider than the width of the input portion 12a1 in the same direction. There is a gap between the end of the chip bonding portion 12a2 on the long side 11a and 11c and the long sides 11a and 11c.

[0026] In the chip junction portion 12a2, semiconductor chips 30a and 30b are arranged sequentially along the long side 11a, on the long side 11a side (from the short side 11d toward the short side 11b). Also in the chip junction portion 12a2, semiconductor chips 30d and 30e are arranged sequentially along the long side 11c, on the long side 11c side (from the short side 11d toward the short side 11b). These semiconductor chips 30a, 30b, 30d, and 30e are arranged so that their control electrodes 31 face each other (facing toward the center line C).

[0027] The protruding portions 12a3 and 12a4 are rectangular in shape when viewed from above. The protruding portions 12a3 and 12a4 are on the +Y direction side of the chip bonding portion 12a2 and extend from the ends on the long sides 11a and 11c to the long sides 11a and 11c. The protruding portions 12a3 and 12a4 are integrally formed with the chip bonding portion 12a2. Therefore, the +Y direction ends of the protruding portions 12a3 and 12a4 protrude further toward the short side 11b than the +Y direction ends of the chip bonding portion 12a2. As a result, a recess is formed in the chip bonding portion 12a2 at the +Y direction end of the wiring board 12a. Semiconductor chips 30c and 30f are placed on the protruding portions 12a3 and 12a4. In this case, the control electrodes 31 of the semiconductor chips 30c and 30f face toward the short side 11b.

[0028] Therefore, semiconductor chips 30a, 30b, and 30c are arranged along the L-shaped end on the long side 11a of the wiring board 12a, and are positioned on that end side. Semiconductor chips 30d, 30e, and 30f are arranged along the L-shaped end on the long side 11c of the wiring board 12a, and are positioned on that end side. In other words, semiconductor chips 30a-30c and 30d-30f are connected in parallel to the wiring board 12a.

[0029] The wiring board 12b (first output wiring board) is provided on the side of the wiring board 12a on the long side 11a. That is, the wiring board 12b is provided in the gap between the end of the wiring board 12a on the long side 11a and the long side 11a. The wiring board 12b extends along the long side 11a of the front surface of the insulating board 11, on the long side 11a side, from the short side 11d to the protruding portion 12a3 of the wiring board 12a. Such a wiring board 12b includes an output portion 12b1, a wiring portion 12b2, a lateral connection portion 12b3, and a vertical connection portion 12b4.

[0030] The output section 12b1 has a rectangular shape in plan view. The output section 12b1 is formed at the corner 11h of the insulating plate 11. The output section 12b1 includes a terminal connection area 12b6. The terminal connection area 12b6 is located on the long side 11c of the output section 12b1. An external connection terminal 8b (intermediate (output) terminal), which is an M terminal, is connected to the terminal connection area 12b6. The output section 12b1 includes a first output section 12b7. The first output section 12b7 is located on the short side 11d of the output section 12b1.

[0031] The wiring section 12b2 has a rectangular shape in plan view and is integrally formed with the output section 12b1. The wiring section 12b2 extends from the output section 12b1 toward the shorter side 11b along the longer side 11a.

[0032] The lateral connection portion 12b3 has a rectangular shape in plan view and is integrally formed with the wiring portion 12b2. The width of the lateral connection portion 12b3 in the ±X direction is wider than the width of the wiring portion 12b2 in the same direction. For this reason, the lateral connection portion 12b3 is connected to the wiring portion 12b2 on its short side 11d and extends from its long side 11a to the chip bonding portion 12a2 of the wiring board 12a.

[0033] The vertical connection portion 12b4 is rectangular in shape when viewed from above and is integrally formed with the horizontal connection portion 12b3. The width of the vertical connection portion 12b4 in the ±X direction is narrower than the width of the horizontal connection portion 12b3 in the same direction. The vertical connection portion 12b4 extends from the horizontal connection portion 12b3 toward the output portion 12b1 toward the shorter side 11d.

[0034] The wiring portion 12b2, the lateral connection portion 12b3, and the vertical connection portion 12b4 of this wiring board 12b form a U-shape in plan view. Furthermore, a slit 12b5 (first slit) is formed between the wiring portion 12b2 and the vertical connection portion 12b4 of the wiring board 12b. The slit 12b5 is formed parallel to the long side 11a, extending from the end of the short side 11d of the vertical connection portion 12b4 toward the lateral connection portion 12b3.

[0035] Furthermore, the lateral connection portion 12b3 and the vertical connection portion 12b4 of the wiring board 12b are connected to the output electrodes 32 of the semiconductor chips 30a and 30b by main current wires 14b, respectively. The lateral connection portion 12b3 of the wiring board 12b is connected to the output electrodes 32 of the semiconductor chip 30c by main current wires 14b, respectively.

[0036] The wiring board 12c (first output wiring board) is similar to the wiring board 12b. That is, the wiring board 12c is provided on the side of the wiring board 12a on the long side 11c. Alternatively, the wiring board 12c is provided in the gap between the end of the wiring board 12a on the long side 11c and the long side 11c. The wiring board 12c extends along the long side 11c of the front surface of the insulating board 11, on the long side 11c side, from the short side 11d to the protruding portion 12a4 of the wiring board 12a. Such a wiring board 12c includes an output portion 12c1, a wiring portion 12c2, a lateral connection portion 12c3, and a vertical connection portion 12c4.

[0037] The output section 12c1 has a rectangular shape in plan view. The output section 12c1 is formed at the corner 11g of the insulating plate 11. The output section 12c1 includes a terminal connection area 12c6. The terminal connection area 12c6 is located on the long side 11a of the output section 12c1. An external connection terminal (intermediate terminal), which is an M terminal, is connected to the terminal connection area 12c6. The output section 12c1 includes a first output section 12c7. The first output section 12c7 is located on the short side 11d of the output section 12c1.

[0038] The wiring section 12c2 has a rectangular shape in plan view and is integrally formed with the output section 12c1. The wiring section 12c2 extends from the output section 12c1 toward the short side 11b along the long side 11c, on the long side 11c side.

[0039] The lateral connection portion 12c3 has a rectangular shape in plan view and is integrally formed with the wiring portion 12c2. The width of the lateral connection portion 12c3 in the ±X direction is wider than the width of the wiring portion 12c2 in the same direction. For this reason, the lateral connection portion 12c3 is connected to the wiring portion 12c2 on its short side 11d and extends from its long side 11c to the chip bonding portion 12a2 of the wiring board 12a.

[0040] The vertical connection portion 12c4 has a rectangular shape in plan view and is integrally formed with the horizontal connection portion 12c3. The width of the vertical connection portion 12c4 in the ±X direction is narrower than the width of the horizontal connection portion 12c3 in the same direction. The vertical connection portion 12c4 extends from the horizontal connection portion 12c3 toward the output portion 12b1 toward the shorter side 11d.

[0041] The wiring portion 12c2, the lateral connection portion 12c3, and the vertical connection portion 12c4 of this wiring board 12c form a U-shape in plan view. Furthermore, a slit 12c5 (first slit) is formed between the wiring portion 12c2 and the vertical connection portion 12c4 of the wiring board 12c. The slit 12c5 is formed parallel to the long side 11a, extending from the end of the short side 11d of the vertical connection portion 12c4 toward the lateral connection portion 12b3.

[0042] Furthermore, the lateral connection portion 12c3 and the vertical connection portion 12c4 of the wiring board 12c are connected to the output electrodes 32 of the semiconductor chips 30d and 30e by main current wires 14b, respectively. The lateral connection portion 12c3 of the wiring board 12c is connected to the output electrodes 32 of the semiconductor chip 30f by main current wires 14b, respectively.

[0043] The wiring board 12d is formed on the short side 11b of the front surface of the insulating board 11, extending from the long side 11a to the long side 11c parallel to the short side 11b. The wiring board 12d includes a portion in the center that protrudes toward the short side 11d. This portion fits into a recess on the short side 11b of the wiring board 12a.

[0044] The wiring board 12d is electrically connected to the control terminal 6a included in the housing 4. The wiring board 12d is connected to the control electrodes 31 of semiconductor chips 30a and 30b, which are arranged in a straight line, by control wires 14a. The wiring board 12d is connected to the control electrodes 31 of semiconductor chips 30d and 30e, which are arranged in a straight line, by control wires 14a. The wiring board 12d is connected to the control electrodes 31 of semiconductor chips 30c and 30f, by control wires 14a. The control signal input from the control terminal 6a is applied to the control electrodes 31 of semiconductor chips 30a to 30f via the wiring board 12d and the control wires 14a.

[0045] In such an insulated circuit board 10, when current is input from the terminal junction region 12a6, the current flows along the current direction I1 in the wiring board 12a. Similarly, current output from semiconductor chips 30a, 30b, and 30c flows along the current direction O1 in the wiring board 12b. Current output from semiconductor chips 30d, 30e, and 30f also flows through the wiring board 12c in the same manner. Details of this current flow will be described later.

[0046] The metal plate 13 is mainly composed of a metal with excellent thermal conductivity. Examples of such metals include aluminum, iron, silver, copper, or alloys containing at least one of these. Furthermore, plating may be applied to improve corrosion resistance and bonding properties. Examples of plating materials include nickel, nickel-phosphorus alloys, nickel-boron alloys, silver, and silver alloys.

[0047] As an insulated circuit board 10 having such a configuration, for example, a DCB (Direct Copper Bonding) board or an AMB (Active Metal Brazed) board can be used. The insulated circuit board 10 is bonded to the heat dissipation base plate 15 via a bonding member 16. The insulated circuit board 10 can conduct the heat generated in the semiconductor chips 30a to 30f to the heat dissipation base plate 15 side via the wiring board 12a, the insulating plate 11, and the metal plate 13.

[0048] The semiconductor chips 30a to 30f may include a switching element consisting of a power MOSFET. Such semiconductor chips 30a to 30f have a gate electrode as a control electrode 31 and a source electrode as a main electrode, the output electrode 32, on their front surface. The control electrode 31 is located in the center of the side of the front surface, and the output electrode 32 is located in the center of the front surface. The semiconductor chips 30a to 30f also have a drain electrode as a main electrode, the input electrode 33, on their back surface. Such semiconductor chips 30a to 30f may be made of silicon carbide.

[0049] The semiconductor chips 30a to 30f may include an RC (Reverse Conducting)-IGBT switching element. An RC-IGBT incorporates both an IGBT and an FWD (Free Wheeling Diode) within a single chip. Such semiconductor chips 30a to 30f also have a gate electrode as a control electrode 31 and an emitter electrode as a main electrode output electrode 32 on their front surface, and a collector electrode as a main electrode input electrode 33 on their back surface. Such semiconductor chips 30a to 30f may be made of silicon.

[0050] The semiconductor chips 30a to 30f are joined to the wiring boards 12a and 12b by a bonding member 16. The bonding member 16 is either sintered metal or solder. The sintered metal is mainly composed of a porous metal with silver as the main component. The solder is made of lead-free solder mainly composed of a predetermined alloy. The predetermined alloy is, for example, at least one of the following alloys: a tin-silver alloy, a tin-zinc alloy, or a tin-antimony alloy. The solder may also contain additives. Examples of additive materials include copper, bismuth, indium, nickel, germanium, cobalt, or silicon. The bonding member 16 may also be sintered metal. The sintered metal is made of a metal mainly composed of silver.

[0051] The shapes and arrangement of the wiring boards 12a to 12d of the insulating circuit board 10 included in the semiconductor unit 2 having this configuration are symmetrical with respect to the center line C shown in Figure 2. Furthermore, the semiconductor chips 30a to 30c and 30d to 30f placed on the wiring board 12a are also arranged to be symmetrical with respect to the center line C shown in Figure 2.

[0052] Next, the lower arm portion included in the semiconductor device 1 will be described using Figures 4 and 5. Figure 4 is a plan view of the semiconductor unit (lower arm portion) included in the semiconductor device of the embodiment. Figure 5 is a cross-sectional view of the semiconductor unit (lower arm portion) included in the semiconductor device of the embodiment. Here, semiconductor unit 3a, which constitutes the lower arm portion, will be used as an example. Semiconductor unit 3b has a similar configuration. Semiconductor units 3a and 3b will be collectively referred to as semiconductor unit 3. Note that the center line C in Figure 4 is parallel to the long sides 21a and 21c and passes through the centers of the short sides 21b and 21d.

[0053] The semiconductor unit 3 includes an insulating circuit board 20 and a plurality of semiconductor chips 40a to 40f. The insulating circuit board 20 has an insulating plate 21, a plurality of wiring boards 22a, 22b, and 22d formed on the front surface of the insulating plate 21, and a metal plate 23 formed on the back surface of the insulating plate 21. The outer shapes of the plurality of wiring boards 22a, 22b, and 22d and the metal plate 23 are smaller than the outer shape of the insulating plate 21 in a plan view and are formed inside the insulating plate 21. Note that the shape and number of the plurality of wiring boards 22a, 22b, and 22d are examples only.

[0054] The insulating plate 21 is constructed in the same way as the insulating plate 11. That is, the insulating plate 21 has a rectangular shape when viewed from above. The corners of the insulating plate 21 may also be chamfered. For example, they may be C-chamfered or R-chamfered. The insulating plate 21 is surrounded on all four sides by the outer perimeter, which consists of long sides 21a, short sides 21b, long sides 21c, and short sides 21d. The insulating plate 21 also includes a corner 21e formed by the long side 21a and short side 21b, and a corner 21f formed by the short side 21b and long side 21c. Furthermore, the insulating plate 21 includes a corner 21g formed by the long side 21c and short side 21d, and a corner 21h formed by the short side 21d and long side 21a.

[0055] The insulating plate 21 is made of a ceramic material with good thermal conductivity. The ceramic material is made of, for example, a material mainly composed of aluminum oxide, aluminum nitride, or silicon nitride. The thickness of the insulating plate 21 is 0.2 mm or more and 2.0 mm or less.

[0056] The wiring boards 22a, 22b, and 22d are made of a metal with excellent conductivity. Examples of the metal include copper or copper alloys. The wiring boards 22a, 22b, and 22d may be plated. Examples of the plating material include nickel, nickel-phosphorus alloy, nickel-boron alloy, silver, and silver alloy. Plating improves the corrosion resistance and bonding properties of the wiring boards 22a, 22b, and 22d. The thickness of the wiring boards 22a, 22b, and 22d is, for example, 0.1 mm or more and 1.0 mm or less.

[0057] The wiring board 22a (second output wiring board) has a roughly T-shape in plan view. The wiring board 22a is formed on the short side 21b of the front surface of the insulating board 21. Such a wiring board 22a includes an output section 22a1, a wiring section 22a2, a lateral connection section 22a3, and vertical connection sections 22a4 and 22a5.

[0058] The output section 22a1 (second output region) has a rectangular shape in plan view. The output section 22a1 is formed by extending from the center of the short side 21b of the insulating plate 21 to the long sides 21a and 21c, respectively. A terminal connection region 22a8 is provided in the output section 22a1. An external connection terminal 8c (output terminal), which is an N terminal, is connected to the terminal connection region 22a8.

[0059] The wiring portion 22a2 has a rectangular shape in plan view. The wiring portion 22a2 is integrally formed with the output portion 22a1, is parallel to the long sides 21a and 21c, and extends toward the short side 21d. The width of the wiring portion 22a2 (in the ±X direction) is narrower than the width of the output portion 22a1 in the same direction.

[0060] The lateral connection portion 22a3 has a rectangular shape in plan view and is integrally formed with the wiring portion 22a2. The width of the lateral connection portion 22a3 in the ±X direction is wider than the width of the wiring portion 22a2 in the same direction. For this reason, the lateral connection portion 22a3 extends further than the wiring portion 22a2 towards the longer sides 21a and 21c.

[0061] The vertical connection sections 22a4 and 22a5 are rectangular in shape when viewed from above and are integrally formed with the horizontal connection section 22a3. The width of the vertical connection sections 22a4 and 22a5 in the ±X direction (second vertical connection wiring width) is narrower than the width of the wiring section 22a2 in the same direction (second output connection wiring width). The vertical connection sections 22a4 and 22a5 extend from the horizontal connection section 22a3 toward the shorter side 21b to the output section 22a1.

[0062] The wiring portion 22a2, the lateral connection portion 22a3, and the vertical connection portions 22a4 and 22a5 of this wiring board 22a each form a U-shape in plan view. In addition, slits 22a6 and 22a7 (second slits) are formed between the wiring portion 22a2 and the vertical connection portions 22a4 and 22a5 of the wiring board 22a. The slits 22a6 and 22a7 are formed parallel to the long side 21a, extending from the short side 21b end of the vertical connection portions 22a4 and 22a5 toward the lateral connection portion 22a3.

[0063] Furthermore, the vertical connection portions 22a4 and 22a5 of the wiring board 22a are connected to the output electrodes 42 of the semiconductor chips 40b, 40c, 40e, and 40f, which will be described later, via the main current wires 24b. The horizontal connection portion 22a3 of the wiring board 22a is connected to the output electrodes 42 of the semiconductor chips 40a and 40d, which will be described later, via the main current wires 14b.

[0064] The wiring board 22b has a U-shape when viewed from above. The wiring board 22b is formed on the insulating board 21, surrounding the wiring board 22a between each end of the wiring board 22a and the long side 21a, short side 21d, and long side 21c.

[0065] Semiconductor chips 40a-40c and 40d-40f are bonded to the chip bonding region 22b1 of the wiring board 22b. Specifically, semiconductor chips 40c, 40b and semiconductor chips 40f, 40e are arranged on the wiring board 22b in the portion opposite to the vertical connection portions 22a4 and 22a5 of the wiring board 22a. The control electrodes 41 of semiconductor chips 40c, 40b and semiconductor chips 40f, 40e face the longer sides 21a and 21c. Furthermore, the control electrodes 41 are arranged in a straight line with respect to the ±Y direction. Semiconductor chips 40a and 40d are arranged on the wiring board 22b in the portion opposite to the horizontal connection portion 22a3 of the wiring board 22a. The control electrodes 41 of semiconductor chips 40a and 40d face the shorter side 21d. Furthermore, the control electrodes 41 are arranged in a straight line with respect to the ±X direction.

[0066] The wiring board 22b includes second input regions 22b9 and 22b10 on its short side 21b. The second input regions 22b9 and 22b10 are electrically connected to the first output regions 12b7 and 12c7 of the wiring boards 12b and 12c of the semiconductor unit 2 by connecting wires 7a and 7b, respectively.

[0067] The wiring board 22d is formed on the short side 21d of the front surface of the insulating board 21, extending from the long side 21a to the long side 21c parallel to the short side 21d. The wiring board 22d includes a portion in the center that protrudes toward the short side 21d.

[0068] The wiring board 22d is electrically connected to the control terminal 6b included in the housing 4. The wiring board 22d is connected to the control electrodes 41 of semiconductor chips 40a and 40d by control wires 14a. The wiring board 22d is connected to the control electrodes 41 of semiconductor chips 40c and 40b by control wires 14a. The wiring board 22d is connected to the control electrodes 41 of semiconductor chips 40c and 40f by control wires 14a. The control signal input from the control terminal 6b is applied to the control electrodes 41 of semiconductor chips 40a to 40f via the wiring board 22d and the control wires 14a.

[0069] In such an insulated circuit board 20, when current is input from the semiconductor unit 2, the current flows along the current direction I2 in the wiring board 22b. Furthermore, the current output from the semiconductor chips 40a, 40b, 40c and semiconductor chips 40d, 40e, 40f flows along the current direction O2 in the wiring board 22a. Details of this current flow will be described later.

[0070] The metal plate 23 is the same as the metal plate 13. That is, the metal plate 23 is mainly composed of a metal with excellent thermal conductivity. Examples of such metals include aluminum, iron, silver, copper, or alloys containing at least one of these. Furthermore, plating may be applied to improve corrosion resistance and bonding properties. Examples of plating materials in this case include nickel, nickel-phosphorus alloy, nickel-boron alloy, silver, and silver alloy.

[0071] The insulated circuit board 20 having such a configuration can also be, for example, a DCB board or an AMB board. The insulated circuit board 20 is joined to the heat dissipation base plate 15 via a bonding member 26. The insulated circuit board 20 can conduct the heat generated by the semiconductor chips 40a to 40f to the heat dissipation base plate 15 side via the wiring board 22a, the insulating plate 21, and the metal plate 23.

[0072] The semiconductor chips 40a to 40f are the same as semiconductor chips 30a to 30f. That is, semiconductor chips 40a to 40f are equipped with a control electrode 41 and a main electrode, which is an output electrode 42, on the front surface, and an input electrode 43 on the back surface. The control electrode 41 is located in the center of the side of the front surface, and the output electrode 42 is located in the center of the front surface. Such semiconductor chips 40a to 40f are bonded to the wiring board 22b by a bonding member 26.

[0073] The shapes and arrangement of the wiring boards 22a, 22b, and 22d of the insulating circuit board 20 included in the semiconductor unit 3 having this configuration are symmetrical with respect to the center line C shown in Figure 4. Furthermore, the semiconductor chips 40a to 40c and 40d to 40f placed on the wiring board 22b are also arranged to be symmetrical with respect to the center line C shown in Figure 4.

[0074] Semiconductor unit 1 is obtained by arranging semiconductor units 3a and 3b in the -Y direction relative to the semiconductor units 2a and 2b described above, and electrically connecting them with connecting wires 7a and 7b, respectively. In other words, semiconductor units 3a and 3b are arranged such that their respective short sides 21b face each other with respect to the respective short sides 11d of semiconductor units 2a and 2b.

[0075] Next, the half-bridge circuit including the upper arm and lower arm portions of the semiconductor device 1 will be described using Figure 6. Figure 6 is a circuit diagram of the semiconductor unit included in the semiconductor device of the embodiment.

[0076] Connection point P is connected to the positive terminal of an external power supply (not shown in the diagram). Connection point P and connection point C1 of the input electrode 33 (collector electrode) of semiconductor chips 30a to 30f are connected by the wiring board 12a.

[0077] Connection point M is connected to the load (not shown in the diagram). Connection point M and connection point E1C2 of the output electrode 32 (emitter electrode) of semiconductor chips 30a to 30f are connected by the main current wire 14b and the wiring boards 12b and 12c. In addition, connection point M and connection point E1C2 of the input electrode 43 (collector electrode) of semiconductor chips 40a to 40f are connected by the wiring board 22b and connection wires 7a and 7b.

[0078] Connection point N is connected to the negative terminal of an external power supply (not shown in the figure). Connection point N and connection point E2 of the output electrode 42 (emitter electrode) of semiconductor chips 40a to 40f are connected by the main current wire 24b and the wiring board 22a.

[0079] Connection points G1 and G2 are connected to a control power supply (not shown). Connection point G1 is connected to the control electrodes 31 of semiconductor chips 30a to 30f via a wiring board 12d and control wire 14a. Connection point G2 is connected to the control electrodes 41 of semiconductor chips 40a to 40f via a wiring board 22d and control wire 24a.

[0080] The upper arm A of the semiconductor device 1 includes a semiconductor unit 2. The lower arm B of the semiconductor device 1 includes a semiconductor unit 3. Furthermore, the upper arm A and the lower arm B are connected by connecting wires 7a and 7b, which electrically connect the wiring boards 12b and 12c of the semiconductor unit 2 and the wiring board 22b of the semiconductor unit 3. In this way, the semiconductor device 1 can function as a half-bridge circuit including the upper arm A and the lower arm B.

[0081] Next, the current path in such a semiconductor unit 2 will be explained using Figure 7. Figure 7 is a plan view illustrating the current flow in the semiconductor unit (upper arm portion) included in the semiconductor device of the embodiment. Note that Figure 7 is an enlarged view of the wiring board 12b of the semiconductor unit 2. Here, the wiring board 12b will be described. The wiring board 12c is similar to the wiring board 12b.

[0082] A positive electrode is connected externally to the terminal junction area 12a6 of the wiring board 12a of semiconductor unit 2, and a negative electrode is connected externally to the terminal junction area 22a8 of the wiring board 22a of semiconductor unit 3. A control signal is applied to the control electrodes 31 of semiconductor chips 30a to 30f. As a result, as shown in Figure 7, current flows from the terminal junction area 12a6 to the wiring board 12a parallel to the long side 11a (+Y direction).

[0083] The current flowing through the semiconductor chip 30a, which is located closest to the terminal junction area 12a6, will now be described. The current flowing from the terminal junction area 12a6 in the +Y direction (current path R1a) through the wiring board 12a is input to the input electrode 33 on the back surface of the semiconductor chip 30a. When current is input to the input electrode 33 on the back surface of the semiconductor chip 30a, the semiconductor chip 30a outputs current from the output electrode 32 on the front surface of the semiconductor chip 30a. The current output from the output electrode 32 of the semiconductor chip 30a (current path R1b) flows through the main current wire 14b into the vertical connection portion 12b4 of the wiring board 12b, and conducts current in the +Y direction. The current that has conducted through the vertical connection portion 12b4 conducts current through the horizontal connection portion 12b3 on the long side 11a side (-X direction) and through the wiring portion 12b2 on the short side 11d side (-Y direction). The current is then output from the terminal junction area 12b6 of the output section 12b1, or from the connecting wire 7a of the first output section 12b7. In other words, the current passing through the semiconductor chip 30a flows through the current path (R1a + R1b).

[0084] Next, we will explain the current flowing through the semiconductor chip 30c, which is located furthest from the terminal junction area 12a6. The current flowing from the terminal junction area 12a6 in the +Y direction (current path R2a) through the wiring board 12a is input to the input electrode 33 on the back surface of the semiconductor chip 30c. When current is input to the input electrode 33 on the back surface of the semiconductor chip 30c, the semiconductor chip 30c outputs current from the output electrode 32 on the front surface of the semiconductor chip 30c. The current output from the output electrode 32 of the semiconductor chip 30c (current path R2b) flows through the main current wire 14b to the lateral connection portion 12b3 of the wiring board 12b, and conducts current in the -Y direction. The current that has conducted current through the lateral connection portion 12b3 conducts current through the wiring portion 12b2 on the short side 11d side (-Y direction). Then, it is output from the terminal junction area 12b6 of the output portion 12b1, or from the connection wire 7a of the first output portion 12b7. In other words, the current passing through the semiconductor chip 30c flows through the current path (R2a + R2b).

[0085] Furthermore, the width W1 (first output connection wiring width) of the wiring section 12b2 is wider than the width W2 (first vertical connection wiring width) of the vertical connection section 12b4. Therefore, even when the currents output from the semiconductor chips 30a, 30b, and 30c merge at the wiring section 12b2, sufficient current can flow.

[0086] Here, the current path in the semiconductor unit of the reference example will be explained using Figure 8. Figure 8 is a plan view illustrating the current flow in the semiconductor unit (upper arm portion) included in the semiconductor device of the reference example. The semiconductor unit 200 in Figure 8 is the case where the slit 12b5 is not formed in the semiconductor unit 2 of Figure 7. That is, in the semiconductor unit 200 of Figure 8, the vertical connection portion 12b4 and the wiring portion 12b2 of the semiconductor unit 2 of Figure 7 are integrally connected.

[0087] Here, as in the case of Figure 7, we will explain the current passing through semiconductor chips 30a and 30c. We will explain the current passing through semiconductor chip 30a. The current (current path r1a) flowing from the terminal junction area 12a6 in the +Y direction on the wiring board 12a is input to the input electrode 33 on the back surface of the semiconductor chip 30a. When current is input to the input electrode 33 on the back surface of the semiconductor chip 30a, the semiconductor chip 30a outputs current from the output electrode 32 on the front surface of the semiconductor chip 30a. The current output from the output electrode 32 of the semiconductor chip 30a (current path r1b) flows into the wiring board 12b via the main current wire 14b. The current that has flowed in energizes the wiring board 12b (wiring portion 12b2) on the short side 11d side (-Y direction). Then, it is output from the terminal junction area 12b6 of the output portion 12b1, or from the connecting wire 7a of the first output region 12b7. In other words, the current passing through semiconductor chip 30a flows through the current path (r1a + r1b). In this case, the current passing through semiconductor chip 30c flows through the current path (R2a + R2b), similar to the case in Figure 7.

[0088] As shown in Figure 8, the current path (R2a + R2b) is longer than the current path (r1a + r1b). When the lengths of the current paths differ in this way, a difference in impedance occurs according to the length. As a result, current inequality (current imbalance) occurs in semiconductor chips 30a and 30c. When such current imbalance occurs, the losses in each current path become uneven, hindering the extension of the lifespan of semiconductor device 1.

[0089] Therefore, in semiconductor unit 2, the wiring boards 12b and 12c are provided with output portions 12b1 and 12c1 on the short side 11d, and on the short side 11b, they are provided with lateral connection portions 12b3 and 12c3 and vertical connection portions 12b4 and 12c4 that are electrically connected to the output electrodes 32 of semiconductor chips 30a to 30c and 30d to 30f. The vertical connection portions 12b4 and 12c4 have slits 12b5 and 12c5 formed along the long sides 11a and 11c from the end on the output portion 12b1 and 12c1 side. As a result, the current output from the semiconductor chip 30a located closest to the terminal junction region 12a6 passes through the vertical connection portions 12b4 and 12c4 and the lateral connection portions 12b3 and 12c3 before reaching the output portions 12b1 and 12c1 of the wiring boards 12b and 12c. In other words, the current path (R1a + R1b) from the semiconductor chip 30a to the output portions 12b1 and 12c1 of the wiring boards 12b and 12c becomes longer. As a result, the difference between the current path (R1a + R1b) and the current path (R2a + R2b) from the semiconductor chip 30c, which is located furthest from the terminal junction region 12a6, to the output portions 12b1 and 12c1 of the wiring boards 12b and 12c1 becomes smaller. Therefore, current imbalances in parallel-connected semiconductor chips 30a~30c and 30d~30f according to their distance from the terminal junction region 12a6 can be suppressed. As a result, unevenness in losses for each current path is suppressed, the lifespan of the semiconductor device 1 is extended, and the reliability of the semiconductor device 1 is improved.

[0090] Next, the current path in the semiconductor unit 3 will be explained using Figure 9. Figure 9 is a plan view illustrating the current flow in the semiconductor unit (lower arm portion) included in the semiconductor device of the embodiment. Note that Figure 9 is an enlarged view of the portion of the wiring board 22b on the long side 21a side of the semiconductor unit 3. Here, we will explain the portion of the wiring board 22b on the long side 21a side. The portion of the wiring board 22b on the long side 21c side is the same as in this case.

[0091] The current flowing through the semiconductor chip 40c, which is located closest to the second input region 22b9 to which the connecting wire 7a is connected to the semiconductor unit 2, will now be described. The current flowing from the second input region 22b9 in the -Y direction through the wiring board 22b (current path R3a) is input to the input electrode 43 on the back surface of the semiconductor chip 40c. When current is input to the input electrode 43 on the back surface of the semiconductor chip 40c, the semiconductor chip 40c outputs current from the output electrode 42 on the front surface of the semiconductor chip 40c. The current output from the output electrode 42 of the semiconductor chip 40c (current path R3b) flows through the main current wire 24b into the vertical connection portion 22a4 of the wiring board 22a, and conducts current in the -Y direction. The current that has conducted through the vertical connection portion 22a4 conducts current through the horizontal connection portion 22a3 on the long side 21c side (+X direction) and conducts current through the wiring portion 22a2 on the short side 21b side (+Y direction). The current is then output from the terminal junction region 22a8 of the output section 22a1. In other words, the current passing through the semiconductor chip 40c flows through the current path (R3a + R3b).

[0092] Next, we will explain the current flowing through the semiconductor chip 40a, which is located furthest from the second input region 22b9. The current flowing through the wiring board 22b from the second input region 22b9 in the -Y direction (current path R4a) is input to the input electrode 43 on the back surface of the semiconductor chip 40a. When current is input to the input electrode 43 on the back surface of the semiconductor chip 40a, the semiconductor chip 40a outputs current from the output electrode 42 on the front surface of the semiconductor chip 40a. The current output from the output electrode 42 of the semiconductor chip 40a (current path R4b) flows through the main current wire 24b to the lateral connection portion 22a3 of the wiring board 22a and conducts current in the +X direction. The current that has conducted current through the lateral connection portion 22a3 conducts current through the wiring portion 22a2 on the short side 21b side (+Y direction). Then, it is output from the terminal junction region 22a8 of the output portion 22a1. In other words, the current flowing through the semiconductor chip 40a conducts current through the current path (R4a + R4b).

[0093] In semiconductor unit 3, the wiring board 22a has an output section 22a1 on the short side 21b, and a lateral connection section 22a3 and a vertical connection section 22a4, 22a5 on the short side 21d relative to the output section 22a1, which are electrically connected to the output electrodes 42 of semiconductor chips 40a-40c, 40d-40f. The vertical connection sections 22a4, 22a5 have slits 22a6, 22b7 formed along the long side 21a from the end on the output section 22a1 side. As a result, the current output from semiconductor chips 40c, 40f, which are located closest to the second input regions 22b9, 22b10, passes through the vertical connection section 22a4, 22a5 and the lateral connection section 22a3 before reaching the output section 22a1 of the wiring board 22a. In other words, the current path (R3a + R3b) from the semiconductor chips 40c, 40f to the output section 22a1 of the wiring board 22a is lengthened. Therefore, the difference between the current path (R3a+R3b) and the current path (R4a+R4b) from the semiconductor chips 40a and 40d, which are located furthest from the second input regions 22b9 and 22b10, to the output portion 22a1 of the wiring board 22a becomes smaller. Consequently, current imbalances in parallel-connected semiconductor chips 40a-40c and 40d-40f, depending on their distance from the second input regions 22b9 and 22b10, can be suppressed. As a result, unevenness in losses for each current path is suppressed, the lifespan of the semiconductor device 1 is extended, and the reliability of the semiconductor device 1 is improved.

[0094] The semiconductor device 1 described above comprises semiconductor chips 30a to 30c, 30d to 30f, each having an input electrode 33 on its back surface and an output electrode 32 on its front surface, and an insulating circuit board 10. The insulating circuit board 10 is rectangular in shape and has long sides 11a, short sides 11b, long sides 11c, and short sides 11d in that order, and includes a wiring board 12a extending parallel to the long side 11a, and wiring boards 12b and 12c arranged on the long side 11a and 11c sides of the wiring board 12a and extending parallel to the long side 11a. The wiring board 12a includes a terminal bonding region 12a6 arranged on the short side 11d, and a chip bonding portion 12a2 and protruding portions 12a3 and 12a4 arranged on the short side 11b, to which a plurality of semiconductor chips 30a to 30c, 30e to 30f are bonded. The wiring boards 12b and 12c are provided with output portions 12b1 and 12c1 on the short side 11d, and with vertical connection portions 12b4 and 12c4 and horizontal connection portions 12b3 and 12c3 on the short side 11b, which are electrically connected to the output electrodes 32 of a plurality of semiconductor chips 30a to 30c and 30e to 30f. In this case, the vertical connection portions 12b4 and 12c4 have slits 12b5 and 12c5 formed along the long sides 11a and 11c from the ends on the output portion 12b1 and 12c1 side. As a result, the current output from the semiconductor chips 30a and 30d located closest to the terminal junction region 12a6 passes through the vertical connection portions 12b4 and 12c4 and the horizontal connection portions 12b3 and 12c3 before reaching the output portions 12b1 and 12c1 of the wiring boards 12b and 12c. In other words, the current path from the semiconductor chips 30a and 30d to the output portions 12b1 and 12c1 of the wiring boards 12b and 12c becomes longer. As a result, the difference between this current path and the current path from the semiconductor chips 30c and 30f, which are located furthest from the terminal junction region 12a6, to the output portions 12b1 and 12c1 of the wiring boards 12b and 12c becomes smaller. Therefore, current imbalance in parallel-connected semiconductor chips 30a-30c and 30d-30f according to their distance from the terminal junction region 12a6 can be suppressed. As a result, uneven loss in each current path is suppressed, the lifespan of the semiconductor device 1 is extended, and the reliability of the semiconductor device 1 is improved.

[0095] In this manner, slits 12b5 and 12c5 are formed between the vertical connection portions 12b4 and 12c4 and the wiring portions 12b2 and 12c2 in the wiring boards 12b and 12c, thereby diverting the current output from the semiconductor chips 30a and 30d and increasing the current path. It is desirable that the slits 12b5 and 12c5 be of a length such that all current paths passing through the semiconductor chips 30a-30c and 30d-30f are as equal as possible. The length of such slits 12b5 and 12c5 may extend from the end on the short side 11d of the vertical connection portions 12b4 and 12c4 to a position corresponding to any of the semiconductor chips 30a-30c and 30d-30f. As a specific example, it is preferable that the length of the slits 12b5 and 12c5 extends from the end on the short side 11d of the vertical connection portion 12b4 and 12c4 toward the short side 11b, beyond the semiconductor chip 30a and 30d that is closest to the terminal connection region 12a6.

[0096] Furthermore, in order to extend the current path, the slits 12b5 and 12c5 do not have to be straight. The shape of the slits 12b5 and 12c5 may be, for example, L-shaped, arc-shaped, or crank-shaped in a plan view. Also, the slits 12b5 and 12c5 do not necessarily have to be parallel to the long sides 11a and 11c. The slits 12b5 and 12c5 may be inclined at approximately ±30° with respect to the long sides 11a and 11c.

[0097] (Variation 1) A semiconductor unit 2 of the first modified embodiment will be described using Figure 10. Figure 10 is a plan view of the semiconductor unit (upper arm portion) included in the semiconductor device of the embodiment (modified embodiment 1).

[0098] The semiconductor unit 2 in Modification 1 is the semiconductor unit 2 shown in Figure 7 in which the width of the vertical connection portion 12b4 (in the ±X direction) decreases as it moves in the -Y direction. As the vertical connection portion 12b4 moves in the +Y direction, the amount of current input from the semiconductor chips 30a and 30b increases. Accordingly, the width of the vertical connection portion 12b4 is varied. This can reduce the area of ​​the wiring board 12b and thus reduce costs. Note that this explanation focuses on the wiring board 12b. The width of the vertical connection portion 12c4 may be similarly varied in the wiring board 12c.

[0099] (Modification 2) The semiconductor unit 2 included in the semiconductor device 1 of the modified example 2 will be explained using Figure 11. Figure 11 is a plan view of the semiconductor unit (upper arm portion) included in the semiconductor device of the embodiment (modified example 2).

[0100] The wiring board 12a included in the semiconductor unit 2 of the modified example 2 is formed by removing the protruding portions 12a3 and 12a4 from the wiring board 12a of the semiconductor unit 2 of the embodiment, and arranging semiconductor chips 30a to 30c and 30d to 30f in two rows on the chip bonding portion 12a2.

[0101] The wiring board 12a of the modified example 2 includes an input portion 12a1 and a chip bonding portion 12a2. The chip bonding portion 12a2 has a rectangular shape in plan view. The chip bonding portion 12a2 is integrally formed with the input portion 12a1, is parallel to the long sides 11a and 11c, and extends to the wiring board 12d on the short side 11b. On such a chip bonding portion 12a2, semiconductor chips 30a to 30c and 30e to 30f are arranged in two rows with their control electrodes 31 facing each other.

[0102] The wiring board 12b is provided on the side of the wiring board 12a on the long side 11a. The wiring board 12b extends along the long side 11a of the front surface of the insulating board 11, on the long side 11a side, from the short side 11d to the wiring board 12d. Such a wiring board 12b includes an output portion 12b1, a wiring portion 12b2, a lateral connection portion 12b3, and a vertical connection portion 12b4. Of these, the output portion 12b1, the wiring portion 12b2, and the vertical connection portion 12b4 are the same as in the embodiment.

[0103] The lateral connection portion 12b3 is rectangular in shape when viewed from above and is integrally formed with the wiring portion 12b2. The width of the lateral connection portion 12b3 in the ±X direction is wider than the width of the wiring portion 12b2 in the same direction. Therefore, the lateral connection portion 12b3 is connected to the wiring portion 12b2 on its short side 11d and extends from its long side 11a to the chip bonding portion 12a2 of the wiring board 12a. In addition, the -Y direction (short side 11d) side of the lateral connection portion 12b3 is connected to the wiring portion 12b2 and the vertical connection portion 12b4. The +Y direction (short side 11b) side of the lateral connection portion 12b3 extends to the wiring board 12d.

[0104] Even with the shape of the wiring boards 12a and 12b in semiconductor unit 2, the vertical connection portions 12b4 and 12c4 have slits 12b5 and 12c5 formed along the longer sides 11a and 11c from the ends on the output portion 12b1 and 12c1 side. As a result, the current output from the semiconductor chips 30a and 30d, which are located closest to the terminal junction region 12a6, passes through the vertical connection portions 12b4 and 12c4 and the horizontal connection portions 12b3 and 12c3 before reaching the output portions 12b1 and 12c1 of the wiring boards 12b and 12c. In other words, the current path from the semiconductor chips 30a and 30d to the output portions 12b1 and 12c1 of the wiring boards 12b and 12c is lengthened. Therefore, the difference between this current path and the current path from the semiconductor chips 30c and 30f, which are located furthest from the terminal junction region 12a6, to the output portions 12b1 and 12c1 of the wiring boards 12b and 12c becomes smaller. Consequently, current imbalances in parallel-connected semiconductor chips 30a to 30c and 30d to 30f, depending on their distance from the terminal junction region 12a6, can be suppressed. As a result, unevenness in losses for each current path is suppressed, the lifespan of the semiconductor device 1 is extended, and the reliability of the semiconductor device 1 is improved.

[0105] The shape and arrangement of the wiring boards 12a to 12d of the insulating circuit board 10 included in the semiconductor unit 2 of this modified example 2 are also symmetrical with respect to the center line C shown in Figure 11. Furthermore, the semiconductor chips 30a to 30c, 30d to 30f placed on the wiring board 12a are also arranged to be symmetrical with respect to the center line C shown in Figure 11. [Explanation of Symbols]

[0106] 1 Semiconductor device 2,2a,2b,3,3a,3b Semiconductor Unit 4 cabinets 5 Outer frame 5a,5c Long side 5b,5d short side 5e~5h corner 5i~5l Unit Storage Area 6a, 6b Control terminals 7a, 7b Connecting wires 8a, 8b, 8c External connection terminals 9 Sealing member 10 Insulated circuit board 11 Insulating board 11a, 11c Longer side 11b, 11d Short side 11e~11h corner 12a Wiring board (1st input wiring board) 12a1 Input section 12a2 Chip bonding area 12a3,12a4 protruding part 12a6 Terminal joining area 12b,12c wiring board (1st output wiring board) 12b1,12c1 output part 12b2,12c2 wiring part 12b3, 12c3 lateral connection section 12b4, 12c4 Vertical connection section 12b5, 12c5 slit 12b6,12c6 terminal joining area 12b7,12c7 1st output area 12d Wiring board (1st control wiring board) 13 Metal plate 14a Control wire 14b Main current wire 15 Heat dissipation base plate 16 Joining members 20 Insulated Circuit Boards 21 Insulating board 21a, 21c Longer side 21b, 21d Short side 21e~21h corner 22a Wiring board (2nd output wiring board) 22a1 Output part 22a2 wiring part 22a3 Lateral connection section 22a4, 22a5 Vertical connection section 22a6, 22a7 Slit 22a8 Terminal joining area 22b Wiring board (Second input wiring board) 22b1 Chip bonding area 22b9,22b10 Second input region 22d Wiring board (Second control wiring board) 23 Metal plate 24a Control wire 24b Main current wire 26 Joining members 30a~30f semiconductor chips 31 Control electrode 32 Output electrode (main electrode) 33 Input electrode (main electrode) 40a~40f semiconductor chips 41 Control electrode 42 Output electrode (main electrode) 43 Input electrode (main electrode)

Claims

1. It includes a first arm portion and a second arm portion provided adjacent to the first arm portion, The first arm portion is, Multiple first semiconductor chips, each having input electrodes on the back and output electrodes on the front, A first insulating circuit board comprising: a rectangular first input wiring board having a first side, a second side, a third side, and a fourth side in that order and extending parallel to the first side; and a first output wiring board disposed on at least one of the first side side and the third side side of the first input wiring board and extending parallel to the first side; The first input wiring board comprises a first input region electrically connected to the input terminal and located on the fourth side, and a first chip bonding region located on the second side where the plurality of first semiconductor chips are bonded. The first output wiring board includes a first output region on the fourth side that is electrically connected to a first output terminal, and extends along the first or third side toward the second side to a position corresponding to the plurality of first semiconductor chips, and includes a first connection wiring region on the second side that is electrically connected to the output electrodes of the plurality of first semiconductor chips. The second arm portion is, Multiple second semiconductor chips, each having input electrodes on the back and output electrodes on the front, A second insulating circuit board includes a rectangular second output wiring board having a fifth, sixth, seventh, and eighth side in that order and extending parallel to the fifth side, and a second input wiring board positioned on the fifth and eighth side of the second output wiring board and extending parallel to the fifth side, The second input wiring board comprises a second input region electrically connected to the first output region on the sixth side, and a second chip bonding region arranged on the second output wiring board side to which the plurality of second semiconductor chips are bonded. The second output wiring board has a second output region on the sixth side that is electrically connected to the second output terminal, and a second connection wiring region on the second input wiring board side that is electrically connected to the output electrodes of the plurality of second semiconductor chips. The second arm portion is adjacent to the first arm portion, with the sixth side facing the fourth side of the first arm portion. The first input region, the first output region, and the second output region are located on the boundary side between the fourth side and the sixth side. Semiconductor equipment.

2. The first input wiring board is arranged in a T-shape in a plan view. The semiconductor device according to claim 1.

3. The first input wiring board is arranged in a T-shape in a plan view, The second input wiring board is arranged in a U-shape in plan view, surrounding the fifth, eighth, and seventh sides of the second output wiring board. The semiconductor device according to claim 1.

4. The first output wiring board is provided on the first side and the third side of the first input wiring board, respectively. The input terminals joined to the terminal joining area of ​​the first input region are positioned in a location sandwiched between the first output terminals joined to the terminal joining area of ​​the first output wiring board in the direction parallel to the fourth and sixth sides. The semiconductor device according to claim 3.

5. The second output terminal, which is joined to the terminal joining region of the second output region, is positioned between the first output terminal in a side view in a direction perpendicular to the parallel direction. The semiconductor device according to claim 4.

6. The first arm portion and the second arm portion include a plurality of, The semiconductor device according to claim 1.

Images