Ultrasonic motor starting device and method based on ultra-high performance index output

Abstract

The present invention provides an ultrasonic motor starting device and method based on an index output with high performance, which relates to the field of ultrasonic motor starting. The device includes a two-input AND gate having a first input terminal, a second input terminal and an output terminal, and the first input terminal is T i It is used to input the timing signal, and the second input terminal is connected to the pulse output terminal of the division counter, the output terminal of the AND gate is connected to the input terminal of the D flip-flop, the clock terminal of the D flip-flop is connected to the clock terminal of the division counter, and receives the CLOCK clock, the CLOCK clock is the system clock, the output terminal of the D flip-flop is connected to the clock terminal of the latch, and the input terminal of the latch is i DATA is used to receive the division value, F i The DATA division value is the time length T i The multi-channel data output terminal of the latch is connected to the data input terminal of the frequency divider counter, and the output terminal of the frequency divider counter outputs a SIN driving signal or a COS driving signal. The present invention can improve the safety and reliability of ultrasonic motor starting.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to a Chinese patent application filed with the China Patent Office on October 26, 2023, bearing application number 2023114106053 and titled "Ultra-high performance index output-based ultrasonic motor starting device and starting method," the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to the technical field of starting an ultrasonic motor, and more particularly to a starting device and method for an ultrasonic motor based on an ultra-high performance index output. [Background technology]

[0003] Ultrasonic motors feature friction drive, self-locking when powered off, fast response, a large torque-to-mass ratio, and no electromagnetic interference. After debugging the parameters of a traveling-wave ultrasonic motor and completing mechanical property tests, and after a certain period of time (as short as 10 minutes or as long as several months or years), the ultrasonic motor may occasionally fail to start properly for unknown reasons when first turned on, or may fail to start properly no matter how it is subsequently turned on. This phenomenon severely limits the research, development, and engineering applications of traveling-wave ultrasonic motor technology in unmanned areas such as aviation, aerospace, medical care, marine, vehicles, deep seas, and nuclear power, where 99.99% safety and reliability are required. Currently, starting methods for traveling-wave ultrasonic motors include the linear frequency sweep method (see Figure 1) and the boost method (see Figure 2). While these methods can solve the starting problems of traveling-wave ultrasonic motors, their safety and reliability are relatively poor, at only around 90%, making them suitable for general consumer applications. Summary of the Invention [Problem to be solved by the invention]

[0004] Based on this, the present invention aims to provide a starting device and a starting method for an ultrasonic motor based on an ultra-high performance index output, which solves the problem of low safety and reliability when starting an ultrasonic motor. [Means for solving the problem]

[0005] To achieve the above object, the present invention provides an ultra-high performance index output-based ultrasonic motor starting device, which includes a two-input AND gate, a D flip-flop, a latch, and a frequency divider counter; The two-input AND gate includes a first input terminal, a second input terminal, and an output terminal, and the first input terminal is T i Used to input timing signals, i The timing signal has a duration of T i a trigger level signal of a segment, the second input terminal of which is connected to the pulse output terminal of the divide-by counter, and the output terminal of the two-input AND gate is connected to the input terminal of the D flip-flop; The clock end of the D flip-flop is connected to the clock end of the divide-by counter and receives a CLOCK clock, where the CLOCK clock is a system clock, and the output end of the D flip-flop is connected to the clock end of the latch; The input of the latch is F i DATA is used to receive the division value, i The DATA division value is the time length T i The input signal of the segment, the multi-channel data output terminal of the latch is connected to the data input terminal of the divide-by-counter; The output terminal of the frequency divider counter outputs a SIN driving signal or a COS driving signal; The clock edge of the D flip-flop is synchronized with the CLOCK clock. i When the timing signal is at a high level of "1", the two-input AND gate iThe timing signal and the "1" pulse level output from the pulse output terminal of the frequency division counter are ANDed and then input to the input terminal of the D flip-flop. At the same time, the output terminal of the D flip-flop outputs a rising edge, and the F i-1 The DATA division value is the F i The DATA frequency division value is forcibly switched to, and the latch is held until the next rising edge of the output terminal of the D flip-flop, completing one zero phase synchronization time difference operation. At the same time, the output terminal of the frequency division counter outputs the SIN drive signal and the COS drive signal, completing one half-fold frequency difference operation. Starting from the upper limit drive signal frequency, it jumps to the operating frequency of the ultrasonic motor according to the zero phase synchronization time difference operation and the half-fold frequency difference operation, and completes the startup.

[0006] In order to achieve the above object, the present invention also provides a starting method for an ultrasonic motor based on an ultra-high performance index output, the starting method comprising: Control the CLOCK clock to make it the clock signal of the clock end of the D flip-flop and the clock end of the frequency division counter; T i The timing signal is controlled as an enable signal of a two-input AND gate, and under the action of the CLOCK clock synchronization sequence, the T i When the timing signal is at a high level of "1", the two-input AND gate i The timing signal and the "1" pulse level output from the pulse output terminal of the frequency division counter are ANDed, and then input to the input terminal of the D flip-flop; Current time F i The DATA frequency division value is controlled as an input signal to the input terminal of the latch, and when the clock terminal of the latch receives a rising edge output from the output terminal of the D flip-flop, the multi-channel data output terminal of the latch outputs the F i-1 The DATA division value is input to the input terminal of the latch. iForcefully switch to the DATA division value, and the latch will be held until the next rising edge of the output terminal of the D flip-flop, completing one zero phase synchronization time difference operation; The CLOCK clock is controlled to receive F of the current time input from the data input terminal of the frequency division counter. i According to the DATA frequency division value, after frequency division logic operation, the output terminal of the frequency division counter outputs a SIN driving signal or a COS driving signal, thereby completing one halving frequency difference operation; Starting from the upper limit driving signal frequency, it jumps to the operating frequency of the ultrasonic motor according to the zero phase synchronous time difference operation and the two equal division folded frequency difference operation, and then the start-up is completed.

[0007] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects. The present invention is based on the CLOCK clock synchronization sequence. i When the timing signal is high, "1", the two-input AND gate i The timing signal and the "1" pulse level output from the pulse output terminal of the divider counter are ANDed and then input to the input terminal of the D flip-flop. At the same time, the output terminal of the D flip-flop outputs a rising edge, and the F i-1 The DATA division value is the F of the current time input to the input terminal of the latch. i The DATA frequency division value is forcibly switched to, and the latch is held until the next rising edge of the output terminal of the D flip-flop, completing one zero-phase synchronization time difference operation. At the same time, the output terminal of the frequency division counter outputs the SIN drive signal and the COS drive signal, completing one half-fold frequency difference operation. Starting from the upper limit drive signal frequency, it jumps through the zero-phase synchronization time difference operation and the half-fold frequency difference operation until it reaches the operating frequency of the ultrasonic motor, completing the startup. A safe and reliable startup process can be completed in about four steps, and the present invention improves the startup safety and reliability of traveling wave ultrasonic motors from the initial 90% to over 99.99%. [Brief explanation of the drawings]

[0008] In order to more clearly describe the embodiments of the present invention or the technical solutions of the prior art, the drawings used in the embodiments are briefly introduced below. Obviously, the drawings in the following description are only a part of the drawings, and for the embodiments of the present invention, those skilled in the art can obtain other drawings based on these drawings without any creative efforts. [Figure 1] FIG. 10 is a waveform schematic diagram of a linear frequency modulation start-up process. [Figure 2] FIG. 10 is a waveform schematic diagram of the boost start-up process. [Figure 3] 1 is a structural schematic diagram of the synchronous sequential logic function of the SIN driving signal of an embodiment of the present invention; [Figure 4] FIG. 10 is a schematic diagram of the logic timing of the zero phase synchronization time difference Δti according to an embodiment of the present invention. [Figure 5] FIG. 10 is a schematic diagram of a process waveform of a SIN drive signal frequency hopping. DETAILED DESCRIPTION OF THE INVENTION

[0009] The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, but obviously, the described embodiments are only a part of the embodiments of the present invention, and are not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present invention.

[0010] SUMMARY OF THE INVENTION An object of the present invention is to provide a starting device and a starting method for an ultrasonic motor based on an ultra-high performance index output that can improve safety and reliability when starting an ultrasonic motor.

[0011] In order to make the above objects, features and advantages of the present invention more clearly understandable, the present invention will be described in more detail below with reference to the drawings and specific embodiments.

[0012] Example 1 As shown in FIG. 3, the present invention provides a super-high performance index output-based ultrasonic motor starter device, which is characterized by including a two-input AND gate 1, a D flip-flop 2, a latch 3 and a divide-by counter 4.

[0013] The two-input AND gate 1 includes a first input terminal, a second input terminal, and an output terminal, and the first input terminal is T i Used to input timing signal 5, i The timing signal 5 has a time duration T i It is a trigger level signal of a segment, and the second input terminal is connected to the pulse output terminal (TC terminal) of the frequency divider counter 4, and the output terminal is connected to the input terminal of the D flip-flop 2 (D terminal).

[0014] The clock terminal (CK terminal) of the D flip-flop 2 is connected to the clock terminal (CK terminal) of the frequency divider counter 4, and receives the CLOCK clock 6, which is the system clock. The output terminal (Q terminal) of the D flip-flop 2 is connected to the clock terminal (CK terminal) of the latch 3.

[0015] The input terminal (D terminal) of the latch 3 is F i Used to receive DATA divider value 7, F i The DATA division value 7 is the time length T i The input signal of the segment is the multi-channel data output terminal (Q n The F i The DATA division value 7 is also the timing length T i The predetermined division ratio of the segment.

[0016] The output terminal (OUT terminal) of the frequency divider counter 4 outputs a SIN drive signal or a COS drive signal (denoted as SIN or COS in FIG. 3).

[0017] The clock edge of the D flip-flop 2 is synchronized with the CLOCK clock 6, and the Ti When the timing signal 5 is at a high level of "1", the two-input AND gate 1 i The timing signal 5 and the "1" pulse level output from the pulse output terminal of the frequency divider counter 4 are ANDed and then input to the input terminal of the D flip-flop 2. At the same time, the output terminal of the D flip-flop 2 outputs a rising edge, and the F of the previous time output from the multi-channel data output terminal of the latch 3 is i-1 The DATA division value is input to the input terminal of the latch 3. i The DATA frequency division value is forcibly switched to 7, and the latch is held until the next rising edge of the output terminal of the D flip-flop 2, completing one zero phase synchronization time difference operation. At the same time, the output terminal of the frequency division counter 4 outputs the SIN drive signal and the COS drive signal, completing one half-fold frequency difference operation, starting from the upper limit drive signal frequency, and jumping to the operating frequency of the ultrasonic motor according to the zero phase synchronization time difference operation and the half-fold frequency difference operation, completing the start-up.

[0018] Here, the T i The timing length of the timing signal 5 refers to the length of time required for each change in the frequency of the drive signal. As shown in FIG. 5, the frequencies of the SIN drive signal and the COS drive signal are f0 frequency in the T0 time period, f1 frequency in the T1 time period, f2 frequency in the T2 time period, ..., T n In the time zone n It is the frequency.

[0019] T i The length of the time period may be a few milliseconds, tens of milliseconds, or even longer, and can be determined through experimental studies and application scenarios.

[0020] f i The frequency value change rule (i.e., frequency hopping f0, f1, f3...f n and the folding frequency difference Δf i ) and f i-1 is f i (i.e., zero phase synchronization time difference Δti ) is a safe and reliable startup method that needs to be implemented in an embodiment of the present invention.

[0021] Zero phase synchronization time difference Δt i : The frequency of the drive signal is f i-1 From f i If you want to jump to i-1 Period and f i The ratio of the periods is not an integer, so the T i +Δt i Synchronous zero phase compensation time Δt i (See Figure 4) and the time Δt i is one of the keys to a safe and reliable startup.

[0022] Frequency hopping f0, f1, f3…f n and the folding frequency difference Δf i : The operating frequency of the ultrasonic motor is F w (or operating frequency <F h ), the first load frequency f0 is the upper limit drive signal frequency F at the minimum effective rotation speed of the ultrasonic motor. h Then, the frequency of the second jump drive signal f1=f0+Δf0=f0+(F h -F w ) / 2, the frequency of the third jump drive signal f2=f1+Δf1=f1+(f1-F w ) / 2,..., Nth jump drive signal frequency f n =f n-1 +Δf n-1 =f n-1 +(f n-1 -F w ) / 2, where F w indicates the operating frequency of the ultrasonic motor.

[0023] Bisecting folding frequency difference Δf i Since decreases biexponentially, f i By changing the ultrasonic motor for each frequency value, the rate of change of rotation speed tends to be constant, further improving safety and reliability at startup. iand the folding frequency difference Δf i Under the combined effect of these factors, the starting safety and reliability of the traveling wave ultrasonic motor can reach 99.99% or even higher.

[0024] In practical application, the two-input AND gate 1 is an AND logic gate circuit with two inputs and one output.

[0025] In practical application, the D flip-flop 2 is a data trigger logic circuit. When the input clock CK is triggered by a rising edge pulse, the level value of the data output Q is determined by the level value of the data input D. Otherwise, the level value of the Q remains unchanged and is not affected by the level value of the D.

[0026] In practical application, the latch 3 is a multi-channel data synchronization trigger logic circuit. When a rising edge pulse is triggered at the input clock CK edge, the multi-channel data output Q n The level value of the Q terminal is determined by the level value of the multi-channel data input D terminal. n F on the edge i DATA value is D end F i The DATA value is equal to the other input clock CK edge state. n The level value at the D end does not change and is not affected by the level value at the D end. n F on the edge i-1 DATA value is F at D terminal i It is unrelated to the DATA value.

[0027] In practical application, the divide-by-counter 4 is a kind of down counter logic circuit. When a rising edge pulse is triggered at the input clock CK end, the divide-by-counter 4 counts the input data F at the D end. i-1 Performs subtraction based on the value of DATA.

[0028] The count value of divider counter 4 is F i-1 The level value at the output data OUT terminal is the "0" level value.

[0029] The count value of divider counter 4 is F i-1 The value is equal to or greater than DATA / 2, and the level value at the output data OUT terminal is a "1" level value.

[0030] The count value of divider counter 4 is F i-1 If it is equal to the DATA value, the counter count value is the input data F at the D terminal. i The DATA value is reloaded, and the TC end outputs a pulse with the same period as the input clock CK end.

[0031] In other input clock CK end states, the level value of the OUT end does not change and is not affected by the input data value of D end. At this time, the level value of the OUT end is unrelated to the input data value of D end, and the output pulse TC end maintains the "0" level value.

[0032] Example 2 The present invention also provides an ultra-high performance index output based ultrasonic motor starting method, including: The CLOCK clock 6 is controlled to generate a clock signal at the clock end of the D flip-flop 2 and the clock end of the frequency divider counter 4. The clock signal has a zero phase synchronization time difference Δt i and the folding frequency difference Δf i provides synchronous sequential logic to

[0033] T i The timing signal 5 is used as an enable signal for the two-input AND gate 1, and under the action of the CLOCK clock 6 synchronous sequence, the T i When the timing signal 5 is at a high level of "1", the two-input AND gate 1 i The timing signal 5 and the “1” pulse level output from the pulse output terminal of the frequency divider counter 4 are ANDed and then input to the input terminal of the D flip-flop 2 .

[0034] Current time F iThe DATA frequency division value 7 is controlled as an input signal to the input terminal of the latch 3, and when the clock terminal of the latch 3 receives a rising edge output from the output terminal of the D flip-flop 2, the multi-channel data output terminal of the latch 3 outputs the F i-1 The DATA division value is input to the input terminal of the latch 3 at the current time F i The DATA frequency division value is forcibly switched to 7, and the latch is held until the next rising edge of the output terminal of the D flip-flop 2, completing one zero phase synchronization time difference operation.

[0035] The CLOCK clock 6 is controlled to receive the F of the current time input from the input terminal of the frequency division counter 4. i After performing a frequency division logic operation based on the DATA frequency division value 7, the output terminal of the frequency division counter 4 outputs a SIN driving signal or a COS driving signal, completing one cycle of a frequency difference folding operation by dividing the frequency by two.

[0036] Starting from the upper limit driving signal frequency, it jumps to the operating frequency of the ultrasonic motor according to the zero phase synchronous time difference operation and the two equal division folded frequency difference operation, and then the start-up is completed.

[0037] In practical application, the output terminal of the divide-by-counter 4 outputs a SIN driving signal or a COS driving signal with a duty cycle of 1:1.

[0038] The CK end of the D flip-flop 2 of the present invention is synchronized with the CLOCK clock 6, and the T i Whenever the timing signal 5 becomes "1" high level and the TC terminal of the division counter 4 outputs a pulse, the rising edge of the Q terminal of the D flip-flop 2 is used to set the Q terminal of the latch 3 output. n Edge original data F i-1 The DATA division value is the current data F at the D terminal of the latch 3 input. i The DATA divider value is forced to switch to 7, completing the zero-phase synchronous sequential logic operation for the SIN drive signal. Similarly, the zero-phase synchronous sequential logic operation for the COS drive signal is completed sequentially. The upper limit drive signal frequency F hStarting from zero phase synchronization time difference Δt i and the folding frequency difference Δf i According to the rule, the operating frequency F of the ultrasonic motor w By jumping to the next step, the safe and reliable startup process can be completed in about four steps, and the present invention improves the startup safety and reliability of traveling wave ultrasonic motors from the initial 90% to over 99.99%.

[0039] Each embodiment in this specification will focus on the differences between each embodiment and other embodiments, and similar parts between the embodiments may be referred to as "same" or "same" parts.

[0040] In this specification, specific examples are used to explain the principles and implementation methods of the present invention, and the description of the above embodiments is only used to understand the method of the present invention and its core concept, and at the same time, those skilled in the art will make changes to the specific implementation and application scope based on the concept of the present invention. In summary, the content of this description should not be construed as limiting the present invention.

Claims

1. It includes a two-input AND gate, a D flip-flop, a latch and a divide-by counter, The two-input AND gate includes a first input terminal, a second input terminal, and an output terminal, and the first input terminal is T ｉ It is used to input a timing signal, and the T ｉ The timing signal has a time length T ｉ A trigger level signal of a segment, the second input terminal of which is connected to the pulse output terminal of the frequency division counter, and the output terminal of the two-input AND gate is connected to the input terminal of the D flip-flop; The clock end of the D flip-flop is connected to the clock end of the divide-by counter and receives a CLOCK clock, where the CLOCK clock is a system clock, and the output end of the D flip-flop is connected to the clock end of the latch; The input of the latch is F ｉ DATA division value, and ｉ The DATA division value is the time length T ｉ The input signal of the segment, the multi-channel data output terminal of the latch is connected to the data input terminal of the divide-by-counter; The output terminal of the frequency divider counter outputs a sine drive signal or a cosine drive signal; The clock edge of the D flip-flop is synchronized with the CLOCK clock. ｉ When the timing signal is at a high level of "1", the two-input AND gate ｉ The timing signal and the "1" pulse level output from the pulse output terminal of the frequency division counter are ANDed and then input to the input terminal of the D flip-flop. At the same time, the output terminal of the D flip-flop outputs a rising edge, and the F of the previous time output from the multi-channel data output terminal of the latch is ｉ－１ The DATA frequency division value is input to the input terminal of the latch. ｉ The ultra-high performance index output-based ultrasonic motor starting device is characterized in that: the DATA frequency division value is forcibly switched to, and the latch is held until the next rising edge of the output terminal of the D flip-flop, completing one zero phase synchronization time difference operation; at the same time, the output terminal of the frequency division counter outputs a sine drive signal and a cosine drive signal, completing one half-fold frequency difference operation; starting from the upper limit drive signal frequency, and jumping to the operating frequency of the ultrasonic motor according to the zero phase synchronization time difference operation and the half-fold frequency difference operation, thus completing the starting.

2. The D flip-flop is a data trigger logic circuit, and when the clock edge of the D flip-flop is triggered by a rising edge pulse, the level value of the output terminal of the D flip-flop is determined by the level value of the input terminal of the D flip-flop; 2. The method for starting an ultrasonic motor based on an ultra-high performance index output according to claim 1, wherein when a rising edge pulse trigger is not input to the clock end of the D flip-flop, the level value of the output end of the D flip-flop remains unchanged.

3. The latch is a multi-channel data synchronization trigger logic circuit, and when the clock edge of the latch is triggered by a rising edge pulse, the level value output by the multi-channel data output terminal of the latch is determined by the latch. At this time, F ｉ The DATA division value is F ｉ Equal to the DATA division value, The method for starting an ultrasonic motor based on an index output with ultra-high performance as claimed in claim 1, characterized in that if the clock end of the latch does not receive a rising edge pulse trigger, the level value of the multi-channel data output end of the latch does not change.

4. The divide-by counter is a logic circuit of a down counter, When a clock edge of the divide-by counter is triggered by a rising edge pulse, the divide-by counter is set to the F value at the time before the input edge of the D flip-flop. ｉ－１ Subtract 1 based on the DATA division value, The count value of the frequency division counter is F ｉ－１ DATA / 2, and the level value of the output terminal of the frequency division counter is a "0" level value; The count value of the frequency division counter is F ｉ－１ DATA / 2 or more, and the level value of the output terminal of the frequency division counter is a "1" level value; The count value of the frequency division counter is F ｉ－１ When the count value of the frequency division counter is equal to the current time F of the input terminal of the D flip-flop, ｉ Reload the DATA division value, and the pulse output terminal of the division counter outputs a pulse with the same period as the clock terminal of one of the division counters; If the clock edge of the divide-by counter does not receive a rising edge pulse trigger, the level value of the output end of the divide-by counter will not change, and the F input to the input end of the D flip-flop will ｉ 2. The method for starting an ultrasonic motor based on an index output with ultra-high performance as claimed in claim 1, wherein the pulse output terminal of the frequency division counter maintains a "0" level value regardless of the DATA frequency division value.

5. A method for applying to an ultrasonic motor starting device based on an ultra-high performance index output according to any one of claims 1 to 4, the starting method including: Control the CLOCK clock to make it the clock signal of the clock end of the D flip-flop and the clock end of the frequency division counter; T ｉ The timing signal is controlled as an enable signal of a two-input AND gate, and under the action of the CLOCK clock synchronization sequence, the T ｉ When the timing signal is at a high level of "1", the two-input AND gate ｉ The timing signal and the "1" pulse level output from the pulse output terminal of the frequency division counter are ANDed, and then input to the input terminal of the D flip-flop; Current time F ｉ The frequency division value of DATA is controlled as an input signal to the input terminal of the latch, and when the clock terminal of the latch receives a rising edge output from the output terminal of the D flip-flop, the multi-channel data output terminal of the latch outputs the F of the previous time. ｉ－１ The DATA frequency division value is input to the input terminal of the latch at the current time F ｉ The DATA frequency division value is forcibly switched to, and the latch is held until the next rising edge of the output terminal of the D flip-flop, completing one zero phase synchronization time difference operation; The clock signal is controlled to generate the F of the current time input from the data input terminal of the frequency division counter. ｉ According to the DATA frequency division value, after frequency division logic operation, the output terminal of the frequency division counter outputs a sine wave driving signal or a cosine wave driving signal, thereby completing one half-folding frequency difference operation; The method for starting an ultrasonic motor based on an index output with ultra-high performance is characterized in that it includes: starting from an upper limit driving signal frequency, and according to the zero phase synchronization time difference operation and the two-equal folding frequency difference operation, jumping to the operating frequency of the ultrasonic motor, and completing the starting.

6. 6. The method for starting an ultrasonic motor based on an index output with ultra-high performance as claimed in claim 5, wherein the output terminal of the frequency divider / counter outputs a sine wave driving signal or a cosine wave driving signal with a duty cycle of 1:1.

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