Topologically-enabled charge transport devices for room-temperature applications
Capacitive MIS structures with topological phases enable high-density charge storage and supercurrents at room temperature, addressing the limitations of classical devices by inducing topological electronic states in semiconductors, thereby achieving efficient charge transport and quantum Hall phenomena.
Patent Information
- Application Number
- JP2025521982
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-10-28
- Filing Date
- 2023-10-30
- Publication Date
- 2026-01-06
AI Technical Summary
Existing charge storage and transport devices require extremely low temperatures or strong magnetic fields to exhibit nonclassical electrical effects, limiting their practical application at room temperature.
The development of capacitive MIS structures that induce topological phases through electric and/or magnetic field distributions, enabling charge storage and transport with significantly higher densities and supercurrents at room temperature, utilizing in-plane and out-of-plane electrical biasing to form topological electronic states in semiconductors.
These devices achieve anomalously high charge storage and current transport densities, supporting supercurrents up to 1000 Amperes/cm² without damage, and demonstrate quantum Hall phenomena at room temperature without a large magnetic field, enhancing energy and power density performance.
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Abstract
Description
[Technical Field]
[0001] The present invention relates to charge storage and transport devices. [Background technology]
[0002] It is well known in the art that nonclassical electrical effects, such as superconductivity and the quantum Hall effect, require extremely low temperatures, strong magnetic fields, or both. Although various theoretical proposals have been made regarding the possibility of nonclassical electrical effects at room temperature, few experimental demonstrations have been performed to date. Therefore, providing nonclassical electrical effects at room temperature would be an advancement in the art. Summary of the Invention [Means for solving the problem]
[0003] The present inventors have found experimental evidence of non-classical behavior in capacitive MIS (metal-insulator-semiconductor) structures. In particular, the present inventors' experimental results reveal that the charge storage, charge release, and current transport at room temperature are much higher (i.e., orders of magnitude higher) than would be expected for the classical capacitance of MIS structures.
[0004] Without being bound by theory, it is currently believed that in these and similar geometries, certain electric and / or magnetic field distributions can transform conventional electron charges with random phases into states of matter with topological phases. Finite element simulations using Maxwell's equations reveal that the polarization of transient electric and / or magnetic fields induces regions of high electron density, which in turn leads to topological surface states. Topological electronic phases are characterized by nontrivial topological invariants and represent states of matter with unique physical properties. For example, Maxwell's equations, which govern the behavior of conventional charges and their associated electric and magnetic fields, are modified in the presence of topological phases. The emergence of such topological phases has been suggested by density functional theory simulations, which lead to nontrivial topological invariants.
[0005] Such topological phases enhance charge storage, enabling the creation of topological capacitors with higher releasable charge densities compared to conventional capacitors. Electronic charge can be stored and removed upon voltage reversal. The charge removed is significantly higher than conventional capacitors. The density of charge removed from smaller elements is higher than that removed from larger elements.
[0006] The topological phase difference in these capacitors leads to the formation of a supercurrent to balance the phase difference between the anode and cathode. Such a supercurrent can reach 1000 Amperes / cm² without any observed damage to the sample. 2The current density can significantly exceed 100 volts. Finite element method (FEM) calculations have shown that conventional charge transport with the observed supercurrent densities would result in immediate melting of the sample. In contrast, the disclosed capacitors are capable of delivering high current density pulses without any apparent damage observed. Furthermore, in contrast to conventional capacitive elements, the disclosed capacitors are capable of delivering higher density current pulses with smaller elements compared to current pulses with larger elements. Conventional capacitive currents, as observed here, scale with area, but not across the entire area.
[0007] Thus, for the remainder of this specification, a "topological state" is defined phenomenologically such that any capacitance element in which charge storage, charge release, and / or current transport at room temperature is at least 10 times greater than that expected for the corresponding classical capacitance is considered to have a "topological state" responsible for these remarkable observations. Furthermore, the inventors believe that the observation of quantum Hall phenomena at room temperature and in the absence of a large magnetic field is a sign of the existence of a topological state.
[0008] The present disclosure provides significant advantages. Energy density and power density devices currently have limited performance. The disclosed architecture can significantly improve both. Josephson-like transport is known to occur only at cryogenic temperatures. Devices of the present disclosure have demonstrated supercurrents at room temperature. Some devices of the present disclosure have demonstrated currents of at least 1000 Amperes / cm. 2 The current density is shown.
[0009] Previous experiments by the present inventors have uncovered unusually high charge storage behavior in devices called "all-electron batteries." An exemplary reference for this experiment is U.S. patent application Ser. No. 12 / 798,102, filed March 29, 2010. However, the idea of utilizing in-plane and out-of-plane electrical biasing of a low-dimensional electron gas to form topological electronic states in semiconductors at room temperature is not explored in U.S. patent application Ser. No. 12 / 798,102. [Brief explanation of the drawings]
[0010] [Figure 1-1] 1(A)-(D) show a schematic diagram of the operation of a non-classical MIS device according to the principles of the present invention. [Figure 1-2] 1(A)-(D) show a schematic diagram of the operation of a non-classical MIS device according to the principles of the present invention. [Figure 1-3] 1(A)-(D) show a schematic diagram of the operation of a non-classical MIS device according to the principles of the present invention. [Figure 2A] 2A and 2B show a non-classical MIS device configured to exhibit lateral supercurrent flow. [Figure 2B] 2A and 2B show a non-classical MIS device configured to exhibit lateral supercurrent flow. [Figure 3] FIG. 3 is an exemplary IV curve showing the transverse supercurrent. [Figure 4A] 4A and 4B show schematically two options for lateral transport using non-classical MIS element operation. [Figure 4B] 4A and 4B show schematically two options for lateral transport using non-classical MIS element operation. [Figure 5A] 5A and 5B show the effect of disturbing the operation of a non-classical MIS device on lateral current transport. [Figure 5B] 5A and 5B show the effect of disturbing the operation of a non-classical MIS device on lateral current transport. [Figure 6] FIG. 6 shows the disturbance of the operation of a non-classical MIS device with voltage fluctuations. [Figure 7A] 7A and 7B show the disturbance of non-classical MIS device operation with temperature fluctuations. [Figure 7B] 7A and 7B show the disturbance of non-classical MIS device operation with temperature fluctuations. [Figure 8A] Figures 8A-D show schematically some options for the control of transverse supercurrents by applied perturbations. [Figure 8B] Figures 8A-D show schematically some options for the control of transverse supercurrents by applied perturbations. [Figure 8C] Figures 8A-D show schematically some options for the control of transverse supercurrents by applied perturbations. [Figure 8D] Figures 8A-D show schematically some options for the control of transverse supercurrents by applied perturbations. [Figure 9] FIG. 9 is a histogram of the measured quantum Hall filling factor, showing a dominant filling factor of 1 / 3. [Figure 10] FIG. 10 shows the measured impedance spectrum of the device in the quantum Hall filling unity regime. DETAILED DESCRIPTION OF THE INVENTION
[0011] Section A describes the general principles of embodiments of the present invention. Section B describes some experimental examples.
[0012] (A) General principle
[0013] An exemplary embodiment of the present invention is a method for providing lateral superconducting transport between two MIS structures, comprising: forming a first low-dimensional electron gas in a first MIS (metal-insulator-semiconductor) structure (e.g., 204 in FIG. 2A), wherein a first applied voltage to the first MIS structure generates first electric field components parallel to the first low-dimensional electron gas and perpendicular to the first low-dimensional electron gas; forming a second low-dimensional electron gas in a second MIS structure (e.g., 206 of FIG. 2A), wherein a second applied voltage to the second MIS structure generates second electric field components parallel to the second low-dimensional electron gas and perpendicular to the second low-dimensional electron gas; and laterally coupling a first MIS structure to a second MIS structure (e.g., via fringe fields 210 of FIG. 2B), wherein the first MIS structure has a first topological state formed by injection of charge carriers, and the second MIS structure has a second topological state formed by injection of charge carriers.
[0014] The disclosed method further includes cycling the applied lateral voltage until lateral transport between the first MIS structure and the second MIS structure exhibits an anomalously low resistance, where "anomalously low resistance" is defined as a resistance that is at least 10 times lower than expected from conventional device physics.
[0015] To block lateral transport, which exhibits anomalously low resistance, a perturbation sufficient to disrupt the topological state may be applied to the first and / or second MIS structures, including an applied electrical bias, an applied temperature increase, an applied magnetic field, an applied electric field, an applied radio frequency signal, and an applied laser beam.
[0016] The first MIS structure can be laterally coupled to the second MIS structure by direct lateral contact (eg, as shown in FIG. 4A).
[0017] Alternatively, a first MIS structure can be laterally connected to a second MIS structure by a connecting element (e.g., as shown in Figure 4B). Here, lateral transport exhibiting anomalously low resistance can be blocked by applying a perturbation to the connecting element sufficient to disrupt the topological state. Suitable perturbations include an applied electrical bias, an applied temperature increase, an applied magnetic field, an applied electric field, an applied radio frequency signal, and an applied laser beam.
[0018] A first topological state can be formed by cycling a voltage applied to a first MIS structure until orthogonal transport through the first MIS structure exhibits one or more characteristics of quantum Hall conduction. Similarly, a second topological state can be formed by cycling a voltage applied to a second MIS structure until orthogonal transport through the second MIS structure exhibits one or more characteristics of quantum Hall conduction.
[0019] More generally, another embodiment of the present invention is a method for forming a topological quantum state in a metal-insulator-semiconductor (MIS) structure, comprising: cycling a voltage to the MIS structure until orthogonal transport through the MIS structure exhibits one or more characteristics of quantum Hall conduction; The MIS structure contains a low-dimensional electron gas, A method in which an applied voltage to the MIS structure generates electric field components parallel to the low-dimensional electron gas and perpendicular to the low-dimensional electron gas.
[0020] Quantum Hall conduction in the MIS structure is observed in the temperature range of 25°C to 40°C in the absence of an applied magnetic field. Supercurrent behavior is observed in the temperature range of 25°C to 40°C, as shown in Figure 7A, suggesting that this anomalous quantum Hall conduction exists in a similar temperature range. Such quantum Hall conduction at room temperature can be observed under a DC bias or an AC bias in the frequency range of 1 Hz to 10 kHz (see Figures 9 and 10).
[0021] (B) Experimental example
[0022] (B1) Non-classical MIS element
[0023] FIG. 1A illustrates an exemplary capacitive element of the present disclosure, including a high-mobility semiconductor 106 and a high-breakdown-strength dielectric 104 formed in a slab shape and sandwiched between a top electrode 102 and a bottom electrode 108. For example, the dielectric 104 can be an alumina / silica / alumina trilayer composite. FIGS. 1B and 1C are cross-sectional views of an element of the present disclosure, showing two components of the applied electric field: an out-of-plane component 114 and an in-plane component 112. These two components arise from fringing electric fields 110, which can induce one-dimensional electronic surface states 116, as shown in FIG. 1B, or two-dimensional electron gas states 118, as shown in FIG. 1C. Note that this importance of fringing fields is an unexpected feature of the elements of the present disclosure, since fringing fields are typically considered parasitic and not present in ideal elements. Standard cleanroom processing techniques can be used to fabricate the insulators, semiconductors, and electrodes of the elements of the present disclosure.
[0024] The present inventors have unexpectedly discovered that devices of the present disclosure, such as the example shown in Figures 1A-C, exhibit quantum charge storage and quantum charge transport properties at room temperature. An applied electric field has both an out-of-plane component 114 and an in-plane component 112, which induce electronic boundary states, as shown in Figures 1B and 1C. A portion of the injected electrons are converted to a topological phase in the form of a one-dimensional electronic surface state or a two-dimensional electron gas state. The devices of the present disclosure operate at room temperature and induce a one-dimensional or two-dimensional electron gas solely through an applied electric field. This results in a unique topological state, or charge-free Majorana phase, as shown in Figure 1D. More specifically, reference numeral 120 in Figure 1D indicates a schematic diagram of a topological state, and reference numeral 122 in Figure 1D indicates a schematic diagram of the corresponding energy-momentum energy band.
[0025] Typical geometric parameters for such an element of the present disclosure are as follows: The dielectric 104 can be an alumina / silica / alumina tri-layer composite with a thickness of 100 nm. The semiconductor layer 106 preferably has a conductivity of at least 0.001 S / cm and typically has a thickness of at least 150 nm. In the example below, the semiconductor 106 is p-doped silicon. Exemplary rectangular elements have widths ranging from 0.2 μm to 250 μm and lengths ranging from 1 μm to 250 μm. Exemplary circular elements have diameters ranging from 2 μm to 100 μm.
[0026] An exemplary charging method involves connecting the positive and negative terminals of a source-measurement unit to the top and bottom electrodes of the device of the present disclosure, respectively. A linear voltage sweep is then applied, starting from 0 V, reaching a maximum voltage of 15 V, and then returning to 0 V. Typical ramp rates for this voltage sweep range from 10 mV / s to 500 mV / s. The current-voltage characteristics of the voltage sweep typically exhibit a "peak current" at a "critical voltage" (i.e., an unusual characteristic in which the current does not increase monotonically with voltage). This critical voltage typically ranges from 3 V to 8 V. The high current characteristic at this critical voltage allows a supercurrent to pass through the sample. A current sweep may also be performed instead of a voltage sweep.
[0027] (B2) Lateral transport
[0028] This disclosure also explores lateral coupling between the two elements described above. Figures 2A and 2B show an example. Reference numeral 204 denotes a central island, and reference numeral 206 denotes a surrounding ring, both of which are elements of the present disclosure and extend vertically. These are fabricated by lithography and etching processes on a highly conductive p-type Si wafer 106 with a conductivity of at least 0.001 S / cm. Figure 2B shows a detailed cross-sectional view. Here, electrodes 102a and 102b are both located on the top, and the associated fringe fields include island-to-island and ring-to-ring fringe fields 110, as well as island-to-ring fringe fields 210. The details of the fringe fields depend primarily on the gap width or distance between the structures. Thus far, non-classical coupling has been experimentally observed for gap widths between two elements ranging from 1 μm to 450 μm. When the gap width is short (e.g., on the order of 1 μm), the adjacent fringe fields 210 become significant. As the gap width increases, there is no influence from the adjacent fringe fields 210. It is currently believed that this is why repeated cycles are required when the gap width is large.
[0029] For a set of two structures, such as ring 206 and island 204 in Figures 2A and 2B, each independently exhibiting high vertical current, charge can be transferred laterally by connecting one structure to ground and applying a bias to the other structure (e.g., using top electrodes 102a and 102b). In this process, high current is observed in both structures, and the current flows laterally over a longer distance with little loss. This phenomenon is not observed if one of the structures does not exhibit high vertical current.
[0030] More specifically, in these examples, the setup for achieving lateral supercurrent begins by individually vertically biasing the central island 204 and the surrounding ring 206 to their respective critical voltages (which may be the same or different) using the semiconductor 106 as the bottom electrode. The electrical connection to the semiconductor 106 is then removed, and a voltage is applied between the two top electrodes (e.g., top electrodes 102a and 102b in FIG. 2B ). Thus, elements 204 and 206 have a memory effect that preserves their nonclassical behavior even when not vertically biased. As explained below, lateral supercurrents depend on these elements being in a nonclassical state; if these states are disturbed (e.g., by a perturbation), the lateral supercurrents are also disturbed.
[0031] Each structure (each element) induces a fringe field 110 for charges passing through it, as shown in Figure 2B. However, the fringe fields interact with each other (210 in Figure 2B), which induces the formation of topological electrons on each element. This current transfer does not occur instantly in all cases. If the distance between the separated structures is long, several in-plane charge transfers are required before the grounded structure exhibits nearly lossless current transfer from the first structure. The number of cycles required to establish current transfer is related to the distance between the structures. For example, at a distance of approximately 450 μm, at least 10 voltage cycles are required.
[0032] When this transfer, measured as current, varies over time, the resulting IV plot shows that the voltage remains relatively stable as the current continues to increase, as shown in Figure 3. This trend continues until the current reaches a maximum value, at which point the voltage essentially oscillates over a small range. Beyond the maximum, the current drops and the voltage reaches the maximum limit of the system measurement unit.
[0033] An exemplary charging method for lateral current conduction is to apply a linear current sweep with a starting current of 0 A, a maximum current ranging from 40 μA to 800 μA, and a ramp rate of 16 nA / s to 16 μA / s. For repeated current sweeps, the sweeps previously used have been sawtooth (i.e., abrupt transitions from maximum current to no current to start the next iteration).
[0034] Figure 3 shows an exemplary IV plot for such a device. Between 4.0 V and 4.8 V, the current continues to increase steadily. Eventually, the current stops increasing once the current exceeds 60 μA.
[0035] Connecting such devices in series can support supercurrent transport at room temperature. To harness supercurrents from surface states or topological surface states, including Majorana modes, multiple capacitors (e.g., 402a, 402b, ...) are connected into a ring, either by contact or using dedicated bridges (e.g., 404a, 404b, ...), as shown in Figures 4A and 4B, respectively. With such connected capacitors, the supercurrent observed in a single capacitor is expected to flow laterally in the in-plane direction through the multiple connected capacitors. In this way, in-plane transport is not limited by the conductivity of the material, but rather by the effectiveness of promoting superconducting surface states.
[0036] It should be noted that the bridges or contact points of successive rings may vary. In particular, having one or more bridges symmetric or asymmetric about the centerline, including overlapping ring structures, may be beneficial for the superconducting propagation mode.
[0037] (B3) Blockade of lateral transport by perturbation
[0038] The applied perturbation destabilizes the protected state, terminating the coherence of the superconducting state. More specifically, the breakdown of the protected state means that one or both of the adjacent semiconductor elements loses the coherence of the superconducting state.
[0039] The behavior of the element with and without communication (i.e., before and after perturbation) is shown in Figures 5A and 5B, respectively.
[0040] Suitable perturbation methods include, but are not limited to, the application or application of an externally generated electric field above a critical voltage, control of the operating temperature, magnetic fields, radio frequencies, and laser beam treatments. Below are two examples:
[0041] As shown in Figure 6, the critical voltage (V critical ) can turn the device off. Alternatively, the device can be turned off by application of high temperature heat, as shown in Figures 7A and 7B. Figure 7A shows that temperatures in the range of 25°C to 40°C turn the device on, and Figure 7B shows that temperatures of 50°C turn the device off.
[0042] 8A-D show schematic examples of how such perturbations can be applied to laterally connected elements. In the example of FIG. 8A, perturbation 802 is applied to the junction between elements 402a and 402b. In the example of FIG. 8B, perturbation 802 is applied to bridge 404 connecting elements 402a and 402b. In the example of FIG. 8C, perturbation 802 is applied directly to one element (element 402a). In the example of FIG. 8D, a multi-ring structure is formed by interconnected elements 804a and 804b, and perturbation 802 is applied to the inner ring of one element (804a).
[0043] (B4) Observation of the quantum Hall effect at room temperature
[0044] By applying a linear DC voltage sweep perpendicular to a metal-insulator-semiconductor (MIS) device, anomalously high currents were generated at several critical voltages due to the formation and transport of topologically charge-free edge / surface states at the conductor / insulator interface. When a constant perpendicular DC bias was applied at these critical voltages, the device exhibited integer and fractional quantum Hall resistances. Figure 9 shows the resistance centered around the fractional quantum Hall state with a quantum Hall filling factor of ν = 1 / 3.
[0045] Another device with the same MIS structure, when perturbed by an AC voltage centered around the vertical critical voltage, also exhibited a resistance value within 0.5% of the integer quantum Hall resistance corresponding to v = 1 due to topological edge / surface states induced by the previous linear voltage and current sweeps. This impedance value remained stable at the quantum Hall resistance level of v = 1 during an AC frequency sweep ranging from 1 Hz to 10 kHz, as shown in Figure 10.
[0046] An exemplary charging method for demonstrating such a quantum Hall effect is as follows. (1) Apply a constant bias voltage at the “critical voltage.” The critical voltages of the two devices shown in this observation were 7.7 V (Fig. 9) and 3.5 V (Fig. 10), respectively. (2) Next, the change in the current response is observed to calculate the resistance (voltage / current) of the element. Alternatively, a small sinusoidal voltage (AC voltage) is applied and different frequencies are swept to obtain the impedance spectrum of the element. Here, the root mean square value of the AC voltage can be in the range of 50 mV to 200 mV at a frequency ranging from 1 Hz to 10 kHz.
Claims
1. 1. A method for providing lateral superconducting transport between two MIS structures, comprising: forming a first low-dimensional electron gas in a first MIS structure, wherein a first applied voltage to the first MIS structure generates first electric field components parallel to the first low-dimensional electron gas and perpendicular to the first low-dimensional electron gas; forming a second low-dimensional electron gas in a second MIS structure, wherein a second applied voltage to the second MIS structure generates second electric field components parallel to the second low-dimensional electron gas and perpendicular to the second low-dimensional electron gas; laterally coupling the first MIS structure to the second MIS structure; the first MIS structure has a first topological state formed by injection of charge carriers; The second MIS structure has a second topological state formed by injection of charge carriers.
2. 10. The method of claim 1, The method further comprises cycling an applied lateral voltage until lateral transport between the first MIS structure and the second MIS structure exhibits an unusually low resistance.
3. 3. The method of claim 2, The method further comprises blocking lateral transport exhibiting anomalously low resistance by applying a perturbation to the first MIS structure and / or the second MIS structure sufficient to disrupt a topological state.
4. 4. The method of claim 3, The method, wherein the perturbation is selected from the group consisting of an applied electrical bias, an applied temperature increase, an applied magnetic field, an applied electric field, an applied radio frequency signal, and an applied laser beam.
5. 10. The method of claim 1, The method wherein the first MIS structure is laterally coupled to the second MIS structure by direct lateral contact.
6. 10. The method of claim 1, The method wherein the first MIS structure is laterally connected to the second MIS structure by a connecting element.
7. 7. The method of claim 6, The method further comprises blocking lateral transport exhibiting anomalously low resistance by applying a perturbation to the connection element sufficient to disrupt the topological state.
8. 8. The method of claim 7, The method, wherein the perturbation is selected from the group consisting of an applied electrical bias, an applied temperature increase, an applied magnetic field, an applied electric field, an applied radio frequency signal, and an applied laser beam.
9. 10. The method of claim 1, The method of claim 1, wherein the first topological state is formed by cycling a voltage applied to the first MIS structure until orthogonal transport through the first MIS structure exhibits one or more characteristics of quantum Hall conduction.
10. 10. The method of claim 1, The second topological state is formed by cycling an applied voltage to the second MIS structure until orthogonal transport through the second MIS structure exhibits one or more characteristics of quantum Hall conduction.
11. 1. A method for forming a topological quantum state in a metal-insulator-semiconductor (MIS) structure, comprising: cycling a voltage to the MIS structure until orthogonal transport through the MIS structure exhibits one or more characteristics of quantum Hall conduction; the MIS structure includes a low-dimensional electron gas; A method wherein an applied voltage to the MIS structure generates electric field components parallel to the low-dimensional electron gas and perpendicular to the low-dimensional electron gas.
12. 12. The method of claim 11, The method wherein the quantum Hall conduction of the MIS structure is observed at a temperature in the range of 25° C. to 40° C. in the absence of an applied magnetic field.
13. 12. The method of claim 11, The quantum Hall conduction is observed under DC or AC bias in the frequency range of 1 Hz to 10 kHz.