MEMORY AND ITS OPERATION METHOD, MEMORY SYSTEM, AND WORD LINE VOLTAGE CONTROL CIRCUIT - Patent application

Abstract

One example of the present application discloses a memory, a method of operating the same, a memory system, and a word line voltage control circuit, the memory including an array of memory cells and peripheral circuitry coupled to the array of memory cells, the array of memory cells including a plurality of word lines, the peripheral circuitry being configured to: begin providing a precharge voltage to a selected word line from the plurality of word lines at a first time, wherein a voltage provided to an unselected word line adjacent to the selected word line is changed from a first voltage to a second voltage at a second time before the first time; and begin floating the selected word line at a third time after the first time, wherein a voltage provided to an adjacent unselected word line is changed from a second voltage to a third voltage at a fourth time before the third time and after the first time, wherein the second voltage is lower than the first voltage and the third voltage.

Description

[Technical Field]

[0001] This application relates to, but is not limited to, memories and methods of operating the same, memory systems, and word line voltage control circuits. [Background technology]

[0002] As memory densities continue to increase, memory cells are characterized by shrinking physical volumes, bringing word lines within a memory cell closer together, increasing capacitive coupling between adjacent word lines. If the number of accesses to a particular row within a memory cell exceeds a threshold, this can cause anomalies in the data in rows adjacent to that row, a phenomenon commonly referred to as row hammer. Summary of the Invention [Means for solving the problem]

[0003] In a first aspect, an example of the present application provides a memory, the memory comprising: an array of memory cells; and peripheral circuitry coupled to the array of memory cells, the array of memory cells including a plurality of word lines, the peripheral circuitry configured to: begin providing a precharge voltage to a selected word line from the plurality of word lines at a first time, wherein a voltage provided to an unselected word line adjacent to the selected word line is changed from a first voltage to a second voltage at a second time before the first time; and begin floating the selected word line at a third time after the first time, wherein a voltage provided to an adjacent unselected word line is changed from the second voltage to a third voltage at a fourth time before the third time and after the first time, wherein the second voltage is lower than the first voltage and the third voltage.

[0004] In a second aspect, an example of the present application provides a memory system including a memory in the manner described above, and a controller coupled to the memory and configured to control the memory.

[0005] In a third aspect, an example of the present application provides a word line voltage control circuit including: a first voltage transfer circuit configured to provide a first transfer voltage in response to a first enable signal before starting to provide a precharge voltage to a selected word line; a second voltage transfer circuit configured to provide a second transfer voltage in response to a second enable signal before starting to float the selected word line and after starting to provide the precharge voltage to the selected word line; and a local word line driver circuit connected to both the first voltage transfer circuit and the second voltage transfer circuit, the driver circuit configured to connect unselected word lines adjacent to the selected word line to the first voltage transfer circuit before starting to provide the precharge voltage to the selected word line and to connect the adjacent unselected word lines to the second voltage transfer circuit before starting to float the selected word line and after starting to provide the precharge voltage to the selected word line.

[0006] In a fourth aspect, one example of the present application provides a method for operating a memory, the method including: beginning, at a first time, providing a precharge voltage to a selected word line from a plurality of word lines of the memory, wherein a voltage provided to an unselected word line adjacent to the selected word line is changed from a first voltage to a second voltage at a second time before the first time; and beginning, at a third time after the first time, floating the selected word line, wherein a voltage provided to the adjacent unselected word line is changed from the second voltage to a third voltage at a fourth time before the third time and after the first time, wherein the second voltage is lower than the first voltage and the third voltage.

[0007] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the accompanying drawings refer to the same or similar parts or elements. The accompanying drawings are not necessarily to scale. It should be understood that these accompanying drawings illustrate only some examples disclosed in accordance with the present application and should not be considered as limiting the scope of the present application. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic structural diagram of an exemplary electronic device 1 including a memory according to an example of the present application. [Figure 2] 1 is a schematic diagram of an exemplary dynamic random access memory according to an example of the present application; [Figure 3] FIG. 2 is a schematic connection diagram of word lines, bit lines, and memory cells of an exemplary dynamic random access memory according to one example of the present application. [Figure 4] FIG. 10 is a timing diagram of the associated signals, word lines, and voltage transfer line voltages when a selected word line is accessed, provided by an example of the present application. [Figure 5] 1 is a structural schematic diagram of a memory provided by an example of the present application; [Figure 6] FIG. 10 is a schematic timing diagram of the voltages on the associated signals, word lines, and voltage transfer lines when a selected word line is accessed, provided by another example of the present application. [Figure 7] FIG. 2 is a schematic diagram of a partial structure of a peripheral circuit provided by an example of the present application. [Figure 8a] 1 is a schematic diagram illustrating the distribution of an array of memory cells and peripheral circuitry in an exemplary memory, according to one example of the present application; [Figure 8b] 1 is a top view schematic diagram illustrating the distribution of an array of memory cells and peripheral circuitry in an exemplary memory, according to one example of the present application. [Figure 9a] FIG. 2 is a schematic diagram illustrating the distribution of an array of memory cells and peripheral circuitry in an exemplary memory, according to another example of the present application. [Figure 9b] FIG. 2 is a top view schematic diagram illustrating the distribution of an array of memory cells and peripheral circuitry in an exemplary memory, according to another example of the present application. [Figure 10] 1 is a schematic flowchart of an implementation of a method for operating a memory provided by an example of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0009] Implementations disclosed in the present application are described in further detail below with reference to the accompanying drawings. While example implementations of the present application are illustrated in the accompanying drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific implementations described herein. Rather, these examples are provided so that the present application may be more fully understood and the scope of the present application may be fully conveyed to those skilled in the art.

[0010] In the following description, numerous specific details are presented to provide a more complete understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other instances, some technical features known in the art are not described to avoid confusion with the present application. That is, not all features of the actual example are described herein, and well-known functions and structures are not described in detail.

[0011] Furthermore, the accompanying drawings are merely schematic diagrams of the present application and are not necessarily drawn to scale. The same reference numerals in the accompanying drawings represent the same or similar parts, and therefore, redundant descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separated entities. These functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0012] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all steps. For example, some steps may be separated, some steps may be integrated or partially integrated, and therefore the actual order of execution may vary according to actual circumstances.

[0013] The terms used herein are for the purpose of describing particular examples only and are not to be construed as limiting the present application. As used herein, the singular forms "a," "an," and "said / the" are intended to include the plural forms unless the context clearly dictates otherwise. Also, as used herein, the terms "consists of" and / or "comprising" should be understood to identify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0014] FIG. 1 is a schematic structural diagram of an exemplary electronic device 1 having a memory according to an example of the present application. The electronic device 1 may be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device incorporating a memory device. As shown in FIG. 1 , the electronic device 1 may include a host HOST and a memory system 30, which includes a memory controller 10 and one or more memories 20. The host HOST may be a processor of the electronic device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)). The host HOST may be configured to transmit data to or receive data from the memory 20. The memory controller 10 is coupled to the memory 20 and the host HOST and configured to control the memory 20. The memory controller 10 may manage data stored in the memory 20 and communicate with the host HOST.

[0015] Memory controller 10 may be configured to control operations of memory 20, such as read, erase, write, and refresh operations. In some implementations, memory controller 10 is further configured to process error correction codes (ECC) associated with data read from or written to memory 20. Memory controller 10 may also perform any other suitable functions, such as formatting memory 20.

[0016] In some particular examples, memory controller 10 and one or more memories 20 may be integrated into various types of electronic devices, for example, memory controller 10 may be integrated into the northbridge of a computer motherboard or directly into the computer's CPU, multiple memories 20 may be integrated into a memory stick, etc. That is, memory system 30 may be implemented and packaged in various types of end electronic products.

[0017] The memory controller 10 may transmit and receive data to and from the host HOST and may send a command CMD and an address ADDR to the memory 20. The memory controller 10 may include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 may receive a command CMD and an address ADDR from the host HOST. The command generator 110 may generate an access command, a row hammer refresh command, etc. by decoding the command CMD received from the host HOST and provide the access command and the row hammer refresh command to the memory 20 through the device interface 130. The access command may be a signal instructing the memory 20 to write or read data by accessing a row of the array 220 of memory cells corresponding to the address ADDR. The row hammer refresh command may be a signal instructing the memory 20 to perform an additional refresh operation on a word line adjacent to a word line accessed intensively in a short period of time. In other words, an additional refresh operation may be performed on a word line adjacent to a word line accessed multiple times in a short period of time. A high number of accesses may be the result of repeated requests to access the same word line.

[0018] Address generator 120 in memory controller 10 may generate row and column addresses to be accessed in array of memory cells 220 by decoding address ADDR received from host interface 140. Additionally, memory 20 may generate the address of the bank to be accessed if array of memory cells 220 includes multiple banks.

[0019] Furthermore, the memory controller 10 may control memory operations, such as writing and reading, by providing various signals to the memory 20 via the device interface 130. For example, the memory controller 10 may provide a write command to the memory 20. The write command instructs the memory 20 to perform a write operation and store data in the memory 20. In some examples, the memory 20 includes an array of memory cells 220 and peripheral circuits 210. The array of memory cells 220 includes multiple banks, each bank includes multiple blocks, each block includes multiple rows of memory cells and multiple columns of memory cells, each row of memory cells coupled to a corresponding word line and each column of memory cells coupled to a corresponding bit line. The peripheral circuits 210 may write data to or read data from the array of memory cells 220 or provide control signals CTRL to row decoders and column decoders to refresh memory cells included in the array of memory cells 220 based on a command CMD and an address ADDR received from the memory controller 10. In other words, the peripheral circuit 210 may perform all operations for processing data in the array of memory cells 220. The peripheral circuit 210 may include control circuits corresponding to each block, such as sense amplifiers (SAs) and word line drivers (WLDs), control circuits corresponding to each bank, such as row decoders, column decoders, and control circuits corresponding to all banks, such as command buffers, command decoders, address buffers, data input / output buffers, mode registers, and the like.

[0020] The memory 20 can be a random access memory (RAM), such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), a double data rate SDRAM (DDR SDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), etc. In the following description, only DRAM will be used as an example.

[0021] 2 is a schematic diagram of an exemplary dynamic random access memory according to one example of the present application. FIG. 3 is a schematic connection diagram of word lines, bit lines, and memory cells of an exemplary dynamic random access memory according to one example of the present application.

[0022] The right side of Figure 2 shows the circuitry of a memory cell in a DRAM. A DRAM includes at least one DRAM die, and each DRAM die includes an array of memory cells. The array of memory cells includes a plurality of memory cells 201 arranged in an array. Each memory cell 201 includes a transistor T and a capacitor C. The main operating principle of a memory cell is to represent a binary bit of 1 or 0 according to the amount of charge stored in the capacitor. The memory cells are arranged in an array that can be considered a typical mesh structure. For details of the mesh structure, see Figure 3. The array of memory cells employs rows and columns for addressing. By specifying the intersection of the rows and columns (by specifying the row address and column address of the DRAM), a memory controller can individually access each memory cell in the DRAM die and perform operations such as reading, writing, or refreshing the data stored therein.

[0023] DRAM memory cells are essentially capacitors that store electrical charge, and the capacitance can leak during the read, write, and refresh processes, making the read process itself destructive. Based on this, a refresh operation must be performed after a read operation or if the memory cell has not been accessed for a long time.

[0024] The data stored in a memory cell is determined by the charge on the capacitor, and the charge is easily affected between refresh cycles. Drifting electrons entering and leaving the memory cell can change the charge on the memory cell. If an address line is accessed many times in a short period of time, memory cells on lines adjacent to that address can accumulate enough charge changes to change the sensed state of the stored value. This is the Row Hammer phenomenon. At smaller sizes, a sensed state change of the stored value can affect nearby rows (rows two or more rows away) as well as adjacent rows.

[0025] 4 is a schematic diagram of the voltage timing of the associated signals, word lines, and voltage transfer lines when a selected word line is accessed, according to an example of the present application. <n>may be understood as the word line connected to the memory cell to be accessed, and the selected word line, as well as the selected word line, determine the target memory cell on which a read, write, or other operation is performed; therefore, these two terms may be used interchangeably to represent the same meaning, and the adjacent unselected word line wl<n+1またはn-1> can be understood as the word lines adjacent to the physical address of the selected word line, and Vneg_local <n>has one end coupled to the selected word line and provides a voltage to the selected word line, and Vneg_local <n>can be understood as a voltage transfer line whose other end is coupled to a power supply terminal, Vneg_local<n+1またはn-1> is connected to the adjacent unselected word line wl<n+1またはn-1> , and can be understood as a voltage transfer line that provides a voltage to an adjacent unselected word line;<n+1またはn-1> Note that the other end of the selected word line wl is coupled to a power supply terminal. <n>Because of the long length of Vneg_local, the resistance may not be neglected. <n>When combined with Vneg_local <n>The end of the selected word line closest to the selected word line near end wl_near <n>It is called Vneg_local <n>The end of the selected word line far from the selected word line is the far end of the selected word line wl_far <n>Similarly, Vneg_local<n+1またはn-1> The end of the adjacent unselected word line closest to wl_near is the near end of the adjacent unselected word line wl_near<n+1またはn-1> It is called Vneg_local<n+1またはn-1> The end of the adjacent unselected word line far from the<n+1またはn-1> It is called.

[0026] For ease of understanding, in this example application, the far end of the adjacent unselected word line wl_far<n+1またはn-1> will be described as an example, which is not used to limit the scope of protection of the present application, and the description in the example of the present application also refers to the near end wl_near of the adjacent unselected word line.<n+1またはn-1> It is also applicable to

[0027] As shown in FIG. 4, the bank select signal Bank_enable, the main word line select signal mwl_n <k>, and the word line selection signal wld <n>is valid, the precharge control signal xpp <n>When the word line near end wl_near of the selected word line is switched from the inactive state to the active state, at the first time node Q1, the memory starts to perform a precharge operation on the selected word line. <n>(shown by the dotted parabola after Q1 in Figure 4) and the far end of the selected word line wl_far <n>The time period required for the first time node Q1 to start charging from the initial voltage vneg to the voltage Vpp is different depending on the near end of the selected word line wl_near (shown by the solid line below the dotted line after Q1 in FIG. 4). <n>Vneg_local <n>It can be seen that the far end of the selected word line wl_far is closer to the power supply terminal, i.e., closer to the power supply terminal, and therefore may be charged to the voltage Vpp more quickly. <n>Vneg_local <n>The adjacent unselected word line wl is farther away from the selected word line and therefore takes longer to charge to the voltage Vpp. Figure 4 shows that the slope of the dotted parabolic section is greater than the slope of the solid parabolic section.<n+1またはn-1> If , the far end of the adjacent unselected word line wl_far<n+1またはn-1> For example, the far end of the selected word line wl_far <n>The voltage at the far end of the selected word line wl_far begins to charge from the initial voltage vneg to the voltage Vpp at the first time node Q1. <n>In the process of increasing the voltage of the word line, the far end of the adjacent unselected word line wl_far<n+1またはn-1> The voltage at the far end of the selected word line wl_far is gradually increased. <n>After the voltage Vpp stabilizes, the far end of the adjacent unselected word line wl_far<n+1またはn-1> The voltage at vneg gradually decreases and returns to a value equal to or slightly greater than the initial voltage vneg.

[0028] Selected word line wl_far <n>After the far end of the <n>At a second time node Q2 when switches from an enabled state to an disabled state, the memory begins to float the selected word line.

[0029] Next, at a third time node Q3, a certain buffer time after the second time node Q2, the selected word line starts discharging. Here, the buffer discharge can be realized through a falling edge delay circuit. In the operation to start discharging from the voltage Vpp to the initial voltage VNEG at the third time node Q3, the near end wl_near of the selected word line <n>The time period required by the far end of the selected word line (shown by the dotted parabola after Q3 in FIG. 4) is <n>(shown by the solid line on the dotted line after Q3 in FIG. 4). <n>In the process of increasing the voltage of the word line, the far end of the adjacent unselected word line wl_far<n+1またはn-1> The voltage at the far end of the selected word line wl_far gradually drops below the initial voltage vneg. <n>After the voltage of the adjacent unselected word line wl_far stabilizes at the initial voltage vneg,<n+1またはn-1> The voltage at vneg gradually increases and returns to near the initial voltage vneg. Thus, if the voltage of an adjacent unselected word line increases or decreases during the precharge operation and subsequent discharge operation performed on the selected word line, a large voltage difference will occur on the adjacent unselected word line due to coupling, which is shown as ΔV1 in FIG. 4. In some aspects, this voltage change ΔV1 may change the detected state of the storage value of the memory cell coupled to the adjacent unselected word line, thereby threatening data security and exacerbating the row hammer problem. In other aspects, this voltage change ΔV1 may also create a risk of gate-induced drain leakage (GIDL), which may cause hole accumulation and increase the floating body potential. The high floating body potential may turn on a parasitic transistor between the floating body and drain junction, thus causing a series of problems.

[0030] Increasing the frequency of periodic refresh can mitigate some of the risks posed by row hammer, ensuring that each row is refreshed before row hammer damages the charge in the cells enough to generate errors. However, the above methods consume unnecessary time or power, thereby increasing system power consumption and reducing system performance. Furthermore, GIDL leakage is also an unresolved hidden risk.

[0031] To this end, the present application proposes the following implementation to reduce the large voltage difference between adjacent unselected word lines caused by coupling, thereby mitigating the row hammer and GIDL leakage problems.

[0032] An example of the present application provides a memory as shown in FIG. 5 , wherein the memory 20 includes an array 220 of memory cells and a peripheral circuit 210 coupled to the array 220 of memory cells, wherein the array 220 of memory cells includes a plurality of word lines, and the peripheral circuit 210 is configured to: begin providing a precharge voltage to a selected word line from the plurality of word lines at a first time, wherein a voltage provided to an unselected word line adjacent to the selected word line is changed from a first voltage to a second voltage at a second time before the first time; and begin floating the selected word line at a third time after the first time, wherein a voltage provided to an adjacent unselected word line is changed from the second voltage to a third voltage at a fourth time before the third time and after the first time, wherein the second voltage is lower than the first voltage and the third voltage.

[0033] 6 is a schematic diagram of voltage timing of related signals, word lines, and voltage transfer lines when a selected word line is accessed, provided by another example of the present application. In some examples, referring to FIGS. 5 and 6, the peripheral circuit 210 begins to provide a precharge voltage Vpp to a selected word line from a plurality of word lines at a first time T1, and a voltage provided to an unselected word line adjacent to the selected word line is changed from a first voltage V1 to a second voltage V2 at a second time T2 before the first time T1;

[0034] The method is configured to begin floating the selected word line at a third time T3 after the first time T1, and the voltage provided to the adjacent unselected word line is changed from a second voltage V2 to a third voltage V3 at a fourth time T4 before the third time T3 and after the first time T1, the second voltage V2 being lower than the first voltage V1 and the third voltage V3, thereby beginning to float the selected word line.

[0035] In one example, as shown in FIG. 6, a bank select signal Bank_enable, a main word line select signal mwl_n <k>, and the word line selection signal wld <n>is valid, the precharge control signal xpp <n>When the word line near end wl_near of the selected word line is switched from the inactive state to the active state, a precharge operation for the selected word line begins to be performed at a first time T1. <n>(shown by the dotted parabola after T1 in FIG. 6) and the far end of the selected word line wl_far <n>The time periods required to start charging from the first voltage V1 to the precharge voltage Vpp at the first time (the portion indicated by the solid line below the dotted line after T1 in FIG. 6) are different.

[0036] Bank selection signal Bank_enable, main word line selection signal mwl_n <k>, and the word line selection signal wld <n>Note that all valid states of the precharge control signal xpp are low voltages such as Vss, and all invalid states are high voltages such as Vpp or Vdd. <n>The valid state of is a high level voltage such as Vpp or Vdd, and the invalid state is a low level voltage such as Vss.

[0037] wld shown in Figure 6 <n>represents the word line select signal for the selected word line, and the word line select signals corresponding to the adjacent unselected word lines are always in an inactive state, i.e., at a high voltage level, and not as shown in FIG.

[0038] Adjacent unselected word lines wl<n+1またはn-1> If , the far end of the adjacent unselected word line wl_far<n+1またはn-1> For example, at a second time T2 before the first time T1, VNEG_local<n+1またはn-1> The voltage at the far end wl_far of the unselected word line adjacent to the selected word line is changed from the first voltage V1 to the second voltage V2.<n+1またはn-1> Vneg_local on<n+1またはn-1> It can be seen that the voltage provided by is changed from a first voltage V1 to a second voltage V2, where the second voltage V2 is lower than the first voltage V1. Thus, before the selected word line starts precharging at the first time T1, the voltage provided to the adjacent unselected word line is pre-reduced to reduce the initial voltage of the adjacent unselected word line that is pulled up by coupling. If the boost voltage difference between the adjacent unselected word lines caused by the coupling effect does not change substantially, it effectively reduces the absolute voltage of the adjacent unselected word line after being coupled up.

[0039] In the example of the present application, at the third time T3, the precharge control signal xpp <n>switches from an enabled state to an disabled state, the memory stops precharging the selected word line, and the memory begins floating the selected word line.

[0040] In some examples, as shown in FIG. 6, the memory begins floating the selected word line at a third time T3, and the selected word line begins discharging at a seventh time T7, a certain buffer time after the third time T3.

[0041] Adjacent unselected word lines wl<n+1またはn-1> If , the far end of the adjacent unselected word line wl_far<n+1またはn-1> Still taking the example, at a fourth time T4 which is before the third time T3 and after the first time T1, Vneg_local<n+1またはn-1> The voltage at the far end wl_far of the unselected word line adjacent to the selected word line is changed from the second voltage V2 to the third voltage V3.<n+1またはn-1> Vneg_local on<n+1またはn-1> It can be seen that the voltage provided by is changed from a second voltage V2 to a third voltage V3, with the second voltage V2 being lower than the third voltage V3. In this way, the voltage provided to the adjacent unselected word lines is pre-elevated to raise the initial voltage of the adjacent unselected word lines that are being pulled up by the coupling before starting to float the selected word line. If the reduced voltage difference between the adjacent unselected word lines caused by the coupling effect remains substantially unchanged, the absolute voltage of the adjacent unselected word lines that are pulled up by the coupling is effectively raised.

[0042] 6, by reducing the voltage provided to the adjacent unselected word lines before precharging the selected word line, the final voltage raised by the coupling from the voltage of the adjacent unselected word lines is controlled, i.e., it is the maximum voltage in the subsequent voltage change; on the other hand, by increasing the voltage provided to the adjacent unselected word lines before discharging the selected word line, the final voltage lowered by the coupling from the voltage of the adjacent unselected word lines is controlled, i.e., it is the minimum voltage in the subsequent voltage change. The maximum voltage causing the voltage change becomes smaller and the minimum voltage becomes larger, so that the voltage change ΔV2 of the adjacent unselected word lines during the charging and discharging process of the selected word line can be effectively reduced, thereby alleviating the row hammer problem and the GIDL leakage problem.

[0043] In one example of the present application, as shown in FIG. 6, the voltage of the adjacent unselected word line reaches a second voltage V2 at a fifth time T5, and the period between the second time T2 and the fifth time T5 is a first period ΔT1, and the voltage of the adjacent unselected word line reaches a third voltage V3 at a sixth time T6, and the period between the fourth time T4 and the sixth time T6 is a second period ΔT2.

[0044] a time difference between the first time T1 and the second time T2 is equal to or greater than a first period ΔT1;

[0045] The time difference between the third time T3 and the fourth time T4 is equal to or greater than the second period ΔT2.

[0046] Vneg_local<n+1またはn-1> via the adjacent unselected word line wl_<n+1またはn-1> When the voltage is transferred to Vneg_local<n+1またはn-1> The voltage of the adjacent unselected word line wl_ is changed from the first voltage V1 to the second voltage V2 at time T2.<n+1またはn-1> It can be understood that the first time ΔT1 is the time it takes for the voltage V1 to start decreasing to the stable second voltage V2 required for the selected word line. Based on this, here, the time difference between the first time T1 and the second time T2 is equal to or greater than the first time ΔT1. The precharge operation of the selected word line is performed by the adjacent unselected word line wl_<n+1またはn-1> The voltage on the adjacent unselected word line wl_<n+1またはn-1> When the voltage of the adjacent unselected word line wl_ is not reduced to the second voltage V2 but is between the first voltage V1 and the second voltage V2, the voltage of the adjacent unselected word line wl_ is pulled up by coupling.<n+1またはn-1> It can be seen that the initial voltage of is not controlled to a minimum.

[0047] Similarly, here, the time difference between the third time T3 and the fourth time T4 is equal to or greater than the second time length ΔT2. The discharge operation of the selected word line is also performed by the adjacent unselected word line wl_<n+1またはn-1> The voltage on the adjacent unselected word line wl_<n+1またはn-1> When the voltage of the adjacent unselected word line wl_ is not increased to the third voltage V3 but is between the second voltage V2 and the third voltage V3, the voltage of the adjacent unselected word line wl_ is pulled down by coupling.<n+1またはn-1> It can be understood that the initial voltage of the selected word line is not controlled to the maximum. Thus, by setting the first time period to ensure that the voltage of the adjacent unselected word line reaches the second voltage V2 before the precharge of the selected word line, and by setting the second time period to ensure that the voltage of the adjacent unselected word line reaches the third voltage V3 before the discharge of the selected word line, the control effect on the voltage change amplitude of the adjacent unselected word line during the charge / discharge process of the selected word line is further improved.

[0048] In another example, the timing to start the precharge operation of the selected word line after the second time T2 can be selected according to actual needs. For example, the precharge operation of the selected word line can be started at any time between the second time T2 and the fifth time T5. The ...<n+1またはn-1> It can be seen that the voltage of the adjacent unselected word line wl_ is pulled up by coupling, starting before the voltage of the adjacent unselected word line wl_ is pulled up to the second voltage V2.<n+1またはn-1> The latency of the precharge operation can also be controlled while reducing the initial voltage of the precharger.

[0049] Similarly, the timing to start the discharge operation of the selected word line after the fourth time T4 can be selected according to actual needs. For example, the discharge operation of the selected word line can be started at any time between the fourth time T4 and the sixth time T6. The ...<n+1またはn-1> It can be seen that the voltage of the adjacent unselected word line wl_wl_ is pulled down by coupling before the voltage of the adjacent unselected word line wl_wl_ is pulled down by coupling.<n+1またはn-1> The waiting time of the discharge operation may also be controlled while increasing the initial voltage of the first voltage V1 and the third voltage V3. In some examples, the first voltage V1 and the third voltage V3 are the same.

[0050] In some examples, the relationship between the second voltage, the first voltage, and the precharge voltage is as shown in the following equation (1). |V2|=r(Vpp-V1)…Equation (1) In the above equation, V1 is the first voltage, V2 is the second voltage, Vpp is the precharge voltage, and r is the coupling coefficient.

[0051] In one example, the coupling coefficient r=C1 / C2, where C1 represents the capacitance between the selected word line and an adjacent unselected word line, and C2 represents the capacitance of the selected word line.

[0052] Note that word lines are connected to memory cells through the gates of transistors (see Figure 2), and the capacitance of a word line refers to the sum of its write capacitance and load capacitance. Here, write capacitance refers to the amount of charge charged or discharged on a word line when data is written to a memory cell. A write operation involves transferring charge between a word line and a memory cell to change the charge state of the memory cell. The size of the write capacitor is related to the amount of charge required, the size of the memory cell, etc. The load capacitance refers to the capacitance caused by other circuit components (e.g., read circuits, decode circuits, buffers, etc.) connected to the word line. In some examples, the coupling coefficient r is related to the physical distance between a selected word line and an adjacent unselected word line. The smaller the physical distance between a selected word line and an adjacent unselected word line, the greater the capacitance between the selected word line and the adjacent unselected word line, and the greater the coupling coefficient r.

[0053] It can be understood that when the first voltage V1 and the third voltage V3 are different, the relationship between the second voltage, the third voltage, and the precharge voltage is as shown in the following equation (2). |V2|=r(Vpp-V3)…Equation (2) where V3 is the third voltage, V2 is the second voltage, Vpp is the precharge voltage, and r is the coupling coefficient.

[0054] 5, the peripheral circuit 210 includes a first voltage generator 214, a second voltage generator 215, a first voltage transfer circuit 211, and a second voltage transfer circuit 212, where the first voltage generator 214 connected to the first voltage transfer circuit 211 is configured to provide a first voltage V1, the second voltage generator 215 connected to the second voltage transfer circuit 212 is configured to provide a second voltage V2, the first voltage transfer circuit 211 is configured to transfer the first voltage V1 to an adjacent unselected word line in response to a first control signal wlup_enb at a fourth time T4, and the second voltage transfer circuit 212 is configured to transfer the second voltage V2 to an adjacent unselected word line in response to a second control signal wlup_vneg2 at a second time T2.

[0055] In some examples, the first voltage generator 214 and the second voltage generator 215 may belong to a peripheral circuit voltage generator. In some particular examples, both the first voltage generator 214 and the second voltage generator 215 may include a charge pump. The first voltage generator 214 and the second voltage generator 215 may be integrated into one charge pump with multiple outputs or may belong to different charge pumps.

[0056] In some examples, as shown in Figures 5 and 6, the peripheral circuit 210 further includes a control signal generation circuit 216, which is configured to receive an enable control signal wlup_en and to provide a first control signal wlup_enb to the first voltage transfer circuit 211 and a second control signal wlup_vneg2 to the second voltage transfer circuit 212.

[0057] In some examples, as shown in FIG. 5, the peripheral circuitry further includes a plurality of local word line driver circuits 213 that correspond one-to-one to the word lines;

[0058] The local word line driver circuit 213 receives the main word line selection signal mwl_n <k>, word line selection signal wld <n>, and the precharge control signal xpp <n>In response to the signal, the control circuit 210 is configured to connect adjacent unselected word lines to the first voltage transfer circuit 211 at a first time T1 and connect adjacent unselected word lines to the second voltage transfer circuit 212 at a second time T2.

[0059] Main word line selection signal mwl_n <k>indicates that one main word line is selected from a plurality of main word lines in the peripheral circuit, each of which corresponds to a plurality of word lines, and the word line selection signal wld <n>indicates the selection of one word line from a plurality of word lines corresponding to the main word line, and the precharge control signal xpp <n>indicates providing a precharge voltage to the selected word line.

[0060] In some examples, as shown in FIG. 5 , the control signal generating circuit 216 is connected to the first voltage transfer circuit 211 through a first node N1, and the control signal generating circuit 216 is connected to the second voltage transfer circuit 212 through a second node N2;

[0061] The first voltage transfer circuit 211 and the second voltage transfer circuit 212 are both connected to the local word line driver circuit 213 through a third node N3;

[0062] The first voltage generator 214 and the second voltage generator 215 are both connected to a control signal generating circuit 216 .

[0063] In some examples, the driver circuits for the multiple local word lines are divided into multiple groups, each group corresponding to one first voltage generator, one second voltage generator, one first voltage transfer circuit, and one second voltage transfer circuit.

[0064] Main word line selection signal mwl_n <k>and word line selection signal wld <n>and each word line corresponds to a local word line driver circuit, and multiple local word line driver circuits corresponding to multiple word lines are connected to different word line select signals wld <n>The word lines are divided into multiple groups according to the word line selection signal wld <n>are at the same level, and the main word line selection signal mwl_n corresponds to the selected word line or an unselected word line in the same group. <k>It can be seen that the are at different levels.

[0065] In one example, one block shares a control signal generating circuit, and 16 local word line driver circuits in one block are divided into four groups, and each group shares the same first voltage generator, the same second voltage generator, the same first voltage transfer circuit, and the same second voltage transfer circuit. That is, 16 word lines corresponding to the local word line driver circuits are divided into four groups, and each group is connected to four first voltage transfer circuits and four second voltage transfer circuits, and every four word lines are connected to the same first voltage transfer circuit and the same second voltage transfer circuit, and the four word lines connected to the same first voltage transfer circuit and the same second voltage transfer circuit are simultaneously selected or deselected, and the corresponding word line selection signal wld <n>is the same.

[0066] In this way, the circuit area can be significantly reduced by having multiple local word line driver circuits in each group of local word line driver circuits share one first voltage generator, one second voltage generator, one first voltage transfer circuit, and one second voltage transfer circuit.

[0067] 7 is a partial structural schematic diagram of a peripheral circuit provided by an example of the present application. In some examples, as shown in FIG. 7, the first voltage transfer circuit 211 includes a first transistor M1, and the second voltage transfer circuit 212 includes a second transistor M2 and a third transistor M3.

[0068] A first terminal of the first transistor M1 receives a first control signal wlup_enb, a second terminal of the first transistor M1 is connected to a first voltage generator (not shown in FIG. 7), and a third terminal of the first transistor M1 is connected to the third terminal of the second transistor M2. An output terminal of the first voltage generator outputs a first voltage V1, which may be a voltage VNEG.

[0069] A first terminal of the second transistor M2 receives the second control signal wlup_vneg2, and a second terminal of the second transistor M2 is connected to a third terminal of the third transistor M3.

[0070] The first terminal of the third transistor M3 receives the word line select signal wld <n>and a second terminal connected to the output terminal of a second voltage generator (not shown in FIG. 7), the output terminal of which outputs a second voltage V2, which may be a voltage VNEG2.

[0071] It can be seen that the third terminal of the first transistor M1 and the third terminal of the second transistor M2 are connected through a third node N3.

[0072] In some examples, as shown in FIG. 7, the control signal generating circuit 216 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7,

[0073] A first terminal of the fourth transistor M4 receives an enable control signal wlup_en, a second terminal receives a high-level voltage such as Vpp or Vdd, and a third terminal is connected to the third terminal of the fifth transistor M5 for outputting a first control signal wlup_enb. It can be understood that the third terminal of the fourth transistor M4 and the third terminal of the fifth transistor M5 are connected through a first node N1.

[0074] A first terminal of the fifth transistor M5 is connected to the first terminal of the fourth transistor M4, and a second terminal thereof receives the voltage VNEG.

[0075] A first terminal of the sixth transistor M6 receives the first control signal wlup_en, a second terminal receives a high-level voltage such as Vpp or Vdd, and a third terminal is connected to the third terminal of the seventh transistor M7 for outputting the second control signal wlup_vneg2. It can be understood that the third terminal of the sixth transistor M6 and the third terminal of the seventh transistor M7 are connected through a second node N2.

[0076] A first terminal of the seventh transistor M7 is connected to the first terminal of the sixth transistor M6, and a second terminal receives the voltage VNEG2.

[0077] In some examples, as shown in FIG. 4, the local word line driver circuit 213 includes an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10;

[0078] The first terminal of the eighth transistor M8 is connected to the main word line select signal mwl_n. <k>and the second terminal receives the precharge control signal xpp <n>and the third terminal receives the selected word line wl <n>is connected to.

[0079] The first terminal of the ninth transistor M9 is connected to the main word line select signal mwl_n. <k>, the second terminal is connected to the second terminal of the tenth transistor M10, and the third terminal is connected to the word line wl <n>is connected to.

[0080] The first terminal of the tenth transistor M10 receives the word line select signal wld <n>, and the second terminal is connected to the N3 node, i.e., the third terminal of the first transistor M1 and the third terminal of the second transistor M2, and the third terminal is connected to the word line wl <n>is combined with

[0081] In some examples, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are field-effect MOS transistors, wherein a first terminal of the field-effect MOS transistor is a gate, a second terminal of the field-effect MOS transistor is a source, and a third terminal of the field-effect MOS transistor is a drain.

[0082] In some examples, the first transistor M1, the second transistor M2, the third transistor M3, the fifth transistor M5, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10 are N-channel field-effect MOS transistors, and the fourth transistor M4, the sixth transistor M6, and the eighth transistor M8 are P-channel field-effect MOS transistors.

[0083] It should be noted that although FIG. 7 shows only one local word line driver circuit 213 corresponding to one word line, in reality each word line is provided with its corresponding local word line driver circuit 213.

[0084] In one example of the present application, the precharge voltage is a high-level voltage, and the first voltage, the second voltage, and the third voltage are all negative voltages. In one example, the precharge voltage is Vpp and has a voltage range of 2.2 V to 2.8 V, the first voltage and the third voltage are VNEG and have a voltage range of −0.2 V to −0.1 V, and the second voltage is VNEG2 and has a voltage range of −0.8 V to −0.4 V.

[0085] In the following, by combining Figures 6 and 7, we will explain in detail how to implement voltage supply to unselected word lines through various specific circuits in the peripheral circuit during the process of the selected word line from precharge operation to discharge operation, thereby reducing the large voltage difference caused by coupling with adjacent word lines.

[0086] 6 and 7, before the second time T2, the enable control signal wlup_en (not shown in FIG. 6) is a low-level voltage, the fourth transistor M4 is turned on, and the fifth transistor M5 is turned off, so that the first control signal wlup_enb provided to the first voltage transfer circuit 211 by the control signal generation circuit 216 is a high-level voltage Vpp, and the first transistor M1 is turned on, so that the voltage VNEG is transferred to the local word line driver circuit 213 corresponding to the word line through the first transistor M1 in the first voltage transfer circuit 211 that is turned on. <k>and the word line selection signal wld <n>is at a high-level voltage Vpp before time T2, the ninth transistor M9 is turned on, and the tenth transistor M10 is turned on, based on which the voltage provided to all word lines by the first voltage transfer circuit 211 through M9 and M10 becomes the voltage VNEG, where the voltage VNEG is equal to the first voltage V1 shown in FIG.

[0087] At the same time, before time T2, the voltage of the first node N1 is a high-level voltage Vpp, the sixth transistor M6 is turned off, and the seventh transistor M7 is turned on, therefore the second control signal wlup_vneg2 provided to the second voltage transfer circuit 212 by the control signal generating circuit 216 is voltage VNEG2, and the second transistor M2 is turned off, therefore there is no connection between the second voltage transfer circuit 211 and the local word line drive circuit, i.e., the second voltage transfer circuit 211 does not provide a voltage to the local word line drive circuit.

[0088] Next, at a second time T2, the enable control signal wlup_en is changed from a low-level voltage to a high-level voltage, the fourth transistor M4 is turned off, and the fifth transistor M5 is turned on, and thus the first control signal wlup_enb provided to the first voltage transfer circuit 211 by the control signal generation circuit 216 switches from the high-level voltage Vpp to the voltage VNEG.

[0089] At time T2, the voltage at the first node N1 also switches from the high-level voltage Vpp to the voltage VNEG, the sixth transistor M6 is turned on, and the seventh transistor M7 is turned off, so that the second control signal wlup_vneg2 provided from the control signal generating circuit 216 to the second voltage transferring circuit 212 switches from the voltage VNEG2 to the high-level voltage Vpp, where the voltage VNEG2 is equal to the second voltage V2 shown in FIG.

[0090] At the same time, at a second time T2, for the adjacent unselected word line, the first control signal wlup_enb is at a voltage VNEG, turning off the first transistor M1, and the second control signal wlup_vneg2 is at a high level Vpp, turning on the second transistor M2. For the unselected word line, the word line selection signal wld <n>is a high-level voltage, and the third transistor M3 is turned on. Therefore, the voltage VNEG2 is transferred to the local word line driver circuit 213 corresponding to the adjacent unselected word line through the second transistor M2 and the third transistor M3 in the second voltage transfer circuit 212. For the adjacent unselected word line, the word line select signal wld <n>is at a high level voltage, the tenth transistor M10 is turned on, and thus the voltage VNEG2 is transferred to the corresponding adjacent unselected word line through the local word line driver circuit 213. Based on this, at a second time T2, the voltage provided to the adjacent unselected word line is reduced from the voltage VNEG to the voltage VNEG2.

[0091] At a second time T2, for the selected word line, the word line select signal wld <n>is a low-level voltage, the third transistor M3 is turned off, the tenth transistor M10 is turned off, and each main word line selection signal mwl_n <k>Each of the precharge control signals xpp <n>Note that V is low at time T2, when both the eighth transistor M8 and the ninth transistor M9 are turned off and the selected word line is allowed to float, but due to the coupling effect with adjacent unselected word lines, the voltage on the selected word line gradually drops from voltage V.

[0092] Next, at a first time T1, for the selected word line, the precharge control signal xpp <n>is changed from a low level voltage to a high level voltage, and the main word line selection signal mwl_n <k>is a low level voltage, and the word line selection signal wld <n>is at a low level voltage, at this time, the eighth transistor M8 is turned on, the ninth transistor M9 and the tenth transistor M10 are turned off, and the local word line driver circuit 213 corresponding to the selected word line starts to provide the precharge voltage Vpp to the selected word line through the eighth transistor M8.

[0093] At the same time, at the first time T1, the voltage VNEG2 is still transferred to the corresponding adjacent unselected word lines through the local word line driver circuit 213. However, due to the coupling effect with the selected word line, the voltage of the adjacent unselected word lines begins to gradually rise from the voltage VNEG2.

[0094] Next, at a fourth time T4, the local word line driver circuit 213 corresponding to the selected word line still provides the precharge voltage Vpp to the selected word line through the eighth transistor M8.

[0095] At the same time, at a fourth time T4, for the adjacent unselected word line, the first control signal wlup_enb switches from the voltage VNEG to the high-level voltage Vpp, turning on the first transistor M1. The second control signal wlup_vneg2 switches from the high-level voltage Vpp to the voltage VNEG2, turning off the second transistor M2. <n>is a high-level voltage, and the third transistor M3 is turned on. At this time, the voltage VNEG is transferred to the local word line driver circuit 213 corresponding to the adjacent unselected word line through the first transistor M1 in the first voltage transfer circuit 211. For the adjacent unselected word line, the word line selection signal wld <n>is a high-level voltage, the tenth transistor M10 is turned on, and thus the voltage VNEG is transferred to the corresponding adjacent unselected word line through the local word line driver circuit 213.

[0096] It is understood that at a fourth time T4, the voltage provided to the adjacent unselected word lines is changed from voltage VNEG2 to voltage VNEG, where voltage VNEG is equal to the third voltage V3 shown in FIG.

[0097] Next, at a third time T3, the precharge control signal xpp is applied to the selected word line. <n>is changed from a high-level voltage to a low-level voltage, the eighth transistor M8 is turned off, the local word line driver circuit 213 corresponding to the selected word line stops providing the precharge voltage Vpp to the selected word line, and the memory begins to float the selected word line.

[0098] Next, at a seventh time T7, a certain buffer time after the third time T3, the selected word line begins to discharge. Here, the buffer discharge can be achieved through a falling edge delay circuit (not shown in FIG. 7). At this time, the voltage provided by the local word line driver circuit 213 corresponding to the adjacent unselected word line is still VNEG, but due to the coupling effect with the selected word line, the voltage of the adjacent unselected word line begins to gradually decrease from voltage VNEG.

[0099] As mentioned above, as memory sizes shrink, the physical distance between word lines shrinks further, and row hammers can affect not only word lines in adjacent rows, but also word lines in nearby rows (two or more adjacent lines).

[0100] Based on this, in some examples, when the selected word line is the Nth word line, the adjacent unselected word lines include at least the (N-1)th word line and the (N+1)th word line.

[0101] In some particular examples, the adjacent unselected word lines further include word lines that are M word lines away from the selected word line, where M is a natural number and 1≦M≦4.

[0102] Here, M can be determined based on the range of surrounding rows affected by row hammer in practical applications.

[0103] In one example, if the selected word line is the sixth word line, the adjacent unselected word lines include the fifth and seventh word lines. The adjacent unselected word lines may also include the fourth and eighth word lines, the third and ninth word lines, and the second and tenth word lines.

[0104] Note that if the adjacent unselected word lines include multiple word lines, each word line will have a corresponding voltage applied according to the timing required by one example of the present application.

[0105] In some examples, for each adjacent unselected word line among the plurality of adjacent unselected word lines, at the start of the upward coupling, each adjacent unselected word line may be pre-lowered from a first voltage V1 to the same second voltage V2, and at the start of the downward coupling, each adjacent unselected word line may be pre-highered from the second voltage V2 to the same third voltage V3.

[0106] In some other examples, for each adjacent unselected word line among the plurality of adjacent unselected word lines, at the start of the up-coupling, each adjacent unselected word line may be pre-lowered from a first voltage V1 to a different second voltage V2, and at the start of the down-coupling, each adjacent unselected word line may be pre-highered from the second voltage V2 to a different third voltage V3. Here, the adjustment value between the different second voltages V2 and the adjustment value between the different third voltages V3 may be determined according to the distance between each adjacent unselected word line and the selected word line. For example, the shorter the distance, the greater the coupling effect, and the greater the absolute value of the difference between the first voltage V1 and the second voltage V2, and the greater the absolute value of the difference between the second voltage V2 and the third voltage V3. The greater the distance, the smaller the coupling effect, and the smaller the absolute value of the difference between the first voltage V1 and the second voltage V2, and the smaller the absolute value of the difference between the second voltage V2 and the third voltage V3.

[0107] It can be understood that as the distance between the adjacent unselected word line and the selected word line increases, the absolute value of the voltage difference between the second voltage and the first voltage decreases. For example, the greater the distance between the selected word line and the adjacent unselected word line, the smaller the capacitance between the selected word line and the adjacent unselected word line, the smaller the coupling coefficient r, and the smaller the influence of the selected word line on the adjacent unselected word line. Therefore, when the absolute value of the voltage difference between the second voltage and the first voltage is small, the selected word line can be prevented from interfering with the adjacent unselected word line.

[0108] By improving the Row Hammer problem, the memory refresh frequency caused by the Row Hammer problem can be reduced to some extent, and therefore the memory power can be reduced to some extent, and the reduction in power can also reduce the complexity of the memory peripheral circuits.

[0109] 8a and 8b are schematic top view diagrams illustrating the distribution of an array of memory cells and peripheral circuitry in an exemplary memory according to one example of the present application;

[0110] 8a, the memory cell array 220 and the peripheral circuit 210 are arranged in parallel, more specifically, the memory cell array includes M banks, each bank includes N blocks, at least one side of each block is provided with a control circuit corresponding to the block, at least one side of each bank is provided with a control circuit corresponding to the bank, the M banks form one bank row for every K banks, the M banks form M / K bank rows, and the peripheral circuits corresponding to all the banks are provided between the two central bank rows, where it should be noted that M, N, and K are all positive integers, and M is an integer multiple of K.

[0111] 8b, the memory cell array 220 includes 16 banks Bank0 to Bank15, each including a plurality of blocks, each surrounded by a corresponding block SA and a corresponding block WLD, each bank being provided with a column decoder and a row decoder corresponding to the bank on both sides, each bank forming one bank row every four banks, the 16 banks forming four bank rows, and control circuits corresponding to all banks being provided between the two central bank rows. Note that the number of banks in FIG. 8b is used as an example only and is not used to limit the number of banks in the memory in this application.

[0112] As described above, in order to suppress the coupling effect in the example of the present application, the first voltage generator 214, the second voltage generator 215, the control signal generation circuit 216, the first voltage transfer circuit 211, and the second voltage transfer circuit 212 are added. However, in the distribution method of the memory cell array and the peripheral circuits shown in Figures 8a and 8b, there may be no free space for arranging these newly added circuits. Considering that the memory cell array in the DRAM occupies a larger area than the peripheral circuits, in some examples, because the memory cell array and the peripheral circuits in the DRAM are stacked and electrically connected through bonding, there may be some free space in the semiconductor layer where the peripheral circuits are arranged, and this free space may be used to arrange the above newly added circuits.

[0113] 9a and 9b are schematic top view diagrams illustrating the distribution of an array of memory cells and peripheral circuitry in an exemplary memory according to another example of the present application;

[0114] 9a, a first semiconductor structure 100 is disposed above a second semiconductor structure 200. The first semiconductor structure 100 includes an array of memory cells 220, and the second semiconductor structure 200 includes peripheral circuitry 210.

[0115] 9b, the first semiconductor structure corresponding to FIG. 9a is disposed above the second semiconductor structure, the structures corresponding to the solid lines in FIG. 9b are disposed within the first semiconductor structure, and the structures corresponding to the dotted lines are disposed within the second semiconductor structure, and note that for ease of understanding, the structures within the second semiconductor structure are shown in perspective. That is, in the enlarged view corresponding to each block in FIG. 9b, the solid lines represent the enlarged portion of the block, and the dotted lines represent the structures within the second semiconductor structure at a position directly below the block.

[0116] In one example, as shown in FIG. 9b, the memory cell array 220 includes 16 banks Bank0 to Bank15, each of which includes a plurality of blocks Block. Directly below each block are provided a first voltage generator 214, a second voltage generator 215, a control signal generation circuit 216, a first voltage transfer circuit 211, and a second voltage transfer circuit 212. According to actual needs, the control signal generation circuit 216 shared by the blocks, and a plurality of first voltage generators 214, a plurality of second voltage generators 215, a plurality of first voltage transfer circuits 211, and a plurality of second voltage transfer circuits 212 corresponding to the blocks may be provided directly below the blocks.

[0117] Please note that the number of control signal generating circuits 216, first voltage generators 214, multiple second voltage generators 215, first voltage transfer circuits 211, and second voltage transfer circuits 212 in Figure 9b are used as examples only and are not used to limit the number and locations of corresponding circuits in the memory in this application.

[0118] Note that in addition to the newly added circuits described above, if space allows, the SA and WLD corresponding to each block may be set directly below the block, i.e., within the dotted box shown in Figure 9b.

[0119] In some particular examples, the array of memory cells 220 and the peripheral circuitry 210 are bonded together by methods including, but not limited to, hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, and the like.

[0120] When the memory is stacked in a bonding manner, the newly added circuitry in the example of this application, as well as related circuits such as SA and WLD, can be placed under the array. Due to the way the stacking is configured, no additional area cost is added.

[0121] With the development of memories such as DRAM, process measures have been adopted to improve or eliminate line hammer leakage, but the scale of the process is becoming larger and larger, and the effectiveness is limited. The example of this application improves the nearby wl coupling effect from the perspective of design control without increasing memory overhead.

[0122] 10 is a schematic flowchart of an implementation of a method for operating a memory provided by an example of the present application. The example of the present application provides a method for operating a memory, and the method for operating a memory specifically includes the following steps:

[0123] Step S10: At a first time, start providing a precharge voltage to a selected word line from a plurality of word lines of the memory, and the voltage provided to an unselected word line adjacent to the selected word line is changed from a first voltage to a second voltage at a second time before the first time.

[0124] Step S20: At a third time after the first time, the selected word line begins to float, and the voltage provided to the adjacent unselected word line is changed from the second voltage to the third voltage at a fourth time before the third time and after the first time;

[0125] The second voltage is lower than the first voltage and the third voltage.

[0126] This method will be described below with reference to Figures 6 and 10. As for the structure of the memory, reference may be made to the relevant description in the above example, and therefore it will not be repeated here.

[0127] In some examples, the method includes, at a first time T1, beginning to provide a precharge voltage Vpp to a selected word line from the plurality of word lines, wherein the voltage provided to unselected word lines adjacent to the selected word line is changed from a first voltage V1 to a second voltage V2 at a second time T2 before the first time T1; and, at a third time T3 after the first time T1, beginning to float the selected word line, wherein the voltage provided to the adjacent unselected word line is changed from a second voltage V2 to a third voltage V3 at a fourth time T4 before the third time T3 and after the first time T1, wherein the second voltage V2 is lower than the first voltage V1 and the third voltage V3.

[0128] By reducing the voltage provided to the adjacent unselected word lines before precharging the selected word line, the final voltage raised by the coupling from the voltage of the adjacent unselected word lines is controlled, i.e., it is the highest voltage in the subsequent voltage change; on the other hand, by increasing the voltage provided to the adjacent unselected word lines before discharging the selected word line, the final voltage lowered by the coupling from the voltage of the adjacent unselected word lines is controlled, i.e., it is the lowest voltage in the subsequent voltage change. In this way, during the charging and discharging process of the selected word line, the voltage change of the adjacent unselected word lines can be effectively reduced, and the change in the contents of the adjacent memory cells and the bit flip can be avoided, thereby protecting the data security.

[0129] In some examples, the voltage of the adjacent unselected word line reaches a second voltage V2 at a fifth time T5, and the period between the second time T2 and the fifth time T5 is a first period ΔT1, and the voltage of the adjacent unselected word line reaches a third voltage V3 at a sixth time T6, and the period between the fourth time T4 and the sixth time T6 is a second period ΔT2.

[0130] The time difference between the first time T1 and the second time T2 is equal to or greater than the first period ΔT1, and the time difference between the third time T3 and the fourth time T4 is equal to or greater than the second period ΔT2.

[0131] In this way, by setting the first time period to ensure that the voltage of the adjacent unselected word lines reaches the second voltage before the precharging of the selected word line, and by setting the second time period to ensure that the voltage of the adjacent unselected word lines reaches the third voltage before the discharging of the selected word line, the control effect on the voltage change amplitude of the adjacent unselected word lines during the charging and discharging process of the selected word line is further improved.

[0132] In some examples, the first voltage V1 and the third voltage V3 are the same.

[0133] An example of the present application further provides a memory system including at least one memory disclosed in an example of the present application and a controller coupled to the memory and configured to control the memory.

[0134] Here, the memory may be understood with reference to the memory in the previous examples of this application, and the internal configuration of the memory system may be understood with reference to the memory system described above.

[0135] One example of the present application further provides a word line voltage control circuit including: a first voltage transfer circuit configured to provide a first transfer voltage in response to a first enable signal before starting to provide a precharge voltage to a selected word line; a second voltage transfer circuit configured to provide a second transfer voltage in response to a second enable signal after starting to provide a precharge voltage to the selected word line before starting to float the selected word line; and a local word line driver circuit connected to both the first voltage transfer circuit and the second voltage transfer circuit, the driver circuit configured to connect unselected word lines adjacent to the selected word line to the first voltage transfer circuit before starting to provide the precharge voltage to the selected word line and to connect the adjacent unselected word lines to the second voltage transfer circuit before starting to float the selected word line and after starting to provide a precharge voltage to the selected word line.

[0136] Here, the structure of the above-mentioned first voltage transfer circuit can be understood with reference to the second voltage transfer circuit in Figure 7, and the above-mentioned second voltage transfer circuit can be understood with reference to the first voltage transfer circuit shown in Figure 7.

[0137] The first enable signal may be understood with reference to the second control signal wlup_vneg2 shown in Figure 7, and the first transfer voltage may be understood with reference to the second voltage V2 shown in Figure 6. The second enable signal may be understood with reference to the first control signal wlup_enb shown in Figure 7, and the second transfer voltage may be understood with reference to the first voltage V1 shown in Figure 6.

[0138] The methods disclosed in the several example methods provided in this application may be combined in any consistent manner to obtain new example methods.

[0139] The features disclosed in the several device examples provided in this application may be combined in any consistent manner to obtain new device examples.

[0140] The above is merely a specific implementation form of the present application, and the scope of the claims of the present application is not limited thereto. Modifications or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application are intended to be included in the scope of the claims of the present application. [Industrial Applicability]

[0141] Examples of the present application provide a memory and its operating method, a memory system, and a word line voltage control circuit. The memory controls the final voltage of the adjacent unselected word lines, which is pulled up by coupling, by reducing the voltage provided to the adjacent unselected word lines before precharging the selected word line, i.e., it is the highest voltage in the subsequent voltage change. On the other hand, the memory controls the final voltage of the adjacent unselected word lines, which is pulled down by coupling, by increasing the voltage provided to the adjacent unselected word lines before discharging the selected word line, i.e., it is the lowest voltage in the subsequent voltage change. The highest voltage causing the voltage change becomes smaller and the lowest voltage becomes larger, so that the voltage change of the adjacent unselected word lines can be effectively reduced during the charging and discharging process of the selected word line, thereby mitigating the row hammer problem and the GIDL leakage problem. [Explanation of symbols]

[0142] 1. Electronic Devices 10 Memory Controller 20 memory 30 Memory System 100 First semiconductor structure 110 Command Generator 120 Address Generator 130 Device Interface 140 Host Interface 200 Second Semiconductor Structure 201 memory cells 210 Peripheral Circuit 211 first voltage transfer circuit 212 Second voltage transfer circuit 213 Local word line driver circuit 214 First Voltage Generator 215 Second Voltage Generator 216 Control signal generation circuit Array of 220 memory cells< / n> < / n> < / n> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / k> < / n> < / n> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. an array of memory cells including a plurality of word lines; peripheral circuitry coupled to the array of memory cells, beginning to provide a precharge voltage to a selected word line from the plurality of word lines at a first time; beginning to provide a voltage to an unselected word line adjacent to the selected word line, the voltage being changed from a first voltage to a second voltage at a second time prior to the first time; beginning to float the selected word line at a third time after the first time; the voltage provided to the adjacent unselected word line is changed from the second voltage to a third voltage at a fourth time that is before the third time and after the first time; the second voltage is lower than the first voltage and the third voltage and begins to float; a peripheral circuit configured to perform the Including memory.

2. the voltage on the adjacent unselected word line reaches the second voltage at a fifth time, the period between the second time and the fifth time being a first period; the voltage on the adjacent unselected word line reaches the third voltage at a sixth time, and a period between the fourth time and the sixth time is a second period; a time difference between the first time and the second time is equal to or greater than the first period; The memory of claim 1 , wherein a time difference between the third time and the fourth time is equal to or greater than the second time period.

3. The memory of claim 1 or 2, wherein the first voltage and the third voltage are the same.

4. The relationship between the second voltage, the first voltage, and the precharge voltage is as follows: |V2|=r(Vpp-V1) 4. The memory of claim 3, wherein V1 is the first voltage, V2 is the second voltage, Vpp is the precharge voltage, and r is a coupling coefficient.

5. The peripheral circuitry a first voltage transfer circuit configured to transfer the first voltage to the adjacent unselected word line in response to a first control signal at the fourth time; a second voltage transfer circuit configured to transfer the second voltage to the adjacent unselected word line in response to a second control signal at the second time; a first voltage generator coupled to the first voltage transfer circuit and configured to provide the first voltage; a second voltage generator coupled to the second voltage transfer circuit and configured to provide the second voltage; 4. The memory of claim 3, comprising:

6. The peripheral circuit includes: receiving an enable control signal; providing the first control signal to a first voltage transfer circuit and the second control signal to the second voltage transfer circuit; The memory of claim 5 , further comprising a control signal generation circuit configured to:

7. The peripheral circuit further includes a plurality of local word line driver circuits corresponding to the word lines in one-to-one correspondence, and the local word line driver circuits are responsive to a main word line select signal, a word line select signal, and a precharge control signal to: connecting the adjacent unselected word lines to the first voltage transfer circuit at the first time; connecting the adjacent unselected word lines to the second voltage transfer circuit at the second time; configured to: The main word line selection signal indicates selection of one main word line from a plurality of main word lines in the peripheral circuit, each of the main word lines corresponding to a plurality of word lines of the word line; the word line selection signal indicates selection of one word line from the plurality of word lines corresponding to the main word line; 7. The memory of claim 6, wherein the precharge control signal indicates providing the precharge voltage to the selected word line.

8. the control signal generating circuit is connected to the first voltage transfer circuit through a first node and to the second voltage transfer circuit through a second node; the first voltage transfer circuit and the second voltage transfer circuit are both connected to the driver circuit of the local word line through a third node; The memory of claim 7 , wherein the first voltage generator and the second voltage generator are both connected to the control signal generation circuit.

9. 8. The memory of claim 7, wherein the plurality of local word line driver circuits are divided into a plurality of groups, each of which corresponds to one first voltage generator, one second voltage generator, one first voltage transfer circuit, and one second voltage transfer circuit.

10. The first voltage transfer circuit includes: a first transistor, a first terminal of the first transistor receiving the first control signal; a second terminal of the first transistor connected to the first voltage generator; a first transistor, the third terminal of which is connected to the third terminal of the second transistor; The second voltage transfer circuit includes: The second transistor, a first terminal of the second transistor receiving the second control signal; a second transistor, the second terminal of which is connected to a third terminal of a third transistor; and the third transistor, a first terminal of the third transistor receiving the word line select signal; a second terminal of the third transistor connected to the second voltage generator; and 9. The memory of claim 8, comprising:

11. the first transistor, the second transistor, and the third transistor comprise field-effect MOS transistors; 11. The memory of claim 10, wherein a first terminal of the field effect MOS transistor is a gate, a second terminal of the field effect MOS transistor is a source, and a third terminal of the field effect MOS transistor is a drain.

12. 12. The memory of claim 11, wherein the first transistor, the second transistor, and the third transistor comprise N-channel field effect MOS transistors.

13. 2. The memory of claim 1, wherein the precharge voltage comprises a high-level voltage, and the first voltage, the second voltage, and the third voltage each comprise a negative voltage.

14. The memory of claim 1 , wherein the memory comprises a dynamic random access memory.

15. The memory of claim 14 , wherein the array of memory cells and the peripheral circuitry are coupled by bonding.

16. 2. The memory of claim 1, wherein when the selected word line is the Nth word line, the adjacent unselected word lines include the (N-1)th word line and the (N+1)th word line.

17. 17. The memory of claim 16, wherein the adjacent unselected word lines further include a word line that is M word lines away from the selected word line, where M is a natural number and 1≦M≦4.

18. 17. The memory of claim 16, wherein the absolute value of the voltage difference between the second voltage and the first voltage decreases as the distance between the adjacent unselected word line and the selected word line increases.

19. At least one memory according to any one of claims 1 to 18; a controller coupled to the memory and configured to control the memory; a memory system including:

20. a first voltage transfer circuit configured to provide a first transfer voltage in response to a first enable signal prior to beginning to provide the precharge voltage to the selected word line; a second voltage transfer circuit configured to provide a second transfer voltage in response to a second enable signal before beginning to float the selected word line and after beginning to provide a precharge voltage to the selected word line; a local word line driver circuit connected to both the first voltage transfer circuit and the second voltage transfer circuit, connecting an unselected word line adjacent to the selected word line to the first voltage transfer circuit before beginning to provide a precharge voltage to the selected word line; connecting the adjacent unselected word line to the second voltage transfer circuit before starting to float the selected word line and after starting to provide a precharge voltage to the selected word line; a drive circuit configured to perform a word line voltage control circuit including:

21. beginning, at a first time, to provide a precharge voltage to a selected word line from the plurality of word lines of the memory; a voltage provided to an unselected word line adjacent to the selected word line is changed from a first voltage to a second voltage at a second time before the first time; beginning to float the selected word line at a third time after the first time, the voltage provided to the adjacent unselected word line is changed from the second voltage to a third voltage at a fourth time that is before the third time and after the first time; the second voltage is lower than the first voltage and the third voltage; 10. A method for operating a memory, comprising:

22. the voltage on the adjacent unselected word line reaches the second voltage at a fifth time, the period between the second time and the fifth time being a first period; the voltage on the adjacent unselected word line reaches the third voltage at a sixth time, and a period between the fourth time and the sixth time is a second period; a time difference between the first time and the second time is equal to or greater than the first period; 22. The method of claim 21, wherein the time difference between the third time and the fourth time is equal to or greater than the second time period.

23. 23. The method of claim 21 or 22, wherein the first voltage and the third voltage are the same.

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