Method for forming a semiconductor device using a modified photomask layer

Abstract

A method for manufacturing a semiconductor device is disclosed. The method includes forming a photomask layer disposed on a dielectric material, the photomask layer including a polymer layer. The method includes partially etching the polymer layer to form a first opening. The method includes covering a partial sidewall of the first opening with a first silicon layer. The method includes further etching the polymer layer with the first silicon layer acting as a mask to extend the first opening to form a second opening.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Non-Provisional Patent Application No. 18 / 090,436, filed December 28, 2022, which is incorporated herein by reference in its entirety.

[0002] FIELD OF THE DISCLOSURE The present disclosure relates generally to photomask layers for semiconductor processing, and more particularly to photomask layers for fabricating semiconductor devices having geometries with different aspect ratios. [Background technology]

[0003] The semiconductor integrated circuit (IC) industry is growing rapidly. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of IC processing and manufacturing, and achieving these advances requires similar developments in IC processing and manufacturing. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while feature size (i.e., the smallest components that can be constructed using the fabrication process) has decreased. Summary of the Invention

[0004] At least one aspect of the present disclosure is directed to a method for manufacturing a semiconductor device. The method includes forming a photomask layer disposed on a dielectric material, the photomask layer including a polymer layer. The method includes partially etching the polymer layer to form a first opening. The method includes covering a sidewall of the first opening with a first silicon layer. The method includes further etching the polymer layer with the first silicon layer acting as a mask to extend the first opening to form a second opening.

[0005] In some embodiments, covering the sidewall of the first opening with the first silicon layer further includes sputtering an electrode of the chamber via a plasma to generate a plurality of sputtered silicon atoms, and redepositing at least a portion of the plurality of sputtered silicon atoms onto the first opening to form the first silicon layer. The plasma includes an argon plasma. The electrode includes silicon. The electrode is electrically connected to a DC bias.

[0006] In some embodiments, the method further includes partially etching the polymer layer to form a third opening, covering sidewalls of the third opening with a second silicon layer, the first silicon layer having a first thickness and the second silicon layer having a different second thickness, and further etching the polymer layer with the second silicon layer acting as a mask to extend the third opening to form a fourth opening. The first opening has a first width and the third opening has a second width, the first width being greater than the second width. The first thickness is greater than the second thickness.

[0007] The method further includes etching the dielectric material through the second opening and removing remaining portions of each of the photomask layer and the first silicon layer.

[0008] At least another aspect of the present disclosure is directed to a method for manufacturing a semiconductor device, the method including: forming a photomask layer disposed on a dielectric material, the photomask layer including a polymer layer; partially etching the polymer layer to form a first opening and a second opening, the first opening having a first width and the second opening having a second width different from the first width; covering partial sidewalls of the first opening and partial sidewalls of the second opening with a first silicon layer and a second silicon layer, respectively, the first silicon layer having a first thickness and the second silicon layer having a second thickness different from the first thickness; and further etching the polymer layer with the first silicon layer and the second silicon layer functioning as respective masks to extend the first opening to form a third opening and extend the second opening to form a fourth opening.

[0009] In some embodiments, covering the partial sidewalls of the first opening and the partial sidewalls of the second opening with the first silicon layer and the second silicon layer, respectively, includes sputtering an electrode of the chamber via a plasma to generate a plurality of sputtered silicon atoms, and redepositing at least a portion of the plurality of sputtered silicon atoms on the first opening and the second opening to form the first silicon layer and the second silicon layer, respectively. The electrode includes silicon. The electrode is electrically connected to a DC bias.

[0010] In some embodiments, covering partial sidewalls of the first opening and partial sidewalls of the second opening with a first silicon layer and a second silicon layer, respectively, comprises a physical vapor deposition (PVD)-like process.

[0011] In some embodiments, the first width is greater than the second width, such that the first thickness is greater than the second thickness.

[0012] In some embodiments, the method further includes etching the dielectric material through the third opening and the fourth opening to form a first trench and a second trench, respectively, and removing remaining portions of the photomask layer, the first silicon layer, and the second silicon layer, and filling the first trench and the second trench with a metal material to form a first interconnect structure and a second interconnect structure, respectively.

[0013] Yet another aspect of the present disclosure is directed to a semiconductor fabrication apparatus including: a chamber configured to house a semiconductor device including a dielectric layer covered by a photomask layer, the photomask layer including a polymer layer; an electrode including silicon; and the chamber configured to contain a plasma that sputters the electrode to generate a plurality of silicon atoms and redeposits the plurality of silicon atoms onto an opening extending partially through the polymer layer.

[0014] In some embodiments, the plurality of silicon atoms form a silicon layer that extends along an upper portion of a sidewall of the opening.

[0015] In some embodiments, the electrodes are electrically connected to a DC bias.

[0016] These and other aspects and implementations are described in detail below. The foregoing information and the following detailed description, including illustrative examples of various aspects and implementations, provide an overview or framework for understanding the nature and characteristics of the claimed aspects and implementations. The drawings provide illustrations and a further understanding of various aspects and implementations and are incorporated into and constitute a part of this specification. It will be readily understood that multiple aspects can be combined and that features described in the context of one aspect of the invention can be combined with other aspects. The aspects can be implemented in any convenient manner. As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. [Brief explanation of the drawings]

[0017] Non-limiting embodiments of the present disclosure are described by way of example with reference to the accompanying drawings, which are schematic and are not intended to be drawn to scale. Unless otherwise indicated as representing background art, the drawings represent aspects of the present disclosure. For clarity, not every component is necessarily labeled in every drawing.

[0018] [Figure 1] 1 illustrates a flowchart of an exemplary method for fabricating a semiconductor device, according to some embodiments. [Figure 2] 2A-2D show cross-sectional views of a semiconductor device at various stages of fabrication produced by the method of FIG. 1, according to some embodiments. [Figure 3] 2A-2D show cross-sectional views of a semiconductor device at various stages of fabrication produced by the method of FIG. 1, according to some embodiments. [Figure 4] 2A-2D show cross-sectional views of a semiconductor device at various stages of fabrication produced by the method of FIG. 1, according to some embodiments. [Figure 5] 2A-2D show cross-sectional views of a semiconductor device at various stages of fabrication produced by the method of FIG. 1, according to some embodiments. [Figure 6] 2A-2D show cross-sectional views of a semiconductor device at various stages of fabrication produced by the method of FIG. 1, according to some embodiments. [Figure 7] 2A-2D show cross-sectional views of a semiconductor device at various stages of fabrication produced by the method of FIG. 1, according to some embodiments. [Figure 8] 2A-2D show cross-sectional views of a semiconductor device at various stages of fabrication produced by the method of FIG. 1, according to some embodiments. [Figure 9] 9 illustrates an exemplary apparatus configured to form at least a portion of the semiconductor device shown in FIGS. 2-8, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0019] Reference will now be made to the exemplary embodiments illustrated in the drawings, and specific language will be used to describe the embodiments herein. It will be understood, however, that no limitation on the scope of the claims or the present disclosure is intended. Alterations and further modifications to the inventive features illustrated herein, and further applications of the principles of the subject matter illustrated herein that may occur to one skilled in the art in possession of this disclosure, are intended to be within the scope of the subject matter disclosed herein. Other embodiments may be used and / or other changes may be made without departing from the spirit or scope of the disclosure. The exemplary embodiments described in the detailed description do not limit the presented subject matter.

[0020] The reduction in feature size (sometimes referred to as "critical dimension" (CD)) can lead to various manufacturing challenges. For example, a three-layer photomask layer is commonly used to pattern layers in semiconductor processes. However, as device sizes become smaller and smaller, using only a three-layer photoresist may require some trade-offs, which can degrade semiconductor device performance and even lead to device failure. As the number of features with different CDs formed on a single substrate increases, forming features with smaller CDs generally compromises features with larger CDs, and vice versa. For example, while relaxing etching conditions is required to form features with smaller CDs, such relaxing etching conditions can cause features with larger CDs to be incompletely formed. Such problems are sometimes referred to as a compromise in local CD uniformity. Thus, while existing methods for patterning semiconductor devices have generally been adequate for their intended purposes, in some aspects the methods have not been entirely satisfactory.

[0021] FIG. 1 illustrates a flowchart of an exemplary method 100 for forming a semiconductor device using a modified photomask layer, according to various embodiments. FIGS. 2-8 are cross-sectional views of such a semiconductor device 200, illustrating some of the key operations described in the method 100 of FIG. 1. For example, features (e.g., openings) having high aspect ratios are formed (e.g., etched) in one or more dielectric layers disposed over a semiconductor substrate. Such high aspect ratio openings can be rectangular, square, circular (such as contacts), or any other regular or irregular shape. In various embodiments, the high aspect ratio openings can be trenches or holes.

[0022] 1 and the cross-sectional view of FIG. 2, a photomask layer 204 is deposited on a substrate 200. The substrate 200 may comprise a semiconductor substrate 206 having an overlying dielectric layer 208. While the dielectric layer 208 is shown as a single layer, it should be understood that the dielectric layer 208 may include multiple layers stacked on top of each other. Additionally, an etch stop layer (not shown) may be formed interposed between the semiconductor substrate 206 and the dielectric layer 208.

[0023] In various embodiments, the semiconductor substrate 206 may be a single-crystal semiconductor substrate, such as a single-crystal silicon wafer or a silicon-on-insulator substrate. As described above, in some embodiments, the dielectric layer 208 may include one or more dielectric layers, each formed of silicon oxide or an insulating material (e.g., a low-k dielectric material). A low-k dielectric material is a material having a dielectric constant lower than that of standard silicon dioxide (which has a dielectric constant of approximately 3.9). For example, low-k dielectric materials include, but are not limited to, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, spin-on organic polymer dielectrics, spin-on silicone-based polymer dielectrics, polyimides, aromatic polymers, fluorine-doped amorphous carbon, vapor-deposited parylene, and the like. In some other embodiments, the dielectric layer 208 may include a plurality of alternating first and second dielectric layers, each of which includes silicon dioxide and each of which includes silicon nitride or silicon oxynitride. In such an embodiment, the nitride-based second dielectric layer may later be replaced with a metal layer, while the oxide-based first dielectric layer may serve as a separation layer between those metal layers.

[0024] The photomask layer 204 may be a three-layer photomask (shown in the example of FIG. 2 ) having a bottom organic layer 216, an intermediate anti-reflective coating layer 218, and a top photoresist layer 220 stacked on top of each other. For example, the material of the bottom organic layer 216 may include multiple uncrosslinked monomers or polymers. The material of the intermediate anti-reflective coating layer 218 may include a silicon-containing inorganic polymer. The top photoresist layer (e.g., 220) may include a photosensitive element such as a photoacid generator (PAG), which allows a photolithography process to be performed to pattern the top photoresist layer. The pattern from the photoresist layer can then be transferred to layers 218 and 216, which subsequently function as an etch mask for etching the underlying layers, such as 208. However, it should be understood that the photomask layer 204 may include any suitable single layer or any number of stacked layers while remaining within the scope of the present disclosure. For example, the photomask layer 204 can be a two-layer photomask having a bottom anti-reflective coating layer and a top photoresist layer.

[0025] Referring to operation 104 of FIG. 1 and the cross-sectional view of FIG. 3 , several patterns, e.g., 310 and 320, are formed in the upper photoresist layer 220 of the photomask layer 204. Once the upper photoresist layer 220 is formed, a photolithography process is performed on the upper photoresist layer 220 to form patterns 310 and 320, each of which may extend through the upper photoresist layer 220. In some embodiments, the patterns 310 and 320 may have different widths, e.g., W1 and W2, respectively. The photolithography process may include exposing the workpiece to a radiation beam. The radiation beam may expose the upper photoresist layer 220 using a lithography system that provides a pattern of radiation according to an IC design layout. In one embodiment, the lithography system includes ultraviolet (UV) radiation, deep ultraviolet (DUV) radiation, extreme ultraviolet (EUV) radiation, X-ray radiation, and / or other suitable radiation types. In an alternative embodiment, the lithography system includes a charged particle lithography system, such as an electron beam or ion beam lithography system.

[0026] Referring to operation 106 of FIG. 1 and the cross-sectional view of FIG. 4, several first openings, e.g., 410 and 420, are formed in the bottom organic layer 216 of the photomask layer 204. As shown, the first openings 410 and 420 are formed by transferring or otherwise extending the patterns 310 and 320, respectively, into the bottom organic layer 216. In some embodiments, the first openings 410 and 420 may not extend all the way through the bottom organic layer 216, as shown in FIG. 4. In other words, each of the first openings 410 and 420 has a bottom surface formed from a corresponding remaining portion of the bottom organic layer 216. When the patterns 310 and 320 are transferred into the first openings 410 and 420, the first openings 410 and 420 may also have different widths, respectively.

[0027] The first openings 410 and 420 can be formed by an etching process to "open" the bottom organic layer 216. The etching gas for the etching process includes HBr, Cl, O, and N. The HBr gas may have a flow rate in a range from about 40 sccm to about 60 sccm, such as about 50 sccm, the Cl gas may have a flow rate in a range from about 5 sccm to about 40 sccm, such as about 20 sccm, the O gas may have a flow rate in a range from about 40 sccm to about 150 sccm, such as about 90 sccm, and the N gas may have a flow rate in a range from about 30 sccm to about 80 sccm, such as about 50 sccm.

[0028] Referring to operation 108 of FIG. 1 and the cross-sectional view of FIG. 5 , first openings 410 and 420 are partially covered by silicon layers 510 and 520, respectively. In some embodiments, silicon layers 510 and 520 may be formed by a physical vapor deposition (PVD)-like process, which may sometimes be referred to as a non-conformal deposition process. Given the non-conformal nature, silicon layers 510 and 520 may be formed to have different thicknesses. For example, silicon layer 510 formed in first opening 410 may have a thinner thickness, and silicon layer 520 formed in first opening 420 may have a thicker thickness. Furthermore, in some embodiments, silicon layer 510 may extend only partially along the upper sidewall of first opening 410, and silicon layer 520 may extend only partially along the upper sidewall of first opening 420.

[0029] Referring to operation 110 of FIG. 1 and the cross-sectional view of FIG. 6, several second openings, e.g., 610 and 620, are formed by extending the first openings 410 and 420, respectively. Once the silicon layers 510 and 520 are formed, they can serve as an "extra" mask for etching the bottom organic layer 216 to form the second openings 610 and 620, respectively. Specifically, the second openings 610 and 620 can be formed by an etching process to etch the remaining portions of the bottom organic layer 216 below the first openings 410 and 420 (FIG. 5). The etching gas for the etching process includes HBr, Cl, O, and N. The HBr gas may have a flow rate in the range of about 40 sccm to about 60 sccm, for example, about 50 sccm, the Cl gas may have a flow rate in the range of about 5 sccm to about 40 sccm, for example, about 20 sccm, the O gas may have a flow rate in the range of about 40 sccm to about 150 sccm, for example, about 90 sccm, and the N gas may have a flow rate in the range of about 30 sccm to about 80 sccm, for example, about 50 sccm.

[0030] In some embodiments, the silicon layers 510 and 520 may advantageously reduce the difference (i.e., W1-W2) between the patterns 310 and 320 initially formed in the upper photoresist layer 220 by extending the silicon layers 510 and 520 along the upper sidewalls of the first openings 410 and 420, respectively. For example, if the silicon layers 510 and 520 serve as a mask for the first openings 410 and 420, when the first openings 410 and 420 are extended to form the second openings 610 and 620, respectively, the difference in width (i.e., W3-W4) of the second openings 610 and 620 is small compared to the difference between W1 and W2. Furthermore, the presence of the silicon layer 510 in the smaller first opening 410 may advantageously increase the over-etch margin, thereby allowing a greater amount of over-etching to be performed on the larger first opening 410 while simultaneously maintaining the original CD of the smaller first opening 420. In other words, even if an additional amount of over-etching is performed (which can ensure that a larger second opening 620 is formed), the original dimensions (e.g., W1) of the smaller first opening 410 are not overly exaggerated, i.e., W3 can be precisely controlled to be substantially close to W1.

[0031] 1 and the cross-sectional view of FIG. 7, by extending the second openings 610 and 620, several third openings, for example, 710 and 720, are formed in the dielectric layer 208. In some embodiments, the third openings 710 and 720 may be formed by an etching process to etch the dielectric layer 208, and the remaining portions of the photomask layer 204 may function as a mask. The etching gas for the etching process includes CF, CHF, H, N, and Ar. In this embodiment, CHF gas functions as a main gas, and in this embodiment, N and Ar gases function as auxiliary gases. The CF4 gas may have a flow rate in a range from about 50 sccm to about 70 sccm, e.g., about 60 sccm, the CHF3 gas may have a flow rate in a range from about 45 sccm to about 65 sccm, e.g., about 55 sccm, the H2 gas may have a flow rate in a range from about 50 sccm to about 250 sccm, e.g., about 150 sccm, the N2 gas may have a flow rate in a range from about 50 sccm to about 80 sccm, e.g., about 65 sccm, and the Ar gas may have a flow rate in a range from about 40 sccm to about 60 sccm, e.g., about 50 sccm. Once the third openings 710 and 720 are formed, the remaining portions of the photomask layer 204 (including the silicon layers 510 and 520) may be removed from the workpiece.

[0032] Referring to operation 114 of FIG. 1 and the cross-sectional view of FIG. 8 , third openings 710 and 720 are filled with a conductive material to form several interconnect structures, e.g., 810 and 820, respectively. In some embodiments, third openings 710 and 720 may each include at least one of a trench or a via opening. The conductive material may include, for example, a barrier layer, a seed layer, a liner, or multiple layers, or combinations thereof, not shown. A fill material, such as copper, a copper alloy, aluminum, an aluminum alloy, or the like, or combinations thereof, may be formed on the layer / liner using an electrochemical plating (ECP) method and / or other deposition method. A chemical-mechanical polishing (CMP) process and / or an etching process may be used to remove excess conductive material from above the top surface of patterned dielectric layer 208 to form interconnect structures 810 and 820 in patterned dielectric layer 208.

[0033] In various embodiments, silicon layers 510 and 520 can be formed by an apparatus 900 shown in FIG. 9 . As shown, apparatus 900 includes a chamber 910, which can house a stage 920 configured to position a workpiece 930 (e.g., the semiconductor device 200 described above) and one or more electrodes 950. In some embodiments, electrode 950 is positioned on a top side of workpiece 930, i.e., its bottom side faces stage 920, and electrode 950 is positioned opposite workpiece 930 from stage 920. However, it should be understood that electrode 950 can be positioned anywhere within chamber 910. Furthermore, chamber 950 can include any number of various other electrodes while remaining within the scope of the present disclosure. In some embodiments, electrode 950 is made of silicon atoms, or at least has a workpiece-facing surface made of silicon atoms. Thus, the plasma 940 induced in the chamber 910 can sputter silicon atoms from the electrode 950 and redeposit these sputtered silicon atoms onto the top surface of the workpiece (e.g., to form silicon layers 510 and 520). In some embodiments, the sputtering gas of the plasma 940 includes argon or another suitable inert gas. Furthermore, to stabilize the plasma 940, the electrode 950 can be electrically connected to a DC bias (e.g., a DC voltage, a DC current), sometimes referred to as a DC-superimposed plasma.

[0034] In the preceding description, specific details have been set forth, such as the particular configuration of the processing system and descriptions of the various components and processes used in the system. However, it should be understood that the technology herein can be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numerical values, materials, and configurations have been set forth to provide a thorough understanding. However, embodiments can be practiced without such specific details. Components having substantially the same functional structure are designated by similar reference numerals, and therefore some redundant description may be omitted.

[0035] To facilitate understanding of various embodiments, various techniques have been described as multiple separate operations. The order of description should not be construed as implying that these operations are necessarily order dependent. In fact, these operations need not be performed in the order presented. The operations described may be performed in a different order than in the described embodiments. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0036] As used herein, "substrate" or "target substrate" generally refers to an object to be processed in accordance with the present invention. A substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be, for example, a base substrate structure such as a semiconductor wafer, a reticle, or a layer, e.g., a thin film, on or overlying the base substrate structure. Thus, substrate is not limited to any particular base structure, underlying or overlying layer, patterned or unpatterned, but rather is intended to include any such layer or base structure, and any combination of layers and / or base structures. While the specification may refer to particular types of substrates, this is for illustrative purposes only.

[0037] Those skilled in the art will appreciate that many variations are possible in the operation of the techniques described above while still achieving the same objectives of the present invention. Such variations are intended to be within the scope of the present disclosure. Accordingly, the above description of embodiments of the present invention is not intended to be limiting. Rather, any limitations to embodiments of the present invention are presented in the following claims.

Claims

1. 1. A method of forming a semiconductor device, comprising: forming a photomask layer disposed on a dielectric material, the photomask layer comprising a polymer layer; partially etching the polymer layer to form a first opening; covering a sidewall of the first opening with a first silicon layer; further etching the polymer layer using the first silicon layer as a mask to extend the first opening to form a second opening; A method comprising:

2. The step of covering the sidewall of the first opening with a first silicon layer includes: sputtering an electrode of the chamber via a plasma to generate a plurality of sputtered silicon atoms; redepositing at least a portion of the plurality of sputtered silicon atoms over the first opening to form the first silicon layer; The method of claim 1 , comprising:

3. The method of claim 2 , wherein the plasma comprises an argon plasma.

4. The method of claim 2 , wherein the electrode comprises silicon.

5. The method of claim 2 , wherein the electrodes are electrically connected to a DC bias.

6. partially etching the polymer layer to form a third opening; covering sidewalls of the third opening with a second silicon layer, the first silicon layer having a first thickness and the second silicon layer having a different second thickness; further etching the polymer layer using the second silicon layer as a mask to extend the third opening to form a fourth opening; The method of claim 1 further comprising:

7. The method of claim 6 , wherein the first opening has a first width and the third opening has a second width, the first width being greater than the second width.

8. The method of claim 7 , wherein the first thickness is greater than the second thickness.

9. etching the dielectric material through the second opening; removing remaining portions of the photomask layer and the first silicon layer; The method of claim 1 , comprising:

10. 1. A method of forming a semiconductor device, comprising: forming a photomask layer disposed on a dielectric material, the photomask layer comprising a polymer layer; partially etching the polymer layer to form a first opening and a second opening, the first opening having a first width and the second opening having a second width different from the first width; covering a partial sidewall of the first opening and a partial sidewall of the second opening with a first silicon layer and a second silicon layer, respectively, the first silicon layer having a first thickness and the second silicon layer having a second thickness different from the first thickness; further etching the polymer layer with the first silicon layer and the second silicon layer acting as respective masks to extend the first opening to form a third opening and extend the second opening to form a fourth opening; A method comprising:

11. The step of covering a partial sidewall of the first opening and a partial sidewall of the second opening with a first silicon layer and a second silicon layer, respectively, includes: sputtering an electrode of the chamber via a plasma to generate a plurality of sputtered silicon atoms; redepositing at least a portion of the sputtered silicon atoms over the first opening and the second opening to form the first silicon layer and the second silicon layer, respectively; The method of claim 10, comprising:

12. The method of claim 11 , wherein the electrode comprises silicon.

13. The method of claim 11 , wherein the electrodes are electrically connected to a DC bias.

14. 11. The method of claim 10, wherein the steps of covering partial sidewalls of the first opening and partial sidewalls of the second opening with a first silicon layer and a second silicon layer, respectively, comprise a physical vapor deposition (PVD)-like process.

15. The method of claim 10 , wherein the first width is greater than the second width, such that the first thickness is greater than the second thickness.

16. etching the dielectric material through the third opening and the fourth opening to form a first trench and a second trench, respectively; removing remaining portions of the photomask layer, the first silicon layer, and the second silicon layer; The method of claim 10, comprising:

17. 17. The method of claim 16, further comprising filling the first trench and the second trench with a metal material to form a first interconnect structure and a second interconnect structure, respectively.

18. A semiconductor manufacturing apparatus comprising: a chamber configured to house a semiconductor device having a dielectric layer covered by a photomask layer, the photomask layer comprising a polymer layer; and an electrode comprising silicon; The chamber is configured to contain a plasma that sputters the electrode to generate a plurality of silicon atoms and redeposits the plurality of silicon atoms onto the opening that extends partially through the polymer layer.

19. 20. The apparatus of claim 18, wherein the plurality of silicon atoms form a silicon layer that extends along an upper portion of a sidewall of the opening.

20. 20. The apparatus of claim 18, wherein the electrodes are electrically connected to a DC bias.

Images