Indication device

Abstract

The display device includes a first lower pattern disposed in a first region and in the same layer as a light-emitting lower electrode, a second lower pattern disposed in a second region adjacent to the first region and in the same layer as the first lower pattern, and an upper electrode disposed on the first lower pattern and the second lower pattern, contacting the first lower pattern in the first region and overlapping the second lower pattern in the second region.

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] The display device includes an upper electrode (e.g., a cathode electrode) formed as a plate electrode, and the upper electrode is formed in a display area and a peripheral area adjacent to the display area. The upper electrode formed in the display area can apply a voltage to a light-emitting layer together with a lower electrode. The upper electrode formed in the peripheral area receives a voltage from an external source.

[0003] Since the upper electrode receives the voltage from the peripheral region, it can come into contact with the lower pattern formed in the peripheral region. Therefore, the lower pattern formed in the peripheral region is exposed during the manufacturing process of the display device. However, during the process of forming the upper electrode, if a mask collides with the lower pattern, the upper electrode may be peeled off, which reduces the yield of the display device. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device with improved yield.

[0005] Another object of the present invention is to provide a method for manufacturing the display device.

[0006] However, the object of the present invention is not limited to the above object, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Means for solving the problem]

[0007] In order to achieve the object of the present invention, a display device according to one embodiment of the present invention is characterized by including: a light-emitting lower electrode arranged in a display area on a substrate; a first lower pattern arranged in a first area adjacent to the display area and arranged in the same layer as the light-emitting lower electrode; a second lower pattern arranged in a second area adjacent to the first area and arranged in the same layer as the first lower pattern; and an upper electrode arranged on the first lower pattern and the second lower pattern, contacting the first lower pattern in the first area and overlapping the second lower pattern in the second area.

[0008] The upper electrode is disconnected from the second lower pattern in the second region.

[0009] The pixel alignment film may further include a pixel alignment layer disposed on the first lower pattern and the second lower pattern, and no opening is defined in the pixel alignment layer that overlaps the second lower pattern.

[0010] The pixel defining layer completely covers the second lower pattern.

[0011] An opening exposing the first lower pattern is defined in the pixel defining layer.

[0012] The pixel defining layer defines an opening exposing the light emitting lower electrode, and the light emitting layer is disposed between the light emitting lower electrode and the upper electrode.

[0013] The light emitting lower electrode, the first lower pattern, and the second lower pattern have the same shape.

[0014] The display device further includes a dam structure disposed in a non-display area adjacent to the second area, and the second lower pattern is disposed between the first lower pattern and the dam structure.

[0015] The display device further includes a first inorganic layer disposed on the upper electrode, an organic layer disposed on the first inorganic layer, and a second inorganic layer disposed on the organic layer.

[0016] The display device further includes a transistor arranged below the light-emitting lower electrode, the transistor including a lower metal pattern arranged on the substrate, an active pattern arranged on the lower metal pattern, a gate electrode arranged on the active pattern, and a connection electrode arranged on the gate electrode, and the light-emitting lower electrode is electrically connected to the active pattern through the connection electrode.

[0017] In order to achieve another object of the present invention, a method for manufacturing a display device according to one embodiment of the present invention includes the steps of: forming a light-emitting lower electrode in a display area on a substrate; forming a first lower pattern together with the light-emitting lower electrode in a first area adjacent to the display area; forming a second lower pattern together with the first lower pattern in a second area adjacent to the first area; and forming an upper electrode on the first lower pattern and the second lower pattern, the upper electrode contacting the first lower pattern in the first area and overlapping the second lower pattern in the second area.

[0018] The manufacturing method further includes forming a preliminary pixel definition layer covering the first lower pattern and the second lower pattern, and patterning the preliminary pixel definition layer using a first mask to expose the first lower pattern.

[0019] While the preliminary pixel defining layer is patterned, the preliminary pixel defining layer overlapping the second region is not removed.

[0020] The first mask includes a blocking portion that overlaps the second region.

[0021] The first mask further includes a pattern portion overlapping the first region and an opening portion overlapping the non-display region, and the blocking portion is located between the pattern portion and the opening portion.

[0022] The manufacturing method further includes forming a light-emitting layer on the first lower pattern using a second mask, the upper electrode is formed using a third mask, and the second region can correspond to an alignment error region of the third mask.

[0023] The first mask is used to pattern the preliminary pixel defining layer so as to expose the light-emitting bottom electrode.

[0024] The manufacturing method further includes forming a first inorganic layer on the upper electrode, forming an organic layer on the first inorganic layer, and forming a second inorganic layer on the organic layer.

[0025] The manufacturing method further includes forming a lower metal pattern on the substrate, forming an active pattern on the lower metal pattern, forming a gate electrode on the active pattern, and forming a connection electrode on the gate electrode. [Effects of the Invention]

[0026] A display device according to the present invention includes a light-emitting lower electrode, a first lower pattern, a second lower pattern, and an upper electrode. The first lower pattern disposed in a first region is connected to the upper electrode and transmits a voltage to the upper electrode. The second lower pattern disposed in a second region adjacent to the first region may be completely covered by a pixel defining layer and overlap the upper electrode, thereby preventing a mask from colliding with the second lower pattern during a process of forming the upper electrode, thereby preventing peeling defects of the upper electrode overlapping the second region.

[0027] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 is a plan view illustrating a display device according to one embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram illustrating a pixel included in the display device of FIG. [Figure 3] FIG. 3 is a cross-sectional view for explaining the display device in FIG. [Figure 4] FIG. 4 is a cross-sectional view for explaining the display device in FIG. [Figure 5] FIG. 5 is an enlarged view of region B in FIG. [Figure 6] FIG. 6 is an enlarged view of region A in FIG. [Figure 7] FIG. 7 is a cross-sectional view illustrating a method for manufacturing the display device in FIG. [Figure 8] 8A to 8C are cross-sectional views illustrating a method for manufacturing the display device in FIG. [Figure 9] 9A to 9C are cross-sectional views illustrating a method for manufacturing the display device in FIG. [Figure 10] 10A to 10C are cross-sectional views illustrating a method for manufacturing the display device in FIG. [Figure 11] FIG. 11 is a cross-sectional view illustrating a method for manufacturing the display device in FIG. [Figure 12] 12A to 12C are cross-sectional views illustrating a method for manufacturing the display device in FIG. [Figure 13] FIG. 13 is a cross-sectional view illustrating a method for manufacturing the display device in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0029] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used to designate the same components in the drawings, and redundant description of the same components will be omitted.

[0030] FIG. 1 is a plan view illustrating a display device according to one embodiment of the present invention.

[0031] As shown in FIG. 1, a display device 1000 according to one embodiment of the present invention is divided into a display area (DA), a first area (AR1), a second area (AR2), and a non-display area (NDA).

[0032] The display area (DA) can have various shapes such as a circle or a polygon, and can have, for example, a square shape as shown in Fig. 1. Pixels (PX) are arranged in the display area (DA) and an image is displayed.

[0033] The first area (AR1) is located adjacent to the display area (DA) and surrounds at least a portion of the display area (DA). For example, the metal pattern disposed in the first area (AR1) can electrically connect the metal pattern disposed in the display area (DA) and the metal pattern disposed in the non-display area (NDA).

[0034] The second area (AR2) is adjacent to the first area (AR1) and is positioned so as to surround at least a part of the first area (AR1). For example, the second area (AR2) is a margin area between the first area (AR1) and the non-display area (NDA).

[0035] The non-display area (NDA) is located adjacent to the second area (AR2) and surrounds at least a portion of the second area (AR2). Various lines for driving the display area (DA) are arranged in the non-display area (NDA).

[0036] An image is displayed in the display area (DA). In one embodiment, at least one pixel (PX) is arranged in the display area (DA).

[0037] The pixels (PX) are electrically connected to data lines (DL), driving voltage lines (PL), and gate lines (GL).

[0038] The gate driver is disposed on at least one side (e.g., the left and / or right side) of the display device 1000. The gate driver receives a clock signal from a clock line. The gate driver generates a first gate signal (e.g., the first gate signal (SC) in FIG. 2) and a second gate signal (e.g., the second gate signal (SS) in FIG. 2) based on the clock signal. The first gate signal (SC) and the second gate signal (SS) are provided to the pixels (PX) via the gate lines (GL).

[0039] In one embodiment, a first pad (PD1), a second pad (PD2), a third pad (PD3), a first voltage line (VL1), and a second voltage line (VL2) are arranged in the non-display area (NDA). However, this is an example, and various lines, drivers, patterns, etc. for driving the display area (DA) are also arranged in the non-display area (NDA).

[0040] In one embodiment, the first to third pads (PD1, PD2, PD3) are arranged in the non-display area (NDA) adjacent to the lower side of the display area (DA). The first to third pads (PD1, PD2, PD3) are provided with signals and / or voltages via a printed circuit board (PCB).

[0041] The first pad (PD1) is provided with a data voltage (for example, the data voltage (DATA) in FIG. 2), which is provided to the pixel (PX) via the data line (DL).

[0042] The second pad (PD2) is provided with a first voltage (e.g., the first voltage (ELVDD) in FIG. 2), which is provided to the pixel (PX) via the first voltage line (VL1) and the driving voltage line (PL).

[0043] The third pad (PD3) is provided with a second voltage (e.g., the second voltage (ELVSS) in FIG. 2), which is provided to the pixel (PX) via an upper electrode (e.g., the upper electrode (CTE) in FIG. 3).

[0044] The second voltage line (VL2) is disposed to surround the second region (AR2). The second voltage (ELVSS) is applied to the second voltage line (VL2), and the second voltage (ELVSS) is transmitted to the upper electrode (CTE) through a first lower pattern (e.g., the first lower pattern (ADE1) in FIG. 4) disposed in the first region (AR1).

[0045] FIG. 2 is a circuit diagram illustrating a pixel included in the display device of FIG.

[0046] As shown in FIG. 2, the pixel (PX) includes a first transistor (T1), a second transistor (T2), a third transistor (T3), a storage capacitor (CST), and a light-emitting element (LED).

[0047] The first transistor (T1) includes a first terminal, a second terminal, and a gate terminal. The first terminal is provided with the first voltage (ELVDD). The second terminal is connected to the light emitting element (LED). The gate terminal is connected to the second transistor (T2). The first transistor (T1) generates a driving current based on the first voltage (ELVDD) and the data voltage (DATA).

[0048] The second transistor (T2) includes a first terminal, a second terminal, and a gate terminal. The first terminal is provided with the data voltage (DATA). The second terminal is connected to the first transistor (T1). The gate terminal is provided with the first gate signal (SC). The second transistor (T2) transmits the data voltage (DATA) in response to the first gate signal (SC).

[0049] The third transistor (T3) includes a first terminal, a second terminal, and a gate terminal. The first terminal is connected to the first transistor (T1). The second terminal is provided with an initialization voltage (VINT). The gate terminal is provided with the second gate signal (SS). The third transistor (T3) transmits the initialization voltage (VINT) in response to the second gate signal (SS).

[0050] The storage capacitor (CST) includes a first terminal and a second terminal. The first terminal is connected to the gate terminal of the first transistor (T1). The second terminal is connected to the first terminal of the third transistor (T3). The storage capacitor (CST) maintains a voltage level of the gate terminal of the first transistor (T1) during an inactive period of the first gate signal (SC).

[0051] The light emitting device (LED) includes a first terminal and a second terminal. The first terminal is connected to the second terminal of the first transistor (T1). The second terminal receives the second voltage (ELVSS). The light emitting device can emit light having a brightness corresponding to the driving current. The light emitting device (LED) can be an organic light emitting device that uses an organic material as an emission layer, or an inorganic light emitting device that uses an inorganic material as an emission layer.

[0052] 3 and 4 are cross-sectional views for explaining the display device of FIG. 1, and FIG. 5 is an enlarged view of region B in FIG.

[0053] As shown in Figure 3, the substrate (SUB) comprises a transparent or opaque material. In one embodiment, materials used as the substrate (SUB) include glass, quartz, plastic, etc. These may be used alone or in combination with each other. The substrate (SUB) may be configured as a single layer or multiple layers combined with each other.

[0054] A lower metal pattern (BML) is disposed on the substrate (SUB). For example, the lower metal pattern (BML) may be formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. Materials used for the lower metal pattern (BML) include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), and indium zinc oxide (IZO). These materials may be used alone or in combination. The lower metal pattern (BML) may be formed as a single layer or as a multilayer structure.

[0055] In one embodiment, the lower metal pattern (BML) receives the initialization voltage (VINT). For example, the lower metal pattern (BML) corresponds to the second terminal of the storage capacitor (CST) described in FIG. 2. In another embodiment, the lower metal pattern (BML) receives the data voltage (DATA). For example, the lower metal pattern (BML) may correspond to the data line (DL) described in FIG. 1. However, the lower metal pattern (BML) is not limited thereto.

[0056] A buffer layer (BFR) is disposed on the substrate (SUB) and covers the lower metal pattern (BML). In one embodiment, the buffer layer (BFR) is formed of an inorganic insulating material. Examples of the inorganic insulating material include silicon oxide, silicon nitride, and silicon oxynitride. These materials may be used alone or in combination with each other. The buffer layer (BFR) may prevent atoms, such as metal atoms, or impurities from diffusing from the substrate (SUB) to the active pattern (ACT). The buffer layer (BFR) may also adjust the rate of heat application during a crystallization process for forming the active pattern (ACT).

[0057] The active pattern (ACT) is disposed on the buffer layer (BFR). In one embodiment, the active pattern (ACT) is formed of a silicon semiconductor material or an oxide semiconductor material. Examples of the silicon semiconductor material that can be used for the active pattern (ACT) include amorphous silicon and polycrystalline silicon. Examples of the oxide semiconductor material that can be used for the active pattern (ACT) include IGZO (InGaZnO) and ITZO (InSnZnO). The oxide semiconductor material can further include indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). These may be used alone or in combination.

[0058] A gate insulating layer (GI) is disposed on the buffer layer (BFR) and covers the active pattern (ACT). In one embodiment, the gate insulating layer (GI) is formed of an insulating material. Insulating materials that can be used for the gate insulating layer (GI) include silicon oxide, silicon nitride, and silicon oxynitride, which can be used alone or in combination with each other.

[0059] A gate electrode (GAT) is disposed on the gate insulating layer (GI). In one embodiment, the gate electrode (GAT) is formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. For example, the gate electrode (GAT) may correspond to the gate terminal of the first transistor (T1) described in FIG. 2.

[0060] An interlayer dielectric layer (ILD) is disposed on the buffer layer (BFR) and the gate dielectric layer (GI). The interlayer dielectric layer (ILD) covers the gate electrode (GAT). In one embodiment, the interlayer dielectric layer (ILD) is formed of an insulating material. Insulating materials that can be used for the interlayer dielectric layer (ILD) include silicon oxide, silicon nitride, and silicon oxynitride, which can be used alone or in combination with each other.

[0061] A first connection electrode (SE) and a second connection electrode (DE) are disposed on the interlayer insulating layer (ILD). For example, the first connection electrode (SE) and the second connection electrode (DE) are formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc.

[0062] In one embodiment, the first connection electrode (SE) and the second connection electrode (DE) are in contact with the active pattern (ACT). Thus, the lower metal pattern (BML), the active pattern (ACT), the gate electrode (GAT), the first connection electrode (SE), and the second connection electrode (DE) can form a transistor (TFT). In another embodiment, the lower metal pattern (BML) can be omitted, and the active pattern (ACT), the gate electrode (GAT), the first connection electrode (SE), and the second connection electrode (DE) can form a transistor (TFT).

[0063] A passivation layer (PVX) is disposed on the interlayer dielectric layer (ILD). In one embodiment, the passivation layer (PVX) is formed of an inorganic insulating material. Inorganic insulating materials that can be used for the passivation layer (PVX) include silicon oxide, silicon nitride, and silicon oxynitride, which can be used alone or in combination with each other.

[0064] A via insulating layer (VIA) is disposed on the passivation layer (PVX). In one embodiment, the via insulating layer (VIA) includes an organic material. Examples of organic materials that can be used as the via insulating layer (VIA) include photoresist, polyacrylic resin, polyimide resin, and acrylic resin. These can be used alone or in combination with each other.

[0065] In another embodiment, the passivation layer (PVX) can be omitted. In this case, the via insulating layer (VIA) includes organic and inorganic materials. Materials that can be used for the via insulating layer (VIA) include photoresist, polyacrylic resin, polyimide resin, acrylic resin, silicon oxide, silicon nitride, silicon oxynitride, etc., which can be used alone or in combination with each other.

[0066] The via insulating layer (VIA) overlaps the display area (DA), and can provide a flat upper surface for forming a light-emitting bottom electrode (EADE).

[0067] The light-emitting bottom electrode (EADE) is disposed on the via insulating layer (VIA). In one embodiment, the light-emitting bottom electrode (EADE) is electrically connected to the transistor (TFT) through the second connecting electrode (DE). In another embodiment, the light-emitting bottom electrode (EADE) is connected to the first connecting electrode (SE). In yet another embodiment, the light-emitting bottom electrode (EADE) is connected to the bottom metal pattern (BML) through the first connecting electrode (SE).

[0068] The light-emitting bottom electrode (EADE) may be formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. Materials that can be used for the light-emitting bottom electrode (EADE) include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These materials may be used alone or in combination.

[0069] The light emitting lower electrode (EADE) may be formed as a single layer or as a multi-layer structure, for example, an ITO / Ag / ITO structure.

[0070] A pixel defining layer (PDL) is disposed on the via insulating layer (VIA). The pixel defining layer (PDL) includes an organic material. Examples of organic materials that can be used as the pixel defining layer (PDL) include photoresist, polyacrylic resin, polyimide resin, and acrylic resin. These materials can be used alone or in combination with each other.

[0071] An opening for forming an emitting layer (EL) is defined in the pixel defining layer (PDL) of the display area (DA).

[0072] The light-emitting layer (EL) is disposed on the light-emitting bottom electrode (EADE). The top electrode (CTE) is disposed on the light-emitting layer (EL). The light-emitting layer (EL) can emit light based on a voltage difference between the light-emitting bottom electrode (EADE) and the top electrode (CTE).

[0073] A first inorganic layer (IL1) is disposed on the top electrode (CTE). In one embodiment, the first inorganic layer (IL1) is formed as an inorganic material. Inorganic materials that can be used for the first inorganic layer (IL1) include silicon oxide, silicon nitride, and silicon oxynitride, which can be used alone or in combination with each other.

[0074] An organic layer (OL) is disposed on the first inorganic layer (IL1). In one embodiment, the organic layer (OL) comprises an organic material. Examples of organic materials that can be used for the organic layer (OL) include photoresist, polyacrylic resin, polyimide resin, and acrylic resin. These can be used alone or in combination with each other.

[0075] The second inorganic layer (IL2) is disposed on the organic layer (OL). The second inorganic layer (IL2) is formed as an inorganic material, and includes, for example, the same material as the first inorganic layer (IL1).

[0076] 4 and 5, a first driving circuit pattern (DCP1), a first lower clock line (LCL1), and a second lower clock line (LCL2) are disposed on the substrate (SUB). In one embodiment, the first driving circuit pattern (DCP1), the first lower clock line (LCL1), and the second lower clock line (LCL2) are disposed in the same layer as the lower metal pattern (BML) and include the same material.

[0077] The first driving circuit pattern (DCP1) is disposed in the second area (AR2) and constitutes the gate driver. The first lower clock line (LCL1) and the second lower clock line (LCL2) are disposed in the non-display area (NDA) and constitute the clock lines. However, the areas in which the first driving circuit pattern (DCP1), the first lower clock line (LCL1), and the second lower clock line (LCL2) are disposed are not limited thereto.

[0078] A second driving circuit pattern (DCP2) may be disposed in the second region (AR2) on the buffer layer (BFR). In one embodiment, the second driving circuit pattern (DCP2) is disposed in the same layer as the gate electrode (GAT) and includes the same material. The second driving circuit pattern (DCP2) and the first driving circuit pattern (DCP1) constitute the gate driver.

[0079] A transmission line (TL), a first upper clock line (UCL1), and a second upper clock line (UCL2) are disposed on the interlayer dielectric layer (ILD). In one embodiment, the transmission line (TL) is electrically connected to the first connection electrode (SE) and / or the second connection electrode (DE). The first upper clock line (UCL1) contacts the first lower clock line (LCL1), and the second upper clock line (UCL2) contacts the second lower clock line (LCL2).

[0080] The first lower pattern (ADE1) and the second lower pattern (ADE2) are disposed on the via insulating layer (VIA). In one embodiment, the first lower pattern (ADE1) and the second lower pattern (ADE2) are disposed in the same layer as the light emitting lower electrode (EADE), and may include the same material and have the same shape.

[0081] The first lower pattern (ADE1) is disposed in the first region (AR1). The first lower pattern (ADE1) is electrically connected to the second voltage line (VL2) described in FIG. 1. The first lower pattern (ADE1) may also contact the upper electrode (CTE) through an opening in the pixel defining layer (PDL) defined in the first region (AR1). As a result, the first lower pattern (ADE1) may transfer the second voltage (ELVSS) applied to the second voltage line (VL2) to the upper electrode (CTE).

[0082] The second lower pattern (ADE2) is disposed in the second region (AR2). The second lower pattern (ADE2) is electrically connected to or separated from the first lower pattern (ADE1). The second lower pattern (ADE2) is separated from or separated from the upper electrode (CTE) by the pixel defining layer (PDL) formed in the second region (AR2).

[0083] The pixel definition layer (PDL) extends to the first region (AR1) and the second region (AR2). An opening having the same shape as the display region (DA) is defined in the pixel definition layer (PDL) overlapping the first region (AR1), thereby exposing the first lower pattern (ADE1). No opening is defined in the pixel definition layer (PDL) overlapping the second region (AR2), thereby completely covering the second lower pattern (ADE2).

[0084] The upper electrode (CTE) extends to the first region (AR1) and the second region (AR2). The upper electrode (CTE) overlapping the first region (AR1) may contact the first lower pattern (ADE1) through an opening defined in the pixel defining layer (PDL). The upper electrode (CTE) overlapping the second region (AR2) contacts the pixel defining layer (PDL) and is disconnected from the second lower pattern (ADE2).

[0085] In one embodiment, at least one dam structure is disposed in the non-display area (NDA). For example, a first dam structure (DS1), a second dam structure (DS2), a third dam structure (DS3), and a fourth dam structure (DS4) are disposed. The first to fourth dam structures (DS1, DS2, DS3, DS4) are spaced apart from each other in the first direction (D1) and extend side by side in the second direction (D2). The first to fourth dam structures (DS1, DS2, DS3, DS4) can prevent the organic layer (OL) from flowing outward.

[0086] In one embodiment, the first dam structure (DS1) is a single-story structure, and each of the second dam structure (DS2), the third dam structure (DS3), and the fourth dam structure (DS4) is a multi-story structure including a substructure and a superstructure.

[0087] The first dam structure (DS1), the second lower structure (LDS2), the third lower structure (LDS3), and the fourth lower structure (LDS4) are disposed in the same layer as the via insulating layer (VIA) and include the same material. Also, the second upper structure (UDS2), the third upper structure (UDS3), and the fourth upper structure (UDS4) are disposed on the second lower structure (LDS2), the third lower structure (LDS3), and the fourth lower structure (LDS4), respectively, and are disposed in the same layer as the pixel defining layer (PDL) and include the same material.

[0088] Since the pixel defining layer (PDL) remains in the second region (AR2), the second lower pattern (ADE2) is covered with the pixel defining layer (PDL), so that in the process of forming the upper electrode (CTE), a mask does not collide with the second lower pattern (ADE2), and peeling failure of the upper electrode (CTE) overlapping the second region (AR2) can be prevented.

[0089] FIG. 6 is an enlarged view of region A in FIG.

[0090] Referring to FIG. 6, as described above, the pixel defining layer (PDL) is disposed in the display area (DA), the first area (AR1), and the second area (AR2).

[0091] The pixel defining layer (PDL) disposed in the display area (DA) has an opening defined therein, and the light emitting layer (EL) is accommodated in the opening. The pixel defining layer (PDL) disposed in the first area (AR1) has an opening defined therein having the same shape as the display area (DA), and the first lower pattern (ADE1) exposed through the opening contacts the upper electrode (CTE). The pixel defining layer (PDL) disposed in the second area (AR2) has no opening defined therein, and the second lower pattern (ADE2) can be completely covered by the pixel defining layer (PDL).

[0092] 7 to 13 are cross-sectional views for explaining a method for manufacturing the display device of FIG.

[0093] 7, the light emitting lower electrode (EADE), the first lower pattern (ADE1), and the second lower pattern (ADE2) are formed on the via insulating layer (VIA). The light emitting lower electrode (EADE), the first lower pattern (ADE1), and the second lower pattern (ADE2) have the same shape, and the light emitting lower electrode (EADE) is formed in the display area (DA), the first lower pattern (ADE1) is formed in the first area (AR1), and the second lower pattern (ADE2) is formed in the second area (AR2).

[0094] 8, a preliminary pixel defining layer (PDL') is formed in the display area (DA), the first area (AR1), the second area (AR2), and the non-display area (NDA). The preliminary pixel defining layer (PDL') covers the light emitting bottom electrode (EADE), the first lower pattern (ADE1), and the second lower pattern (ADE2).

[0095] 9 and 10, the preliminary pixel defining layer (PDL') is patterned. In one embodiment, the preliminary pixel defining layer (PDL') is patterned using a first mask (MS1), and the pixel defining layer (PDL), the second upper structure (UDS2), the third upper structure (UDS3), and the fourth upper structure (UDS4) may be formed together.

[0096] Specifically, the first mask (MS1) includes a pattern portion (PP), a blocking portion (BP), and an opening portion (OP), where the pattern portion (PP) overlaps the display area (DA) and the first area (AR1), the blocking portion (BP) overlaps the second area (AR2), and the opening portion (OP) overlaps the non-display area (NDA).

[0097] The pattern portion (PP) is aligned to overlap the display area (DA) and the first area (AR1), and may have a shape corresponding to an opening formed in the pixel defining layer (PDL) overlapping the display area (DA) and the first area (AR1).

[0098] The blocking portion (BP) is aligned to overlap the second region (AR2). The blocking portion (BP) can block ultraviolet (UV) light. Therefore, while the preliminary pixel defining layer (PDL') is patterned, the preliminary pixel defining layer (PDL') overlapping the second region (AR2) remains without being removed. In addition, the blocking portion (BP) can further overlap the second to fourth upper structures (UDS2, UDS3, UDS4).

[0099] The opening (OP) is aligned to overlap the non-display area (NDA), and allows ultraviolet (UV) light to pass through the opening (OP), thereby removing the preliminary pixel defining layer (PDL') that overlaps the opening (OP).

[0100] 11, the light-emitting layer (EL) is formed using a second mask (MS2), for example, a fine metal mask having a shape corresponding to an opening formed in the pixel defining layer (PDL) overlapping the display area (DA).

[0101] The top electrode (CTE) is formed as shown in Figure 12. In one embodiment, the top electrode (CTE) is formed using a third mask (MS3).

[0102] Specifically, the third mask (MS3) is aligned to form the upper electrode (CTE) in the display area (DA), the first area (AR1), and the second area (AR2). During the alignment of the third mask (MS3), an edge of the third mask (MS3) may be misaligned within the second area (AR2). That is, the second area (AR2) may correspond to an alignment error area of ​​the third mask (MS3). As described above with reference to FIGS. 9 and 10, the pixel defining layer (PDL) remains in the second area (AR2). This prevents the third mask (MS3) from colliding with the second lower pattern (ADE2) in the second area (AR2), thereby preventing poor peeling of the upper electrode (CTE) in the second area (AR2).

[0103] Referring to FIG. 13, the first inorganic layer (IL1), the organic layer (OL), and the second inorganic layer (IL2) may be formed in sequence.

[0104] While exemplary embodiments of the present invention have been described above, those skilled in the art will appreciate that various modifications and variations can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims that follow. [Industrial Applicability]

[0105] The present invention can be applied to display devices and electronic devices including the same, such as high-resolution smartphones, mobile phones, smart pads, smart watches, tablet PCs, vehicle navigation systems, televisions, computer monitors, and laptop computers. [Explanation of symbols]

[0106] 1000:Display device DA:Display area AR1: First Area AR2: Second Area EADE: Light-emitting bottom electrode ADE1: First lower pattern ADE2: Second lower pattern PDL: Pixel-defined membrane CTE:Top electrode

Claims

1. a light-emitting lower electrode disposed in a display region on the substrate; a first lower pattern disposed in a first region adjacent to the display region and in the same layer as the light-emitting lower electrode; a second lower pattern disposed in a second region adjacent to the first region and in the same layer as the first lower pattern; an upper electrode disposed on the first lower pattern and the second lower pattern, contacting the first lower pattern in the first region and overlapping the second lower pattern in the second region.

2. The display device of claim 1 , wherein the upper electrode does not contact the second lower pattern.

3. a pixel defining layer disposed on the first lower pattern and the second lower pattern; The display device of claim 1 , wherein the pixel defining layer does not include an opening in an area overlapping the second lower pattern.

4. The display device of claim 3 , wherein the pixel defining layer completely covers the second lower pattern.

5. The display device of claim 3 , wherein the pixel defining layer includes an opening disposed in a region corresponding to the first lower pattern.

6. the pixel defining layer includes an opening disposed in a region corresponding to the light emitting lower electrode; 4. The display device according to claim 3, wherein a light-emitting layer is disposed between the light-emitting lower electrode and the upper electrode.

7. The display device of claim 1 , wherein the light-emitting lower electrode, the first lower pattern, and the second lower pattern have the same shape.

8. further comprising a dam structure disposed in a non-display area adjacent to the second area; The display device of claim 1 , wherein the second lower pattern is disposed between the first lower pattern and the dam structure.

9. a first inorganic layer disposed on the upper electrode; an organic layer disposed on the first inorganic layer; 2. The display device according to claim 1, further comprising a second inorganic layer disposed on the organic layer.

10. Further comprising a transistor disposed below the light-emitting lower electrode, The transistor is a lower metal pattern disposed on the substrate; an active pattern disposed on the lower metal pattern; a gate electrode disposed on the active pattern; a connection electrode disposed on the gate electrode, The display device of claim 1 , wherein the lower light-emitting electrode is electrically connected to the active pattern through the connection electrode.

11. forming a light-emitting bottom electrode on the substrate in a display area; forming a first lower pattern in a first region adjacent to the display region; forming a second lower pattern in a second region adjacent to the first region; and forming an upper electrode on the first lower pattern and the second lower pattern, the upper electrode contacting the first lower pattern in the first region and overlapping the second lower pattern in the second region.

12. forming a preliminary pixel defining layer covering the first lower pattern and the second lower pattern; 12. The method of claim 11, further comprising: patterning the preliminary pixel defining layer using a first mask to expose the first lower pattern.

13. 13. The method of claim 12, wherein the preliminary pixel definition layer overlapping the second region is not removed while the preliminary pixel definition layer is patterned.

14. The method of claim 13 , wherein the first mask includes a blocking portion that entirely overlaps the second region.

15. the first mask further includes a pattern portion overlapping the first region and an opening portion overlapping a non-display region; The method of claim 14, wherein the blocking portion is located between the pattern portion and the opening portion.

16. further comprising forming a light-emitting layer on the first lower pattern using a second mask; the top electrode is formed using a third mask; 13. The method of claim 12, wherein the second region corresponds to an alignment error region of the third mask.

17. 13. The method of claim 12, wherein the preliminary pixel defining layer is patterned using the first mask to expose the lower light emitting electrode.

18. forming a first inorganic layer on the upper electrode; forming an organic layer on the first inorganic layer; 12. The method for manufacturing a display device according to claim 11, further comprising the step of forming a second inorganic layer on the organic layer.

19. forming a lower metal pattern on the substrate; forming an active pattern on the lower metal pattern; forming a gate electrode on the active pattern; 12. The method for manufacturing a display device according to claim 11, further comprising the step of forming a connection electrode on the gate electrode.

20. The method of claim 11, wherein the upper electrode does not contact the second lower pattern.

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