Method for manufacturing porous EUV pellicle through protective layer deposition and structure used therefor

Abstract

In order to provide a method for manufacturing a porous EUV pellicle, the method for manufacturing a porous EUV pellicle includes the steps of: preparing a substrate structure having first and second mask layers formed on a first surface of a substrate layer and a second surface opposite to the first surface, respectively; forming a core layer on the first mask layer; forming a plurality of holes through the core layer and the first mask layer so that a region of the first surface of the substrate layer is exposed; forming a protective layer to fill the plurality of holes and cover the core layer; etching the second mask layer so that a region of the second surface of the substrate layer is exposed; and etching the exposed second surface of the substrate layer with an etching solution to expose the first surface of the substrate layer in which the plurality of holes are formed, toward the second surface.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a porous EUV pellicle and a structure used therefor, and more particularly to a method for manufacturing a porous EUV pellicle through protective layer deposition and a structure used therefor. [Background technology]

[0002] EUV (extreme ultraviolet) lithography is a technology that uses a 13.5nm light source in the photolithography process, which is an important step in engraving patterns on semiconductors. In the manufacture of semiconductor chips, it is necessary to engrave extremely fine circuits on wafers. This is to integrate more elements such as transistors into a limited wafer space, thereby improving performance and power efficiency. Summary of the Invention [Problem to be solved by the invention]

[0003] If dust or contaminant particles adhere to the mask used to inscribe circuits, the circuit will not be properly drawn on the wafer. To prevent this mask contamination, a pellicle must be used. A pellicle is a thin, transparent protective layer that protects the mask by preventing contaminant particles from falling on it. Unlike conventional DUV technology, EUV exposure technology requires a reflective mask rather than a transmissive mask because EUV light is absorbed by all materials. Therefore, due to the characteristics of reflective masks, EUV light must pass through the pellicle twice, resulting in a double loss of light. To minimize this loss of light source, high transmittance is essential. In addition to optical properties, EUV pellicles must also meet mechanical, thermal, and chemical requirements. They must have high mechanical strength to withstand the mechanical load generated by the pressure difference between both ends of the pellicle during mask stage acceleration and pump-down, high thermal durability to withstand the thermal shock generated by the absorption of high-power EUV light, and chemical resistance to hydrogen radicals used in optical system cleaning. To date, the technical difficulty of pellicle fabrication and stringent requirements have made their adoption difficult.

[0004] EUV light sources with a wavelength of 13.5 nm are absorbed by many naturally occurring substances, so to ensure the high transmittance necessary for improved productivity in semiconductor manufacturing, EUV pellicles must be in the form of a thin membrane, just a few tens of nanometers thick. The process of manufacturing such EUV pellicles involves thin film deposition, transfer printing, and wet etching. The wet etching process generally involves depositing a thin film on a silicon wafer, then wet etching the silicon with a KOH solution to create a free-standing thin film. KOH solution is inexpensive, has good selectivity, and is therefore primarily used for silicon wet etching.

[0005] However, when an EUV pellicle having a porous structure is manufactured using a conventional EUV pellicle manufacturing process, various problems arise. Specifically, as shown in Figures 1 to 5, a method for manufacturing an EUV pellicle having a porous structure using a conventional EUV pellicle manufacturing process includes the steps of: preparing a substrate structure (ST) in which first and second mask layers 210 and 220 are formed on a first surface 100a and a second surface 100b opposite to the first surface 100a of a substrate layer 100, respectively (S10); forming a core layer 300 on the first mask layer 210; and forming a core layer 300 and a second mask layer 210 on the first mask layer 210 (S20). The method includes a step (S30) of forming a plurality of holes (H) penetrating through the second mask layer 220; a step (S40) of dry-etching the second mask layer 220 so as to expose a region of the second surface 100b of the substrate layer 100; and a step (S50) of wet-etching the exposed second surface 100b of the substrate layer 100 with a potassium hydroxide (KOH) solution to expose the first surface 100a of the substrate layer 100 in which the plurality of holes (H) are formed, in the direction of the second surface 100b.

[0006] When an EUV pellicle having a porous structure is manufactured through the above-described process, contamination and physical damage (e.g., scratches) may occur when the core layer 300 comes into contact with the chatter and arm of an etching device during dry etching of the second mask layer 220 in step S40, and chemical damage may occur to the holes (H) and the core layer 300 due to hydrogen gas generated by reaction of the silicon wafer used as the substrate layer 100 with the potassium hydroxide solution in step S50, resulting in reduced productivity in pellicle manufacturing. Therefore, the present invention provides a method for minimizing physical and chemical damage that occurs during the manufacturing process of an EUV pellicle having a porous structure.

[0007] An object of the present invention is to provide a method for manufacturing an EUV pellicle having a porous structure, and a structure used therefor.

[0008] Another object of the present invention is to provide a method for manufacturing a porous EUV pellicle that minimizes contamination and physical damage caused by a dry etching device, and a structure used therefor.

[0009] Another object of the present invention is to provide a method for manufacturing a porous EUV pellicle that minimizes chemical damage caused by hydrogen gas generated during the etching process of a silicon wafer using potassium hydroxide (KOH), and a structure used therefor.

[0010] Furthermore, another object of the present invention is to provide a method for manufacturing a porous EUV pellicle with improved productivity, and a structure used therefor.

[0011] The object of the present invention is not limited to the above. [Means for solving the problem]

[0012] To achieve the above object, the present invention provides a method for manufacturing a porous EUV pellicle.

[0013] According to one aspect, the method for manufacturing the porous EUV pellicle includes the steps of: preparing a substrate structure having first and second mask layers formed on a first surface and a second surface opposite to the first surface of a substrate layer, respectively; forming a core layer on the first mask layer; forming a plurality of holes through the core layer and the first mask layer so as to expose a region of the first surface of the substrate layer; forming a protection layer to fill the plurality of holes and cover the core layer; etching the second mask layer so as to expose a region of the second surface of the substrate layer; and etching the exposed second surface of the substrate layer with an etching solution to expose the first surface of the substrate layer in which the plurality of holes are formed, toward the second surface.

[0014] The etching solution etches the substrate layer and also removes the protective layer.

[0015] The time required for the protective layer to be completely removed by the etching solution is longer than the time required for the first surface of the substrate layer to be exposed by the etching solution.

[0016] By removing the protective layer, the upper and lower portions of the holes are exposed to the outside.

[0017] The protective layer is formed to cover the inner walls of the holes.

[0018] The core layer with the multiple holes formed therein and the first mask layer are referred to as a pellicle membrane, and the etched second mask layer and the etched substrate layer are referred to as a pellicle frame that supports the pellicle membrane.

[0019] The substrate layer includes a silicon wafer.

[0020] The first and second mask layers include silicon nitride (SiNx).

[0021] The protective layer includes one of an oxide or a nitride.

[0022] The core layer includes any one of silicon (Si), silicon carbide (SiC), silicon oxycarbide (SiCO), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiCON), amorphous carbon (amorphous C), graphene, carbon nanotubes (CNT), molybdenum silicide (Mo silicide), boron carbide (B4C), and zirconium (Zr).

[0023] In another aspect, the method for manufacturing the porous EUV pellicle includes the steps of: preparing a substrate structure having a first mask layer formed on a first surface of the substrate layer and a second mask layer formed on a second surface opposite the first surface; forming a plurality of holes through the first mask layer to expose a region of the first surface of the substrate layer; forming a protective layer to fill the plurality of holes and cover the first mask layer; etching the second mask layer to expose a region of the second surface of the substrate layer; and etching the exposed second surface of the substrate layer with an etching solution to expose the first surface of the substrate layer with the plurality of holes formed therein toward the second surface, wherein the step of etching the exposed second surface of the substrate layer with the etching solution includes immersing the substrate structure in the etching solution so that the first surface of the substrate layer is perpendicular to an upper surface of the etching solution.

[0024] To achieve the above object, the present invention provides a structure for use in fabricating a porous EUV pellicle.

[0025] According to one embodiment, the structure includes a substrate layer having a first surface and a second surface opposite to the first surface, first and second mask layers respectively disposed on the first and second surfaces of the substrate layer, a core layer disposed on the first mask layer, and a protective layer disposed on the core layer, wherein a plurality of holes are formed through the first mask layer and the core layer, and the protective layer is disposed to cover the core layer and fill the plurality of holes.

[0026] The substrate layer and the protective layer are etched by the etching solution and comprise different materials.

[0027] The thickness of the protective layer is greater than the D2 value calculated by the following equation 1.

number

[0028] A method for manufacturing a porous EUV pellicle according to the present invention includes the steps of preparing a substrate structure having first and second mask layers (e.g., silicon nitride) formed on a first surface and a second surface opposite to the first surface of a substrate layer (e.g., a silicon wafer), respectively; forming a core layer on the first mask layer; forming a plurality of holes penetrating the core layer and the first mask layer so as to expose a region of the first surface of the substrate layer; forming a protective layer to fill the plurality of holes and cover the core layer; dry-etching the second mask layer so as to expose a region of the second surface of the substrate layer; and wet-etching the exposed second surface of the substrate layer with a potassium hydroxide solution to expose the first surface of the substrate layer in which the plurality of holes have been formed, in the direction of the second surface.

[0029] Therefore, unlike manufacturing an EUV pellicle having a porous structure using a conventional EUV pellicle manufacturing process, the core layer can be protected from the chuck and arm of equipment used to dry etch the second mask layer, thereby minimizing chemical contamination and physical damage, and the holes and the core layer can be protected from hydrogen gas generated by the reaction of a silicon wafer with a potassium hydroxide solution, thereby minimizing chemical damage, thereby improving productivity in manufacturing porous EUV pellicles. [Brief explanation of the drawings]

[0030] [Figure 1]FIG. 1 is a diagram illustrating step S10 of a method for manufacturing an EUV pellicle having a porous structure by applying a conventional EUV pellicle manufacturing process. [Figure 2] FIG. 2 is a diagram illustrating step S20 of a method for manufacturing an EUV pellicle having a porous structure by applying a conventional EUV pellicle manufacturing process. [Figure 3] FIG. 3 is a diagram illustrating step S30 of a method for manufacturing an EUV pellicle having a porous structure by applying a conventional EUV pellicle manufacturing process. [Figure 4] FIG. 4 is a diagram illustrating step S40 of a method for manufacturing an EUV pellicle having a porous structure by applying a conventional EUV pellicle manufacturing process. [Figure 5] FIG. 5 is a diagram illustrating step S50 of a method for manufacturing an EUV pellicle having a porous structure by applying a conventional EUV pellicle manufacturing process. [Figure 6] FIG. 6 is a sequence diagram for explaining the method for manufacturing a porous EUV pellicle according to the first embodiment of the present invention. [Figure 7] FIG. 7 is a diagram illustrating step S110 in the method for manufacturing a porous EUV pellicle according to the first embodiment of the present invention. [Figure 8] FIG. 8 is a diagram illustrating step S120 in the method for manufacturing a porous EUV pellicle according to the first embodiment of the present invention. [Figure 9] FIG. 9 is a diagram illustrating step S130 in the method for manufacturing a porous EUV pellicle according to the first embodiment of the present invention. [Figure 10] FIG. 10 is a diagram illustrating step S140 in the method for manufacturing a porous EUV pellicle according to the first embodiment of the present invention. [Figure 11] FIG. 11 is a diagram illustrating step S150 in the method for manufacturing a porous EUV pellicle according to the first embodiment of the present invention. [Figure 12]FIG. 12 is a diagram illustrating step S160 in the method for manufacturing a porous EUV pellicle according to the first embodiment of the present invention. [Figure 13] FIG. 13 is a sequence diagram for explaining a method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention. [Figure 14] FIG. 14 is a diagram illustrating step S210 in the method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention. [Figure 15] FIG. 15 is a diagram illustrating step S220 in the method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention. [Figure 16] FIG. 16 is a diagram illustrating step S230 in the method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention. [Figure 17] FIG. 17 is a diagram illustrating step S240 in the method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention. [Figure 18] FIG. 18 is a diagram illustrating step S250 in the method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention. [Figure 19] FIG. 19 is a diagram illustrating step S250 in the method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention. [Figure 20] FIG. 20 is a photograph showing the state in which a hole-patterned thin film is damaged during the wet etching process using potassium hydroxide solution. [Figure 21] FIG. 21 is a photograph of a porous EUV pellicle manufactured by the method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention. [Figure 22] FIG. 22 is a photograph of the physical damage that occurred without the protective layer. [Figure 23] FIG. 23 is a photograph comparing chemical damage with and without a protective layer. [Figure 24]FIG. 24 is a diagram for explaining the relationship between the etching time of the substrate layer and the etching time of the protective layer with a potassium hydroxide solution. [Figure 25] FIG. 25 is a diagram for explaining the state in which the protective layer is removed after wet etching using a potassium hydroxide solution. DETAILED DESCRIPTION OF THE INVENTION

[0031] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical concept of the present invention is not limited to the embodiments described herein and may be embodied in other forms. The embodiments described herein are provided so that the disclosure will be thorough and complete, and so that the concept of the present invention will be fully conveyed to those skilled in the art.

[0032] In this specification, when a component is described as being on another component, it means that it can be directly formed on the other component, or a third component can be sandwiched between them. Also, in the drawings, shapes and sizes are exaggerated for the purpose of effectively explaining the technical content.

[0033] Furthermore, in various embodiments of this specification, terms such as "first," "second," and "third" are used to describe various components, but these components should not be limited by such terms. These terms are used merely to distinguish one component from another. Thus, what is referred to as a "first" component in one embodiment may be referred to as a "second" component in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. Furthermore, in this specification, "and / or" is used to mean that at least one of the components listed before and after it is included.

[0034] In this specification, the singular expression includes the plural expression unless the context clearly dictates otherwise. Furthermore, the terms "comprise" or "have" are intended to specify the presence of a feature, number, step, component, or combination thereof described in the specification, and should not be understood to exclude the presence or possibility of addition of one or more other features, numbers, steps, components, or combinations thereof. Furthermore, in this specification, the term "coupled" is used to mean both indirectly and directly coupling multiple components.

[0035] Furthermore, when describing the present invention, if a detailed description of related publicly known functions or configurations is deemed to unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0036] FIG. 6 is a sequence diagram illustrating a method for manufacturing a porous EUV pellicle according to the first embodiment of the present invention; FIG. 7 is a diagram illustrating step S110 of the method for manufacturing a porous EUV pellicle according to the first embodiment of the present invention; FIG. 8 is a diagram illustrating step S120 of the method for manufacturing a porous EUV pellicle according to the first embodiment of the present invention; FIG. 9 is a diagram illustrating step S130 of the method for manufacturing a porous EUV pellicle according to the first embodiment of the present invention; FIG. 10 is a diagram illustrating step S140 of the method for manufacturing a porous EUV pellicle according to the first embodiment of the present invention; FIG. 11 is a diagram illustrating step S150 of the method for manufacturing a porous EUV pellicle according to the first embodiment of the present invention; and FIG. 12 is a diagram illustrating step S160 of the method for manufacturing a porous EUV pellicle according to the first embodiment of the present invention.

[0037] 6 and 7, a substrate structure (ST) is prepared (S110). The substrate structure (ST) includes a substrate layer 100 having a first surface 100a and a second surface 100b opposite to the first surface 100a, a first mask layer 210 formed on the first surface 100a of the substrate layer 100, and a second mask layer 220 formed on the second surface 100b of the substrate layer 100.

[0038] According to one embodiment, the substrate layer 100 comprises a silicon wafer. The first surface 100a is referred to as the top surface of the substrate layer 100, and the second surface 100b is referred to as the bottom surface of the substrate layer 100.

[0039] The first mask layer 210 and the second mask layer 220 include a material having an etching selectivity with respect to a silicon wafer. Specifically, the first mask layer 210 and the second mask layer 220 include silicon nitride (SiN X According to one embodiment, the first mask layer 210 and the second mask layer 220 are formed by a low pressure chemical vapor deposition method.

[0040] 6 and 8, a core layer 300 is formed on the first mask layer 210 (S120). In one embodiment, the core layer 300 includes any one of silicon (Si), silicon carbide (SiC), silicon oxycarbide (SiCO), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiCON), amorphous carbon (amorphous C), graphene, carbon nanotubes (CNT), molybdenum silicide (Mo silicide), boron carbide (B4C), and zirconium (Zr). In one embodiment, the core layer 300 is formed by a physical vapor deposition method. More specifically, the core layer 300 may be formed by a sputtering method.

[0041] 6 and 9, a plurality of holes (H) are formed through the core layer 300 and the first mask layer 210 to expose a region of the first surface 100a of the substrate layer 100 (S130). According to one embodiment, a photoresist is coated on the core layer 300, and then a photoresist pattern is formed by exposure and development. A selective etching process is performed using the photoresist pattern as an etching mask to form a plurality of holes (H) through the core layer 300 and the first mask layer 210. According to one embodiment, the plurality of holes (H) are formed in various shapes, such as a honeycomb shape, a checkerboard shape, a chessboard shape, a triangular shape, a square shape, or a diamond shape.

[0042] 6 and 10, a protective layer 400 is formed (S140) to fill the holes (H) and cover the core layer 300. More specifically, the protective layer 400 is formed to cover the inner walls of the holes (H).

[0043] According to one embodiment, the protective layer 400 includes a material that can be etched with a potassium hydroxide (KOH) solution. For example, the protective layer 400 includes one of an oxide or a nitride. More specifically, the protective layer 400 includes one of a silicon oxide or a silicon nitride. According to one embodiment, the protective layer 400 can be formed by a plasma enhanced chemical vapor deposition method.

[0044] 6 and 11, the second mask layer 220 is dry-etched (S150) to expose a region of the second surface 100b of the substrate layer 100. More specifically, as shown in FIG. 11, the second mask layer 220 is dry-etched to expose a central portion of the second surface 100b of the substrate layer 100.

[0045] When a conventional EUV pellicle fabrication process is used to fabricate an EUV pellicle having a porous structure, there is a problem that the core layer 300 comes into contact with the chuck and arm of an etching device in step S150, resulting in chemical contamination and physical damage (e.g., scratches). However, in the present invention, by forming the protective layer 400 to cover the core layer 300 in step S140, the core layer 300 is protected from the chuck and arm of equipment used to dry etch the second mask layer 220, thereby minimizing chemical contamination and physical damage.

[0046] 6 and 12, the exposed second surface 100b of the substrate layer 100 is wet-etched with a potassium hydroxide (KOH) solution to expose the first surface 100a of the substrate layer 100, in which the plurality of holes (H) are formed, toward the second surface 100b (S160). In addition, in step S160, the substrate layer 100 is etched with the potassium hydroxide solution, and the protective layer 400 can also be removed. As a result, the upper and lower portions of the plurality of holes (H) are exposed to the outside.

[0047] The core layer 300 in which the holes (H) are formed and the first mask layer 210 are referred to as a pellicle membrane (PM). Separately, the etched second mask layer 220 and the etched substrate layer 100 are referred to as a pellicle frame (PF) that supports the pellicle membrane (PM).

[0048] When a porous EUV pellicle is manufactured using a conventional EUV pellicle manufacturing process, hydrogen gas generated by the reaction of the silicon wafer used as the substrate layer 100 with the potassium hydroxide solution in step S160 can chemically damage the holes (H) and the core layer 300. However, in the present invention, by forming the protective layer 400 to cover the core layer 300 in step S140, the holes (H) and the core layer 300 can be protected from hydrogen gas generated by the reaction of the silicon wafer with the potassium hydroxide solution, thereby minimizing chemical damage.

[0049] According to one embodiment, in step S160, the time it takes for the potassium hydroxide solution to completely remove the protective layer 400 is longer than the time it takes for the potassium hydroxide solution to expose the first surface 100a of the substrate layer 100. On the other hand, if the time it takes for the potassium hydroxide solution to completely remove the protective layer 400 is shorter than the time it takes for the potassium hydroxide solution to expose the first surface 100a of the substrate layer 100, even though the protective layer 400 is completely removed, hydrogen gas continues to be generated by the reaction between the silicon wafer and potassium hydroxide, causing damage to the holes (H) and the core layer 300.

[0050] Furthermore, the thickness of the protective layer 400 is controlled so that the time required for the potassium hydroxide solution to completely remove the protective layer 400 is longer than the time required for the potassium hydroxide solution to expose the first surface 100a of the substrate layer 100. Specifically, the thickness of the protective layer 400 is controlled to be thicker than the value D2 calculated by the following equation 1.

[0051]

number

[0052] The etching rate (E1) of the substrate layer 100 with respect to potassium hydroxide is calculated by the following equation 2, and the etching rate (E2) of the protective layer 400 with respect to potassium hydroxide is calculated by the following equation 3.

[0053]

number

[0054]

number

[0055] Contrary to the above, if the thickness of the protective layer 400 is thinner than the value D2 calculated by Equation 1, even though the protective layer 400 is completely removed, hydrogen gas continues to be generated by the reaction between the silicon wafer and potassium hydroxide, causing damage to the holes (H) and the core layer 300.

[0056] As a result, the method for manufacturing a porous EUV pellicle according to an embodiment of the present invention includes the steps of: preparing a substrate structure (ST) in which first and second mask layers 210, 220 are formed on a first surface 100a of a substrate layer 100 and a second surface 100b opposite to the first surface 100a; forming a core layer 300 on the first mask layer 210; and forming a plurality of holes (H) through the core layer 300 and the first mask layer 210 so that a region of the first surface 100a of the substrate layer 100 is exposed (S110). 30), a step of forming a protective layer 400 to fill the plurality of holes (H) and cover the core layer 300 (S140), a step of dry-etching the second mask layer 220 so as to expose a region of the second surface 100b of the substrate layer 100 (S150), and a step of wet-etching the exposed second surface 100b of the substrate layer 100 with a potassium hydroxide (KOH) solution to expose the first surface 100a of the substrate layer 100 in which the plurality of holes (H) are formed, in the direction of the second surface 100b (S160).

[0057] Therefore, unlike manufacturing an EUV pellicle having a porous structure using a conventional EUV pellicle manufacturing process, the core layer 300 can be protected from the chuck and arm of equipment used to dry etch the second mask layer 220, thereby minimizing chemical contamination and physical damage, and the holes (H) and the core layer 300 can be protected from hydrogen gas generated by the reaction of a silicon wafer with a potassium hydroxide solution, thereby minimizing chemical damage, thereby improving productivity in manufacturing porous EUV pellicles.

[0058] The method for manufacturing a porous EUV pellicle according to the first embodiment of the present invention has been described above. Hereinafter, a method for manufacturing a porous EUV pellicle according to a second embodiment of the present invention will be described.

[0059] FIG. 13 is a sequence diagram illustrating a method for manufacturing a porous EUV pellicle according to a second embodiment of the present invention; FIG. 14 is a diagram illustrating step S210 of the method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention; FIG. 15 is a diagram illustrating step S220 of the method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention; FIG. 16 is a diagram illustrating step S230 of the method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention; FIG. 17 is a diagram illustrating step S240 of the method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention; and FIGS. 18 and 19 are diagrams illustrating step S250 of the method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention.

[0060] 13 and 14, a substrate structure (ST) is prepared (S210). The substrate structure (ST) includes a substrate layer 100 having a first surface 100a and a second surface 100b opposite to the first surface 100a, a first mask layer 210 formed on the first surface 100a of the substrate layer 100, and a second mask layer 220 formed on the second surface 100b of the substrate layer 100.

[0061] According to one embodiment, the substrate layer 100 comprises a silicon wafer. The first surface 100a is referred to as the top surface of the substrate layer 100, and the second surface 100b is referred to as the bottom surface of the substrate layer 100.

[0062] The first mask layer 210 and the second mask layer 220 include a material having an etching selectivity with respect to a silicon wafer. Specifically, the first mask layer 210 and the second mask layer 220 include silicon nitride (SiN X According to one embodiment, the first mask layer 210 and the second mask layer 220 are formed by a low pressure chemical vapor deposition method.

[0063] 13 and 15, a plurality of holes (H) are formed through the first mask layer 210 to expose a region of the first surface 100a of the substrate layer 100 (S220). According to one embodiment, a photoresist is coated on the first mask layer 210, and then a photoresist pattern is formed by exposure and development. A selective etching process is performed using the photoresist pattern as an etching mask, thereby forming a plurality of holes (H) through the first mask layer 210. According to one embodiment, the plurality of holes (H) are formed to form an array of various shapes, such as a honeycomb shape, a checkerboard shape, a chessboard shape, a triangular shape, a square shape, or a diamond shape.

[0064] 13 and 16, a protective layer 300 is formed (S230) to fill the holes (H) and cover the first mask layer 210. More specifically, the protective layer 300 is formed to cover the inner walls of the holes (H).

[0065] According to one embodiment, the protective layer 300 includes a material that can be etched with a potassium hydroxide (KOH) solution. For example, the protective layer 300 includes one of an oxide or a nitride. More specifically, the protective layer 300 may include one of silicon oxide or silicon nitride. According to one embodiment, the protective layer 300 is formed by a plasma enhanced chemical vapor deposition method.

[0066] 13 and 17, the second mask layer 220 is dry-etched (S240) to expose a region of the second surface 100b of the substrate layer 100. More specifically, as shown in FIG. 17, the second mask layer 220 is dry-etched to expose a central portion of the second surface 100b of the substrate layer 100.

[0067] 13, 18, and 19, the exposed second surface 100b of the substrate layer 100 is wet-etched with a potassium hydroxide (KOH) solution to expose the first surface 100a of the substrate layer 100, in which the plurality of holes (H) are formed, toward the second surface 100b (S250). In addition, in step S250, the substrate layer 100 is etched with the potassium hydroxide solution, and the protective layer 300 can also be removed. As a result, the upper and lower portions of the plurality of holes (H) are exposed to the outside.

[0068] The first mask layer 210 having the plurality of holes (H) formed therein is referred to as a pellicle membrane (PM). Separately, the etched second mask layer 220 and the etched substrate layer 100 are referred to as a pellicle frame (PF) that supports the pellicle membrane (PM).

[0069] According to one embodiment, step S250 is performed by immersing the substrate structure (ST) in the potassium hydroxide solution such that the first surface 100a of the substrate layer 100 is perpendicular to the potassium hydroxide solution, as shown in Figure 18. In this case, hydrogen gas generated by the reaction between the silicon wafer and potassium hydroxide is transported toward the first surface 100a of the substrate layer 100, thereby minimizing damage to the holes (H) caused by the hydrogen gas.

[0070] The method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention has been described above. Hereinafter, specific experimental configurations and characteristic evaluation results of the method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention will be described.

[0071] FIG. 20 is a photograph showing the state in which a hole-patterned thin film is damaged during the wet etching process using potassium hydroxide solution.

[0072] As shown in FIG. 20, it can be seen that the hole-patterned thin film was damaged by hydrogen gas generated by the silicon wafer and potassium hydroxide solution during the wet etching process of the silicon wafer.

[0073] FIG. 21 is a photograph of a porous EUV pellicle manufactured by the method for manufacturing a porous EUV pellicle according to the second embodiment of the present invention.

[0074] FIG. 21 shows an image of a porous EUV pellicle fabricated using the porous EUV pellicle fabrication method according to the second embodiment. The total membrane size is 30 mm x 30 mm, of which the hole area is 10 mm x 10 mm. FIG. 21 confirms that the transmittance of the hole-patterned area is improved. If holes with a hole diameter:space ratio of 1 are patterned into a SiNx pellicle membrane with a transmittance of 88%, the expected transmittance is 90.8%. If the hole diameter is increased to pattern holes with a 2:1 ratio, the expected transmittance is 93.2%.

[0075] Figure 22 shows a photograph of the physical damage that occurs when no protective layer is present.

[0076] 22 shows a photograph of the state of the first mask layer when a porous EUV pellicle is manufactured using the porous EUV pellicle manufacturing method according to the second embodiment and the second mask layer is dry-etched without a protective layer. From FIG. 22, it can be seen that without the protective layer, the first mask layer comes into contact with the chuck and arm of the etching equipment during the dry-etching of the second mask layer, resulting in contamination and damage such as scratches.

[0077] FIG. 23 is a photograph comparing chemical damage with and without a protective layer.

[0078] As shown in Figures 23(a) to 23(c), a porous EUV pellicle was manufactured using the porous EUV pellicle manufacturing method according to the second embodiment, and the presence or absence of a protective layer shows chemical damage to the first mask layer caused by the reaction between the potassium hydroxide solution and the silicon wafer.

[0079] Specifically, as shown in Figure 23(a), photographs are taken of the state of the first mask layer (top) and the substrate layer (bottom) before wet etching using a potassium hydroxide solution. As shown in Figure 23(b), photographs are taken of the state of the first mask layer after wet etching using a potassium hydroxide solution when there is no protective layer. As shown in Figure 23(c), photographs are taken of the state of the first mask layer after wet etching using a potassium hydroxide solution when there is a protective layer.

[0080] From (a) to (c) of FIG. 23, it can be seen that when there is no protective layer, chemical damage by potassium hydroxide solution occurs, whereas when there is a protective layer, chemical damage by potassium hydroxide solution does not occur.

[0081] FIG. 24 is a diagram for explaining the relationship between the etching time of the substrate layer and the etching time of the protective layer with a potassium hydroxide solution.

[0082] 24(a) shows a photograph of the state of the first mask layer when a porous EUV pellicle is manufactured using the method for manufacturing a porous EUV pellicle according to the second embodiment and the time required for the protective layer to be completely removed by the potassium hydroxide solution is shorter than the time required for the first surface of the substrate layer to be exposed by the potassium hydroxide solution. FIG. 24(b) shows a photograph of the state of the first mask layer when a porous EUV pellicle is manufactured using the method for manufacturing a porous EUV pellicle according to the second embodiment and the time required for the protective layer to be completely removed by the potassium hydroxide solution is longer than the time required for the first surface of the substrate layer to be exposed by the potassium hydroxide solution.

[0083] From (a) of Figure 24, it can be seen that if the time it takes for the potassium hydroxide solution to completely remove the protective layer is shorter than the time it takes for the potassium hydroxide solution to expose the first surface of the substrate layer, damage occurs to the hole and the first mask layer, whereas from (b) of Figure 24, it can be seen that if the time it takes for the potassium hydroxide solution to completely remove the protective layer is longer than the time it takes for the potassium hydroxide solution to expose the first surface of the substrate layer, no damage occurs to the hole and the first mask layer.

[0084] FIG. 25 is a diagram for explaining the state in which the protective layer is removed after wet etching using a potassium hydroxide solution.

[0085] Figure 25(a) shows the results of spectroscopic ellipsometry (non-destructive method) analysis to determine whether the protective layer was removed after wet etching using a potassium hydroxide solution in the process of manufacturing a porous EUV pellicle according to the second embodiment, and Figure 25(b) shows a TEM (Transmission Electron Microscopy, destructive method) image to determine whether the protective layer was removed after wet etching using a potassium hydroxide solution in the process of manufacturing a porous EUV pellicle according to the second embodiment. Figures 25(a) and (b) show that not only the substrate layer (silicon wafer) but also the protective layer was removed by the potassium hydroxide solution.

[0086] Although the present invention has been described in detail using the preferred embodiment, the scope of the present invention is not limited to the specific embodiment, but should be interpreted by the appended claims. Furthermore, those skilled in the art will understand that many modifications and variations are possible without departing from the scope of the present invention. [Industrial Applicability]

[0087] The method for manufacturing an EUV pellicle according to the present invention can be used in the semiconductor industry.

Claims

1. providing a substrate structure having first and second mask layers formed on a first surface and a second surface opposite to the first surface of a substrate layer, respectively; forming a core layer on the first mask layer; forming a plurality of holes through the core layer and the first mask layer so that an area of ​​the first surface of the substrate layer is exposed; forming a protective layer to fill the holes and cover the core layer; etching the second mask layer to expose an area of ​​the second surface of the substrate layer; and etching the exposed second surface of the substrate layer with an etching solution to expose the first surface of the substrate layer in which the plurality of holes are formed toward the second surface.

2. The method for manufacturing a porous EUV pellicle according to claim 1 , wherein the substrate layer is etched by the etching solution and the protective layer is also removed.

3. The method for manufacturing a porous EUV pellicle according to claim 2, characterized in that the time required for the protective layer to be completely removed by the etching solution is longer than the time required for the first surface of the substrate layer to be exposed by the etching solution.

4. 3. The method of claim 2, wherein the protective layer is removed, so that upper and lower portions of the holes are exposed to the outside.

5. The method of claim 1 , wherein the protective layer is formed to cover the inner walls of the plurality of holes.

6. the core layer in which the plurality of holes are formed and the first mask layer are referred to as a pellicle membrane; 2. The method of claim 1, wherein the etched second mask layer and the etched substrate layer are referred to as a pellicle frame that supports the pellicle membrane.

7. The method of claim 1 , wherein the substrate layer comprises a silicon wafer.

8. 2. The method of claim 1, wherein the first and second mask layers comprise silicon nitride (SiNx).

9. 2. The method of claim 1, wherein the protective layer includes one of an oxide and a nitride.

10. The core layer may be made of silicon (Si), silicon carbide (SiC), silicon oxycarbide (SiCO), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiCON), amorphous carbon (amorphous C), graphene, carbon nanotubes (CNT), molybdenum silicide (Mo silicide), boron carbide (B 4 2. The method for manufacturing a porous EUV pellicle according to claim 1, wherein the porous EUV pellicle contains any one of titanium dioxide (TiO 3 ) and zirconium (Zr).

11. providing a substrate structure having first and second mask layers formed on a first surface and a second surface opposite to the first surface of a substrate layer, respectively; forming a plurality of holes through the first mask layer to expose an area of ​​the first surface of the substrate layer; forming a protective layer to fill the holes and cover the first mask layer; etching the second mask layer to expose an area of ​​the second surface of the substrate layer; etching the exposed second surface of the substrate layer with an etching solution to expose the first surface of the substrate layer in which the plurality of holes are formed toward the second surface; A method for manufacturing a porous EUV pellicle, characterized in that the step of etching the exposed second surface of the substrate layer with an etching solution includes immersing the substrate structure in the etching solution so that the first surface of the substrate layer is perpendicular to an upper surface of the etching solution.

12. 1. A structure for use in the manufacture of a porous EUV pellicle, comprising: a substrate layer having a first surface and a second surface opposite the first surface; first and second mask layers disposed on the first and second surfaces of the substrate layer, respectively; a core layer disposed on the first mask layer; a protective layer disposed on the core layer, a plurality of holes are formed through the first mask layer and the core layer; The protective layer is disposed so as to cover the core layer and fill the holes.

13. 13. The structure of claim 12, wherein the substrate layer and the protective layer are etched by the etching solution and comprise different materials.

14. The thickness of the protective layer is calculated by the following equation: ２ 14. The structure of claim 13, wherein the thickness is greater than the value. [Equation 1] Here, E １ : Etching rate of the substrate layer with respect to the etching solution, E ２ : the etching rate of the protective layer with respect to the etching solution, D １ : the thickness of the substrate layer etched by the etching solution for a first time, D ２ : the thickness of the protective layer that is etched by the etching solution during the first time period.

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