Memory cell protection layer in a three-dimensional memory array

Abstract

Methods, systems, and devices for memory cell protection layers in a three-dimensional memory array are described. The memory device may support access to memory cells of the memory array arranged in a three-dimensional architecture. The three-dimensional architecture may include levels of memory cells separated by levels of dielectric material such that the memory cells are formed between the dielectric material. To prevent or reduce diffusion between a given memory cell and the dielectric material, a barrier material may be formed on the dielectric material before forming the memory cell. The barrier material may be located between the memory cell and the dielectric material, which may reduce or prevent diffusion of the material.

Description

[Technical Field]

[0001] cross reference This patent application claims priority to U.S. Patent Application No. 18 / 520,377 by Good, entitled "MEMORY CELL PROTECTIVE LAYERS IN A THREE-DIMENSIONAL MEMORY ARRAY," filed November 27, 2023, which claims the benefit of U.S. Provisional Patent Application No. 63 / 430,272 by Good, entitled "MEMORY CELL PROTECTIVE LAYERS IN A THREE-DIMENSIONAL MEMORY ARRAY," filed December 5, 2022, each of which is assigned to the assignee herein and each of which is expressly incorporated by reference herein.

[0002] The following relates to one or more systems for memory that include a memory cell protection layer in a three-dimensional memory array. [Background technology]

[0003] Memory devices are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, often represented by a logic 1 or a logic 0. In some examples, a single memory cell can support more than two states and store any one of them. To access the stored information, a component can read (e.g., sense, detect, acquire, identify, determine, evaluate) the states stored in the memory device. To store information, a component can write (e.g., program, set, or assign) states to the memory device.

[0004] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, etc. Memory cells can be described in terms of volatile or non-volatile configurations. Memory cells can maintain a stored logic state for extended periods of time, even in the absence of an external power source. Memory cells configured in a volatile configuration may lose their stored state when disconnected from an external power source. [Brief explanation of the drawings]

[0005] [Figure 1] 1 illustrates an example memory device that supports a memory cell protection layer in a three-dimensional memory array, according to examples disclosed herein. [Figure 2] 1 illustrates a top view of an example memory array supporting a memory cell protection layer in a three-dimensional memory array according to examples disclosed herein. [Figure 3A] 1 illustrates a side view of an example memory array supporting a memory cell protection layer in a three-dimensional memory array according to examples disclosed herein. [Figure 3B] 1 illustrates a side view of an example memory array supporting a memory cell protection layer in a three-dimensional memory array according to examples disclosed herein. [Figure 4A] 1 illustrates example operations of a manufacturing process to support a memory cell protection layer in a three-dimensional memory array, according to examples disclosed herein. [Figure 4B] 1 illustrates example operations of a manufacturing process to support a memory cell protection layer in a three-dimensional memory array, according to examples disclosed herein. [Figure 4C] 1 illustrates example operations of a manufacturing process to support a memory cell protection layer in a three-dimensional memory array, according to examples disclosed herein. [Figure 5]1 illustrates example operations of a manufacturing process to support a memory cell protection layer in a three-dimensional memory array, according to examples disclosed herein. [Figure 6] 1 illustrates a flowchart illustrating one or more methods for supporting a memory cell protection layer in a three-dimensional memory array, according to examples disclosed herein. [Figure 7] 1 illustrates a flowchart illustrating one or more methods for supporting a memory cell protection layer in a three-dimensional memory array, according to examples disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0006] In some memory architectures, a memory device may include a memory array arranged in a three-dimensional architecture with memory cells arranged according to different levels (e.g., layers, decks, planes, tiers). In some such architectures, levels of memory cells may be separated by layers of dielectric material, and memory cells may be formed in contact with respective layers of dielectric material (e.g., layers of dielectric material above and below the memory cell). However, in some cases, when a given memory cell is accessed, the memory cell may experience an increase in temperature, which may contribute to material diffusion between the respective memory cell and the dielectric material (e.g., diffusion of selenium from the memory cell, diffusion of oxygen into the memory cell, etc.). Additionally or alternatively, memory cells may experience an increase in temperature as a result of thermal processing, material processing, assembly processes, test operations, and / or electrical heating during cell operation, each of which may cause material diffusion. Material diffusion may change the material properties of the memory cell and adversely affect overall performance. For example, changes in the material properties of a memory cell may affect how the memory cell responds to various voltage biases applied across the memory cell, which may result in less reliable access to the memory cell, among other issues.

[0007] According to examples described herein, barrier materials can be used to reduce or eliminate diffusion between memory cells and dielectric materials. For example, before forming memory cells, a manufacturing process can include forming a boron-containing barrier material (e.g., boron nitride, silicon boron nitride, among other boron-containing materials) on portions of each dielectric material layer in which memory cells are to be formed. The memory cells can be formed between the barrier materials on each dielectric material layer. That is, the barrier material can be located between the memory cells and the dielectric material to prevent or reduce diffusion between the memory cells and the dielectric material while supporting access operations of the memory cells.

[0008] Features of the present disclosure are first described in terms of memory devices and arrays with reference to Figures 1, 2, 3A, and 3B. Features of the present disclosure are described in terms of manufacturing operations with reference to Figures 4A, 4B, 4C, and 5. These and other features of the present disclosure are further illustrated by and described with reference to apparatus diagrams and flow charts for memory cell protection layers in three-dimensional memory arrays as described with reference to Figures 6 and 7.

[0009] 1 shows an example of a memory device 100 supporting a memory cell protection layer in a three-dimensional memory array according to examples disclosed herein. In some examples, memory device 100 may be referred to as or include a memory die, a memory chip, or an electronic memory device. Memory device 100 may be operable to provide locations for storing information (e.g., physical memory addresses) that can be used by a system (e.g., a host device coupled with memory device 100 to write information to and read information from).

[0010] Memory device 100 may include one or more memory cells 105, each of which may be programmable to store different logic states (e.g., a programmed one of a set of more than two possible states). For example, memory cells 105 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some examples, memory cells 105 (e.g., multi-level memory cells 105) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some examples, memory cells 105 may be arranged in an array.

[0011] Memory cell 105 may store logical states using a configurable material, which may be referred to as, among other things, a memory element, a storage element, a memory storage element, a material element, a material memory element, a material portion, or a polarizable write material portion. The configurable material of memory cell 105 may refer to a chalcogenide-based storage component. For example, a chalcogenide storage element may be used in a phase-change memory cell, a threshold memory cell, or a self-selection memory cell, among other architectures.

[0012] In some examples, the material of memory cell 105 may include chalcogenide materials or other alloys containing selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some examples, chalcogenide materials containing primarily selenium (Se), arsenic (As), and germanium (Ge) may be referred to as SAG alloys. In some examples, SAG alloys may also include silicon (Si), and such chalcogenide materials may be referred to as SiSAG alloys. In some examples, SAG alloys may include silicon (Si) or indium (In), or combinations thereof, and such chalcogenide materials may be referred to as SiSAG alloys or InSAG alloys, respectively, or combinations thereof. In some examples, chalcogenide materials may include additional elements such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form.

[0013] In some examples, memory cell 105 may be an example of a phase-change memory cell. In these examples, the material used in memory cell 105 may be based on an alloy (such as the alloys listed above) and may operate to change to different physical states (e.g., undergo a phase change) during normal operation of memory cell 105. For example, phase-change memory cell 105 may be associated with a relatively disordered atomic configuration (e.g., a relatively amorphous state) and a relatively ordered atomic configuration (e.g., a relatively crystalline state). The relatively disordered atomic configuration may correspond to a first logic state (e.g., a RESET state, logic 0), and the relatively ordered atomic configuration may correspond to a second logic state (e.g., a logic state different from the first logic state, a SET state, logic 1). In some examples, memory cell 105 may operate to change logic states without a physical phase change. For example, memory cell 105 may implement a threshold switching mechanism in which logic states may be changed via positive and negative programming signals.

[0014] In some examples (e.g., in the case of threshold memory cells 105, in the case of self-selecting memory cells 105), some or all of the set of logical states supported by memory cell 105 may be associated with morphological changes (e.g., structural changes in bonding configurations) induced through operation of the memory cell. For example, some or all of the set of logical states may be associated with the relatively disordered atomic configuration of a chalcogenide material (e.g., a material in an amorphous state may be operable to store different logical states). In some examples, the storage element of memory cell 105 may be an example of a self-selecting storage element. In these examples, the material used in memory cell 105 may be based on an alloy (e.g., such as the alloys listed above) and may be operable to undergo changes to different physical states during normal operation of memory cell 105. For example, a self-selecting or threshold memory cell 105 may have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state may correspond to a first logic state (e.g., a RESET state, logic 0), and the low threshold voltage state may correspond to a second logic state (e.g., a logic state different from the first logic state, a SET state, logic 1).

[0015] During a write operation (e.g., a programming operation) of a self-selected or threshold memory cell 105, the polarity used in the write operation may affect (e.g., determine, set, or program) the behavior or characteristics of the material of the memory cell 105, such as the threshold characteristic (e.g., threshold voltage) of the material. The difference between the threshold characteristics of the material of the memory cell 105 for different logic states stored by the material of the memory cell 105 (e.g., the difference between the threshold voltage when the material is storing a logic state "0" versus a logic state "1") may correspond to the read window of the memory cell 105.

[0016] The memory device 100 may include access lines arranged in a pattern, such as a grid pattern (e.g., row lines 115 each extending along an exemplary x-direction and column lines 125 each extending along an exemplary y-direction). The access lines may be formed of one or more conductive materials. In some examples, the row lines 115, or portions thereof, may be referred to as word lines. In some examples, the column lines 125, or portions thereof, may be referred to as digit lines or bit lines. References to access lines, or the like, may be interchangeable without loss of understanding. Memory cells 105 may be positioned at intersections of access lines, such as row lines 115 and column lines 125. In some examples, the memory cells 105 may also be arranged (e.g., addressed) along the exemplary z-direction, such as in an implementation of a set of memory cells 105 located at different levels (e.g., layers, decks, planes, tiers) along the exemplary z-direction. In some examples, a memory device 100 including memory cells 105 at different levels may be supported by access lines, decoders, and other support circuitry in configurations different from those shown.

[0017] Operations, such as read operations and write operations, may be performed on memory cells 105 by activating access lines, such as one or more of row lines 115 or column lines 125, among other access lines associated with alternative configurations. For example, by activating row lines 115 and column lines 125 (e.g., by applying a voltage to row line 115 or column line 125), memory cells 105 may be accessed according to their intersections. In various two-dimensional or three-dimensional configurations, the intersections of row lines 115 and column lines 125, among other access lines, may be referred to as the addresses of memory cells 105. In some examples, access lines may be conductive lines coupled to memory cells 105 and may be used to perform access operations on memory cells 105. In some examples, memory device 100 may perform operations in response to commands that may be issued by a host device coupled to memory device 100 or generated by memory device 100 (e.g., by local memory controller 150).

[0018] Access to memory cells 105 may be controlled via one or more decoders, such as row decoder 110 and column decoder 120, among other examples. For example, row decoder 110 may receive a row address from local memory controller 150 and may activate row lines 115 based on the received row address. Column decoder 120 may receive a column address from local memory controller 150 and may activate column lines 125 based on the received column address.

[0019] The sense component 130 may be operable to detect a state (e.g., a material state, a resistance state, a threshold state) of the memory cell 105 and determine a logic state of the memory cell 105 based on the detected state. The sense component 130 may include one or more sense amplifiers to convert (e.g., amplify) signals resulting from accessing the memory cell 105 (e.g., signals on column lines 125 or other access lines). The sense component 130 may compare the detected signal from the memory cell 105 to a reference 135 (e.g., a reference voltage, a reference charge, a reference current). The detected logic state of the memory cell 105 may be provided as an output of the sense component 130 (e.g., to the input / output component 140), which may indicate the detected logic state to another component of the memory device 100 or to a host device coupled to the memory device 100.

[0020] The local memory controller 150 may control access of the memory cells 105 via various components (e.g., row decoder 110, column decoder 120, sense component 130, among other components). In some examples, one or more of the row decoder 110, column decoder 120, and sense component 130 may be co-located with the local memory controller 150. The local memory controller 150 may be operable to receive information (e.g., commands, data) from one or more different controllers (e.g., an external memory controller associated with a host device, another controller associated with the memory device 100), convert the information into signaling usable by the memory device 100, perform one or more operations on the memory cells 105, and communicate data from the memory device 100 to the host device based on performing the one or more operations. The local memory controller 150 may generate row address signals and column address signals to activate access lines such as the target row line 115 and the target column line 125. Local memory controller 150 may also generate and control various signals (e.g., voltages, currents) used during operation of memory device 100. In general, the amplitude, shape, or duration of the applied signals discussed herein may vary and may differ for the various operations discussed in the operation of memory device 100.

[0021] The local memory controller 150 may be operable to perform one or more access operations on one or more memory cells 105 of the memory device 100. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, the access operation may be performed or otherwise coordinated by the local memory controller 150 in response to an access command (e.g., from a host device). The local memory controller 150 may be operable to perform other access operations not enumerated herein or other operations related to the operation of the memory device 100 that are not directly related to accessing the memory cells 105.

[0022] In some examples, the memory device 100 may include an array of memory cells 105 arranged in a three-dimensional architecture, including the memory cells 105 arranged according to different levels (e.g., layers, decks, tiers). For example, the levels of memory cells 105 may be separated by levels of dielectric material, such that the memory cells 105 are formed in contact with the dielectric material. However, in some cases, when a given memory cell 105 is accessed, the memory cell 105 may experience an increase in temperature, and diffusion of material between the respective memory cell 105 and the dielectric material may occur as a result of the increase in temperature (e.g., direct contact between the memory cell 105 and the dielectric material). Additionally or alternatively, the memory cells 105 may experience an increase in temperature as a result of thermal processing, material processing, assembly processes, test operations, and / or electrical heating during cell operation, each of which may cause material diffusion. In some cases, material diffusion may change the material properties of the memory cells 105, adversely affecting overall performance.

[0023] To prevent or reduce diffusion between the memory cell 105 and the dielectric material while supporting access operations of the memory cell 105, a barrier material can be used to insulate the memory cell 105 from the dielectric material. For example, before forming the memory cell 105, the fabrication process can include forming a boron-containing barrier material (e.g., boron nitride, silicon boron nitride, among other boron-containing materials) on the dielectric material. The memory cell 105 can be formed such that the barrier material is located between the memory cell 105 and the dielectric material, thereby reducing or eliminating contact between the memory cell 105 and the dielectric material. The barrier material can be a material that prevents diffusion of materials between the memory cell 105 and the barrier material. The barrier material can also be a material that reduces or prevents diffusion of oxygen into the memory cell (e.g., due to attraction between the boron material and the oxygen material). Thus, the barrier material can help reduce or eliminate diffusion between the memory cell 105 and the dielectric material.

[0024] Memory device 100 may include any quantity of non-transitory computer-readable media that support memory cell protection layers in a three-dimensional memory array. For example, local memory controller 150, row decoder 110, column decoder 120, sense component 130, or input / output component 140, or any combination thereof, may include or have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing functions attributed to memory device 100 herein. For example, such instructions, when executed by memory device 100, may cause memory device 100 to perform one or more associated functions described herein.

[0025] 2, 3A, and 3B illustrate an example memory array 200 supporting a memory cell protection layer in a three-dimensional memory array according to examples disclosed herein. The memory array 200 illustrates an example three-dimensional arrangement of memory cells 105 that may be included in a memory device 100 and that may be accessed by various conductive structures (e.g., access lines). FIG. 2 illustrates a top cross-sectional view (e.g., cross-section AA) of the memory array 200 taken along cross-section AA shown in FIGS. 3A and 3B. FIG. 3A illustrates a side cross-sectional view (e.g., cross-section BB) of the memory array 200 taken along cross-section BB as shown in FIG. 2. FIG. 3B illustrates a side cross-sectional view (e.g., cross-section CC) of the memory array 200 taken along cross-section CC as shown in FIG. 2. These cross-sectional views may be examples of cross-sectional views of the memory array 200, with some aspects (e.g., dielectric structures) removed for clarity. Elements of the memory array 200 may be described with respect to the x-direction, y-direction, and z-direction as shown in FIGS. 2, 3A, and 3B, respectively. 2, 3A, and 3B are labeled with numerical indicators while other corresponding elements are not labeled, but will be understood to be identical or similar to enhance visibility and clarity of the depicted features. Additionally, while the illustrative example of memory array 200 shows a certain number of repeated elements, the example techniques described herein may be applicable to any quantity of such elements or ratio of quantity between one repeated element and another.

[0026] In the example memory array 200, the memory cells 105 and word lines 205 may be wired along the z-direction according to levels 230 (e.g., decks, layers, planes, tiers as shown in FIGS. 3A and 3B ). In some examples, the z-direction may be perpendicular to a substrate (not shown) of the memory array 200, which may be below the structures shown along the z-direction. While the illustrative example of the memory array 200 includes four levels 230, the memory array 200 according to examples disclosed herein may include any number of one or more levels 230 along the z-direction (e.g., 64 levels, 128 levels).

[0027] Each word line 205 may be an example of a portion of an access line formed by one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As shown, the word lines 205 may be formed in a comb-tooth structure including portions (e.g., protrusions, teeth) that extend along the y-direction through gaps (e.g., alternating gaps) between the pillars 220. For example, as shown, the memory array 200 may include two word lines 205 per level 230 (e.g., with odd word lines 205-a-n1 and even word lines 205-a-n2 for a given level, n), and such word lines 205 on the same level 230 may be described as interleaved (e.g., portions of the odd word lines 205-a-n1 protrude along the y-direction between portions of the even word lines 205-a-n2, and vice versa). In some examples, an odd word line 205 (e.g., of a level 230) may be associated with a first memory cell 105 on a first side (e.g., along the x-direction) of a given pillar 220, and an even word line (e.g., of the same level 230) may be associated with a second memory cell 105 on a second side (e.g., opposite the first memory cell 105 along the x-direction) of the given pillar 220. Thus, in some examples, a memory cell 105 of a given level 230 may be addressed (e.g., selected and activated) according to an even word line 205 or an odd word line 205.

[0028] Each pillar 220 may be an example of a portion (e.g., a conductive pillar portion) of an access line formed by one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As shown, the pillars 220 may be arranged in a two-dimensional array (e.g., in the x-y plane), which may have a first quantity of pillars 220 along a first direction (e.g., eight pillars along the x-direction, eight rows of pillars) and a second quantity of pillars 220 along a second direction (e.g., five pillars along the y-direction, five columns of pillars). While the illustrative example of memory array 200 includes a two-dimensional array of eight pillars 220 along the x-direction and five pillars 220 along the y-direction, memory array 200 according to examples disclosed herein may include any quantity of pillars 220 along the x-direction and any quantity of pillars 220 along the y-direction. Further, as shown, each pillar 220 may be coupled to a respective set of memory cells 105 (e.g., one or more memory cells 105 per level 230 along the z direction). The pillars 220 may have a cross-sectional area in the xy plane that extends along the z direction. Although shown with a circular cross-sectional area in the xy plane, the pillars 220 may be formed with different shapes, such as having an oval, square, rectangular, polygonal, or other cross-sectional area in the xy plane.

[0029] Each memory cell 105 may include a chalcogenide material. In some examples, the memory cells 105 may be examples of threshold memory cells. Each memory cell 105 may be accessed (e.g., addressed, selected) according to an intersection between a word line 205 (e.g., a level selection, which may include an even or odd selection within level 230) and a pillar 220. For example, as shown, a selected memory cell 105-a in level 230-a-3 may be accessed according to an intersection between pillar 220-a-43 and word line 205-a-32.

[0030] The memory cell 105 is configured to apply an access bias (e.g., an access voltage, V access) to the selected word line 205. In some examples, the access bias is a first voltage (e.g., V access / 2), which may also have the opposite sign to the first voltage, access The word line bias may be applied by biasing the selected pillar 220 with a voltage (e.g., a first voltage) of 0 V. For the selected memory cell 105-a, a corresponding access bias (e.g., a first voltage) may be applied to word line 205-a-32, and other unselected word lines 205 may be grounded (e.g., biased to 0 V). In some examples, the word line bias may be provided by a word line driver (not shown) coupled to one or more of the word lines 205.

[0031] The pillars 220 may be configured to be selectively coupled to the sense lines 215 (e.g., digit lines, column lines, access lines extending along the y-direction) via respective transistors 225 coupled (e.g., physically, electrically) between the pillars 220 and the sense lines 215 to apply a corresponding access bias (e.g., second voltage) to the pillars 220. In some examples, the transistors 225 may be vertical transistors (e.g., transistors having channels along the z-direction, transistors having semiconductor junctions along the z-direction) that may be formed above a substrate of the memory array 200 using various technologies (e.g., thin-film technologies). In some examples, the selected pillars 220, the selected sense lines 215, or a combination thereof may be examples of the selected column lines 125 (e.g., bit lines) described with reference to FIG. 1.

[0032] The transistors 225 (e.g., channel portions of the transistors 225) may be activated by gate lines 210 (e.g., activation lines, select lines, row lines, access lines extending along the x-direction) coupled to respective gates of a set (e.g., a set along the x-direction) of transistors 225. In other words, each pillar 220 may have a first end (e.g., a bottom end toward the negative z-direction) configured to couple with an access line (e.g., a sense line 215). In some examples, the gate lines 210, the transistors 225, or both may be considered components of the row decoder 110 (e.g., pillar decoder components). In some examples, selection of (e.g., biasing of) the pillars 220, or the sense lines 215, or various combinations thereof may be supported by the column decoder 120, or the sense components 130, or both.

[0033] The corresponding access bias (e.g., -V access To apply a voltage (V / 2) to pillar 220-a-43, sense line 215-a-4 may be biased by an access bias, and gate line 210-a-3 may be grounded (e.g., biased to 0 V) ​​or otherwise biased by an activation voltage. In an example where transistor 225 is an n-type transistor, gate line 210-a-3 biased by a relatively higher voltage than sense line 215-a-4 may activate transistor 225-a (e.g., cause transistor 225-a to operate in a conductive state), thereby coupling pillar 220-a-43 to sense line 215-a-4 and biasing pillar 220-a-43 with the associated access bias. However, transistor 225 may include different channel types or operate according to different bias schemes to support various access operations.

[0034] In some examples, unselected pillars 220 of the memory array 200 may be electrically floating or coupled to another voltage source (e.g., via a high-resistance path, via a leakage path, or to ground) to avoid voltage drift of the pillars 220 when transistor 225-a is activated. For example, a ground voltage, when applied to gate line 210-a-3, cannot activate other transistors coupled to gate line 210-a-3 because the ground voltage of gate line 210-a-3 cannot be greater than the voltage of other sense lines 215 (e.g., which may be biased by a ground voltage or may be floating). Furthermore, other unselected gate lines 210, including gate line 210-a-5 shown in FIG. 3A , may be biased with an access bias (e.g., −V access 2. / 2, or some other negative bias or bias relatively close to the access bias voltage), transistor 225-b coupled to gate line 210-a-5 may be deactivated (e.g., may operate in a non-conductive state), thereby isolating the voltage on sense line 215-a-4 from pillar 220-a-45, among other pillars 220.

[0035] During a write operation, the memory cell 105 is configured to apply a write bias (e.g., V access =V writeA write bias may be written by applying a write bias (which may be a positive or negative voltage) to the material of memory cell 105. In some examples, the polarity of the write bias may affect (e.g., determine, set, or program) the behavior or characteristics of the material of memory cell 105, such as the threshold voltage of the material. For example, applying a write bias with a first polarity may set a first threshold voltage in the material of memory cell 105, which may be associated with storing a logic 0. Further, applying a write bias with a second polarity (e.g., opposite the first polarity) may set a second threshold voltage in the material of memory cell 105, which may be associated with storing a logic 1. The difference between the threshold voltages of the material of memory cell 105 for different logic states stored by the material of memory cell 105 (e.g., the difference between the threshold voltages when the material is storing a logic state "0" versus a logic state "1") may correspond to a read window of memory cell 105.

[0036] During a read operation, the memory cell 105 is configured to apply a read bias (e.g., V access =V read , which may be a positive or negative voltage). In some examples, the logic state of the memory cell 105 may be evaluated based on whether the memory cell 105 thresholds in the presence of an applied read bias. For example, with such a read bias, the memory cell 105 may threshold (e.g., allow current flow, such as allowing current flow above a threshold current) when storing a first logic state (e.g., logic 0) and may not threshold (e.g., not allow current flow, such as allowing current flow below a threshold current) when storing a second logic state (e.g., logic 1).

[0037] In some examples, levels 230 of memory cells 105 may be separated by levels of dielectric material such that the memory cells 105 are formed in contact with the dielectric material. However, in some cases, when a given memory cell 105 is accessed, the memory cell 105 may experience an increase in temperature, and diffusion of material between the respective memory cell 105 and the dielectric material may result. In some cases, the diffusion of material may change the material properties of the memory cells 105, adversely affecting overall performance.

[0038] To prevent or reduce diffusion between the memory cell 105 and the dielectric material while supporting access operations of the memory cell 105, a barrier material may be used to insulate the memory cell 105 from the dielectric material. For example, before forming the memory cell 105, the fabrication process may include forming a barrier material including boron on the dielectric material. The memory cell 105 may then be formed such that the barrier material may be located between the memory cell 105 and the dielectric material, thereby preventing or reducing diffusion between the memory cell 105 and the dielectric material.

[0039] 4-5 illustrate example operations for supporting a memory cell protection layer in a three-dimensional memory array, according to examples disclosed herein. For example, FIGS. 4A, 4B, and 4C may illustrate an example of a sequence of operations for fabricating an embodiment of layout 400, which may be a portion of a memory device (e.g., a portion of memory device 100, a portion of memory array 200, a portion of a memory die, layout 400), and similarly, FIG. 5 may illustrate an example of a sequence of operations for fabricating an embodiment of layout 500, which may be a portion of a memory device. Each view of the diagrams may be described with reference to x-, y-, and z-directions, which may correspond to the respective directions described with reference to memory array 200, as illustrated. Some of the provided figures include cross-sectional views illustrating example cross-sections of layouts 400 and 500, respectively. 4A, 4B, 4C, and 5, view "section AA" may be associated with a cross section in the xz plane (e.g., according to cutting plane AA) through a portion of layout 400, and view "section BB" may be associated with a cross section in the yz plane (e.g., according to cutting plane BB) through a portion of layout 400. Although layouts 400 and 500 show examples of particular relative dimensions and quantities of various features, aspects of layouts 400 and 500 may be implemented with other relative dimensions or quantities of such features according to examples disclosed herein.

[0040] 4-5 may be performed by a manufacturing system, such as a semiconductor manufacturing system configured to perform additive operations such as depositing, doping, or bonding; removal operations such as etching, trenching, planarizing, or polishing; and support operations such as masking, patterning, photolithography, or alignment, among other operations supporting the described techniques. In some examples, the operations performed by such a manufacturing system may be supported by a process controller or components thereof, as described herein.

[0041] FIG. 4A illustrates a portion 400-a of a layout 400 after a first set of one or more fabrication operations that support a memory cell protection layer in a three-dimensional memory array, according to examples disclosed herein.

[0042] The first set of fabrication operations may include forming (e.g., depositing) a layer stack on a substrate 401. The substrate 401 may be a semiconductor wafer or other substrate on which the layer stack is deposited. The layer stack may include alternating layers of a first material and a dielectric material 435 (e.g., by material-alternating deposition operations). In some examples, the first material may be a dielectric material such as a nitride (e.g., silicon nitride or another tier nitride), and the layer of the first material may be a sacrificial layer. That is, the first material may then be removed (e.g., undercut or etched) and replaced with one or more other materials that form aspects of the memory device. The dielectric material 435 may include a dielectric material such as an oxide (e.g., silicon dioxide or another tier oxide) and may provide electrical isolation between the levels 230. While the layer stack is shown using two layers of the dielectric material 435, a layer stack according to examples disclosed herein may include any number (e.g., tens, hundreds, etc.) of alternating layers of the first material and the dielectric material 435.

[0043] In some cases, the stack of layers may be deposited in direct contact with the substrate 401, while in some other examples, the layout 400 may include other materials or components between the stack of layers and the substrate 401, such as interconnect or routing circuitry (e.g., access lines, sense lines 215, gate lines 210), control circuitry (e.g., transistors 225, aspects of the local memory controller 150, decoders, multiplexers, etc.), or another stack of layers (e.g., another stack of layers processed according to examples as disclosed herein) that may include various conductive, semiconductor, or dielectric materials between the stack of layers and the substrate 401. In some examples, the substrate 401 itself may include such interconnect or routing circuitry (e.g., based on doping various portions of the substrate 401). In some cases, the stack of layers may be deposited within a memory region of a memory device (e.g., a region of the memory device where the memory cells 105 are located). Additionally, the top view of FIG. 4A may show a view of the layout 400 at a given level (e.g., level 230).

[0044] The first set of fabrication operations may also include operations that support the formation of pillars, piers, or both (e.g., pillar etching operations, pier etching operations) according to examples disclosed herein. For example, the first set of fabrication operations may include forming one or more cavities through the layer stack (e.g., by removing portions of the first material and dielectric material 435 along the z-direction down to the substrate 401 or to an intervening material between the layer stack and the substrate 401).

[0045] The first set of fabrication operations may include additional operations (e.g., pier fill operations, pier gap fill operations) that support the formation of piers according to examples disclosed herein. For example, the first set of fabrication operations may include forming a set of piers 405 through the stack of layers by depositing one or more materials (e.g., one or more third materials) into (e.g., fill) the cavities, such as a dielectric material (e.g., a second dielectric material) or a semiconductor (e.g., polysilicon), among other materials. In some examples, the material of the piers 405 may be an oxide (e.g., a pier oxide), which may be the same as or similar to the dielectric material 435. In some examples, the material of the piers 405 may be selected to have relatively high strength, high stiffness, or bond strength with the dielectric material 435. In some examples, the first set of fabrication operations may include a polishing or planarization operation to planarize the top surface of the layout 400, which may support aspects of subsequent operations.

[0046] In some cases, the first set of fabrication operations may include removing (e.g., etching) portions of the stack of layers to form a set of cavities in the memory region along the z-direction. For example, the first set of fabrication operations may include removing portions of the first material between layers of dielectric material 435 to form a set of cavities (e.g., portions of the first material in level 230). Forming the set of cavities may define a set of interleaved comb structures that enable the formation of word line structures such as word lines 412 (e.g., word lines 205). For example, one or more conductive materials may be deposited within the set of cavities to form word lines such as word lines 412-a and 412-b, which may be examples of word lines 205 (e.g., portions of word lines 205).

[0047] The first set of fabrication operations may include further operations (e.g., bottom electrode deposition) supporting the formation of the electrode 410, which may be an electrode 410 between the memory cell 105 and the respective word line 412. For example, the fabrication operations may include depositing an electrode material in contact with the material of the pier 405 and the dielectric material 435 to form the electrode 410. The electrode material may be an example of a conductive material (e.g., tin nitride, tantalum nitride, etc.) and may enable current flow between the storage component of the memory cell and associated access circuitry (e.g., word line 412, pillar 220). For example, the memory cell may be coupled to the associated access circuitry via the electrode 410. In some examples, the electrode material may be a metal or carbide. The first set of fabrication operations may include further operations (e.g., bottom electrode recess etching operations) supporting the formation of the electrode. For example, the fabrication operations may include removing (e.g., etching) exposed portions of the electrode material, which may create a recess in the portion of the electrode material. For example, two portions of the electrode material may remain, as shown by 410-a and 410-c.

[0048] The first set of fabrication operations may also include operations that support the formation of memory cell 105. For example, the first set of fabrication operations may include depositing a placeholder or sacrificial material 430 (e.g., a dielectric material such as silicon nitride, among others) that contacts exposed portions of the electrode material of electrode 410 and the material of pier 405. In some examples, portions of sacrificial material 430 may be removed from the memory region and, in a later operation, replaced with a memory material such as a chalcogenide material. The fabrication operations may include removing (e.g., etching) exposed portions of sacrificial material 430, which may create recesses in the portions of sacrificial material 430. For example, two portions of sacrificial material 430 may remain, as partially shown by 430-a and 430-b.

[0049] The first set of fabrication operations may include operations (e.g., gap-fill operations) that support the formation of pillars (e.g., pillars 220) within the set of cavities. For example, the fabrication operations may include depositing a third portion of the electrode material (e.g., electrode 410-b), a ceramic material 415, and a metallic material 420 within the cavities to form the pillars. In some examples, the electrode material may be etched after its deposition and prior to deposition of the ceramic material 415 and the metallic material 420 to expose the substrate 401 (e.g., or materials or components between the layer stack and the substrate 401) so that the ceramic material 415 and the metallic material 420 within the cavities may contact the substrate 401 (e.g., materials or components between the layer stack and the substrate 401). In some examples, the ceramic material 415 may be an example of titanium nitride (TiN) and may act as a barrier between the metallic material 420 and other materials. In some examples, the metal material 420 may be an example of a conductive material, such as tungsten (W), and may form the conductive portion of a pillar (eg, pillar 220).

[0050] The first set of fabrication operations may include forming cavity 425 by removing a portion of sacrificial material 430, leaving portions of sacrificial material 430 (e.g., sacrificial materials 430-a and 430-b). Thus, after the first set of fabrication operations, portion 400-a of layout 400 may include sacrificial material 430-a between electrodes 410-a and 410-b, and sacrificial material 430-b between electrodes 410-b and 410-c, as shown by a top view of portion 400-a of layout 400. Furthermore, each of portions of sacrificial material 430-a and 430-b may be located between a first layer of dielectric material 435-a and a second layer of dielectric material 435-b, as shown by cross section AA. Furthermore, each of electrodes 410-a, 410-b, and 410-c may be located between a first layer of dielectric material 435-a and a second layer of dielectric material 435-b, as shown by cross section BB.

[0051] 4B shows a portion 400-b of layout 400 after a second set of one or more fabrication operations supporting a memory cell protection layer in a three-dimensional memory array, according to examples disclosed herein. The second set of fabrication operations may include additional operations (e.g., barrier formation operations) supporting the formation of a protective barrier that reduces or eliminates diffusion of material between the memory cells and dielectric material 435. The second set of fabrication operations may be performed after the first set of fabrication operations or may be a continuation of the first set of fabrication operations.

[0052] A second set of fabrication operations may include forming a barrier material 440 in the cavity 425 on one or more exposed surfaces of the material. The barrier material 440 may include boron (e.g., may be referred to as a boron-based material) because including boron in the barrier material 440 may support the formation of a thin barrier between the memory cell and the dielectric material 435 and may also support electrical coupling of the memory cell to associated access circuitry via the electrode 410, even when a portion of the barrier material 440 is formed on the surface of the electrode 410. In some cases, the fabrication operations may include performing a plasma procedure (e.g., chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), etc.) in the cavity 425. For example, fabrication operations may include depositing a boron-containing material (e.g., a boron halide, a non-halogenated boron, a boron trihalide, or other forms including BH, BH(CH), BBr, BF, BCl, borazine, among other boron-containing materials) into the cavities 425 on the surfaces of the layers of dielectric material 435-a and 435-b. The boron-containing material may also be deposited on the surfaces of the electrodes 410 (e.g., on the surfaces of the sacrificial material 430). By a plasma procedure, nitrogen may combine with the boron-containing material to form the barrier material 440. For example, as part of a plasma procedure (e.g., a remote plasma procedure), nitrogen radicals may be formed in the cavities 425 (e.g., on the surfaces of the layers of dielectric material 435-a and 435-b) and combine with the boron-containing material to form the barrier material 440. In some examples, barrier material 440 can include boron nitride, silicon boron nitride, or other materials (e.g., examples of boron- and transition metal-containing materials such as BGeN, BHfN, BAlN, BZrN, or BTiN, e.g., atomic layer deposition (ALD) gases of such materials are present). In some examples, a fabrication operation can include multiple cycles of forming a boron-containing material in cavity 425 and performing a plasma procedure in cavity 425 to form barrier material 440 (e.g., to form a thicker layer of barrier material 440).

[0053] In some examples, forming the boron-containing material in the cavity may include forming a vapor. For example, a boron-containing vapor (e.g., a boron source gas) may be formed (e.g., introduced, injected) into cavity 425. In some examples, the vapor may be formed (e.g., adhered, adsorbed) on the surface of the layer of dielectric material 435-a and on the surface of the layer of dielectric material 435-b. While vapor (e.g., a boron-containing material) is formed on the bottom surface of dielectric material 435-a and on the top surface of dielectric material 435-b in the illustrative example of portion 400-b of layout 400, vapor may also be formed on the top surface of dielectric material 435-a, on the bottom surface of dielectric material 435-b, and on the top or bottom of one or more other layers of dielectric material 435 in connection with the formation of memory cells included in other levels of the memory device. In some cases, vapor may also form on the surface of electrode 410-a, one or more surfaces of electrode 410-b, and the surface of electrode 410-c.

[0054] In some cases, the plasma procedure may excite a vapor material with a plasma. For example, the plasma procedure may be a remote plasma procedure in which some materials of the plasma (e.g., hydrogen, helium, argon) are filtered (e.g., not exposed to surfaces within cavity 425) and other materials of the plasma (e.g., nitrogen, such as nitrogen radicals) may be applied to surfaces within cavity 425. The plasma may excite the vapor (e.g., heat the surface and react with the vapor) such that the nitrogen radicals combine with the vapor to form boron-containing barrier material 440 on the respective surfaces. In some examples, barrier material 440 may be formed on the surface of layer of dielectric material 435-a within cavity 425 and on the surface of layer of dielectric material 435-b within cavity 425 (e.g., where vapor was formed on the dielectric layer). Although barrier material 440 is formed on the bottom surface of dielectric material 435-a and on the top surface of dielectric material 435-b in the illustrative example of portion 400-b of layout 400, barrier material 440 may also be formed on the top surface of dielectric material 435-a, on the bottom surface of dielectric material 435-b, and on the top or bottom of one or more other layers of dielectric material 435 in connection with the formation of memory cells included in other levels of the memory device. In some examples, the plasma procedure may be performed in parallel with forming a boron-containing material (e.g., a boron-containing vapor). Furthermore, the plasma procedure and vapor formation may be performed cyclically.

[0055] In some cases, barrier material 440 may also be formed over all or a portion of the surfaces of electrodes 410-a and 410-b within cavity 425 (e.g., at locations where vapor formed on electrode 410), as illustrated by cross section BB of portion 400-b of layout 400. For example, barrier material 440 may be electrically compatible (e.g., have a compatible bandgap) with electrode 410 so that electrode 410 may interact with memory cell 105 without interference (e.g., minimal or substantially no interference) from barrier material 440. That is, barrier material 440 may enable coupling of memory cell 105 and associated access circuitry through electrode 410 (e.g., even though it is located between and physically separate from the memory cell and electrode 410).

[0056] In some examples, the portion of the barrier material 440 formed on the electrode 410 can be thinner than the portion of the barrier material 440 formed on the dielectric material 435. For example, the layer of barrier material 440 formed on the dielectric material 435 can be thick enough to prevent or reduce diffusion between the dielectric material 435 and the memory cells 105, and the layer of barrier material 440 formed on the electrode 410 can be thin enough to support electrical coupling between each of the electrodes 410 and the memory cells, as described with reference to FIG. 4C . In some examples, the thickness of the barrier material 440 formed on the electrode 410 (e.g., the length of the barrier material 440 in the y-direction on the electrode 410) can be in the angstrom range (e.g., only 5 to 25 angstroms). In some examples, the thickness of the barrier material 440 formed on the dielectric material 435 may be in the angstrom range. In some examples, the thickness of the barrier material 440 formed on the dielectric material 435 can be in the nanometer range (e.g., between 1 and 15 nanometers, among other nanometer ranges).

[0057] In some examples, the thickness of the barrier material 440 formed on the dielectric material 435 relative to the electrode 410 may be due to differences in the material properties of the dielectric material 435 and the electrode 410. For example, a greater amount of the boron-containing material formed in the cavity 425 may adhere to the surface of the dielectric material 435 compared to the amount of the boron-containing material adhering to the surface of the electrode 410. As a result, a greater amount, and therefore a thicker layer, of the barrier material 440 may be formed on the dielectric material 435 than on the electrode 410.

[0058] In some examples, a barrier material 440 may also be formed on the surface of the sacrificial material 430 .

[0059] In some examples, a growth process may be performed in addition to the plasma procedure. For example, after barrier material 440 is formed in cavity 425, a second material (e.g., silicon radicals) may be applied to (e.g., formed on) the surface of barrier material 440, and a second plasma procedure may excite the second material (e.g., a second vapor material) with the plasma. The second material may combine with nitrogen radicals of the plasma to form barrier material 445 (e.g., silicon nitride) over barrier material 440 (e.g., a dual barrier).

[0060] In some cases, the plasma procedure, the growth process, or both may be combined with one or more etching procedures. For example, instead of a thin layer of barrier material 440 on electrode 410, the etching procedure may remove a portion of barrier material 440 from the surface of electrode 410 while maintaining barrier material 440 on the surface of dielectric material 435.

[0061] 4C shows a portion 400-c of layout 400 after a third set of one or more fabrication operations supporting a memory cell protection layer in a three-dimensional memory array, according to examples disclosed herein. The third set of fabrication operations may include further operations (e.g., memory cell formation operations) supporting the formation of memory cells 450 (e.g., memory cells 105) protected by barrier material 440. The third set of fabrication operations may be performed after the second set of fabrication operations or may be a continuation of the second set of fabrication operations.

[0062] A third set of one or more fabrication operations may support the formation of memory cell 105. For example, the fabrication operations may include depositing a storage material in cavity 425 (e.g., the remaining portion of cavity 425 after formation of barrier material 440), as described with reference to FIGS. 4A and 4B. In some cases, the storage material may be a material configured to store the logic state of the memory cell, such as a chalcogenide glass or chalcogenide alloy. Thus, after deposition, the storage material may be in contact with barrier material 440, one or more electrodes 410, or both. Alternatively, if the cavity has a dual barrier, the storage material may be in contact with barrier material 445, one or more electrodes 410, or both. Fabrication operations may also include recessing or etching storage material to form memory cell 450 within cavity 425 such that protected memory cell 450 is located between barrier materials 440, 445, or both, over the layer of dielectric material 435 and between barrier materials 440, 445, or both, over electrode 410. That is, barrier material 440 (e.g., and barrier material 445) may be located between memory cell 450 and dielectric material 435. In some examples, barrier material 440 (e.g., and barrier material 445) may also be located between memory cell 450 and electrode 410. In some examples, barrier material 440 (e.g., and barrier material 445) may also be located between memory cell 450 and sacrificial material 430. In some cases, memory cell 450 may be coupled to pillar material (e.g., 415 and 420) via electrode 410-b and to word line 412-a (e.g., a word line member of word line 205) via electrode 410-a.

[0063] The fabrication operations may also include depositing a seal material 455, which may be an example of a dielectric material, within the cavities 425. For example, the fabrication operations may perform ALD within the cavities 425. In some cases, the seal material may be deposited in contact with each memory cell 450 of each cavity 425. The seal material 455, along with a gap fill material, may form a respective set of dielectric portions. In some cases, forming the set of dielectric portions may further include performing a polishing or planarization process to smooth or polish the tops of portions 400-c of layout 400.

[0064] Barrier material 440 can insulate memory cell 450 from the layers of dielectric material 435-a and 435-b. For example, barrier material 440 can physically separate memory cell 450 from the layers of dielectric material 435, supporting access to the memory cell via electrodes 410-a and 410-b, while preventing or reducing diffusion between memory cell 450 and the layers of dielectric material 435-a and 435-b, such as the diffusion of element combinations with low binary bond activation energies (e.g., the diffusion of oxygen into memory cell 450 and the diffusion of elements from memory cell 450 such as In—Se, As—Se, In—In, In—Sb, In—Te, In—S, Se—Se, As—H, Se—H, among other element combinations).

[0065] 5 illustrates layout 500 after a fourth set of one or more fabrication operations supporting a memory cell protection layer in a three-dimensional memory array, according to examples disclosed herein. The fourth set of fabrication operations may include additional operations (e.g., barrier formation operations) supporting the formation of a protective barrier between memory cell 550 and dielectric material 535. In some cases, the fourth set of fabrication operations may be an alternative to the second set of fabrication operations and before the third set of fabrication operations, as described with reference to FIGS. 4B and 4C. Alternatively, the fourth set of fabrication operations may be performed after the first set of fabrication operations and before the second and third sets of fabrication operations, thereby supporting the formation of an additional barrier (e.g., in addition to barrier material 440).

[0066] For example, before memory cell 550 is formed, a fourth set of fabrication operations may include performing a doping procedure (e.g., boron doping) of dielectric materials 535-a and 535-b, electrodes 510 (e.g., electrodes 510-a, 510-b, 510-c), or both, formed on substrate 501, which may be examples of dielectric material 435, electrode 410, and substrate 401 described with reference to Figures 4A-4C. For example, boron-containing material 560 (e.g., boron halide, boron non-halide, boron trihalide, or other forms including B2H6, B2H2(CH3)4, BBr3, BF3, BCl3, borazine, among other boron-containing materials) may be deposited on the layer of dielectric material 535, electrode 510, or a combination thereof (e.g., the material may be formed in cavity 425). In some examples, the doping procedure may cause material 560 to bond with oxygen and / or silicon contained within the layer of dielectric material 535, which may prevent or reduce subsequent diffusion of oxygen into memory cell 550. For example, due to oxygen bonding with material 560, oxygen may not be able to bond with the material of memory cell 550.

[0067] The material 560 may diffuse into each deposition region, including the layer of dielectric material 535-a, the layer of dielectric material 535-b, the electrode 510, or a combination thereof. In some cases, the diffusion may be performed thermally. In some cases, the diffusion may be performed through an exposure procedure or a growth procedure (e.g., CVD). For example, the material 560 may be formed on the surface of the dielectric material 535, the electrode 510, or a combination thereof, and a rapid thermal annealing procedure, laser treatment, microwave treatment, or a combination thereof may be performed to diffuse the material 560 into the surface. The diffusion of the material 560 may be relatively localized to the surface of the dielectric material 535, the electrode 510, or both. In some examples, the doping procedure may also include doping the sacrificial material 530, which may be an example of the sacrificial material 430. The sacrificial material 530 may contact the pier 505, which may be an example of the pier 405.

[0068] In some cases, the fourth set of fabrication operations may include a second procedure to add nitrogen to the diffusion material 560 (e.g., nitriding the material 560). For example, nitrogen may be deposited in the cavity 425 by a plasma procedure, as described with reference to FIGS. 4A-4B. The plasma may excite (e.g., heat and react with) the material 560 such that nitrogen radicals combine with the material 560 to form a boron-containing barrier material 540 (e.g., boron nitride, or silicon boron nitride, or other material containing boron and a transition metal) on the respective surfaces. In some cases, the plasma procedure may form the barrier material 540 from all of the diffusion material 560. Alternatively, a first portion of the diffusion material 560 may remain, and the plasma procedure may form the barrier material 540 from a second portion of the diffusion material 560.

[0069] In some examples, barrier material 540 may be formed on (e.g., directly above) the surface of the layer of dielectric material 535-a within the cavity (e.g., cavity 425) and on the surface of the layer of dielectric material 535-b within the cavity (e.g., where material 560 has diffused into the dielectric layer). Although barrier material 540 is formed on the bottom surface of dielectric material 535-a and on the top surface of dielectric material 535-b in the illustrative example of layout 500, barrier material 540 may also be formed on the top surface of dielectric material 535-a, on the bottom surface of dielectric material 535-b, and on the top or bottom of one or more other layers of dielectric material 535. In some examples, the plasma procedure may be performed cyclically.

[0070] In some examples, a barrier material 440 (e.g., and barrier material 445) as described with reference to Figures 4B and 4C may be formed on the surface of the dielectric material 535 doped with material 560 (e.g., on barrier material 540).

[0071] 4C may be performed after the fourth set of one or more fabrication operations. For example, after material 560 is diffused and nitridized, or alternatively, after barrier material 540 is formed, the fabrication operations may include depositing a storage material in cavity 425, as described with reference to FIGS. 4A and 4B. Thus, after deposition, the storage material may be in contact with the layer of boron-doped dielectric material 535 (e.g., dielectric material 535 doped with material 560), one or more electrodes 510, or both. Alternatively, if the cavity has barrier material 540, the storage material may be in contact with barrier material 540, one or more of electrodes 510, or both. The fabrication operations may also include recessing or etching the storage material to form the memory cell 550 within the cavity such that the protected memory cell 550 is located between the barrier material 540 on the layer of dielectric material 535 and the barrier material 540 on the electrode 510, or alternatively, between the boron-doped layer of dielectric material 535 and the electrode 510 (the boron-doped electrode 510). In some cases, the memory cell 550 may be coupled to a pillar material (e.g., pillar materials 515 and 520) via electrode 510-b and to a word line 512 (e.g., word line 412) via electrode 510-a.

[0072] The fabrication operations may also include depositing a seal material 555, which may be an example of a dielectric material, within the cavities. For example, the fabrication operations may perform ALD within the cavities. In some cases, the seal material may be deposited in contact with each memory cell 550 in each cavity. The seal material 555, along with a gap fill material, may form a respective set of dielectric portions. In some cases, forming the set of dielectric portions may further include performing a polishing or planarization process to smooth or polish the tops of the layout 500.

[0073] In some cases, the boron-doped layers of dielectric materials 535-a and 535-b may prevent or reduce diffusion of material 560 into memory cell 550 by bonding with oxygen in dielectric materials 535-a and 535-b. Additionally or alternatively, barrier material 540 may insulate memory cell 550 from the layers of dielectric materials 535-a and 535-b. For example, barrier material 540 may prevent or reduce diffusion between memory cell 550 and the layers of dielectric materials 535-a and 535-b, such as the diffusion of elemental combinations with low dyadic bond activation energies (e.g., elements with low diatomic bond strengths), while supporting access to the memory cell via electrodes 510-a and 510-b.

[0074] 6 illustrates a flowchart showing a method 600 for supporting a memory cell protection layer in a three-dimensional memory array, according to examples disclosed herein. The operations of method 600 may be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some examples, the one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally, or alternatively, the one or more controllers may perform aspects of the described functions using dedicated hardware.

[0075] At 605, the method may include forming a stack of layers on a substrate, where the stack of layers may include a layer of a first material and a layer of a dielectric material. The operations of 605 may be performed according to examples disclosed herein.

[0076] At 610, the method may include removing a portion of the layer of first material, wherein a cavity between the first layer of dielectric material and the second layer of dielectric material is formed at least in part based on the removing. The operations of 610 may be performed according to examples as disclosed herein.

[0077] At 615, the method may include forming a barrier material including boron in the cavity, the barrier material being formed on a first surface of the first layer of dielectric material and on a second surface of the second layer of dielectric material. The operations of 615 may be performed according to examples as disclosed herein.

[0078] At 620, the method may include forming a memory cell between a barrier material on a first surface of the first layer of dielectric material and a barrier material on a second surface of the second layer of dielectric material, the memory cell being isolated from the dielectric material based at least in part on the barrier material. The operations of 620 may be performed according to examples as disclosed herein.

[0079] In some examples, an apparatus (e.g., a manufacturing system) described herein may perform one or more methods, such as method 600. The apparatus may include features, circuits, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of the manufacturing system), or any combination thereof, to perform the following aspects of the present disclosure.

[0080] Aspect 1: A method or apparatus comprising: forming a stack of layers on a substrate, the stack of layers including multiple layers of a first material and multiple layers of a dielectric material; removing a portion of the layer of the first material, wherein a cavity is formed between the first layer of dielectric material and the second layer of dielectric material based at least in part on the removing; forming a barrier material including boron in the cavity, the barrier material being formed on a first surface of the first layer of dielectric material and on a second surface of the second layer of dielectric material; and forming a memory cell between the barrier material on the first surface of the first layer of dielectric material and the barrier material on the second surface of the second layer of dielectric material, wherein the memory cell is insulated from the dielectric material based at least in part on the barrier material.

[0081] Aspect 2: The method or apparatus of aspect 1, wherein forming the barrier material includes operations, features, circuits, logic, means, or instructions, or any combination thereof, for depositing a second material comprising boron in the cavity on the first surface and the second surface, and performing a plasma procedure in the cavity.

[0082] Aspect 3: The method or apparatus of aspect 2, wherein depositing the second material is concurrent with performing the plasma procedure.

[0083] Aspect 4: The method or apparatus of any of Aspects 2-3, wherein performing the plasma procedure includes an operation, feature, circuit, logic, means, or instruction, or any combination thereof, for combining nitrogen associated with the plasma procedure with the second material to form the barrier material.

[0084] Aspect 5: The method or apparatus of any of Aspects 1-4, wherein forming the barrier material includes operations, features, circuits, logic, means, or instructions, or any combination thereof, for forming a vapor comprising boron in the cavity and exciting the vapor with a plasma, wherein the plasma reacts with the vapor to form the barrier material based at least in part on the exciting.

[0085] Aspect 6: The method or apparatus of any one of Aspects 1-5, further comprising: an operation, feature, circuit, logic, means, or instructions, or any combination thereof, for forming a first electrode and a second electrode based at least in part on removing the layer of the first material, wherein forming the barrier material comprises forming the barrier material on a third surface of the first electrode and on a fourth surface of the second electrode, and forming the memory cell comprises forming the memory cell between the barrier material on the third surface of the first electrode and the barrier material on the fourth surface of the second electrode.

[0086] Aspect 7: The method or apparatus of aspect 6, wherein a first thickness of the barrier material on the first surface of the first layer of the dielectric material or on the second surface of the second layer of the dielectric material is greater than a second thickness of the barrier material on the third surface of the first electrode and on the fourth surface of the second electrode.

[0087] Aspect 8: The method or apparatus described in aspect 7, wherein the first electrode couples the memory cell to a word line and the second electrode couples the memory cell to a pillar associated with accessing the memory cell based at least in part on the second thickness of the barrier material.

[0088] Aspect 9: The method or apparatus of any one of Aspects 1-8, further comprising: forming a second barrier material on the barrier material on the first surface of the first layer of dielectric material and on the barrier material on the second surface of the second layer of dielectric material, the second barrier material comprising silicon nitride; and forming the memory cell between the second barrier material on the first surface of the first layer of dielectric material and the second barrier material on the second surface of the second layer of dielectric material, the memory cell being isolated from the dielectric material based at least in part on the barrier material and the second barrier material.

[0089] Embodiment 10: The method or apparatus of any one of embodiments 1-9, wherein the barrier material comprises boron nitride.

[0090] Embodiment 11: The method or apparatus of any of embodiments 1-10, wherein each of the layers of the first material are separated from one another by respective layers of the dielectric material.

[0091] 7 illustrates a flowchart showing a method 700 for supporting a memory cell protection layer in a three-dimensional memory array, according to examples disclosed herein. The operations of method 700 may be implemented by a manufacturing system or one or more controllers associated with the manufacturing system. In some examples, the one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally, or alternatively, the one or more controllers may perform aspects of the described functions using dedicated hardware.

[0092] At 705, the method may include forming a stack of layers on the substrate, where the stack of layers may include a layer of a first material and a layer of a dielectric material. The operations of 705 may be performed according to examples disclosed herein.

[0093] At 710, the method may include removing a portion of the layer of first material, wherein a cavity between the first layer of dielectric material and the second layer of dielectric material is formed at least in part based on the removing. The operations of 710 may be performed according to examples as disclosed herein.

[0094] At 715, the method may include doping both the first surface of the first layer of dielectric material and the second surface of the second layer of dielectric material with a second material including boron. The operations of 715 may be performed according to examples as disclosed herein.

[0095] At 720, the method may include forming a memory cell between the doped first surface of the first layer of dielectric material and the doped second surface of the second layer of dielectric material. The operation of 720 may be performed according to examples as disclosed herein.

[0096] In some examples, an apparatus (e.g., a manufacturing system) described herein may perform one or more methods, such as method 700. The apparatus may include features, circuits, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of the manufacturing system), or any combination thereof, to perform the following aspects of the present disclosure.

[0097] Aspect 12: A method or apparatus comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for: forming a stack of layers on a substrate, the stack of layers comprising a first material and a layer of dielectric material; removing a portion of the layer of first material, wherein a cavity between the first layer of dielectric material and the second layer of dielectric material is formed at least in part based on the removing; doping both a first surface of the first layer of dielectric material and a second surface of the second layer of dielectric material with a second material comprising boron; and forming a memory cell between the doped first surface of the first layer of dielectric material and the doped second surface of the second layer of dielectric material.

[0098] Aspect 13: The method or apparatus of aspect 12, wherein doping the first surface of the first layer of dielectric material and the second surface of the second layer of dielectric material with the second material includes operations, features, circuits, logic, means, or instructions, or any combination thereof, for depositing the second material on the first surface of the first layer of dielectric material and the second surface of the second layer of dielectric material, and diffusing the second material into the first surface of the first layer of dielectric material and the second surface of the second layer of dielectric material.

[0099] Example 14: The method or apparatus of example 13, wherein diffusing the second material comprises performing a rapid thermal annealing procedure, a laser treatment, a microwave treatment, or any combination thereof.

[0100] Aspect 15: The method or apparatus of any of Aspects 12-14, further comprising an operation, feature, circuit, logic, means, or instructions, or any combination thereof, for forming a barrier material comprising boron on the doped first surface of the first layer of the dielectric material and on the doped second surface of the second layer of the dielectric material, wherein the memory cell is isolated from the dielectric material based at least in part on the barrier material.

[0101] Aspect 16: The method or apparatus described in aspect 15, wherein forming the barrier material includes an operation, feature, circuit, logic, means, or instruction, or any combination thereof, for performing a plasma procedure in the cavity, and nitrogen associated with the plasma procedure is combined with the second material to form the barrier material based at least in part on the doping and performing the plasma procedure.

[0102] Embodiment 17: The method or apparatus of any of embodiments 15-16, wherein the barrier material comprises boron nitride, or silicon boron nitride, germanium, aluminum, one or more doped transition metals, or any combination thereof.

[0103] Aspect 18: The method or apparatus of any of Aspects 12-17, further including operations, features, circuits, logic, means, or instructions, or any combination thereof, for: forming a first electrode and a second electrode based at least in part on removing the layer of the first material; and doping a third surface of the first electrode and a fourth surface of the second electrode with the second material, wherein forming the memory cell includes forming the memory cell between the third surface of the first electrode and the fourth surface of the second electrode.

[0104] It should be noted that the methods described herein describe possible implementations, and that the operations and steps may be rearranged or modified, and that other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0105] DEVICES ARE DISCLOSED The following provides a summary of aspects of the devices described herein.

[0106] Aspect 19: A device comprising: a plurality of levels of memory arrays arranged on a substrate and separated from one another by respective layers of a plurality of layers of dielectric material; pillars extending in a first direction through the memory arrays of the plurality of levels, wherein at each level of the plurality of levels, one or more memory cells of the memory array are coupled to a respective word line and the pillar; and a barrier material comprising boron and located between each memory cell and the respective layer of the dielectric material in which the each memory cell is located, wherein the each memory cell is insulated from the dielectric material based at least in part on the barrier material.

[0107] Aspect 20: The device of aspect 19, wherein each of the respective layers of the dielectric material includes a surface doped with a second material including boron.

[0108] Aspect 21: The device of any of aspects 19-20, further comprising a first electrode between each memory cell and each word line and a second electrode between each memory cell and the pillar, wherein the barrier material is located between each memory cell and each of the first electrode and the second electrode in which the each memory cell is located.

[0109] Aspect 22: The device described in Aspect 21, wherein a first thickness of the barrier material located between each memory cell and each layer of the dielectric material is greater than a second thickness of the barrier material located between each memory cell and the first electrode or the second electrode.

[0110] Aspect 23: The device described in any of aspects 19 to 22, further comprising a second barrier material positioned between each memory cell and the barrier material, wherein each memory cell is insulated from the dielectric material based at least in part on the barrier material and the second barrier material.

[0111] Aspect 24: The device of Aspect 23, wherein the second barrier material comprises silicon nitride.

[0112] Aspect 25: The device of any of aspects 19-24, wherein the barrier material comprises boron nitride, silicon boron nitride, germanium, aluminum, one or more doped transition metals, or any combination thereof.

[0113] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, signaling data, instructions, commands, information, signals, bits, or symbols that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. While some drawings may show a signal as a single signal, the signal may represent a bus of signals, and the bus may have various bit widths.

[0114] The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication with each other (or in conductive contact, or connected, or coupled) if any conductive path exists between the components that can support the flow of signals between the components at all times. At any time, the conductive path between components that are in electronic communication with each other (or in conductive contact, or connected, or coupled) may be an open circuit or a closed circuit based on the operation of the device including the connected components. The conductive path between connected components may be a direct conductive path between the components, or the conductive path between connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between connected components may be temporarily interrupted using one or more intermediate components, such as, for example, switches or transistors.

[0115] The term "coupling" refers to a transition from an open-circuit relationship between components, where signals cannot currently be communicated between the components via conductive paths, to a closed-circuit relationship between the components, where signals can be communicated between the components via conductive paths. When a component, such as a controller, couples other components together, that component initiates a change that allows signals to flow between other components via conductive paths that previously did not allow signals to flow.

[0116] The term "isolated" refers to a relationship between components in which signals cannot currently flow between them. Components are isolated from one another if an open circuit exists between them. For example, two components separated by a switch positioned between them are isolated from one another when the switch is open. When a controller isolates two components, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously allowed signals to flow.

[0117] As used herein, the term "layer" or "level" refers to a stratum or sheet of a geometric structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure, such as a thin film, with two dimensions greater than the other. A layer or level may comprise different elements, components, or materials. In some examples, a layer or level may be composed of two or more sublayers or sublevels.

[0118] As used herein, the term "electrode" may refer to an electrical conductor, which in some examples may be used as an electrical contact to a memory cell or other component of a memory array. Electrodes may include traces, wires, conductive lines, conductive layers, etc. that provide conductive paths between elements or components of a memory array.

[0119] The devices described herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, or gallium nitride. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled through doping using various chemical species, including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed by ion implantation during the initial formation or growth of the substrate, or by any other doping means.

[0120] The switching components or transistors described herein may represent field-effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals can be connected to other electronic elements through conductive materials, such as metals. The source and drain can be conductive and include heavily doped, e.g., degenerate, semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrodes), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can result in the channel becoming conductive. A transistor can be "on" or "activated" when a voltage equal to or greater than the transistor's threshold voltage is applied to the transistor gate. When a voltage less than the transistor's threshold voltage is applied to the transistor gate, the transistor can be "off" or "deactivated."

[0121] The description set forth herein with reference to the accompanying drawings describes exemplary configurations and does not represent every embodiment that may be practiced or that is within the scope of the claims. As used herein, the term "exemplary" means "serving as an example, instance, or illustration," and does not mean "preferred" or "advantageous over other embodiments." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described embodiments.

[0122] In the accompanying figures, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. When only a first reference label is used in the specification, the description can apply to any one of the similar components having the same first reference label, regardless of the second reference label.

[0123] The functions described herein may be implemented by hardware, software executed by a processor, firmware, or any combination thereof. When implemented in software executed by a processor, the functions may be stored or transmitted as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions may also be physically located in various locations, including being distributed such that portions of the functions are implemented in different physical locations.

[0124] For example, the various example blocks and modules described in connection with the disclosure herein may be implemented or performed by a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0125] As used herein, including the claims, "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such as, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" is not to be construed as referring to a closed set of conditions. For example, an example step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" is to be construed the same as the phrase "based at least in part on."

[0126] Computer-readable media includes both non-transitory computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another. Non-transitory storage media may be any available medium that can be accessed by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Also, any connection may be properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included within the definition of medium. As used herein, disk and disc include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs; typically, disks reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0127] The description herein is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. forming a stack of layers on a substrate, the stack of layers including a plurality of layers of a first material and a plurality of layers of a dielectric material; removing a portion of the layer of first material, wherein a cavity between the first layer of dielectric material and the second layer of dielectric material is formed at least in part based on the removing; forming a barrier material including boron in the cavity, the barrier material being formed on a first surface of the first layer of dielectric material and on a second surface of the second layer of dielectric material; forming a memory cell between the barrier material on the first surface of the first layer of dielectric material and the barrier material on the second surface of the second layer of dielectric material, the memory cell being insulated from the dielectric material based at least in part on the barrier material; A method comprising:

2. forming the barrier material depositing a second material comprising boron in the cavity over the first surface and the second surface; performing a plasma procedure in said cavity; The method of claim 1 , comprising:

3. The method of claim 2 , wherein the depositing of the second material is concurrent with the performing of the plasma procedure.

4. The method of claim 2 , wherein performing the plasma procedure includes combining nitrogen associated with the plasma procedure with the second material to form the barrier material.

5. forming the barrier material forming a vapor containing boron within the cavity; exciting the vapor with a plasma, wherein the plasma reacts with the vapor to form the barrier material based at least in part on the exciting; The method of claim 1 , comprising:

6. forming a first electrode and a second electrode based at least in part on removing the layer of the first material; forming the barrier material includes forming the barrier material on a third surface of the first electrode and on a fourth surface of the second electrode; 2. The method of claim 1 , wherein forming the memory cell comprises forming the memory cell between the barrier material on the third surface of the first electrode and the barrier material on the fourth surface of the second electrode.

7. 7. The method of claim 6, wherein a first thickness of the barrier material on the first surface of the first layer of dielectric material or on the second surface of the second layer of dielectric material is greater than a second thickness of the barrier material on the third surface of the first electrode and on the fourth surface of the second electrode.

8. 8. The method of claim 7, wherein the first electrode couples the memory cell to a word line and the second electrode couples the memory cell to a pillar associated with accessing the memory cell based at least in part on the second thickness of the barrier material.

9. forming a second barrier material over the barrier material on the first surface of the first layer of dielectric material and over the barrier material on the second surface of the second layer of dielectric material, the second barrier material comprising silicon nitride; forming the memory cell between the second barrier material on the first surface of the first layer of dielectric material and the second barrier material on the second surface of the second layer of dielectric material, the memory cell being insulated from the dielectric material based at least in part on the barrier material and the second barrier material; The method of claim 1 further comprising:

10. The method of claim 1 , wherein the barrier material comprises boron nitride.

11. The method of claim 1 , wherein each of the layers of the first material are separated from each other by a respective layer of the dielectric material.

12. forming a stack of layers on a substrate, the stack of layers including a layer of a first material and a layer of a dielectric material; removing a portion of the layer of first material, wherein a cavity between the first layer of dielectric material and the second layer of dielectric material is formed at least in part based on the removing; doping both a first surface of the first layer of dielectric material and a second surface of the second layer of dielectric material with a second material comprising boron; forming a memory cell between the doped first surface of the first layer of dielectric material and the doped second surface of the second layer of dielectric material; A method comprising:

13. Doping the first surface of the first layer of dielectric material and the second surface of the second layer of dielectric material includes: depositing the second material over the first surface of the first layer of dielectric material and the second surface of the second layer of dielectric material; diffusing the second material into the first surface of the first layer of dielectric material and the second surface of the second layer of dielectric material; 13. The method of claim 12, comprising:

14. The method of claim 13 , wherein diffusing the second material comprises performing a rapid thermal annealing procedure, a laser treatment, a microwave treatment, or any combination thereof.

15. 13. The method of claim 12, further comprising forming a barrier material comprising boron on the doped first surface of the first layer of dielectric material and on the doped second surface of the second layer of dielectric material, wherein the memory cell is isolated from the dielectric material based at least in part on the barrier material.

16. 16. The method of claim 15, wherein forming the barrier material includes performing a plasma procedure in the cavity, and wherein nitrogen associated with the plasma procedure combines with the second material to form the barrier material based at least in part on the doping and the performing the plasma procedure.

17. 16. The method of claim 15, wherein the barrier material comprises boron nitride, or silicon boron nitride, germanium, aluminum, one or more doped transition metals, or any combination thereof.

18. forming a first electrode and a second electrode based at least in part on removing the layer of the first material; doping a third surface of the first electrode and a fourth surface of the second electrode with the second material; further comprising 13. The method of claim 12, wherein forming the memory cell comprises forming the memory cell between the third surface of the first electrode and the fourth surface of the second electrode.

19. a plurality of levels of memory arrays arranged on a substrate and separated from one another by respective layers of a plurality of layers of dielectric material; pillars extending in a first direction through the memory array of the plurality of levels, wherein at each level of the plurality of levels, one or more memory cells of the memory array are coupled to a respective word line and the pillar; a barrier material including boron and located between each memory cell and the respective layer of the dielectric material in which the respective memory cell is located, the barrier material being insulated from the dielectric material based at least in part on the barrier material; 1. An apparatus comprising:

20. 20. The apparatus of claim 19, wherein each of the respective layers of dielectric material includes a surface doped with a second material comprising boron.

21. a first electrode between each of the memory cells and each of the word lines; a second electrode between each of the memory cells and the pillar; further comprising 20. The device of claim 19, wherein the barrier material is located between the respective memory cell and each of the first and second electrodes on which the respective memory cell is located.

22. 22. The device of claim 21, wherein a first thickness of the barrier material located between the respective memory cell and the respective layer of dielectric material is greater than a second thickness of the barrier material located between the respective memory cell and the first electrode or the second electrode.

23. 20. The device of claim 19, further comprising a second barrier material located between the respective memory cell and the barrier material, the respective memory cell being insulated from the dielectric material based at least in part on the barrier material and the second barrier material.

24. 24. The apparatus of claim 23, wherein the second barrier material comprises silicon nitride.

25. 20. The apparatus of claim 19, wherein the barrier material comprises boron nitride, silicon boron nitride, germanium, aluminum, one or more doped transition metals, or any combination thereof.

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